diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 13a3a9696821..206686f3eebc 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -84,6 +84,12 @@ properties: - altr,socfpga-stratix10-swvp - const: altr,socfpga-stratix10 + - description: Stratix 10 SoCDK eMMC variant + items: + - const: altr,socfpga-stratix10-socdk-emmc + - const: altr,socfpga-stratix10-socdk + - const: altr,socfpga-stratix10 + - description: AgileX boards items: - enum: @@ -105,6 +111,7 @@ properties: - enum: - intel,socfpga-agilex5-socdk - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml index cff1cdaadb13..48ab3356e383 100644 --- a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml +++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml @@ -15,11 +15,11 @@ description: |+ provides a flexible compute architecture that combines Cortex‑A and Cortex‑M processors. - Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion - systems for M-Class (or other) processors for adding sensors, connectivity, - video, audio and machine learning at the edge System and security IPs to build - a secure SoC for a range of rich IoT applications, for example gateways, smart - cameras and embedded systems. + Support for Cortex‑A32, Cortex‑A35, Cortex‑A53 and Cortex-A320 processors. + Two expansion systems for M-Class (or other) processors for adding sensors, + connectivity, video, audio and machine learning at the edge System and + security IPs to build a secure SoC for a range of rich IoT applications, for + example gateways, smart cameras and embedded systems. Integrated Secure Enclave providing hardware Root of Trust and supporting seamless integration of the optional CryptoCell™-312 cryptographic @@ -39,6 +39,11 @@ properties: implementation of this system. See ARM ecosystems FVP's. items: - const: arm,corstone1000-fvp + - description: Corstone1000-A320 FVP is the Fixed Virtual Platform + implementation of this system with Cortex-A320 cores and Ethos-U85 + NPU. See ARM ecosystems FVP's. + items: + - const: arm,corstone1000-a320-fvp additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index ba04576f0ad6..95d4baa85506 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -119,6 +119,16 @@ properties: items: - const: arm,foundation-aarch64 - const: arm,vexpress + - description: Arm Zena Compute Subsystem Platforms + Arm Zena Compute Subsystem (CSS) is a compute platform targeting + the automotive sector. Arm Zena CSS is a high-performance Arm + Cortex-A720AE Application Processor system augmented with an Arm + Cortex-R82AE based Safety Island and real-time domain. + items: + - enum: + - arm,zena-css-fvp + - const: arm,zena-css + - const: arm,vexpress arm,vexpress,position: description: When daughterboards are stacked on one site, their position diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index f9925a14680e..8ec7a3e74a21 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -35,6 +35,7 @@ properties: - ampere,mtjade-bmc - aspeed,ast2500-evb - asrock,altrad8-bmc + - asrock,ast2500-paul-ipmi-card - asrock,e3c246d4i-bmc - asrock,e3c256d4i-bmc - asrock,romed8hm3-bmc @@ -80,6 +81,7 @@ properties: - ampere,mtmitchell-bmc - aspeed,ast2600-evb - aspeed,ast2600-evb-a1 + - asus,ast2600-kommando-ipmi-card - asus,x4tf-bmc - facebook,anacapa-bmc - facebook,bletchley-bmc diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 68d306d17c2a..bf161e0950ea 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -243,6 +243,12 @@ properties: - const: microchip,lan9668 - const: microchip,lan966 + - description: Microchip LAN9696 EV23X71A Evaluation Board + items: + - const: microchip,ev23x71a + - const: microchip,lan9696 + - const: microchip,lan9691 + - description: Kontron KSwitch D10 MMT series items: - enum: diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml index 63e9aca85db7..3062901196a6 100644 --- a/Documentation/devicetree/bindings/arm/axis.yaml +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -31,6 +31,12 @@ properties: - axis,artpec8-grizzly - const: axis,artpec8 + - description: Axis ARTPEC-9 SoC board + items: + - enum: + - axis,artpec9-alfred + - const: axis,artpec9 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 736b7ab1bd0a..07f3c6a52554 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -218,6 +218,13 @@ properties: - qcom,kryo685 - qcom,kryo780 - qcom,oryon + - qcom,oryon-1-1 + - qcom,oryon-1-2 + - qcom,oryon-1-3 + - qcom,oryon-1-4 + - qcom,oryon-2-1 + - qcom,oryon-2-2 + - qcom,oryon-2-3 - qcom,scorpion - samsung,mongoose-m2 - samsung,mongoose-m3 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml index 09a6c16e7e82..9aa39b002361 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -49,38 +49,37 @@ required: - '#clock-cells' allOf: - - if: - properties: - compatible: - contains: - enum: - - mediatek,mt2701-audsys - - mediatek,mt7622-audsys - then: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-audsys + - mediatek,mt7622-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# - - if: - properties: - compatible: - contains: - const: mediatek,mt8183-audiosys - then: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt8183-audio.yaml# - - - if: - properties: - compatible: - contains: - const: mediatek,mt8192-audsys - then: - properties: - audio-controller: - $ref: /schemas/sound/mt8192-afe-pcm.yaml# + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-audiosys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt8183-audio.yaml# + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mt8192-afe-pcm.yaml# additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1a955d1b14bf..b4943123d2e4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,21 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - enum: + - qcom,eliza-mtp + - const: qcom,eliza + + - items: + - enum: + - qcom,glymur-crd + - const: qcom,glymur + + - items: + - enum: + - qcom,mahua-crd + - const: qcom,mahua + - items: - enum: - fairphone,fp6 @@ -171,6 +186,7 @@ properties: - qcom,msm8916-mtp - samsung,a3u-eur - samsung,a5u-eur + - samsung,coreprimeltevzw - samsung,e5 - samsung,e7 - samsung,fortuna3g @@ -186,6 +202,7 @@ properties: - samsung,serranove - thwc,uf896 - thwc,ufi001c + - wiko,chuppito - wingtech,wt86518 - wingtech,wt86528 - wingtech,wt88047 @@ -195,6 +212,8 @@ properties: - items: - enum: - xiaomi,riva + - xiaomi,rolex + - xiaomi,tiare - const: qcom,msm8917 - items: @@ -243,6 +262,13 @@ properties: - const: qcom,apq8096-sbc - const: qcom,apq8096 + - items: + - const: arrow,apq8096sg-db820c + - const: arrow,apq8096-db820c + - const: qcom,apq8096-sbc + - const: qcom,apq8096sg + - const: qcom,apq8096 + - items: - enum: - oneplus,oneplus3 @@ -297,6 +323,11 @@ properties: - tplink,archer-ax55-v1 - const: qcom,ipq5018 + - items: + - enum: + - qcom,ipq5210-rdp504 + - const: qcom,ipq5210 + - items: - enum: - qcom,ipq5332-ap-mi01.2 @@ -326,8 +357,10 @@ properties: - items: - enum: - qcom,ipq9574-ap-al02-c2 + - qcom,ipq9574-ap-al02-c2-emmc - qcom,ipq9574-ap-al02-c6 - qcom,ipq9574-ap-al02-c7 + - qcom,ipq9574-ap-al02-c7-emmc - qcom,ipq9574-ap-al02-c8 - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 @@ -360,6 +393,7 @@ properties: - qcom,qcs6490-rb3gen2 - radxa,dragon-q6a - shift,otter + - thundercomm,minipc-g1iot - thundercomm,rubikpi3 - const: qcom,qcm6490 @@ -385,6 +419,7 @@ properties: - items: - enum: - acer,aspire1 + - ecs,liva-qc710 - qcom,sc7180-idp - const: qcom,sc7180 @@ -882,6 +917,7 @@ properties: - items: - enum: + - arduino,monza - qcom,monaco-evk - qcom,qcs8300-ride - const: qcom,qcs8300 @@ -889,6 +925,7 @@ properties: - items: - enum: - qcom,qcs615-ride + - qcom,talos-evk - const: qcom,qcs615 - const: qcom,sm6150 @@ -972,6 +1009,7 @@ properties: - sony,pdx201 - xiaomi,ginkgo - xiaomi,laurel-sprout + - xiaomi,willow - const: qcom,sm6125 - items: @@ -1063,6 +1101,7 @@ properties: - items: - enum: + - ayaneo,pocket-s2 - qcom,sm8650-hdk - qcom,sm8650-mtp - qcom,sm8650-qrd @@ -1110,6 +1149,7 @@ properties: - dell,xps13-9345 - hp,elitebook-ultra-g1q - hp,omnibook-x14 + - lenovo,ideacentre-mini-01q8x10 - lenovo,yoga-slim7x - microsoft,romulus13 - microsoft,romulus15 @@ -1128,6 +1168,12 @@ properties: - const: microsoft,denali - const: qcom,x1e80100 + - items: + - enum: + - qcom,purwa-iot-evk + - const: qcom,purwa-iot-som + - const: qcom,x1p42100 + - items: - enum: - asus,zenbook-a14-ux3407qa-lcd @@ -1137,6 +1183,7 @@ properties: - items: - enum: + - asus,vivobook-s15-x1p4 - hp,omnibook-x14-fe1 - lenovo,thinkbook-16 - qcom,x1p42100-crd diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ae77ded9fe47..1a9dde18626d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -754,6 +754,11 @@ properties: - const: khadas,edge2 - const: rockchip,rk3588s + - description: Khadas Edge-2L series boards + items: + - const: khadas,edge-2l + - const: rockchip,rk3576 + - description: Kobol Helios64 items: - const: kobol,helios64 @@ -808,11 +813,22 @@ properties: - const: netxeon,r89 - const: rockchip,rk3288 + - description: Onion Omega4 Evaluation board + items: + - const: onion,omega4-evb + - const: onion,omega4 + - const: rockchip,rv1103b + - description: OPEN AI LAB EAIDK-610 items: - const: openailab,eaidk-610 - const: rockchip,rk3399 + - description: OneThing Edge Cube series + items: + - const: onething,edge-cube + - const: rockchip,rk3566 + - description: Xunlong Orange Pi RK3399 board items: - const: xunlong,rk3399-orangepi @@ -1187,7 +1203,9 @@ properties: - description: Rockchip RK3576 Evaluation board items: - - const: rockchip,rk3576-evb1-v10 + - enum: + - rockchip,rk3576-evb1-v10 + - rockchip,rk3576-evb2-v10 - const: rockchip,rk3576 - description: Rockchip RK3588 Evaluation board diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index f8e20e602c20..753b3ba1b607 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -117,6 +117,7 @@ properties: - description: Exynos5250 based boards items: - enum: + - google,manta # Google Manta (Nexus 10) - google,snow-rev5 # Google Snow Rev 5+ - google,spring # Google Spring - insignal,arndale # Insignal Arndale @@ -216,7 +217,9 @@ properties: items: - enum: - samsung,a2corelte # Samsung Galaxy A2 Core + - samsung,j5y17lte # Samsung Galaxy J5 (2017) - samsung,j6lte # Samsung Galaxy J6 + - samsung,j7xelte # Samsung Galaxy J7 (2016) - samsung,on7xelte # Samsung Galaxy J7 Prime - const: samsung,exynos7870 diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index ad144c02eb7e..c6af3a46364f 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -183,10 +183,12 @@ properties: - const: seeed,stm32mp157c-odyssey-som - const: st,stm32mp157 - - description: Phytec STM32MP1 SoM based Boards + - description: Phytec STM32MP157 SoM based Boards items: - - const: phytec,phycore-stm32mp1-3 - - const: phytec,phycore-stm32mp157c-som + - enum: + - phytec,phycore-stm32mp1-3 # phyBOARD-Sargas with phyCORE-STM32MP157C SoM + - enum: + - phytec,phycore-stm32mp157c-som # phyCORE-STM32MP157C SoM - const: st,stm32mp157 - description: Ultratronik STM32MP1 SBC based Boards diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 9e4627f97d7e..e6443c266fa1 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -901,6 +901,11 @@ properties: - const: allwinner,sl631 - const: allwinner,sun8i-v3 + - description: TaiqiCat A01 + items: + - const: ultrapower,taiqicat-a01 + - const: allwinner,sun50i-h6 + - description: Tanix TX1 items: - const: oranth,tanix-tx1 diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 85deda6d4292..2a6a9441c23d 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -79,6 +79,7 @@ properties: - toradex,verdin-am62-nonwifi-ivy # Verdin AM62 Module on Ivy - toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow - toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia + - toradex,verdin-am62-nonwifi-zinnia # Verdin AM62 Module on Zinnia - const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT - const: toradex,verdin-am62 # Verdin AM62 Module - const: ti,am625 @@ -91,6 +92,7 @@ properties: - toradex,verdin-am62-wifi-ivy # Verdin AM62 Wi-Fi / BT Module on Ivy - toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow - toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia + - toradex,verdin-am62-wifi-zinnia # Verdin AM62 Wi-Fi / BT Module on Zinnia - const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module - const: toradex,verdin-am62 # Verdin AM62 Module - const: ti,am625 @@ -103,6 +105,7 @@ properties: - toradex,verdin-am62p-nonwifi-ivy # Verdin AM62P Module on Ivy - toradex,verdin-am62p-nonwifi-mallow # Verdin AM62P Module on Mallow - toradex,verdin-am62p-nonwifi-yavia # Verdin AM62P Module on Yavia + - toradex,verdin-am62p-nonwifi-zinnia # Verdin AM62P Module on Zinnia - const: toradex,verdin-am62p-nonwifi # Verdin AM62P Module without Wi-Fi / BT - const: toradex,verdin-am62p # Verdin AM62P Module - const: ti,am62p5 @@ -115,6 +118,7 @@ properties: - toradex,verdin-am62p-wifi-ivy # Verdin AM62P Wi-Fi / BT Module on Ivy - toradex,verdin-am62p-wifi-mallow # Verdin AM62P Wi-Fi / BT Module on Mallow - toradex,verdin-am62p-wifi-yavia # Verdin AM62P Wi-Fi / BT Module on Yavia + - toradex,verdin-am62p-wifi-zinnia # Verdin AM62P Wi-Fi / BT Module on Zinnia - const: toradex,verdin-am62p-wifi # Verdin AM62P Wi-Fi / BT Module - const: toradex,verdin-am62p # Verdin AM62P Module - const: ti,am62p5 @@ -208,7 +212,6 @@ properties: items: - enum: - beagle,am67a-beagley-ai - - kontron,sa67 # Kontron SMARC-sAM67 board - ti,j722s-evm - const: ti,j722s diff --git a/Documentation/devicetree/bindings/arm/ti/omap.yaml b/Documentation/devicetree/bindings/arm/ti/omap.yaml index 14f1b9d8f59d..f694dcbf2348 100644 --- a/Documentation/devicetree/bindings/arm/ti/omap.yaml +++ b/Documentation/devicetree/bindings/arm/ti/omap.yaml @@ -144,6 +144,8 @@ properties: - motorola,droid-bionic # Motorola Droid Bionic XT875 - motorola,xyboard-mz609 - motorola,xyboard-mz617 + - samsung,espresso7 + - samsung,espresso10 - ti,omap4-panda - ti,omap4-sdp - const: ti,omap4430 diff --git a/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml b/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml new file mode 100644 index 000000000000..63442b91e7ac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC-9 SoC clock controller + +maintainers: + - Jesper Nilsson + +description: | + ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit) + units, generating clocks for different domains. Those CMU units are modeled + as separate device tree nodes, and might depend on each other. + The root clock in that root tree is an external clock: OSCCLK (25 MHz). + This external clock must be defined as a fixed-rate clock in dts. + + CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and + dividers, all other clocks of function blocks (other CMUs) are usually + derived from CMU_CMU. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/axis,artpec9-clk.h' header. + +properties: + compatible: + enum: + - axis,artpec9-cmu-cmu + - axis,artpec9-cmu-bus + - axis,artpec9-cmu-core + - axis,artpec9-cmu-cpucl + - axis,artpec9-cmu-fsys0 + - axis,artpec9-cmu-fsys1 + - axis,artpec9-cmu-imem + - axis,artpec9-cmu-peri + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + const: axis,artpec9-cmu-cmu + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + const: axis,artpec9-cmu-bus + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_BUS bus clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: bus + + - if: + properties: + compatible: + const: axis,artpec9-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CORE main clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: main + + - if: + properties: + compatible: + const: axis,artpec9-cmu-cpucl + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CPUCL switch clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: switch + + - if: + properties: + compatible: + const: axis,artpec9-cmu-fsys0 + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_FSYS0 bus clock (from CMU_CMU) + - description: CMU_FSYS0 IP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: bus + - const: ip + + - if: + properties: + compatible: + const: axis,artpec9-cmu-fsys1 + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_FSYS1 scan0 clock (from CMU_CMU) + - description: CMU_FSYS1 scan1 clock (from CMU_CMU) + - description: CMU_FSYS1 bus clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: scan0 + - const: scan1 + - const: bus + + - if: + properties: + compatible: + const: axis,artpec9-cmu-imem + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_IMEM ACLK clock (from CMU_CMU) + - description: CMU_IMEM CA5 clock (from CMU_CMU) + - description: CMU_IMEM JPEG clock (from CMU_CMU) + - description: CMU_IMEM SSS clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: aclk + - const: ca5 + - const: jpeg + - const: sss + + - if: + properties: + compatible: + const: axis,artpec9-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_PERI IP clock (from CMU_CMU) + - description: CMU_PERI DISP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: ip + - const: disp + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS1 + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + cmu_fsys1: clock-controller@14c10000 { + compatible = "axis,artpec9-cmu-fsys1"; + reg = <0x0 0x14c10000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>; + clock-names = "fin_pll", "scan0", "scan1", "bus"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml new file mode 100644 index 000000000000..f1cc3fc19085 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5210 + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5210 + + See also: + include/dt-bindings/clock/qcom,ipq5210-gcc.h + include/dt-bindings/reset/qcom,ipq5210-gcc.h + +properties: + compatible: + const: qcom,ipq5210-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: USB3 PHY pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq5210-gcc"; + reg = <0x01800000 0x40000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml index cf244c155f9a..60f1c8ca2c13 100644 --- a/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,milos-gcc.yaml @@ -8,16 +8,21 @@ title: Qualcomm Global Clock & Reset Controller on Milos maintainers: - Luca Weiss + - Taniya Das description: | Qualcomm global clock control module provides the clocks, resets and power domains on Milos. - See also: include/dt-bindings/clock/qcom,milos-gcc.h + See also: + - include/dt-bindings/clock/qcom,eliza-gcc.h + - include/dt-bindings/clock/qcom,milos-gcc.h properties: compatible: - const: qcom,milos-gcc + enum: + - qcom,eliza-gcc + - qcom,milos-gcc clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 3f5f1336262e..9690169baa46 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: enum: + - qcom,eliza-rpmh-clk - qcom,glymur-rpmh-clk - qcom,kaanapali-rpmh-clk - qcom,milos-rpmh-clk diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 784fef830681..ae9aef0e54e8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -15,6 +15,7 @@ description: | power domains on SM8550 See also: + - include/dt-bindings/clock/qcom,eliza-tcsr.h - include/dt-bindings/clock/qcom,glymur-tcsr.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h @@ -24,6 +25,7 @@ properties: compatible: items: - enum: + - qcom,eliza-tcsr - qcom,glymur-tcsr - qcom,kaanapali-tcsr - qcom,milos-tcsr diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index 8c18616e5c4d..c0ce687d83ee 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -28,19 +28,30 @@ properties: - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L - renesas,r9a08g045-cpg # RZ/G3S + - renesas,r9a08g046-cpg # RZ/G3L - renesas,r9a09g011-cpg # RZ/V2M reg: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Clock source to CPG can be either from external clock + input (EXCLK) or crystal oscillator (XIN/XOUT). + - description: ETH0 TXC clock input + - description: ETH0 RXC clock input + - description: ETH1 TXC clock input + - description: ETH1 RXC clock input clock-names: - description: - Clock source to CPG can be either from external clock input (EXCLK) or - crystal oscillator (XIN/XOUT). - const: extal + minItems: 1 + items: + - const: extal + - const: eth0_txc_tx_clk + - const: eth0_rxc_rx_clk + - const: eth1_txc_tx_clk + - const: eth1_rxc_rx_clk '#clock-cells': description: | @@ -74,6 +85,25 @@ required: - '#power-domain-cells' - '#reset-cells' +allOf: + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-cpg + then: + properties: + clocks: + minItems: 5 + clock-names: + minItems: 5 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml index 04b0a5c51e4e..b6d3a04be8f1 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - rockchip,rv1103b-cru - rockchip,rv1126b-cru reg: diff --git a/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml index a77e67f6cb82..0b752f3baaa9 100644 --- a/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml @@ -16,12 +16,7 @@ description: | properties: compatible: - oneOf: - - items: - - enum: - - kontron,sa67mcu - - const: kontron,sl28cpld - - const: kontron,sl28cpld + const: kontron,sl28cpld reg: description: diff --git a/Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml new file mode 100644 index 000000000000..9a926a97e7bf --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,eliza-rpmh.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,eliza-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Eliza SoC + +maintainers: + - Odelu Kukatla + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,eliza-rpmh.h + +properties: + compatible: + enum: + - qcom,eliza-aggre1-noc + - qcom,eliza-aggre2-noc + - qcom,eliza-clk-virt + - qcom,eliza-cnoc-cfg + - qcom,eliza-cnoc-main + - qcom,eliza-gem-noc + - qcom,eliza-lpass-ag-noc + - qcom,eliza-lpass-lpiaon-noc + - qcom,eliza-lpass-lpicx-noc + - qcom,eliza-mc-virt + - qcom,eliza-mmss-noc + - qcom,eliza-nsp-noc + - qcom,eliza-pcie-anoc + - qcom,eliza-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-clk-virt + - qcom,eliza-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-aggre1-noc + - qcom,eliza-aggre2-noc + - qcom,eliza-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + gem_noc: interconnect@24100000 { + compatible = "qcom,eliza-gem-noc"; + reg = <0x24100000 0x163080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-2 { + compatible = "qcom,eliza-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,eliza-aggre1-noc"; + reg = <0x16e0000 0x16400>; + #interconnect-cells = <2>; + clocks = <&gcc_phy_axi_clk>, <&gcc_prim_axi_clk>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 4b9b98fbe8f2..6182599eb3c1 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -28,6 +28,7 @@ properties: - const: qcom,osm-l3 - items: - enum: + - qcom,eliza-epss-l3 - qcom,sa8775p-epss-l3 - qcom,sc7280-epss-l3 - qcom,sc8280xp-epss-l3 diff --git a/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml b/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml index 760cb336dccb..0b73fe5b662f 100644 --- a/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml +++ b/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml @@ -21,6 +21,7 @@ properties: - enum: - allwinner,sun20i-d1-ledc - allwinner,sun50i-r329-ledc + - allwinner,sun55i-a523-ledc - const: allwinner,sun50i-a100-ledc reg: diff --git a/Documentation/devicetree/bindings/npu/arm,ethos.yaml b/Documentation/devicetree/bindings/npu/arm,ethos.yaml index 716c4997f976..d5a1fae4db9d 100644 --- a/Documentation/devicetree/bindings/npu/arm,ethos.yaml +++ b/Documentation/devicetree/bindings/npu/arm,ethos.yaml @@ -30,7 +30,7 @@ properties: - fsl,imx93-npu - const: arm,ethos-u65 - items: - - {} + - const: arm,corstone1000-ethos-u85 - const: arm,ethos-u85 reg: diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml new file mode 100644 index 000000000000..dc4f8725c9f5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 PCIe controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra264-pcie + + reg: + description: | + Of the six PCIe controllers found on Tegra264, one (C0) is used for the + internal GPU and the other five (C1-C5) are routed to connectors such as + PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1 + through C5, but not for C0. + minItems: 4 + items: + - description: ECAM-compatible configuration space + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: data link/physical layer registers (not available on C0) + + reg-names: + minItems: 4 + items: + - const: ecam + - const: xal + - const: xtl + - const: xtl-pri + - const: xpl + + interrupts: + minItems: 1 + maxItems: 4 + + dma-coherent: true + + nvidia,bpmp: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Must contain a pair of phandle (to the BPMP controller node) and + controller ID. The following are the controller IDs for each controller: + + 0: C0 + 1: C1 + 2: C2 + 3: C3 + 4: C4 + 5: C5 + items: + - items: + - description: phandle to the BPMP controller node + - description: PCIe controller ID + maximum: 5 + +required: + - interrupt-map + - interrupt-map-mask + - iommu-map + - msi-map + - nvidia,bpmp + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pci@c000000 { + compatible = "nvidia,tegra264-pcie"; + reg = <0xd0 0xb0000000 0x0 0x10000000>, + <0x00 0x0c000000 0x0 0x00004000>, + <0x00 0x0c004000 0x0 0x00001000>, + <0x00 0x0c005000 0x0 0x00001000>; + reg-names = "ecam", "xal", "xtl", "xtl-pri"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0x00>; + #interrupt-cells = <0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>; + + iommu-map = <0x0 &smmu2 0x10000 0x10000>; + msi-map = <0x0 &its 0x210000 0x10000>; + dma-coherent; + + ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, + <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, + <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; + bus-range = <0x0 0xff>; + + nvidia,bpmp = <&bpmp 0>; + }; + }; + + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pci@8400000 { + compatible = "nvidia,tegra264-pcie"; + reg = <0xa8 0xb0000000 0x0 0x10000000>, + <0x00 0x08400000 0x0 0x00004000>, + <0x00 0x08404000 0x0 0x00001000>, + <0x00 0x08405000 0x0 0x00001000>, + <0x00 0x08410000 0x0 0x00010000>; + reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0x01>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>; + + iommu-map = <0x0 &smmu1 0x10000 0x10000>; + msi-map = <0x0 &its 0x110000 0x10000>; + dma-coherent; + + ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>, + <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, + <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; + bus-range = <0x00 0xff>; + + nvidia,bpmp = <&bpmp 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index c6ec9290fe07..2b0a8a93bb21 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -262,6 +262,23 @@ properties: ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated to ratified state.") + - const: supm + description: | + The standard Supm extension for pointer masking support in user + mode (U-mode) as ratified at commit d70011dde6c2 ("Update to + ratified state") of riscv-j-extension. + + Supm represents a combination of underlying hardware capability + (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode + software configuration that enables pointer masking for U-mode. + + DO NOT include this property in device trees targeting privileged + system software (S-mode or M-mode). + + This property is only appropriate in device trees provided to + U-mode software where the next-higher-privilege-mode supports + Smnpm or Ssnpm and enables it for U-mode. + - const: svade description: | The standard Svade supervisor-level extension for SW-managed PTE A/D @@ -907,6 +924,16 @@ properties: then: contains: const: b + # Supm depends on Smnpm or Ssnpm + - if: + contains: + const: supm + then: + oneOf: + - contains: + const: smnpm + - contains: + const: ssnpm # Za64rs and Ziccrse depend on Zalrsc or A - if: contains: diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 381d6eb6672e..137a6f413430 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/riscv/microchip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Microchip PolarFire SoC-based boards +title: Microchip SoC-based boards maintainers: - Conor Dooley - Daire McNamara description: - Microchip PolarFire SoC-based boards + Microchip SoC-based boards properties: $nodename: @@ -46,6 +46,9 @@ properties: - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs + - items: + - const: microchip,pic64gx-curiosity-kit + - const: microchip,pic64gx additionalProperties: true diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index 73851f19330d..e9e07c2356bc 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -63,7 +63,9 @@ allOf: properties: compatible: contains: - const: spacemit,k1-uart + enum: + - spacemit,k1-uart + - spacemit,k3-uart then: properties: clock-names: @@ -76,6 +78,7 @@ allOf: contains: enum: - spacemit,k1-uart + - spacemit,k3-uart - nxp,lpc1850-uart then: required: diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 0b8e3294c83e..2cc43742b8e3 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -63,6 +63,7 @@ properties: - rockchip,rk3588-vo0-grf - rockchip,rk3588-vo1-grf - rockchip,rk3588-vop-grf + - rockchip,rv1103b-ioc - rockchip,rv1108-usbgrf - const: syscon - items: @@ -98,6 +99,7 @@ properties: - rockchip,rk3576-pmu0-grf - rockchip,rk3576-usb2phy-grf - rockchip,rk3588-usb2phy-grf + - rockchip,rv1103b-pmu-grf - rockchip,rv1108-grf - rockchip,rv1108-pmugrf - rockchip,rv1126-grf @@ -231,6 +233,7 @@ allOf: - rockchip,rk3036-grf - rockchip,rk3308-grf - rockchip,rk3368-pmugrf + - rockchip,rv1103b-pmu-grf then: properties: diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3bab40500df9..3c16b260db04 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -31,6 +31,7 @@ properties: - enum: - canaan,k210-clint # Canaan Kendryte K210 - eswin,eic7700-clint # ESWIN EIC7700 + - microchip,pic64gx-clint # Microchip PIC64GX - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 - spacemit,k3-clint # SpacemiT K3 diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 00bffb9c4469..6339988e3805 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -223,6 +223,8 @@ patternProperties: description: Axiado Corporation "^axis,.*": description: Axis Communications AB + "^ayaneo,.*": + description: Anyun Intelligent Technology (Hong Kong) Co., Ltd "^azoteq,.*": description: Azoteq (Pty) Ltd "^azw,.*": @@ -1207,6 +1209,8 @@ patternProperties: description: One Laptop Per Child "^oneplus,.*": description: OnePlus Technology (Shenzhen) Co., Ltd. + "^onething,.*": + description: Shenzhen OneThing Technologies Co., Ltd. "^onie,.*": description: Open Network Install Environment group "^onion,.*": @@ -1741,6 +1745,8 @@ patternProperties: description: Ufi Space Co., Ltd. "^ugoos,.*": description: Ugoos Industrial Co., Ltd. + "^ultrapower,.*": + description: Beijing Ultrapower Software Co., Ltd. "^uni-t,.*": description: Uni-Trend Technology (China) Co., Ltd. "^uniwest,.*": @@ -1833,6 +1839,8 @@ patternProperties: description: Wi2Wi, Inc. "^widora,.*": description: Beijing Widora Technology Co., Ltd. + "^wiko,.*": + description: Wiko SAS "^wiligear,.*": description: Wiligear, Ltd. "^willsemi,.*": diff --git a/MAINTAINERS b/MAINTAINERS index 387d150a6f7f..ea12aaf625a7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2990,7 +2990,6 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/ F: arch/arm/boot/dts/marvell/armada* -F: arch/arm/boot/dts/marvell/db-falcon* F: arch/arm/boot/dts/marvell/kirkwood* F: arch/arm/configs/mvebu_*_defconfig F: arch/arm/mach-mvebu/ diff --git a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi index 16f784da5a55..ae370d4eb9d8 100644 --- a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi @@ -234,7 +234,7 @@ oscclk0: clock-controller@c { reg = <0x0c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; - vco-offset = <0x0C>; + vco-offset = <0x0c>; clocks = <&xtal24mhz>; }; oscclk1: clock-controller@10 { diff --git a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts index b9b10cbd65aa..a75d8b107fe1 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts @@ -260,7 +260,7 @@ oscclk0: clock-controller@c { reg = <0x0c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; - vco-offset = <0x0C>; + vco-offset = <0x0c>; clocks = <&xtal24mhz>; }; oscclk1: clock-controller@10 { diff --git a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts index db1b6793cd2c..59c78def83f2 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts @@ -343,7 +343,7 @@ oscclk0: clock-controller@c { reg = <0x0c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; - vco-offset = <0x0C>; + vco-offset = <0x0c>; clocks = <&xtal24mhz>; }; oscclk1: clock-controller@10 { diff --git a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi index e625403a9456..0d3d96ffa6e6 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi @@ -256,7 +256,7 @@ oscclk0: clock-controller@c { reg = <0x0c 0x04>; #clock-cells = <0>; lock-offset = <0x20>; - vco-offset = <0x0C>; + vco-offset = <0x0c>; clocks = <&xtal24mhz>; }; oscclk1: clock-controller@10 { diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 20e5b64280a5..767f7c7652d5 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -12,9 +12,11 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-asrock-altrad8.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-asrock-e3c256d4i.dtb \ + aspeed-bmc-asrock-paul-ipmi-card.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ aspeed-bmc-asrock-spc621d8hm3.dtb \ aspeed-bmc-asrock-x570d4u.dtb \ + aspeed-bmc-asus-kommando-ipmi-card.dtb \ aspeed-bmc-asus-x4tf.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-delta-ahe50dc.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-paul-ipmi-card.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-paul-ipmi-card.dts new file mode 100644 index 000000000000..f74f8fee9e1e --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-paul-ipmi-card.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2025 Anirudh Srinivasan + +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include + +/{ + model = "ASRock Paul IPMI Card"; + compatible = "asrock,ast2500-paul-ipmi-card", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + }; + + leds { + compatible = "gpio-leds"; + + led-fan-1 { + gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; + label = "fan1_red"; + default-state = "off"; + }; + + led-fan-2 { + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; + label = "fan2_red"; + default-state = "off"; + }; + + led-fault { + gpios = <&gpio ASPEED_GPIO(Y, 3) GPIO_ACTIVE_LOW>; + label = "panic_red"; + panic-indicator; + default-state = "off"; + }; + + led-heartbeat { + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + label = "heartbeat_green"; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: video { + size = <0x02000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; /* 50 MHz */ +#include "openbmc-flash-layout.dtsi" + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "", "", "", "", "", "", "", "", + /* B */ "", "", "", "", "", "", "", "", + /* C */ "", "", "", "", "", "", "", "", + /* D */ "", "BMC_PWRBTN", "", "BMC_RESETCON", "", "", "", "", + /* E */ "", "", "", "", "", "", "", "", + /* F */ "", "", "", "", "", "", "", "", + /* G */ "", "", "", "", "", "", "", "", + /* H */ "", "", "", "", "", "", "BMC_LED1", "", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "", "", "", "", "", "", "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "", "", "", "", "", "", "", "", + /* M */ "", "", "", "", "", "", "", "", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "", "", "", "", "", "", "", "", + /* Q */ "", "", "", "", "", "", "", "", + /* R */ "", "", "", "", "", "", "", "", + /* S */ "", "", "", "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "", "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "PCIE_STNDBY", "", "", + /* Y */ "", "", "", "SYSTEM_ERR_LED", "", "", "", "", + /* Z */ "", "", "", "", "", "", "", "", + /* AA */ "FAN_1_LED", "FAN_2_LED", "", "", "", "", "", "", + /* AB */ "", "", "", "", "", "", "", "", + /* AC */ "", "", "", "", "", "", "", ""; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts new file mode 100644 index 000000000000..ab7ad320067c --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asus-kommando-ipmi-card.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2025 Anirudh Srinivasan + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include "aspeed-g6-pinctrl.dtsi" +#include + +/ { + model = "Asus Kommando IPMI Expansion Card"; + compatible = "asus,ast2600-kommando-ipmi-card", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = "serial4:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-fault { + gpios = <&gpio1 ASPEED_GPIO(C, 5) GPIO_ACTIVE_HIGH>; + label = "panic_amber"; + panic-indicator; + default-state = "off"; + }; + + led-heartbeat { + gpios = <&gpio0 ASPEED_GPIO(A, 7) GPIO_ACTIVE_LOW>; + label = "heartbeat_green"; + linux,default-trigger = "timer"; + }; + + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&gpio0 { + gpio-line-names = + /*A0 0*/ "", "", "", "", "", "", "", "BMC_HBLED", + /*B0 8*/ "", "", "", "", "", "", "", "", + /*C0 16*/ "", "", "", "", "", "", "", "", + /*D0 24*/ "", "", "", "", "", "", "", "", + /*E0 32*/ "", "", "", "", "", "", "", "", + /*F0 40*/ "", "", "", "", "", "", "", "", + /*G0 48*/ "", "", "", "", "", "", "", "", + /*H0 56*/ "", "", "", "", "", "", "", "", + /*I0 64*/ "", "", "", "BMC_RSTBTN", "", "", "", "", + /*J0 72*/ "", "", "", "", "", "", "", "", + /*K0 80*/ "", "", "", "", "", "", "", "", + /*L0 88*/ "", "", "", "", "", "", "", "", + /*M0 96*/ "", "", "", "", "", "", "", "", + /*N0 104*/ "", "", "", "", "", "", "", "", + /*O0 112*/ "", "", "", "", "", "", "", "", + /*P0 120*/ "", "", "", "", "", "", "", "", + /*Q0 128*/ "", "", "", "", "", "", "", "", + /*R0 136*/ "", "", "", "", "", "", "", "", + /*S0 144*/ "", "", "", "", "", "", "", "", + /*T0 152*/ "", "", "", "", "", "", "", "", + /*U0 160*/ "", "", "", "", "", "", "", "", + /*V0 168*/ "", "", "", "", "BMC_PWRBTN", "", "MB_S0_DETECT", "", + /*W0 176*/ "", "", "", "", "", "", "", "", + /*X0 184*/ "", "", "", "", "", "", "", "", + /*Y0 192*/ "", "", "", "", "", "", "", "", + /*Z0 200*/ "", "", "", "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /*18A0 0*/ "","","","","","","","", + /*18B0 8*/ "","","","","","","","", + /*18C0 16*/ "","","","","","BMC_MLED","","", + /*18D0 24*/ "","","","","","","","", + /*18E0 32*/ "","","","","","","",""; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 221af858cb6b..2cb7bd128d24 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -300,6 +300,12 @@ &gpio1 { &i2c0 { status = "okay"; + eeprom@50 { + compatible = "atmel,24c2048"; + reg = <0x50>; + pagesize = <128>; + }; + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; @@ -334,6 +340,12 @@ i2c0mux0ch3: i2c@3 { &i2c1 { status = "okay"; + eeprom@50 { + compatible = "atmel,24c2048"; + reg = <0x50>; + pagesize = <128>; + }; + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; @@ -802,6 +814,16 @@ i2c13mux0ch7: i2c@7 { reg = <7>; #address-cells = <1>; #size-cells = <0>; + + nfc@28 { + compatible = "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&sgpiom0>; + interrupts = <156 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>; + }; }; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts index 44f95a3986cb..a12d4164de4a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts @@ -67,6 +67,7 @@ flash@1 { spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; status = "okay"; + #include "openbmc-flash-layout-128-alt.dtsi" }; }; diff --git a/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128-alt.dtsi b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128-alt.dtsi new file mode 100644 index 000000000000..08ce2eab472c --- /dev/null +++ b/arch/arm/boot/dts/aspeed/openbmc-flash-layout-128-alt.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "alt-u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "alt-u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "alt-kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x5600000>; // 86MB + label = "alt-rofs"; + }; + + rwfs@6000000 { + reg = <0x6000000 0x2000000>; // 32MB + label = "alt-rwfs"; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi index d0d5f7e52a91..392a25713669 100644 --- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi @@ -95,7 +95,10 @@ L2: cache-controller@22000 { axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; + ranges = <0x00000000 0x18000000 0x00100000>, + <0x08000000 0x08000000 0x08000000>, + <0x20000000 0x20000000 0x08000000>, + <0x28000000 0x28000000 0x08000000>; #address-cells = <1>; #size-cells = <1>; @@ -182,24 +185,75 @@ chipcommon: chipcommon@0 { }; pcie0: pcie@12000 { + compatible = "brcm,iproc-pcie"; reg = <0x00012000 0x1000>; + ranges = <0x82000000 0 0x08000000 0x08000000 0 0x08000000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + device_type = "pci"; + #interrupt-cells = <1>; #address-cells = <3>; #size-cells = <2>; + + pcie_bridge0: pcie@0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1: pcie@13000 { + compatible = "brcm,iproc-pcie"; reg = <0x00013000 0x1000>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x08000000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + device_type = "pci"; + #interrupt-cells = <1>; #address-cells = <3>; #size-cells = <2>; + + pcie_bridge1: pcie@0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2: pcie@14000 { + compatible = "brcm,iproc-pcie"; reg = <0x00014000 0x1000>; + ranges = <0x82000000 0 0x28000000 0x28000000 0 0x08000000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + device_type = "pci"; + #interrupt-cells = <1>; #address-cells = <3>; #size-cells = <2>; + + pcie_bridge2: pcie@0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + bus-range = <0x00 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; usb2: usb2@21000 { @@ -479,7 +533,7 @@ thermal: thermal@2c0 { }; nand_controller: nand-controller@18028000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; reg-names = "nand", "iproc-idm", "iproc-ext"; interrupts = ; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi index 9261b67dbee1..1e76b290510d 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi @@ -141,9 +141,10 @@ v3d: v3d@7ec00000 { interrupts = <1 10>; }; - vc4: gpu { - compatible = "brcm,bcm2835-vc4"; - }; + }; + + vc4: gpu { + compatible = "brcm,bcm2835-vc4"; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi index e9bf41b9f5c1..46c91468f4c5 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi @@ -1,8 +1,8 @@ #include / { - soc { - firmware: firmware { + firmware { + firmware: rpi-firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; mboxes = <&mailbox>; @@ -10,14 +10,16 @@ firmware_clocks: clocks { compatible = "raspberrypi,firmware-clocks"; #clock-cells = <1>; }; - }; - power: power { - compatible = "raspberrypi,bcm2835-power"; - firmware = <&firmware>; - #power-domain-cells = <1>; + power: power { + compatible = "raspberrypi,bcm2835-power"; + firmware = <&firmware>; + #power-domain-cells = <1>; + }; }; + }; + soc { vchiq: mailbox@7e00b840 { compatible = "brcm,bcm2835-vchiq"; reg = <0x7e00b840 0x3c>; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts index 2ba5adf2b7e7..5bbc2ba0f959 100644 --- a/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-linksys-ea9200.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include + #include "bcm4709.dtsi" #include "bcm5301x-nand-cs0-bch8.dtsi" @@ -25,6 +27,10 @@ memory@0 { nvram@1c080000 { compatible = "brcm,nvram"; reg = <0x1c080000 0x180000>; + + et2macaddr: et2macaddr { + #nvmem-cell-cells = <1>; + }; }; gpio-keys { @@ -36,18 +42,69 @@ button-wps { gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; + button-rfkill { + label = "WiFi"; + linux,code = ; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + button-restart { label = "Reset"; linux,code = ; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; }; }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "rfkill-none"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_USB; + function-enumerator = <2>; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&ohci_port2>, <&ehci_port2>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_USB; + function-enumerator = <3>; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&ohci_port1>, <&ehci_port1>, + <&xhci_port1>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; }; &usb3_phy { status = "okay"; }; +&usb2 { + vcc-gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; +}; + &srab { status = "okay"; @@ -70,6 +127,9 @@ port@3 { port@4 { label = "wan"; + + nvmem-cells = <&et2macaddr 1>; + nvmem-cell-names = "mac-address"; }; port@5 { @@ -85,3 +145,43 @@ port@8 { }; }; }; + +&nandcs { + partitions { + compatible = "linksys,ns-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x080000 0x0100000>; + }; + + partition@180000 { + label = "devinfo"; + reg = <0x0180000 0x080000>; + read-only; + }; + + partition@200000 { + reg = <0x0200000 0x02800000>; + compatible = "linksys,ns-firmware", "brcm,trx"; + }; + + partition@2a00000 { + reg = <0x02a00000 0x02800000>; + compatible = "linksys,ns-firmware", "brcm,trx"; + }; + + partition@5200000 { + label = "system"; + reg = <0x05200000 0x02e00000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts index 127ca8741220..d170c71cbd76 100644 --- a/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-netgear-r8000.dts @@ -126,66 +126,53 @@ button-brightness { }; }; -&pcie0 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0,0 { +&pcie_bridge0 { + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,1,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <5735000 5835000>; - brcm,ccode-map = "JP-JP-78", "US-Q2-86"; - }; + ieee80211-freq-limit = <5735000 5835000>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; }; }; -&pcie1 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@1,0,0 { +&pcie_bridge1 { + pcie@0,0 { + device_type = "pci"; reg = <0x0000 0 0 0 0>; + bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>; + ranges; - bridge@1,1,0 { - reg = <0x0000 0 0 0 0>; + pcie@1,0 { + device_type = "pci"; + reg = <0x800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + ranges; - bridge@1,0 { - reg = <0x800 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - brcm,ccode-map = "JP-JP-78", "US-Q2-86"; - }; + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; }; + }; - bridge@1,2,2 { - reg = <0x1000 0 0 0 0>; + pcie@2,0 { + device_type = "pci"; + reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges; - wifi@1,4,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - ieee80211-freq-limit = <5170000 5730000>; - brcm,ccode-map = "JP-JP-78", "US-Q2-86"; - }; + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5170000 5730000>; + brcm,ccode-map = "JP-JP-78", "US-Q2-86"; }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi index 2cfaaabc7a6a..2d2e7e581291 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi @@ -18,6 +18,10 @@ memory@0 { nvram@1c080000 { compatible = "brcm,nvram"; reg = <0x1c080000 0x00180000>; + + et0macaddr: et0macaddr { + #nvmem-cell-cells = <1>; + }; }; gpio-keys { @@ -143,6 +147,9 @@ port@3 { port@4 { label = "wan"; + + nvmem-cells = <&et0macaddr 1>; + nvmem-cell-names = "mac-address"; }; port@5 { diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts index 01ec8c03686a..8bf623c67de0 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts @@ -127,6 +127,9 @@ &srab { ports { port@0 { label = "wan"; + + nvmem-cells = <&et1macaddr 1>; + nvmem-cell-names = "mac-address"; }; port@1 { diff --git a/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts index 2b5c80d835e9..74161b76008a 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts @@ -25,6 +25,10 @@ memory@0 { nvram@1c080000 { compatible = "brcm,nvram"; reg = <0x1c080000 0x100000>; + + et2macaddr: et2macaddr { + #nvmem-cell-cells = <1>; + }; }; gpio-keys { @@ -230,6 +234,9 @@ port@3 { port@4 { label = "wan"; + + nvmem-cells = <&et2macaddr 1>; + nvmem-cell-names = "mac-address"; }; port@5 { diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts index badafa024d24..3a33705c2969 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts @@ -65,39 +65,19 @@ &gmac0 { }; -&pcie0 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0 { +&pcie_bridge0 { + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825"; - }; + brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825"; }; }; -&pcie1 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0 { +&pcie_bridge1 { + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825"; - }; + brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825"; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts index 83c429afc297..8e487f60a2cc 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts @@ -81,39 +81,19 @@ &gmac0 { nvmem-cell-names = "mac-address"; }; -&pcie0 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0 { +&pcie_bridge0 { + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930"; - }; + brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930"; }; }; -&pcie1 { - #address-cells = <3>; - #size-cells = <2>; - - bridge@0,0 { +&pcie_bridge1 { + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; reg = <0x0000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - - wifi@0,0 { - compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; - reg = <0x0000 0 0 0 0>; - brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930"; - }; + brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930"; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi index 4ec568586b14..5b084d61edd7 100644 --- a/arch/arm/boot/dts/broadcom/bcm63138.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi @@ -312,12 +312,21 @@ bootlut: bootlut@8000 { reg = <0x8000 0x50>; }; + i2c0: i2c@3e00 { + compatible = "brcm,brcmper-i2c"; + reg = <0x3e00 0x60>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pl081_dma: dma-controller@d000 { compatible = "arm,pl081", "arm,primecell"; // The magic B105F00D info is missing arm,primecell-periphid = <0x00041081>; reg = <0xd000 0x1000>; - interrupts = ; + interrupts = ; memcpy-burst-size = <256>; memcpy-bus-width = <32>; clocks = <&periph_clk>; diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi index e071cddb28fc..b2ddc2f583e1 100644 --- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi @@ -97,7 +97,7 @@ bus@ff800000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0xfffe8000 0x8000>; + ranges = <0 0xfffe8000 0x20000>; /* GPIOs 0 .. 31 */ gpio0: gpio@100 { @@ -197,5 +197,14 @@ nandcs: nand@0 { reg = <0>; }; }; + + i2c0: i2c@3e00 { + compatible = "brcm,brcmper-i2c"; + reg = <0x3e00 0x60>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi index f5591a45d2e4..47f177323c18 100644 --- a/arch/arm/boot/dts/broadcom/bcm6846.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi @@ -242,6 +242,15 @@ mdio: mdio@2060 { status = "disabled"; }; + i2c0: i2c@2100 { + compatible = "brcm,brcmper-i2c"; + reg = <0x2100 0x60>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pl081_dma: dma-controller@59000 { compatible = "arm,pl081", "arm,primecell"; // The magic B105F00D info is missing diff --git a/arch/arm/boot/dts/broadcom/bcm6855.dtsi b/arch/arm/boot/dts/broadcom/bcm6855.dtsi index a88c3f0fbcb0..b3c4cd24ce53 100644 --- a/arch/arm/boot/dts/broadcom/bcm6855.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6855.dtsi @@ -240,6 +240,15 @@ nandcs: nand@0 { }; }; + i2c0: i2c@2100 { + compatible = "brcm,brcmper-i2c"; + reg = <0x2100 0x60>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + leds: led-controller@3000 { #address-cells = <1>; #size-cells = <0>; @@ -278,5 +287,14 @@ uart1: serial@13000 { clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; + + i2c1: i2c@5a800 { + compatible = "brcm,brcmper-i2c"; + reg = <0x5a800 0x60>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi index dd837bf69390..e7fb45ae1d49 100644 --- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi @@ -239,12 +239,21 @@ nandcs: nand@0 { }; }; + i2c0: i2c@2100 { + compatible = "brcm,brcmper-i2c"; + reg = <0x2100 0x60>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pl081_dma: dma-controller@11000 { compatible = "arm,pl081", "arm,primecell"; // The magic B105F00D info is missing arm,primecell-periphid = <0x00041081>; reg = <0x11000 0x1000>; - interrupts = ; + interrupts = ; memcpy-burst-size = <256>; memcpy-bus-width = <32>; clocks = <&periph_clk>; diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index 4b1685b93989..71ac2b94c6ba 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -328,7 +328,7 @@ sysirq: interrupt-controller@10200100 { efuse: efuse@10206000 { compatible = "mediatek,mt7623-efuse", - "mediatek,mt8173-efuse"; + "mediatek,efuse"; reg = <0 0x10206000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi index b075865e6a76..e708b3df4ccd 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -75,8 +75,6 @@ ahb { ranges; usb0: gadget@500000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "microchip,sam9x60-udc"; reg = <0x00500000 0x100000 0xf803c000 0x400>; diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index e21556f46384..67253bbc08df 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -67,6 +67,11 @@ ns_sram: sram@100000 { #size-cells = <1>; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + }; + soc { compatible = "simple-bus"; ranges; @@ -278,6 +283,41 @@ sdmmc1: mmc@e1208000 { status = "disabled"; }; + xlcdc: lcd-controller@e1400000 { + compatible = "microchip,sama7d65-xlcdc"; + reg = <0xe1400000 0x2000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>, <&clk32k 1>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + status = "disabled"; + + display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pwm { + compatible = "atmel,hlcdc-pwm"; + #pwm-cells = <3>; + }; + }; + + lvdsc: lvds-controller@e1408000 { + compatible = "microchip,sama7d65-lvds", "microchip,sam9x75-lvds"; + reg = <0xe1408000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 104>; + clock-names = "pclk"; + status = "disabled"; + }; + aes: crypto@e1600000 { compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes"; reg = <0xe1600000 0x100>; diff --git a/arch/arm/boot/dts/nvidia/tegra114-tn7.dts b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts index bfbdb345575a..75fbafb4a872 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-tn7.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts @@ -43,7 +43,9 @@ panel@0 { compatible = "lg,ld070wx3-sl01"; reg = <0>; - power-supply = <&vdd_lcd>; + vdd-supply = <&avdd_lcd>; + vcc-supply = <&dvdd_lcd>; + backlight = <&backlight>; }; }; @@ -101,11 +103,10 @@ smps45 { regulator-boot-on; }; - smps6 { + avdd_lcd: smps6 { regulator-name = "va-lcd-hv"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; regulator-boot-on; }; @@ -325,7 +326,7 @@ lcd_bl_en: regulator-lcden { regulator-boot-on; }; - vdd_lcd: regulator-lcd { + dvdd_lcd: regulator-lcd { compatible = "regulator-fixed"; regulator-name = "VD_LCD_1V8"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index a98667641be2..7e8f90d33935 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra114"; @@ -258,6 +259,8 @@ tegra_car: clock@60006000 { reg = <0x60006000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + + nvidia,external-memory-controller = <&emc>; }; flow-controller@60007000 { @@ -311,6 +314,18 @@ ahb: ahb@6000c000 { reg = <0x6000c000 0x150>; }; + actmon: actmon@6000c800 { + compatible = "nvidia,tegra114-actmon"; + reg = <0x6000c800 0x400>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_ACTMON>, + <&tegra_car TEGRA114_CLK_EMC>; + clock-names = "actmon", "emc"; + resets = <&tegra_car TEGRA114_CLK_ACTMON>; + reset-names = "actmon"; + #cooling-cells = <2>; + }; + gpio: gpio@6000d000 { compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; @@ -642,6 +657,16 @@ mc: memory-controller@70019000 { #iommu-cells = <1>; }; + emc: external-memory-controller@7001b000 { + compatible = "nvidia,tegra114-emc"; + reg = <0x7001b000 0x800>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_EMC>; + clock-names = "emc"; + + nvidia,memory-controller = <&mc>; + }; + hda@70030000 { compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda"; reg = <0x70030000 0x10000>; @@ -751,6 +776,46 @@ tegra_i2s4: i2s@70080700 { }; }; + soctherm: thermal-sensor@700e2000 { + compatible = "nvidia,tegra114-soctherm"; + reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ + <0x60006000 0x400>; /* CAR reg_base */ + reg-names = "soctherm-reg", "car-reg"; + interrupts = , + ; + interrupt-names = "thermal", "edp"; + clocks = <&tegra_car TEGRA114_CLK_TSENSOR>, + <&tegra_car TEGRA114_CLK_SOC_THERM>; + clock-names = "tsensor", "soctherm"; + resets = <&tegra_car 78>; + reset-names = "soctherm"; + + assigned-clocks = <&tegra_car TEGRA114_CLK_TSENSOR>, + <&tegra_car TEGRA114_CLK_SOC_THERM>; + assigned-clock-rates = <500000>, <51000000>; + + assigned-clock-parents = <&tegra_car TEGRA114_CLK_CLK_M>, + <&tegra_car TEGRA114_CLK_PLL_P>; + + #thermal-sensor-cells = <1>; + + throttle-cfgs { + throttle_heavy: heavy { + nvidia,priority = <100>; + nvidia,cpu-throt-percent = <80>; + nvidia,gpu-throt-level = ; + #cooling-cells = <2>; + }; + + throttle_light: light { + nvidia,priority = <80>; + nvidia,cpu-throt-percent = <50>; + nvidia,gpu-throt-level = ; + #cooling-cells = <2>; + }; + }; + }; + mipi: mipi@700e3000 { compatible = "nvidia,tegra114-mipi"; reg = <0x700e3000 0x100>; @@ -921,24 +986,28 @@ cpu0: cpu@0 { clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; /* FIXME: what's the actual transition time? */ clock-latency = <300000>; + #cooling-cells = <2>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + #cooling-cells = <2>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <2>; + #cooling-cells = <2>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <3>; + #cooling-cells = <2>; }; }; @@ -951,6 +1020,158 @@ pmu { interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA114_SOCTHERM_SENSOR_CPU>; + + trips { + cpu-shutdown-trip { + temperature = <102000>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_throttle_trip: cpu-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + + cpu_balanced_trip: cpu-balanced-trip { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + + map1 { + trip = <&cpu_balanced_trip>; + cooling-device = <&throttle_light 1 1>; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA114_SOCTHERM_SENSOR_MEM>; + + trips { + mem-shutdown-trip { + temperature = <102000>; + hysteresis = <0>; + type = "critical"; + }; + + mem_throttle_trip: mem-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + + mem_balanced_trip: mem-balanced-trip { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + + gpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA114_SOCTHERM_SENSOR_GPU>; + + trips { + gpu-shutdown-trip { + temperature = <102000>; + hysteresis = <0>; + type = "critical"; + }; + + gpu_throttle_trip: gpu-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + + gpu_balanced_trip: gpu-balanced-trip { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + + map1 { + trip = <&gpu_balanced_trip>; + cooling-device = <&throttle_light 1 1>; + }; + }; + }; + + pllx-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA114_SOCTHERM_SENSOR_PLLX>; + + trips { + pllx-shutdown-trip { + temperature = <102000>; + hysteresis = <0>; + type = "critical"; + }; + + pllx_throttle_trip: pllx-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + + pllx_balanced_trip: pllx-balanced-trip { + temperature = <90000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + /* + * There are currently no cooling maps, + * because there are no cooling devices. + */ + }; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = diff --git a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts index 1408e1e00759..d1093ad569e6 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts @@ -706,6 +706,14 @@ vdd_pnl_reg: regulator-3v0 { enable-active-high; }; + rfkill { + compatible = "rfkill-gpio"; + label = "wifi_rfkill"; + radio-type = "wlan"; + reset-gpios = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>; + }; + sound { compatible = "nvidia,tegra-audio-alc5632-paz00", "nvidia,tegra-audio-alc5632"; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts index 5d9e23a43820..9296e7970ce4 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-tf600t.dts @@ -62,8 +62,11 @@ hdmi: hdmi@54280000 { pll-supply = <&vdd_1v8_vio>; vdd-supply = <&vdd_3v3_sys>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; - nvidia,ddc-i2c-bus = <&hdmi_ddc>; + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; }; }; @@ -2174,6 +2177,20 @@ clk32k_in: clock-32k { clock-output-names = "pmic-oscillator"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + hpd-gpios = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + ddc-i2c-bus = <&hdmi_ddc>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + cpus { cpu0: cpu@0 { cpu-supply = <&vdd_cpu>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts index c6ef0a20c19f..cc14e6dca770 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -116,6 +116,29 @@ rmi4-f11@11 { }; }; + spi@7000dc00 { + dsi@2 { + /* + * JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel + */ + panel@1 { + compatible = "jdi,dx12d100vm0eaa", "renesas,r69328"; + reg = <1>; + + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + vdd-supply = <&vcc_3v0_lcd>; + vddio-supply = <&iovcc_1v8_lcd>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + }; + }; + memory-controller@7000f000 { emc-timings-0 { /* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */ diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts index e32fafc7f5e0..414117fd4382 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts @@ -109,6 +109,39 @@ rmi4-f11@11 { syna,clip-x-high = <1535>; syna,clip-y-high = <2047>; }; + + rmi4-f1a@1a { + reg = <0x1a>; + + linux,keycodes = ; + }; + }; + }; + + spi@7000dc00 { + dsi@2 { + /* + * HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel + */ + panel@1 { + compatible = "koe,tx13d100vm0eaa", "renesas,r61307"; + reg = <1>; + + reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>; + + renesas,gamma = <3>; + renesas,column-inversion; + renesas,contrast; + + vcc-supply = <&vcc_3v0_lcd>; + iovcc-supply = <&iovcc_1v8_lcd>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi index 909260a5d0fb..768e201456d8 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi @@ -20,6 +20,8 @@ aliases { rtc0 = &pmic; rtc1 = "/rtc@7000e000"; + display0 = &lcd; + serial0 = &uartd; /* Console */ serial1 = &uartc; /* Bluetooth */ serial2 = &uartb; /* GPS */ @@ -71,6 +73,21 @@ trustzone@bfe00000 { }; }; + host1x@50000000 { + lcd: dc@54200000 { + rgb { + status = "okay"; + + port { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + vde@6001a000 { assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>; assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>; @@ -1053,6 +1070,38 @@ rmi4-f11@11 { syna,clip-y-low = <0>; }; }; + + max14526: muic@44 { + compatible = "maxim,max14526"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = ; + + muic_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + + muic_to_charger: endpoint@0 { + reg = <0>; + remote-endpoint = <&charger_input>; + }; + }; + }; + + tsc2007: adc@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + + ti,x-plate-ohms = <1>; + #io-channel-cells = <1>; + }; }; cam_i2c: i2c@7000c500 { @@ -1309,6 +1358,22 @@ ldo8 { }; }; + max8971: charger@35 { + compatible = "maxim,max8971"; + reg = <0x35>; + + interrupt-parent = <&gpio>; + interrupts = ; + + monitored-battery = <&battery>; + + port { + charger_input: endpoint { + remote-endpoint = <&muic_to_charger>; + }; + }; + }; + fuel-gauge@36 { compatible = "maxim,max17043"; reg = <0x36>; @@ -1317,6 +1382,10 @@ fuel-gauge@36 { interrupts = ; monitored-battery = <&battery>; + power-supplies = <&max8971>; + + io-channels = <&tbattery 0>; + io-channel-names = "temp"; maxim,alert-low-soc-level = <10>; wakeup-source; @@ -1357,7 +1426,58 @@ spi@7000dc00 { status = "okay"; spi-max-frequency = <25000000>; - /* DSI bridge */ + dsi@2 { + compatible = "solomon,ssd2825"; + reg = <2>; + + #address-cells = <1>; + #size-cells = <0>; + + spi-max-frequency = <1000000>; + + spi-cpha; + spi-cpol; + + reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>; + + dvdd-supply = <&vdd_1v2_rgb>; + avdd-supply = <&vdd_1v2_rgb>; + vddio-supply = <&vdd_1v8_vio>; + + solomon,hs-zero-delay-ns = <300>; + solomon,hs-prep-delay-ns = <65>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_3>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN3>, + <&tegra_pmc TEGRA_PMC_CLK_OUT_3>; + assigned-clock-rates = <24000000>; + + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>, + <&tegra_car TEGRA30_CLK_EXTERN3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + bus-width = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; }; pmc@7000e400 { @@ -1446,12 +1566,13 @@ sdmmc4: mmc@78000600 { usb@7d000000 { compatible = "nvidia,tegra30-udc"; status = "okay"; - dr_mode = "peripheral"; + dr_mode = "otg"; + extcon = <&max14526>, <&max14526>; }; usb-phy@7d000000 { status = "okay"; - dr_mode = "peripheral"; + dr_mode = "otg"; nvidia,hssync-start-delay = <0>; nvidia,xcvr-lsfslew = <2>; nvidia,xcvr-lsrslew = <2>; @@ -1617,6 +1738,17 @@ vdd_1v8_sen: regulator-sen1v8 { vin-supply = <&vdd_3v3_vbat>; }; + vdd_1v2_rgb: regulator-rgb1v2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v2_rgb"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_vbat>; + }; + vcc_3v0_lcd: regulator-lcd3v { compatible = "regulator-fixed"; regulator-name = "vcc_3v0_lcd"; @@ -1724,7 +1856,43 @@ sound { <&tegra_car TEGRA30_CLK_EXTERN1>; }; + tbattery: thermal-sensor-battery { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + + io-channels = <&tsc2007 4>; + io-channel-names = "sensor-channel"; + #io-channel-cells = <1>; + + temperature-lookup-table = < + (-50000) 4100 (-40000) 3980 (-30000) 3815 (-20000) 3610 + (-10000) 3285 0 2880 10000 2445 20000 1955 + 30000 1440 40000 1125 50000 840 60000 665 + 70000 465 80000 350 90000 230 100000 185 >; + }; + thermal-zones { + battery-thermal { + polling-delay-passive = <0>; /* milliseconds */ + polling-delay = <20000>; /* milliseconds */ + + thermal-sensors = <&tbattery>; + + trips { + battery-alert { + temperature = <55000>; + hysteresis = <2000>; + type = "hot"; + }; + + battery-crit { + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + /* * NCT72 has two sensors: * diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index de4142e8f3ce..856c9f21bd70 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -58,6 +58,31 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-voipac-bsb.dtb imx53-qsb-hdmi-dtbs := imx53-qsb.dtb imx53-qsb-hdmi.dtbo imx53-qsrb-hdmi-dtbs := imx53-qsrb.dtb imx53-qsb-hdmi.dtbo + +imx6qdl-dhcom-pdk2-overlay-497-200-x12-dtbs := \ + imx6q-dhcom-pdk2.dtb \ + imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtbo + +imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \ + imx6q-dhcom-pdk2.dtb \ + imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo + +imx6qdl-dhcom-pdk2-overlay-531-100-x21-dtbs := \ + imx6q-dhcom-pdk2.dtb \ + imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtbo + +imx6qdl-dhcom-pdk2-overlay-531-100-x22-dtbs := \ + imx6q-dhcom-pdk2.dtb \ + imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtbo + +imx6qdl-dhcom-pdk2-overlay-560-200-x12-dtbs := \ + imx6q-dhcom-pdk2.dtb \ + imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtbo + +imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \ + imx6q-dhcom-pdk2.dtb \ + imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo + dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-alti6p.dtb \ imx6dl-apf6dev.dtb \ @@ -179,6 +204,18 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-cubox-i-som-v15.dtb \ imx6q-dfi-fs700-m60.dtb \ imx6q-dhcom-pdk2.dtb \ + imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtb \ + imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtbo \ + imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \ + imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \ + imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtb \ + imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtbo \ + imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtb \ + imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtbo \ + imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtb \ + imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtbo \ + imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \ + imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \ imx6q-display5-tianma-tm070-1280x768.dtb \ imx6q-dmo-edmqmx6.dtb \ imx6q-dms-ba16.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts index 2c817c4a4c68..823e7c42910b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1-ads.dts +++ b/arch/arm/boot/dts/nxp/imx/imx1-ads.dts @@ -76,60 +76,58 @@ nor: flash@0,0 { }; &iomuxc { - imx1-ads { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 - MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 - MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 - MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 - MX1_PAD_SPI1_SS__GPIO3_15 0x0 - >; - }; + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 + MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 + MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 + MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 + MX1_PAD_SPI1_SS__GPIO3_15 0x0 + >; + }; - pinctrl_i2c: i2cgrp { - fsl,pins = < - MX1_PAD_I2C_SCL__I2C_SCL 0x0 - MX1_PAD_I2C_SDA__I2C_SDA 0x0 - >; - }; + pinctrl_i2c: i2cgrp { + fsl,pins = < + MX1_PAD_I2C_SCL__I2C_SCL 0x0 + MX1_PAD_I2C_SDA__I2C_SDA 0x0 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX1_PAD_UART1_TXD__UART1_TXD 0x0 - MX1_PAD_UART1_RXD__UART1_RXD 0x0 - MX1_PAD_UART1_CTS__UART1_CTS 0x0 - MX1_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX1_PAD_UART1_TXD__UART1_TXD 0x0 + MX1_PAD_UART1_RXD__UART1_RXD 0x0 + MX1_PAD_UART1_CTS__UART1_CTS 0x0 + MX1_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX1_PAD_UART2_TXD__UART2_TXD 0x0 - MX1_PAD_UART2_RXD__UART2_RXD 0x0 - MX1_PAD_UART2_CTS__UART2_CTS 0x0 - MX1_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX1_PAD_UART2_TXD__UART2_TXD 0x0 + MX1_PAD_UART2_RXD__UART2_RXD 0x0 + MX1_PAD_UART2_CTS__UART2_CTS 0x0 + MX1_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; - pinctrl_weim: weimgrp { - fsl,pins = < - MX1_PAD_A0__A0 0x0 - MX1_PAD_A16__A16 0x0 - MX1_PAD_A17__A17 0x0 - MX1_PAD_A18__A18 0x0 - MX1_PAD_A19__A19 0x0 - MX1_PAD_A20__A20 0x0 - MX1_PAD_A21__A21 0x0 - MX1_PAD_A22__A22 0x0 - MX1_PAD_A23__A23 0x0 - MX1_PAD_A24__A24 0x0 - MX1_PAD_BCLK__BCLK 0x0 - MX1_PAD_CS4__CS4 0x0 - MX1_PAD_DTACK__DTACK 0x0 - MX1_PAD_ECB__ECB 0x0 - MX1_PAD_LBA__LBA 0x0 - >; - }; + pinctrl_weim: weimgrp { + fsl,pins = < + MX1_PAD_A0__A0 0x0 + MX1_PAD_A16__A16 0x0 + MX1_PAD_A17__A17 0x0 + MX1_PAD_A18__A18 0x0 + MX1_PAD_A19__A19 0x0 + MX1_PAD_A20__A20 0x0 + MX1_PAD_A21__A21 0x0 + MX1_PAD_A22__A22 0x0 + MX1_PAD_A23__A23 0x0 + MX1_PAD_A24__A24 0x0 + MX1_PAD_BCLK__BCLK 0x0 + MX1_PAD_CS4__CS4 0x0 + MX1_PAD_DTACK__DTACK 0x0 + MX1_PAD_ECB__ECB 0x0 + MX1_PAD_LBA__LBA 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts index 058e9435524f..794e5bfee367 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts +++ b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts @@ -67,56 +67,54 @@ eth: ethernet@4,c00000 { }; &iomuxc { - imx1-apf9328 { - pinctrl_eth: ethgrp { - fsl,pins = < - MX1_PAD_SIM_SVEN__GPIO2_14 0x0 - >; - }; + pinctrl_eth: ethgrp { + fsl,pins = < + MX1_PAD_SIM_SVEN__GPIO2_14 0x0 + >; + }; - pinctrl_i2c: i2cgrp { - fsl,pins = < - MX1_PAD_I2C_SCL__I2C_SCL 0x0 - MX1_PAD_I2C_SDA__I2C_SDA 0x0 - >; - }; + pinctrl_i2c: i2cgrp { + fsl,pins = < + MX1_PAD_I2C_SCL__I2C_SCL 0x0 + MX1_PAD_I2C_SDA__I2C_SDA 0x0 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX1_PAD_UART1_TXD__UART1_TXD 0x0 - MX1_PAD_UART1_RXD__UART1_RXD 0x0 - MX1_PAD_UART1_CTS__UART1_CTS 0x0 - MX1_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX1_PAD_UART1_TXD__UART1_TXD 0x0 + MX1_PAD_UART1_RXD__UART1_RXD 0x0 + MX1_PAD_UART1_CTS__UART1_CTS 0x0 + MX1_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX1_PAD_UART2_TXD__UART2_TXD 0x0 - MX1_PAD_UART2_RXD__UART2_RXD 0x0 - MX1_PAD_UART2_CTS__UART2_CTS 0x0 - MX1_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX1_PAD_UART2_TXD__UART2_TXD 0x0 + MX1_PAD_UART2_RXD__UART2_RXD 0x0 + MX1_PAD_UART2_CTS__UART2_CTS 0x0 + MX1_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; - pinctrl_weim: weimgrp { - fsl,pins = < - MX1_PAD_A0__A0 0x0 - MX1_PAD_A16__A16 0x0 - MX1_PAD_A17__A17 0x0 - MX1_PAD_A18__A18 0x0 - MX1_PAD_A19__A19 0x0 - MX1_PAD_A20__A20 0x0 - MX1_PAD_A21__A21 0x0 - MX1_PAD_A22__A22 0x0 - MX1_PAD_A23__A23 0x0 - MX1_PAD_A24__A24 0x0 - MX1_PAD_BCLK__BCLK 0x0 - MX1_PAD_CS4__CS4 0x0 - MX1_PAD_DTACK__DTACK 0x0 - MX1_PAD_ECB__ECB 0x0 - MX1_PAD_LBA__LBA 0x0 - >; - }; + pinctrl_weim: weimgrp { + fsl,pins = < + MX1_PAD_A0__A0 0x0 + MX1_PAD_A16__A16 0x0 + MX1_PAD_A17__A17 0x0 + MX1_PAD_A18__A18 0x0 + MX1_PAD_A19__A19 0x0 + MX1_PAD_A20__A20 0x0 + MX1_PAD_A21__A21 0x0 + MX1_PAD_A22__A22 0x0 + MX1_PAD_A23__A23 0x0 + MX1_PAD_A24__A24 0x0 + MX1_PAD_BCLK__BCLK 0x0 + MX1_PAD_CS4__CS4 0x0 + MX1_PAD_DTACK__DTACK 0x0 + MX1_PAD_ECB__ECB 0x0 + MX1_PAD_LBA__LBA 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx1.dtsi b/arch/arm/boot/dts/nxp/imx/imx1.dtsi index a1a89ccacf05..ed04a907b3f7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx1.dtsi @@ -202,7 +202,7 @@ clks: ccm@21b000 { #clock-cells = <1>; }; - iomuxc: iomuxc@21c000 { + iomuxc: pinmux@21c000 { compatible = "fsl,imx1-iomuxc"; reg = <0x0021c000 0x1000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi index 93a6e4e680b4..31dc2a640362 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-cpuimx25.dtsi @@ -34,27 +34,25 @@ rtc@51 { }; &iomuxc { - imx25-eukrea-cpuimx25 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - >; - }; + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 + MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts index 6cddb2cc36fe..e08fcbfef4d5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts @@ -43,10 +43,8 @@ reg_lcd_3v3: regulator-0 { }; &iomuxc { - imx25-eukrea-mbimxsd25-baseboard-cmo-qvga { - pinctrl_reg_lcd_3v3: reg_lcd_3v3 { - fsl,pins = ; - }; + pinctrl_reg_lcd_3v3: reg_lcd_3v3grp { + fsl,pins = ; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts index c7207ea437c4..cf127e00793e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard.dts @@ -68,80 +68,78 @@ tlv320aic23: codec@1a { }; &iomuxc { - imx25-eukrea-mbimxsd25-baseboard { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 - MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 - MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 - MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 + MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 + MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 + MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 + >; + }; - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 - MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 - MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 - MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 - MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 - MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 - >; - }; + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX25_PAD_SD1_CMD__ESDHC1_CMD 0x400000c0 + MX25_PAD_SD1_CLK__ESDHC1_CLK 0x400000c0 + MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x400000c0 + MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x400000c0 + MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x400000c0 + MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x400000c0 + >; + }; - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = ; - }; + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = ; + }; - pinctrl_gpioled: gpioledgrp { - fsl,pins = ; - }; + pinctrl_gpioled: gpioledgrp { + fsl,pins = ; + }; - pinctrl_lcdc: lcdcgrp { - fsl,pins = < - MX25_PAD_LD0__LD0 0x1 - MX25_PAD_LD1__LD1 0x1 - MX25_PAD_LD2__LD2 0x1 - MX25_PAD_LD3__LD3 0x1 - MX25_PAD_LD4__LD4 0x1 - MX25_PAD_LD5__LD5 0x1 - MX25_PAD_LD6__LD6 0x1 - MX25_PAD_LD7__LD7 0x1 - MX25_PAD_LD8__LD8 0x1 - MX25_PAD_LD9__LD9 0x1 - MX25_PAD_LD10__LD10 0x1 - MX25_PAD_LD11__LD11 0x1 - MX25_PAD_LD12__LD12 0x1 - MX25_PAD_LD13__LD13 0x1 - MX25_PAD_LD14__LD14 0x1 - MX25_PAD_LD15__LD15 0x1 - MX25_PAD_GPIO_E__LD16 0x1 - MX25_PAD_GPIO_F__LD17 0x1 - MX25_PAD_HSYNC__HSYNC 0x80000000 - MX25_PAD_VSYNC__VSYNC 0x80000000 - MX25_PAD_LSCLK__LSCLK 0x80000000 - MX25_PAD_OE_ACD__OE_ACD 0x80000000 - MX25_PAD_CONTRAST__CONTRAST 0x80000000 - >; - }; + pinctrl_lcdc: lcdcgrp { + fsl,pins = < + MX25_PAD_LD0__LD0 0x1 + MX25_PAD_LD1__LD1 0x1 + MX25_PAD_LD2__LD2 0x1 + MX25_PAD_LD3__LD3 0x1 + MX25_PAD_LD4__LD4 0x1 + MX25_PAD_LD5__LD5 0x1 + MX25_PAD_LD6__LD6 0x1 + MX25_PAD_LD7__LD7 0x1 + MX25_PAD_LD8__LD8 0x1 + MX25_PAD_LD9__LD9 0x1 + MX25_PAD_LD10__LD10 0x1 + MX25_PAD_LD11__LD11 0x1 + MX25_PAD_LD12__LD12 0x1 + MX25_PAD_LD13__LD13 0x1 + MX25_PAD_LD14__LD14 0x1 + MX25_PAD_LD15__LD15 0x1 + MX25_PAD_GPIO_E__LD16 0x1 + MX25_PAD_GPIO_F__LD17 0x1 + MX25_PAD_HSYNC__HSYNC 0x80000000 + MX25_PAD_VSYNC__VSYNC 0x80000000 + MX25_PAD_LSCLK__LSCLK 0x80000000 + MX25_PAD_OE_ACD__OE_ACD 0x80000000 + MX25_PAD_CONTRAST__CONTRAST 0x80000000 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 - MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 - MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 - MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 + MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 + MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 + MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts index dd176fb54e58..a35778ba6ffa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts @@ -130,109 +130,107 @@ codec: sgtl5000@a { }; &iomuxc { - imx25-pdk { - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX25_PAD_RW__AUD4_TXFS 0xe0 - MX25_PAD_OE__AUD4_TXC 0xe0 - MX25_PAD_EB0__AUD4_TXD 0xe0 - MX25_PAD_EB1__AUD4_RXD 0xe0 - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX25_PAD_RW__AUD4_TXFS 0xe0 + MX25_PAD_OE__AUD4_TXC 0xe0 + MX25_PAD_EB0__AUD4_TXD 0xe0 + MX25_PAD_EB1__AUD4_RXD 0xe0 + >; + }; - pinctrl_can1: can1grp { - fsl,pins = < - MX25_PAD_GPIO_A__CAN1_TX 0x0 - MX25_PAD_GPIO_B__CAN1_RX 0x0 - MX25_PAD_D14__GPIO_4_6 0x80000000 - >; - }; + pinctrl_can1: can1grp { + fsl,pins = < + MX25_PAD_GPIO_A__CAN1_TX 0x0 + MX25_PAD_GPIO_B__CAN1_RX 0x0 + MX25_PAD_D14__GPIO_4_6 0x80000000 + >; + }; - pinctrl_esdhc1: esdhc1grp { - fsl,pins = < - MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 - MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 - MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 - MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 - MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 - MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 - MX25_PAD_A14__GPIO_2_0 0x80000000 - MX25_PAD_A15__GPIO_2_1 0x80000000 - >; - }; + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX25_PAD_SD1_CMD__ESDHC1_CMD 0x80000000 + MX25_PAD_SD1_CLK__ESDHC1_CLK 0x80000000 + MX25_PAD_SD1_DATA0__ESDHC1_DAT0 0x80000000 + MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x80000000 + MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x80000000 + MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x80000000 + MX25_PAD_A14__GPIO_2_0 0x80000000 + MX25_PAD_A15__GPIO_2_1 0x80000000 + >; + }; - pinctrl_fec: fecgrp { - fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - MX25_PAD_A17__GPIO_2_3 0x80000000 - MX25_PAD_D12__GPIO_4_8 0x80000000 - >; - }; + pinctrl_fec: fecgrp { + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + MX25_PAD_A17__GPIO_2_3 0x80000000 + MX25_PAD_D12__GPIO_4_8 0x80000000 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 + MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + >; + }; - pinctrl_kpp: kppgrp { - fsl,pins = < - MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 - MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 - MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 - MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 - MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 - MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 - MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 - MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 - >; - }; + pinctrl_kpp: kppgrp { + fsl,pins = < + MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 + MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 + MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 + MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 + MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 + MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 + MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 + MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 + >; + }; - pinctrl_lcd: lcdgrp { - fsl,pins = < - MX25_PAD_LD0__LD0 0xe0 - MX25_PAD_LD1__LD1 0xe0 - MX25_PAD_LD2__LD2 0xe0 - MX25_PAD_LD3__LD3 0xe0 - MX25_PAD_LD4__LD4 0xe0 - MX25_PAD_LD5__LD5 0xe0 - MX25_PAD_LD6__LD6 0xe0 - MX25_PAD_LD7__LD7 0xe0 - MX25_PAD_LD8__LD8 0xe0 - MX25_PAD_LD9__LD9 0xe0 - MX25_PAD_LD10__LD10 0xe0 - MX25_PAD_LD11__LD11 0xe0 - MX25_PAD_LD12__LD12 0xe0 - MX25_PAD_LD13__LD13 0xe0 - MX25_PAD_LD14__LD14 0xe0 - MX25_PAD_LD15__LD15 0xe0 - MX25_PAD_GPIO_E__LD16 0xe0 - MX25_PAD_GPIO_F__LD17 0xe0 - MX25_PAD_HSYNC__HSYNC 0xe0 - MX25_PAD_VSYNC__VSYNC 0xe0 - MX25_PAD_LSCLK__LSCLK 0xe0 - MX25_PAD_OE_ACD__OE_ACD 0xe0 - MX25_PAD_CONTRAST__CONTRAST 0xe0 - >; - }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX25_PAD_LD0__LD0 0xe0 + MX25_PAD_LD1__LD1 0xe0 + MX25_PAD_LD2__LD2 0xe0 + MX25_PAD_LD3__LD3 0xe0 + MX25_PAD_LD4__LD4 0xe0 + MX25_PAD_LD5__LD5 0xe0 + MX25_PAD_LD6__LD6 0xe0 + MX25_PAD_LD7__LD7 0xe0 + MX25_PAD_LD8__LD8 0xe0 + MX25_PAD_LD9__LD9 0xe0 + MX25_PAD_LD10__LD10 0xe0 + MX25_PAD_LD11__LD11 0xe0 + MX25_PAD_LD12__LD12 0xe0 + MX25_PAD_LD13__LD13 0xe0 + MX25_PAD_LD14__LD14 0xe0 + MX25_PAD_LD15__LD15 0xe0 + MX25_PAD_GPIO_E__LD16 0xe0 + MX25_PAD_GPIO_F__LD17 0xe0 + MX25_PAD_HSYNC__HSYNC 0xe0 + MX25_PAD_VSYNC__VSYNC 0xe0 + MX25_PAD_LSCLK__LSCLK 0xe0 + MX25_PAD_OE_ACD__OE_ACD 0xe0 + MX25_PAD_CONTRAST__CONTRAST 0xe0 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25.dtsi index 82601a4b7b4b..94dbcef63b8c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx25.dtsi @@ -195,7 +195,7 @@ kpp: kpp@43fa8000 { status = "disabled"; }; - iomuxc: iomuxc@43fac000 { + iomuxc: pinmux@43fac000 { compatible = "fsl,imx25-iomuxc"; reg = <0x43fac000 0x4000>; }; @@ -305,7 +305,7 @@ adc: adc@50030800 { status = "disabled"; }; - tsc: tcq@50030400 { + tsc: touchscreen@50030400 { compatible = "fsl,imx25-tcq"; reg = <0x50030400 0x60>; interrupt-parent = <&tscadc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts index 745d5d409952..b67bb21af3de 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27.dts @@ -24,36 +24,34 @@ &clk_osc26m { }; &iomuxc { - imx27-apf27 { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts index 849306cb4532..dba97912cfd7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts @@ -122,116 +122,114 @@ &i2c2 { }; &iomuxc { - imx27-apf27dev { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - >; - }; + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + >; + }; - pinctrl_cspi1_cs: cspi1csgrp { - fsl,pins = ; - }; + pinctrl_cspi1_cs: cspi1csgrp { + fsl,pins = ; + }; - pinctrl_cspi2: cspi2grp { - fsl,pins = < - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - >; - }; + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + >; + }; - pinctrl_cspi2_cs: cspi2csgrp { - fsl,pins = < - MX27_PAD_CSI_D5__GPIO2_17 0x0 - MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 - MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 - >; - }; + pinctrl_cspi2_cs: cspi2csgrp { + fsl,pins = < + MX27_PAD_CSI_D5__GPIO2_17 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = ; - }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = ; + }; - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = ; - }; + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = ; + }; - pinctrl_imxfb1: imxfbgrp { - fsl,pins = < - MX27_PAD_CLS__CLS 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_LSCLK__LSCLK 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_PS__PS 0x0 - MX27_PAD_REV__REV 0x0 - MX27_PAD_SPL_SPR__SPL_SPR 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; + pinctrl_imxfb1: imxfbgrp { + fsl,pins = < + MX27_PAD_CLS__CLS 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_LSCLK__LSCLK 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_PS__PS 0x0 + MX27_PAD_REV__REV 0x0 + MX27_PAD_SPL_SPR__SPL_SPR 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; - pinctrl_max1027: max1027 { - fsl,pins = < - MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ - MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ - >; - }; + pinctrl_max1027: max1027grp { + fsl,pins = < + MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ + MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ + >; + }; - pinctrl_pwm: pwmgrp { - fsl,pins = < - MX27_PAD_PWMO__PWMO 0x0 - >; - }; + pinctrl_pwm: pwmgrp { + fsl,pins = < + MX27_PAD_PWMO__PWMO 0x0 + >; + }; - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - >; - }; + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + >; + }; - pinctrl_sdhc2_cd: sdhc2cdgrp { - fsl,pins = ; - }; + pinctrl_sdhc2_cd: sdhc2cdgrp { + fsl,pins = ; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi index c7e923584878..46acd0dfc589 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-cpuimx27.dtsi @@ -100,52 +100,52 @@ nor: flash@0,0 { fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>; }; - uart8250@3,200000 { + serial@3,200000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart8250_1>; compatible = "ns8250"; clocks = <&clk14745600>; fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>; reg = <3 0x200000 0x1000>; reg-shift = <1>; reg-io-width = <1>; no-loopback-test; }; - uart8250@3,400000 { + serial@3,400000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart8250_2>; compatible = "ns8250"; clocks = <&clk14745600>; fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>; reg = <3 0x400000 0x1000>; reg-shift = <1>; reg-io-width = <1>; no-loopback-test; }; - uart8250@3,800000 { + serial@3,800000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart8250_3>; compatible = "ns8250"; clocks = <&clk14745600>; fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>; reg = <3 0x800000 0x1000>; reg-shift = <1>; reg-io-width = <1>; no-loopback-test; }; - uart8250@3,1000000 { + serial@3,1000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart8250_4>; compatible = "ns8250"; clocks = <&clk14745600>; fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>; - interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>; reg = <3 0x1000000 0x1000>; reg-shift = <1>; reg-io-width = <1>; @@ -154,131 +154,129 @@ uart8250@3,1000000 { }; &iomuxc { - imx27-eukrea-cpuimx27 { - pinctrl_fec: fecgrp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; + pinctrl_fec: fecgrp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; - pinctrl_owire: owiregrp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; + pinctrl_owire: owiregrp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - >; - }; + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + >; + }; - pinctrl_uart4: uart4grp { - fsl,pins = < - MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 - MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 - MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 - MX27_PAD_USBH1_FS__UART4_RTS 0x0 - >; - }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX27_PAD_USBH1_TXDM__UART4_TXD 0x0 + MX27_PAD_USBH1_RXDP__UART4_RXD 0x0 + MX27_PAD_USBH1_TXDP__UART4_CTS 0x0 + MX27_PAD_USBH1_FS__UART4_RTS 0x0 + >; + }; - pinctrl_uart8250_1: uart82501grp { - fsl,pins = < - MX27_PAD_USB_PWR__GPIO2_23 0x0 - >; - }; + pinctrl_uart8250_1: uart82501grp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 + >; + }; - pinctrl_uart8250_2: uart82502grp { - fsl,pins = < - MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 - >; - }; + pinctrl_uart8250_2: uart82502grp { + fsl,pins = < + MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 + >; + }; - pinctrl_uart8250_3: uart82503grp { - fsl,pins = < - MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 - >; - }; + pinctrl_uart8250_3: uart82503grp { + fsl,pins = < + MX27_PAD_USBH1_OE_B__GPIO2_27 0x0 + >; + }; - pinctrl_uart8250_4: uart82504grp { - fsl,pins = < - MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 - >; - }; + pinctrl_uart8250_4: uart82504grp { + fsl,pins = < + MX27_PAD_USBH1_RXDM__GPIO2_30 0x0 + >; + }; - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts index d78793601306..26833ed3339e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts @@ -76,7 +76,7 @@ ads7846@0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touch>; reg = <0>; - interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; spi-cpol; spi-max-frequency = <1500000>; ti,keep-vref-on; @@ -147,113 +147,111 @@ &uart3 { }; &iomuxc { - imx27-eukrea-cpuimx27-baseboard { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ - >; - }; + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */ + >; + }; - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX27_PAD_PWMO__GPIO5_5 0x0 - >; - }; + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX27_PAD_PWMO__GPIO5_5 0x0 + >; + }; - pinctrl_gpioleds: gpioledsgrp { - fsl,pins = < - MX27_PAD_PC_PWRON__GPIO6_16 0x0 - MX27_PAD_PC_CD2_B__GPIO6_19 0x0 - >; - }; + pinctrl_gpioleds: gpioledsgrp { + fsl,pins = < + MX27_PAD_PC_PWRON__GPIO6_16 0x0 + MX27_PAD_PC_CD2_B__GPIO6_19 0x0 + >; + }; - pinctrl_imxfb: imxfbgrp { - fsl,pins = < - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; + pinctrl_imxfb: imxfbgrp { + fsl,pins = < + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; - pinctrl_lcdreg: lcdreggrp { - fsl,pins = < - MX27_PAD_CLS__GPIO1_25 0x0 - >; - }; + pinctrl_lcdreg: lcdreggrp { + fsl,pins = < + MX27_PAD_CLS__GPIO1_25 0x0 + >; + }; - pinctrl_sdhc1: sdhc1grp { - fsl,pins = < - MX27_PAD_SD1_CLK__SD1_CLK 0x0 - MX27_PAD_SD1_CMD__SD1_CMD 0x0 - MX27_PAD_SD1_D0__SD1_D0 0x0 - MX27_PAD_SD1_D1__SD1_D1 0x0 - MX27_PAD_SD1_D2__SD1_D2 0x0 - MX27_PAD_SD1_D3__SD1_D3 0x0 - >; - }; + pinctrl_sdhc1: sdhc1grp { + fsl,pins = < + MX27_PAD_SD1_CLK__SD1_CLK 0x0 + MX27_PAD_SD1_CMD__SD1_CMD 0x0 + MX27_PAD_SD1_D0__SD1_D0 0x0 + MX27_PAD_SD1_D1__SD1_D1 0x0 + MX27_PAD_SD1_D2__SD1_D2 0x0 + MX27_PAD_SD1_D3__SD1_D3 0x0 + >; + }; - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 - MX27_PAD_SSI4_FS__SSI4_FS 0x0 - MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 - MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 - >; - }; + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX27_PAD_SSI4_CLK__SSI4_CLK 0x0 + MX27_PAD_SSI4_FS__SSI4_FS 0x0 + MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1 + MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1 + >; + }; - pinctrl_touch: touchgrp { - fsl,pins = < - MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ - >; - }; + pinctrl_touch: touchgrp { + fsl,pins = < + MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */ + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX27_PAD_UART3_TXD__UART3_TXD 0x0 + MX27_PAD_UART3_RXD__UART3_RXD 0x0 + MX27_PAD_UART3_CTS__UART3_CTS 0x0 + MX27_PAD_UART3_RTS__UART3_RTS 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts index 21d436972aa4..2fc4ea5b9501 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-pdk.dts @@ -110,76 +110,74 @@ &usbotg { }; &iomuxc { - imx27-pdk { - pinctrl_cspi2: cspi2grp { - fsl,pins = < - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ - MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ - >; - }; + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ + MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ + >; + }; - pinctrl_fec: fecgrp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; + pinctrl_fec: fecgrp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; - pinctrl_nand: nandgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; + pinctrl_nand: nandgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts index 27c93b9fe049..2b884cb3e381 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts @@ -65,58 +65,56 @@ adc@64 { }; &iomuxc { - imx27-phycard-s-rdk { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x0 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x0 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; + pinctrl_owire1: owire1grp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX27_PAD_UART3_TXD__UART3_TXD 0x0 + MX27_PAD_UART3_RXD__UART3_RXD 0x0 + MX27_PAD_UART3_CTS__UART3_CTS 0x0 + MX27_PAD_UART3_RTS__UART3_RTS 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi index 31b3fc972abb..2f60b3809f39 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-som.dtsi @@ -58,94 +58,92 @@ eeprom@52 { }; &iomuxc { - imx27-phycard-s-som { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; - pinctrl_usbotgphy: usbotgphygrp { - fsl,pins = < - MX27_PAD_USBH1_RCV__GPIO2_25 0x1 /* reset gpio */ - >; - }; + pinctrl_usbotgphy: usbotgphygrp { + fsl,pins = < + MX27_PAD_USBH1_RCV__GPIO2_25 0x1 /* reset gpio */ + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; + }; - pinctrl_usbh2phy: usbh2phygrp { - fsl,pins = < - MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 /* reset gpio */ - >; - }; + pinctrl_usbh2phy: usbh2phygrp { + fsl,pins = < + MX27_PAD_USBH1_SUSP__GPIO2_22 0x0 /* reset gpio */ + >; + }; - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts index 5398e9067e60..d7136c399ae2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts @@ -89,119 +89,117 @@ camgpio: pca9536@41 { }; &iomuxc { - imx27_phycore_rdk { - pinctrl_csien: csiengrp { - fsl,pins = < - MX27_PAD_USB_OC_B__GPIO2_24 0x0 - >; - }; + pinctrl_csien: csiengrp { + fsl,pins = < + MX27_PAD_USB_OC_B__GPIO2_24 0x0 + >; + }; - pinctrl_cspi1cs1: cspi1cs1grp { - fsl,pins = < - MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 - >; - }; + pinctrl_cspi1cs1: cspi1cs1grp { + fsl,pins = < + MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 + >; + }; - pinctrl_imxfb1: imxfbgrp { - fsl,pins = < - MX27_PAD_LD0__LD0 0x0 - MX27_PAD_LD1__LD1 0x0 - MX27_PAD_LD2__LD2 0x0 - MX27_PAD_LD3__LD3 0x0 - MX27_PAD_LD4__LD4 0x0 - MX27_PAD_LD5__LD5 0x0 - MX27_PAD_LD6__LD6 0x0 - MX27_PAD_LD7__LD7 0x0 - MX27_PAD_LD8__LD8 0x0 - MX27_PAD_LD9__LD9 0x0 - MX27_PAD_LD10__LD10 0x0 - MX27_PAD_LD11__LD11 0x0 - MX27_PAD_LD12__LD12 0x0 - MX27_PAD_LD13__LD13 0x0 - MX27_PAD_LD14__LD14 0x0 - MX27_PAD_LD15__LD15 0x0 - MX27_PAD_LD16__LD16 0x0 - MX27_PAD_LD17__LD17 0x0 - MX27_PAD_CLS__CLS 0x0 - MX27_PAD_CONTRAST__CONTRAST 0x0 - MX27_PAD_LSCLK__LSCLK 0x0 - MX27_PAD_OE_ACD__OE_ACD 0x0 - MX27_PAD_PS__PS 0x0 - MX27_PAD_REV__REV 0x0 - MX27_PAD_SPL_SPR__SPL_SPR 0x0 - MX27_PAD_HSYNC__HSYNC 0x0 - MX27_PAD_VSYNC__VSYNC 0x0 - >; - }; + pinctrl_imxfb1: imxfbgrp { + fsl,pins = < + MX27_PAD_LD0__LD0 0x0 + MX27_PAD_LD1__LD1 0x0 + MX27_PAD_LD2__LD2 0x0 + MX27_PAD_LD3__LD3 0x0 + MX27_PAD_LD4__LD4 0x0 + MX27_PAD_LD5__LD5 0x0 + MX27_PAD_LD6__LD6 0x0 + MX27_PAD_LD7__LD7 0x0 + MX27_PAD_LD8__LD8 0x0 + MX27_PAD_LD9__LD9 0x0 + MX27_PAD_LD10__LD10 0x0 + MX27_PAD_LD11__LD11 0x0 + MX27_PAD_LD12__LD12 0x0 + MX27_PAD_LD13__LD13 0x0 + MX27_PAD_LD14__LD14 0x0 + MX27_PAD_LD15__LD15 0x0 + MX27_PAD_LD16__LD16 0x0 + MX27_PAD_LD17__LD17 0x0 + MX27_PAD_CLS__CLS 0x0 + MX27_PAD_CONTRAST__CONTRAST 0x0 + MX27_PAD_LSCLK__LSCLK 0x0 + MX27_PAD_OE_ACD__OE_ACD 0x0 + MX27_PAD_PS__PS 0x0 + MX27_PAD_REV__REV 0x0 + MX27_PAD_SPL_SPR__SPL_SPR 0x0 + MX27_PAD_HSYNC__HSYNC 0x0 + MX27_PAD_VSYNC__VSYNC 0x0 + >; + }; - pinctrl_i2c1: i2c1grp { - /* Add pullup to DATA line */ - fsl,pins = < - MX27_PAD_I2C_DATA__I2C_DATA 0x1 - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - >; - }; + pinctrl_i2c1: i2c1grp { + /* Add pullup to DATA line */ + fsl,pins = < + MX27_PAD_I2C_DATA__I2C_DATA 0x1 + MX27_PAD_I2C_CLK__I2C_CLK 0x0 + >; + }; - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; + pinctrl_owire1: owire1grp { + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; + }; - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; + pinctrl_sdhc2: sdhc2grp { + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + MX27_PAD_SSI3_FS__GPIO3_28 0x0 /* WP */ + MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; - pinctrl_usbh2: usbh2grp { - fsl,pins = < - MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 - MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 - MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 - MX27_PAD_USBH2_STP__USBH2_STP 0x0 - MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 - MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 - MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 - MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 - MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 - MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 - MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 - MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 - >; - }; + pinctrl_usbh2: usbh2grp { + fsl,pins = < + MX27_PAD_USBH2_CLK__USBH2_CLK 0x0 + MX27_PAD_USBH2_DIR__USBH2_DIR 0x0 + MX27_PAD_USBH2_NXT__USBH2_NXT 0x0 + MX27_PAD_USBH2_STP__USBH2_STP 0x0 + MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0 + MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0 + MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0 + MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0 + MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0 + MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0 + MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0 + MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0 + >; + }; - pinctrl_weim: weimgrp { - fsl,pins = < - MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ - MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ - >; - }; + pinctrl_weim: weimgrp { + fsl,pins = < + MX27_PAD_CS4_B__CS4_B 0x0 /* CS4 */ + MX27_PAD_SD1_D1__GPIO5_19 0x0 /* CAN IRQ */ + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi index e958d7286ae9..7d5d24c781b9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi @@ -192,90 +192,88 @@ lm75@4a { }; &iomuxc { - imx27_phycore_som { - pinctrl_cspi1: cspi1grp { - fsl,pins = < - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ - >; - }; + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 + MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 + MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 + MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ + >; + }; - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ - >; - }; + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ + >; + }; - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ - >; - }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ + >; + }; - pinctrl_ssi1: ssi1grp { - fsl,pins = < - MX27_PAD_SSI1_FS__SSI1_FS 0x0 - MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 - MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 - MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 - >; - }; + pinctrl_ssi1: ssi1grp { + fsl,pins = < + MX27_PAD_SSI1_FS__SSI1_FS 0x0 + MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 + MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 + MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 - MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 - MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 - MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 - MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 - MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 - MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 - MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 - MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 - MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 - MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 - MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 + MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 + MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 + MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 + MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 + MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 + MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 + MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 + MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 + MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 + MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 + MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 + >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27.dtsi index 989b7659b669..28403a34638e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27.dtsi @@ -49,7 +49,7 @@ aitc: aitc-interrupt-controller@10040000 { clocks { clk_osc26m: osc26m { - compatible = "fsl,imx-osc26m", "fixed-clock"; + compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; @@ -289,7 +289,7 @@ sdhci2: mmc@10014000 { status = "disabled"; }; - iomuxc: iomuxc@10015000 { + iomuxc: pinmux@10015000 { compatible = "fsl,imx27-iomuxc"; reg = <0x10015000 0x600>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi index 8541a666747a..c58f855ea851 100644 --- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx31.dtsi @@ -333,7 +333,7 @@ pwm: pwm@53fe0000 { }; }; - emi@b8000000 { /* External Memory Interface */ + emi-bus@b8000000 { /* External Memory Interface */ compatible = "simple-bus"; reg = <0xb8000000 0x5000>; ranges; diff --git a/arch/arm/boot/dts/nxp/imx/imx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35.dtsi index 111d7c0331f5..ab7b64639989 100644 --- a/arch/arm/boot/dts/nxp/imx/imx35.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx35.dtsi @@ -79,7 +79,7 @@ i2c1: i2c@43f80000 { compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; reg = <0x43f80000 0x4000>; clocks = <&clks 51>; - clock-names = "ipg_per"; + clock-names = "ipg"; interrupts = <10>; status = "disabled"; }; @@ -90,7 +90,7 @@ i2c3: i2c@43f84000 { compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; reg = <0x43f84000 0x4000>; clocks = <&clks 53>; - clock-names = "ipg_per"; + clock-names = "ipg"; interrupts = <3>; status = "disabled"; }; @@ -119,7 +119,7 @@ i2c2: i2c@43f98000 { compatible = "fsl,imx35-i2c", "fsl,imx1-i2c"; reg = <0x43f98000 0x4000>; clocks = <&clks 52>; - clock-names = "ipg_per"; + clock-names = "ipg"; interrupts = <4>; status = "disabled"; }; @@ -356,7 +356,7 @@ usbmisc: usbmisc@53ff4600 { }; }; - emi@80000000 { /* External Memory Interface */ + emi-bus@80000000 { /* External Memory Interface */ compatible = "fsl,emi", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -393,21 +393,13 @@ weim: memory-controller@b8002000 { }; }; - usbphy { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + usbphy0: usb-phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; - usbphy0: usb-phy@0 { - reg = <0>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; - - usbphy1: usb-phy@1 { - reg = <1>; - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - }; + usbphy1: usb-phy1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts index 1b6ec55f9068..b17264e06e69 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts @@ -327,7 +327,7 @@ vgen3_reg: vgen3 { }; }; - flash: at45db321d@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts index 079bd3d14999..5118a68dbbdc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts @@ -141,7 +141,7 @@ &weim { pinctrl-0 = <&pinctrl_weim>; status = "okay"; - fpga@0 { + fpga-bus@0,0 { compatible = "simple-bus"; fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000 0x00000000 0x1c092480 0x00000000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts index 386371c816f4..a1e19f9709b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts @@ -31,6 +31,20 @@ key-volume-down { linux,code = ; }; }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &esdhc1 { @@ -253,6 +267,10 @@ &i2c2 { codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX5_CLK_DUMMY>; + VDDA-supply = <®_1v8>; + VDDIO-supply = <®_3v3>; }; magnetometer: mag3110@e { diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts index 9bb36db131c2..aed4fb7843e2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts @@ -193,8 +193,8 @@ &can1 { }; &clks { - clocks = <&clock_ksz8081>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clock_ksz8081>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&clock_ksz8081>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts index 5ed55f74b398..5f61eeb9fad0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-eckelmann-ci4x10.dts @@ -66,8 +66,8 @@ &can2 { }; &clks { - clocks = <&rmii_clk>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&rmii_clk>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&rmii_clk>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts index 47a6d63c8e04..9bde65462558 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-lanmcu.dts @@ -119,8 +119,8 @@ &can2 { }; &clks { - clocks = <&clock_ksz8081>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clock_ksz8081>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&clock_ksz8081>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts index 84f34da06267..69e790ba5662 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plybas.dts @@ -101,8 +101,8 @@ &can2 { }; &clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&clk50m_phy>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts index 0ef24a07dedf..fbff77944ce3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts @@ -199,8 +199,8 @@ &can1 { }; &clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&clk50m_phy>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts index 2160b7177835..dcd5a4099c60 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts @@ -294,8 +294,8 @@ &can2 { }; &clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi index d5baec5e7a78..fb674ac2c248 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi @@ -71,8 +71,9 @@ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0) }; &clks { - clocks = <&rtc_sqw>; - clock-names = "ckil"; + clocks = <&osc>, <&rtc_sqw>, <&ckih1>, <&anaclk1>, <&anaclk2>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2"; + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts index 76b0007d20ad..18019a6bb3af 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-victgo.dts @@ -160,8 +160,8 @@ vdiv_hitch_pos: voltage-divider-hitch-pos { }; &clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&clk50m_phy>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts index d994b32ad825..7326b8ad08cb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dts @@ -140,6 +140,7 @@ port@3 { port@4 { reg = <4>; label = "cpu"; + phy-mode = "gmii"; ethernet = <&switch_nic>; phy-handle = <&switchphy4>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts index b0d345f5d071..9a43935be11c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b650v3.dts @@ -139,6 +139,7 @@ port@3 { port@4 { reg = <4>; label = "cpu"; + phy-mode = "gmii"; ethernet = <&switch_nic>; phy-handle = <&switchphy4>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts index cad112e05475..d00236a07dc4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-b850v3.dts @@ -53,23 +53,20 @@ chosen { }; }; -&ldb { - fsl,dual-channel; - status = "okay"; +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "PWGIN", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; - lvds0: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&stdp4028_in>; - }; - }; - }; +&hdmi { + ddc-i2c-bus = <&mux2_i2c1>; }; &i2c2 { @@ -129,8 +126,23 @@ mux2_i2c8: i2c@7 { }; }; -&hdmi { - ddc-i2c-bus = <&mux2_i2c1>; +&ldb { + fsl,dual-channel; + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&stdp4028_in>; + }; + }; + }; }; &mux1_i2c1 { @@ -286,7 +298,12 @@ port@3 { port@4 { reg = <4>; label = "cpu"; + phy-mode = "gmii"; ethernet = <&switch_nic>; phy-handle = <&switchphy4>; }; }; + +&usdhc4 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi index 1e2266a2368b..2c8d2ab8cda1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi @@ -124,24 +124,28 @@ switchphy0: switchphy@0 { reg = <0>; interrupt-parent = <&switch>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + max-speed = <100>; /* only 100Mbit/s lanes are routed */ }; switchphy1: switchphy@1 { reg = <1>; interrupt-parent = <&switch>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + max-speed = <100>; /* only 100Mbit/s lanes are routed */ }; switchphy2: switchphy@2 { reg = <2>; interrupt-parent = <&switch>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + max-speed = <100>; /* only 100Mbit/s lanes are routed */ }; switchphy3: switchphy@3 { reg = <3>; interrupt-parent = <&switch>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + max-speed = <100>; /* only 100Mbit/s lanes are routed */ }; switchphy4: switchphy@4 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts index 0e02e448db10..5ef1ce808699 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-prtwd2.dts @@ -57,8 +57,8 @@ &can1 { }; &clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&clk50m_phy>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi new file mode 100644 index 000000000000..90259785126b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx6qdl-dhcom-overlay-panel-dpi.dtsi" + +&{/} { + lvds-encoder { + compatible = "onnn,fin3385", "lvds-encoder"; + pclk-sample = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_bridge_in: endpoint { + remote-endpoint = <&ipu1_dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&display_bl { + pwms = <&pwm1 0 5000000 0>; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpio4>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <16384>; + touchscreen-size-y = <9600>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&ipu1_dpi0_out { + remote-endpoint = <&lvds_bridge_in>; +}; + +&panel { + compatible = "chefree,ch101olhlwh-002"; +}; + +&panel_in { + remote-endpoint = <&lvds_bridge_out>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-overlay-panel-dpi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-overlay-panel-dpi.dtsi new file mode 100644 index 000000000000..48d346b6b484 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-overlay-panel-dpi.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021-2026 Marek Vasut + */ +#include +#include +#include +#include + +&{/} { + display_bl: display-bl { + compatible = "pwm-backlight"; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + ipu1_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + ipu1_dpi0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel: panel { + backlight = <&display_bl>; + + port { + panel_in: endpoint { + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&ipu1_display_in>; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtso b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtso new file mode 100644 index 000000000000..a5cb77b351af --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-497-200-x12.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx6qdl-dhcom-overlay-panel-dpi.dtsi" + +&display_bl { + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; +}; + +&ipu1_dpi0_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "dataimage,scf0700c48ggu18"; +}; + +&panel_in { + remote-endpoint = <&ipu1_dpi0_out>; +}; + +&touch_som { /* TSC2004 */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso new file mode 100644 index 000000000000..3e02031b74d0 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx6qdl-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi" + +&{/} { + gpio-keys { + /* BUTTON1 GPIO-B conflicts with touchscreen reset */ + button-1 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; + + led { + /* LED7 GPIO-H conflicts with touchscreen IRQ */ + led-7 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtso b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtso new file mode 100644 index 000000000000..e8cae43f300d --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-531-100-x21.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + eeprom@1 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <1>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtso b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtso new file mode 100644 index 000000000000..6fde50bcda71 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-531-100-x22.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtso b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtso new file mode 100644 index 000000000000..9f5814e7a04f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-pdk2-overlay-560-200-x12.dtso @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx6qdl-dhcom-overlay-panel-dpi.dtsi" + +&display_bl { + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dhcom_e>; + /* Touchscreen IRQ GPIO-E conflicts with LED5 GPIO */ + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; +}; + +&ipu1_dpi0_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "edt,etm0700g0edh6"; +}; + +&panel_in { + remote-endpoint = <&ipu1_dpi0_out>; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso new file mode 100644 index 000000000000..5c380572c409 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023-2026 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx6qdl-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi index af0d95396cd5..74dfb92f1514 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dhcom-som.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2015-2021 DH electronics GmbH - * Copyright (C) 2018 Marek Vasut + * Copyright (C) 2015-2026 DH electronics GmbH + * Copyright (C) 2018-2026 Marek Vasut */ #include @@ -303,7 +303,7 @@ ldo2_reg: ldo2 { }; }; - touchscreen@49 { /* TSC2004 */ + touch_som: touchscreen@49 { /* TSC2004 */ compatible = "ti,tsc2004"; interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&pinctrl_tsc2004>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi index ee2c6bec92e8..74ccfe56828f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi @@ -206,6 +206,10 @@ ethphy: ethernet-phy@3 { }; }; +&gpio1 { + bootph-pre-ram; +}; + &hdmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi>; @@ -214,6 +218,8 @@ &hdmi { }; &i2c1 { + bootph-pre-ram; + tlv320aic32x4: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; @@ -274,6 +280,7 @@ &ssi1 { &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; + bootph-pre-ram; status = "okay"; }; @@ -346,6 +353,7 @@ &usdhc2 { no-sdio; cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + bootph-all; status = "okay"; }; @@ -354,6 +362,7 @@ &wdog1 { pinctrl-0 = <&pinctrl_wdog1>; /* does not work on unmodified starter kit */ /* fsl,ext-reset-output; */ + bootph-pre-ram; status = "okay"; }; @@ -544,6 +553,7 @@ pinctrl_uart2: uart2grp { MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b099 >; + bootph-pre-ram; }; pinctrl_uart3: uart3grp { @@ -587,6 +597,7 @@ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017059 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b099 /* usdhc2 CD */ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x0001b099 /* usdhc2 WP */ >; + bootph-all; }; pinctrl_usbotg: usbotggrp { @@ -602,5 +613,6 @@ pinctrl_wdog1: wdog1grp { /* Watchdog out */ MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x0000b099 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi index c93dbc595ef6..e2631db798a8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -238,8 +238,8 @@ adc: adc@0 { }; &clks { - clocks = <&clk50m_phy>; - clock-names = "enet_ref_pad"; + clocks = <&osc>, <&ckil>, <&ckih1>, <&anaclk1>, <&anaclk2>, <&clk50m_phy>; + clock-names = "osc", "ckil", "ckih1", "anaclk1", "anaclk2", "enet_ref_pad"; assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; assigned-clock-parents = <&clk50m_phy>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi index cd1e682f11ad..8192344d5294 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sr-som-ti.dtsi @@ -41,6 +41,12 @@ #include / { + clk32k: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + nvcc_sd1: regulator-nvcc-sd1 { compatible = "regulator-fixed"; regulator-always-on; @@ -58,7 +64,7 @@ clk_ti_wifi: ti-wifi-clock { */ compatible = "gpio-gate-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clocks = <&clk32k>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_ti_clk>; enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi index 07492f63a1f8..14676d1d905a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi @@ -11,6 +11,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + bootph-pre-ram; status = "okay"; m25p80: flash@0 { @@ -19,6 +20,7 @@ m25p80: flash@0 { spi-max-frequency = <50000000>; vcc-supply = <&sw4_reg>; m25p,fast-read; + bootph-pre-ram; partitions { compatible = "fixed-partitions"; @@ -28,6 +30,10 @@ partitions { }; }; +&gpio3 { + bootph-pre-ram; +}; + &iomuxc { pinctrl_ecspi1: ecspi1grp { fsl,pins = < @@ -38,6 +44,7 @@ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 /* eCSPI1 SS1 */ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 >; + bootph-pre-ram; }; pinctrl_i2c1: i2c1grp { @@ -45,6 +52,7 @@ pinctrl_i2c1: i2c1grp { MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 >; + bootph-pre-ram; }; pinctrl_i2c1_recovery: i2c1recoverygrp { @@ -73,6 +81,7 @@ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; + bootph-all; }; }; @@ -117,6 +126,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + bootph-pre-ram; }; reg_5v_600mA: swbst { @@ -186,6 +196,7 @@ &usdhc3 { bus-width = <8>; #address-cells = <1>; #size-cells = <0>; + bootph-all; status = "okay"; mmccard: mmccard@0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi index e8fd37dd8835..67f8f59aff5a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi @@ -20,6 +20,7 @@ &i2c1 { scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; + bootph-pre-ram; status = "okay"; pmic: pmic@8 { @@ -27,13 +28,13 @@ pmic: pmic@8 { reg = <0x08>; }; - temperature-sensor@48 { + lm75_48: temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; vs-supply = <&sw4_reg>; }; - eeprom@50 { + m24c64_50: eeprom@50 { compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi index 0e404c1f62f2..db552802554d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi @@ -13,6 +13,7 @@ &i2c3 { scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; + bootph-pre-ram; status = "okay"; pmic: pmic@8 { @@ -20,13 +21,13 @@ pmic: pmic@8 { reg = <0x08>; }; - temperature-sensor@48 { + lm75_48: temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; vs-supply = <&sw4_reg>; }; - eeprom@50 { + m24c64_50: eeprom@50 { compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; @@ -40,6 +41,7 @@ pinctrl_i2c3: i2c3grp { MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 >; + bootph-pre-ram; }; pinctrl_i2c3_recovery: i2c3recoverygrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index 76e6043e1f91..4dc2c410cf61 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -54,23 +54,35 @@ aliases { }; clocks { - ckil { + ckil: ckil { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; - ckih1 { + ckih1: ckih1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; - osc { + osc: osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; + + anaclk1: anaclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + anaclk2: anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; }; ldb: ldb { @@ -149,6 +161,7 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; + bootph-all; dma_apbh: dma-controller@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; @@ -297,6 +310,7 @@ aips1: bus@2000000 { /* AIPS1 */ #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; + bootph-pre-ram; spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; @@ -304,6 +318,7 @@ spba-bus@2000000 { #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; + bootph-pre-ram; spdif: spdif@2004000 { compatible = "fsl,imx35-spdif"; @@ -920,6 +935,7 @@ mux: mux-controller { iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; reg = <0x20e0000 0x4000>; + bootph-pre-ram; }; dcic1: dcic@20e4000 { @@ -950,6 +966,7 @@ aips2: bus@2100000 { /* AIPS2 */ #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; + bootph-pre-ram; crypto: crypto@2100000 { compatible = "fsl,sec-v4.0"; @@ -1320,6 +1337,7 @@ ipu1: ipu@2400000 { <&clks IMX6QDL_CLK_IPU1_DI1>; clock-names = "bus", "di0", "di1"; resets = <&src 2>; + bootph-all; ipu1_csi0: port@0 { reg = <0>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 1426f357d474..aefae5a3a6be 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -1304,7 +1304,7 @@ csi2: csi@221c000 { }; lcdif1: lcdif@2220000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx6sx-lcdif"; reg = <0x02220000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, @@ -1325,7 +1325,7 @@ lcdif1_to_ldb: endpoint { }; lcdif2: lcdif@2224000 { - compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx6sx-lcdif"; reg = <0x02224000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi index 2dd635a615cb..4fa98e6a66d7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi @@ -26,6 +26,7 @@ &i2c4 { pinctrl-1 = <&pinctrl_i2c4_recovery>; scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + bootph-pre-ram; status = "okay"; pfuze3000: pmic@8 { @@ -140,9 +141,14 @@ rtc0: rtc@68 { }; }; +&gpio1 { + bootph-pre-ram; +}; + &gpio4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; + bootph-pre-ram; /* * PMIC & temperature sensor IRQ @@ -159,6 +165,7 @@ pmic-int-hog { &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; + bootph-pre-ram; status = "okay"; flash0: flash@0 { @@ -168,6 +175,7 @@ flash0: flash@0 { spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; vcc-supply = <®_vldo4>; + bootph-pre-ram; partitions { compatible = "fixed-partitions"; @@ -189,6 +197,7 @@ &usdhc2 { non-removable; no-sdio; no-sd; + bootph-all; status = "okay"; }; @@ -212,5 +221,6 @@ pinctrl_pmic: pmicgrp { /* PMIC irq */ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi index e2e95dd92263..f81cd09fe0c7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2.dtsi @@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts index 9d9b6b744a1c..9d637c0a12ec 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l-mba6ulx.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright 2018-2022 TQ Systems GmbH + * Copyright 2018-2022 TQ-Systems GmbH * Author: Markus Niebel */ @@ -10,6 +10,6 @@ #include "mba6ulx.dtsi" / { - model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + model = "TQ-Systems TQMa6UL2L SoM on MBa6ULx board"; compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi index 4b87e2dc70dc..11c8f1af4173 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul2l.dtsi @@ -33,6 +33,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi index 5afb9046c202..5c90d0a3ee2e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulx-common.dtsi @@ -39,5 +39,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi index ba84a4f70ebd..133961ee7283 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ulxl-common.dtsi @@ -44,5 +44,6 @@ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 >; + bootph-pre-ram; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi index 6eb80f867f50..24541fdf49ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -115,6 +115,7 @@ osc: clock-osc { #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "osc"; + bootph-pre-ram; }; ipp_di0: clock-di0 { @@ -143,6 +144,7 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; + bootph-pre-ram; ocram: sram@900000 { compatible = "mmio-sram"; @@ -202,6 +204,7 @@ aips1: bus@2000000 { #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; + bootph-pre-ram; spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; @@ -209,6 +212,7 @@ spba-bus@2000000 { #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; + bootph-pre-ram; ecspi1: spi@2008000 { #address-cells = <1>; @@ -580,6 +584,7 @@ clks: clock-controller@20c4000 { #clock-cells = <1>; clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + bootph-pre-ram; }; anatop: anatop@20c8000 { @@ -745,6 +750,7 @@ power-domain@0 { iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6ul-iomuxc"; reg = <0x020e0000 0x4000>; + bootph-pre-ram; }; gpr: iomuxc-gpr@20e4000 { @@ -826,6 +832,7 @@ aips2: bus@2100000 { #size-cells = <1>; reg = <0x02100000 0x100000>; ranges; + bootph-pre-ram; crypto: crypto@2140000 { compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi index 75486e1b0c15..a0adcd3fe122 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-dhcor-som.dtsi @@ -201,7 +201,7 @@ &uart2 { * the speed can be increased accordingly. */ bluetooth: bluetooth { - compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */ + compatible = "brcm,bcm4329-bt"; /* muRata 1DX or 1YN */ max-speed = <3000000>; vbat-supply = <&vcc_3v3>; vddio-supply = <&vcc_3v3>; @@ -222,7 +222,7 @@ &usdhc1 { status = "okay"; brcmf: wifi@1 { - compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */ + compatible = "brcm,bcm4329-fmac"; /* muRata 1DX or 1YN */ reg = <1>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts index 279d46c22cd7..f251a1028355 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts @@ -154,6 +154,7 @@ &tsc { pinctrl-0 = <&pinctrl_tsc>; measure-delay-time = <0x9ffff>; pre-charge-time = <0xfff>; + debounce-delay-us = <62>; xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi index 8541cb3f3b3e..1224ef132439 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2.dtsi @@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts index 33437aae9822..5676904820a9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l-mba6ulx.dts @@ -10,6 +10,6 @@ #include "mba6ulx.dtsi" / { - model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + model = "TQ-Systems TQMa6ULL2L SoM on MBa6ULx board"; compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi index be593d47e3b1..ac18caf5a76c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-tqma6ull2l.dtsi @@ -9,7 +9,7 @@ #include "imx6ul-tqma6ulxl-common.dtsi" / { - model = "TQ Systems TQMa6ULL2L SoM"; + model = "TQ-Systems TQMa6ULL2L SoM"; compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; }; @@ -38,6 +38,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 /* rst */ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 >; + bootph-all; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi index db0c339022ac..ba0ea10c7b74 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi @@ -57,6 +57,7 @@ aips3: bus@2200000 { #size-cells = <1>; reg = <0x02200000 0x100000>; ranges; + bootph-pre-ram; dcp: crypto@2280000 { compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp"; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi index 4d948a9757f9..4192adb27223 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi @@ -287,6 +287,15 @@ &flexcan2 { status = "okay"; }; +&gpio4 { + /* Deassert BOOT_EN after boot to separate BOOT_CFG circuits from LCD signals */ + boot-en-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + output-low; + }; +}; + &i2c1 { lm75: temperature-sensor@49 { compatible = "national,lm75a"; @@ -477,6 +486,7 @@ pinctrl_uart5: uart5grp { }; pinctrl_uart6: uart6grp { + bootph-pre-ram; fsl,pins = , , @@ -511,6 +521,7 @@ pinctrl_usdhc1: usdhc1grp { , , ; + bootph-pre-ram; }; pinctrl_usdhc1_100mhz: usdhc1_100mhzgrp { @@ -602,6 +613,7 @@ &uart6 { pinctrl-0 = <&pinctrl_uart6>; assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + bootph-pre-ram; status = "okay"; }; @@ -646,6 +658,7 @@ &usdhc1 { no-1-8-v; no-sdio; no-mmc; + bootph-pre-ram; status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi index 2966a33bc528..f3d7a2d0cb7b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi @@ -193,6 +193,7 @@ pinctrl_qspi: qspigrp { , , ; + bootph-pre-ram; }; pinctrl_qspi_reset: qspi_resetgrp { @@ -214,6 +215,7 @@ pinctrl_usdhc3: usdhc3grp { , , ; + bootph-pre-ram; }; pinctrl_usdhc3_100mhz: usdhc3_100mhzgrp { @@ -257,6 +259,7 @@ pinctrl_wdog1: wdog1grp { &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>; + bootph-pre-ram; status = "okay"; flash0: flash@0 { @@ -266,6 +269,7 @@ flash0: flash@0 { spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; vcc-supply = <&vgen4_reg>; + bootph-pre-ram; partitions { compatible = "fixed-partitions"; @@ -288,6 +292,7 @@ &usdhc3 { no-sdio; vmmc-supply = <&vgen4_reg>; vqmmc-supply = <&sw2_reg>; + bootph-pre-ram; status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts index 92b6258059ee..25f38acc5350 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts @@ -199,8 +199,6 @@ ov2680: camera@36 { port { ov2680_to_mipi: endpoint { remote-endpoint = <&mipi_from_sensor>; - clock-lanes = <0>; - data-lanes = <1>; link-frequencies = /bits/ 64 <330000000>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi index 9235dd7e93bb..5c9be24ba7c5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -209,6 +209,7 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gpc>; ranges; + bootph-pre-ram; ocram: sram@900000 { compatible = "mmio-sram"; @@ -371,6 +372,7 @@ aips1: bus@30000000 { #size-cells = <1>; reg = <0x30000000 0x400000>; ranges; + bootph-pre-ram; gpio1: gpio@30200000 { compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; @@ -543,6 +545,7 @@ kpp: keypad@30320000 { iomuxc: pinctrl@30330000 { compatible = "fsl,imx7d-iomuxc"; reg = <0x30330000 0x10000>; + bootph-pre-ram; }; gpr: iomuxc-gpr@30340000 { @@ -712,6 +715,7 @@ aips2: bus@30400000 { #size-cells = <1>; reg = <0x30400000 0x400000>; ranges; + bootph-pre-ram; adc1: adc@30610000 { compatible = "fsl,imx7d-adc"; @@ -902,6 +906,7 @@ aips3: bus@30800000 { #size-cells = <1>; reg = <0x30800000 0x400000>; ranges; + bootph-pre-ram; spba-bus@30800000 { compatible = "fsl,spba-bus", "simple-bus"; diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi index 880b9a4f32b0..1355feda1aa7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi @@ -41,6 +41,34 @@ cpu0: cpu@f00 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; + clocks = <&smc1 IMX7ULP_CLK_ARM>, + <&scg1 IMX7ULP_CLK_CORE>, + <&scg1 IMX7ULP_CLK_SYS_SEL>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE>, + <&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>, + <&scg1 IMX7ULP_CLK_FIRC>; + clock-names = "arm", "core", "scs_sel", + "hsrun_core", "hsrun_scs_sel", + "firc"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-500210000 { + opp-hz = /bits/ 64 <500210000>; + opp-microvolt = <1025000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1125000>; + clock-latency-ns = <150000>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi index 65fde4f52587..1fda60d62ffe 100644 --- a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -95,6 +95,7 @@ reg_mba6ul_3v3: regulator-mba6ul-3v3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; + bootph-pre-ram; }; reg_mba6ul_5v0: regulator-mba6ul-5v0 { @@ -336,6 +337,7 @@ &sai1 { &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + bootph-pre-ram; status = "okay"; }; @@ -392,6 +394,7 @@ &usdhc1 { no-1-8-v; no-mmc; no-sdio; + bootph-all; status = "okay"; }; @@ -399,6 +402,7 @@ &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog1>; fsl,ext-reset-output; + bootph-pre-ram; status = "okay"; }; @@ -494,6 +498,7 @@ pinctrl_uart1: uart1grp { MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; + bootph-pre-ram; }; pinctrl_uart3: uart3grp { @@ -542,6 +547,7 @@ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 /* CD */ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 >; + bootph-all; }; pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts b/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts index e372e9327a47..38be7dfabcc0 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts @@ -116,7 +116,7 @@ leds { pinctrl-names = "default"; pinctrl-0 = <&led_pin_gpio2_1>; - user { + led-user { label = "green"; gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23.dtsi b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi index 5e21252fb7c9..58575e2c1ca5 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi @@ -420,9 +420,9 @@ dma_apbx: dma-controller@80024000 { <60>, <58>, <9>, <0>, <0>, <0>, <0>, <0>; interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", - "saif0", "empty", "auart0-rx", "auart0-tx", - "auart1-rx", "auart1-tx", "saif1", "empty", - "empty", "empty", "empty", "empty"; + "saif0", "empty0", "auart0-rx", "auart0-tx", + "auart1-rx", "auart1-tx", "saif1", "empty1", + "empty2", "empty3", "empty4", "empty5"; #dma-cells = <1>; dma-channels = <16>; clocks = <&clks 16>; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts index 6c87266eb135..63bbaa15c54d 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts @@ -29,7 +29,7 @@ reg_can0_vcc: regulator-1 { leds { compatible = "gpio-leds"; - user { + led-user { label = "Heartbeat"; gpios = <&gpio0 21 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts index 0d845ca81e89..774eb49cfbc0 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-apx4devkit.dts @@ -31,7 +31,7 @@ sound { leds { compatible = "gpio-leds"; - user { + led-user { label = "Heartbeat"; gpios = <&gpio3 28 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts index f170df37b3f8..f4485334e9f8 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10036.dts @@ -21,7 +21,7 @@ leds { pinctrl-names = "default"; pinctrl-0 = <&led_pins_cfa10036>; - power { + led-power { gpios = <&gpio3 4 1>; default-state = "on"; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts index f0ce897b9d5c..dfe3f08426ac 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts @@ -107,7 +107,7 @@ hx8357: hx8357@0 { spi-max-frequency = <100000>; spi-cpol; spi-cpha; - gpios-reset = <&gpio3 30 0>; + reset-gpios = <&gpio3 30 0>; im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts index cb68edd6101b..aeac1d29058d 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10055.dts @@ -33,7 +33,7 @@ hx8357: hx8357@0 { spi-max-frequency = <100000>; spi-cpol; spi-cpha; - gpios-reset = <&gpio3 30 0>; + reset-gpios = <&gpio3 30 0>; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts index bc2d6fcad12f..add6a23728e7 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10056.dts @@ -32,7 +32,7 @@ hx8369: hx8369@0 { spi-max-frequency = <100000>; spi-cpol; spi-cpha; - gpios-reset = <&gpio3 30 0>; + reset-gpios = <&gpio3 30 0>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts index b73020ff1053..5e3f09109605 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-485.dts @@ -12,12 +12,12 @@ / { compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; leds { - rs485-red { + led-rs485-red { label = "duckbill:red:rs485"; gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; }; - rs485-green { + led-rs485-green { label = "duckbill:green:rs485"; gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts index 473d99b9b42f..2168a59a33b3 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2-enocean.dts @@ -13,17 +13,17 @@ / { compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; leds { - enocean-blue { + led-enocean-blue { label = "duckbill:blue:enocean"; gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; }; - enocean-red { + led-enocean-red { label = "duckbill:red:enocean"; gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; }; - enocean-green { + led-enocean-green { label = "duckbill:green:enocean"; gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts index 4e28212e9626..9bc703e7b2bc 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill-2.dts @@ -31,13 +31,13 @@ leds { pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - status-red { + led-status-red { label = "duckbill:red:status"; gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - status-green { + led-status-green { label = "duckbill:green:status"; gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts index 13ffd533fdea..d5a1983f9289 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-duckbill.dts @@ -30,13 +30,13 @@ leds { pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - status-red { + led-status-red { label = "duckbill:red:status"; gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - status-green { + led-status-green { label = "duckbill:green:status"; gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts index 330d3aff6b6c..d1ff001b4037 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-evk.dts @@ -108,7 +108,7 @@ leds { pinctrl-names = "default"; pinctrl-0 = <&led_pin_gpio3_5>; - user { + led-user { label = "Heartbeat"; gpios = <&gpio3 5 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts index 34b4d3246db1..0f2bfb4845a9 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts @@ -27,13 +27,13 @@ leds { pinctrl-names = "default"; pinctrl-0 = <&led_pins_gpio>; - user1 { + led-user1 { label = "sd0-led"; gpios = <&gpio2 26 0>; linux,default-trigger = "mmc0"; }; - user2 { + led-user2 { label = "sd1-led"; gpios = <&gpio2 24 0>; linux,default-trigger = "mmc2"; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts index ca62e7933116..9e19c63a4d51 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts @@ -127,7 +127,7 @@ &ssp2 { flash: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "everspin,mr25h256", "mr25h256"; + compatible = "everspin,mr25h256"; spi-max-frequency = <40000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts index 9290635352f1..197eba22f39c 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts @@ -20,11 +20,6 @@ aliases { ds1339 = &ds1339; gpio5 = &gpio5; lcdif = &lcdif; - lcdif_23bit_pins = &tx28_lcdif_23bit_pins; - lcdif_24bit_pins = &lcdif_24bit_pins_a; - reg_can_xcvr = ®_can_xcvr; - spi_gpio = &spi_gpio; - spi_mxs = &ssp3; stk5led = &user_led; usbotg = &usb0; }; @@ -122,7 +117,7 @@ sound { leds { compatible = "gpio-leds"; - user_led: user { + user_led: led-user { label = "Heartbeat"; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -280,7 +275,7 @@ gpio5: pca953x@20 { }; polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&tx28_edt_ft5x06_pins>; diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index c7873dcef154..32a44b02d2fa 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -14,8 +14,6 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8064-asus-nexus7-flo.dtb \ qcom-apq8064-lg-nexus4-mako.dtb \ qcom-apq8074-dragonboard.dtb \ - qcom-apq8084-ifc6540.dtb \ - qcom-apq8084-mtp.dtb \ qcom-ipq4018-ap120c-ac.dtb \ qcom-ipq4018-ap120c-ac-bit.dtb \ qcom-ipq4018-jalapeno.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts deleted file mode 100644 index 1df24c922be9..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-apq8084-ifc6540.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8084.dtsi" -#include "pma8084.dtsi" - -/ { - model = "Qualcomm APQ8084/IFC6540"; - compatible = "qcom,apq8084-sbc", "qcom,apq8084"; - - aliases { - serial0 = &blsp2_uart2; - usid0 = &pma8084_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f995e000 { - status = "okay"; - }; - }; -}; - -&sdhc_1 { - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&sdhc_2 { - cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; - bus-width = <4>; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts deleted file mode 100644 index d4e6aee034af..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-apq8084-mtp.dts +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include "qcom-apq8084.dtsi" -#include "pma8084.dtsi" - -/ { - model = "Qualcomm APQ 8084-MTP"; - compatible = "qcom,apq8084-mtp", "qcom,apq8084"; - - aliases { - serial0 = &blsp2_uart2; - usid0 = &pma8084_0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - soc { - serial@f995e000 { - status = "okay"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi deleted file mode 100644 index cee0694ef127..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ /dev/null @@ -1,852 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "Qualcomm APQ 8084"; - compatible = "qcom,apq8084"; - interrupt-parent = <&intc>; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_mem: smem-region@fa00000 { - reg = <0xfa00000 0x200000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <0>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&l2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; - cpu-idle-states = <&cpu_spc>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <1>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&l2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; - cpu-idle-states = <&cpu_spc>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <2>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&l2>; - qcom,acc = <&acc2>; - qcom,saw = <&saw2>; - cpu-idle-states = <&cpu_spc>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "qcom,krait"; - reg = <3>; - enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&l2>; - qcom,acc = <&acc3>; - qcom,saw = <&saw3>; - cpu-idle-states = <&cpu_spc>; - }; - - l2: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - qcom,saw = <&saw_l2>; - }; - - idle-states { - cpu_spc: cpu-spc { - compatible = "qcom,idle-state-spc", - "arm,idle-state"; - entry-latency-us = <150>; - exit-latency-us = <200>; - min-residency-us = <2000>; - }; - }; - }; - - memory { - device_type = "memory"; - reg = <0x0 0x0>; - }; - - firmware { - scm { - compatible = "qcom,scm-apq8084", "qcom,scm"; - clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; - clock-names = "core", "bus", "iface"; - }; - }; - - thermal-zones { - cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 5>; - - trips { - cpu_alert0: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 6>; - - trips { - cpu_alert1: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit1: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 7>; - - trips { - cpu_alert2: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit2: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; - - thermal-sensors = <&tsens 8>; - - trips { - cpu_alert3: trip0 { - temperature = <75000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit3: trip1 { - temperature = <110000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible = "qcom,krait-pmu"; - interrupts = ; - }; - - clocks { - xo_board: xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - }; - - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <19200000>; - }; - - smem { - compatible = "qcom,smem"; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - memory-region = <&smem_mem>; - - hwlocks = <&tcsr_mutex 3>; - }; - - soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "simple-bus"; - - intc: interrupt-controller@f9000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0xf9000000 0x1000>, - <0xf9002000 0x1000>; - }; - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - sram@fc190000 { - compatible = "qcom,apq8084-rpm-stats"; - reg = <0xfc190000 0x10000>; - }; - - qfprom: efuse@fc4bc000 { - compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; - reg = <0xfc4bc000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - tsens_base1: base1@d0 { - reg = <0xd0 0x1>; - bits = <0 8>; - }; - - tsens_s0_p1: s0-p1@d1 { - reg = <0xd1 0x1>; - bits = <0 6>; - }; - - tsens_s1_p1: s1-p1@d2 { - reg = <0xd1 0x2>; - bits = <6 6>; - }; - - tsens_s2_p1: s2-p1@d2 { - reg = <0xd2 0x2>; - bits = <4 6>; - }; - - tsens_s3_p1: s3-p1@d3 { - reg = <0xd3 0x1>; - bits = <2 6>; - }; - - tsens_s4_p1: s4-p1@d4 { - reg = <0xd4 0x1>; - bits = <0 6>; - }; - - tsens_s5_p1: s5-p1@d4 { - reg = <0xd4 0x2>; - bits = <6 6>; - }; - - tsens_s6_p1: s6-p1@d5 { - reg = <0xd5 0x2>; - bits = <4 6>; - }; - - tsens_s7_p1: s7-p1@d6 { - reg = <0xd6 0x1>; - bits = <2 6>; - }; - - tsens_s8_p1: s8-p1@d7 { - reg = <0xd7 0x1>; - bits = <0 6>; - }; - - tsens_mode: mode@d7 { - reg = <0xd7 0x1>; - bits = <6 2>; - }; - - tsens_s9_p1: s9-p1@d8 { - reg = <0xd8 0x1>; - bits = <0 6>; - }; - - tsens_s10_p1: s10-p1@d8 { - reg = <0xd8 0x2>; - bits = <6 6>; - }; - - tsens_base2: base2@d9 { - reg = <0xd9 0x2>; - bits = <4 8>; - }; - - tsens_s0_p2: s0-p2@da { - reg = <0xda 0x2>; - bits = <4 6>; - }; - - tsens_s1_p2: s1-p2@db { - reg = <0xdb 0x1>; - bits = <2 6>; - }; - - tsens_s2_p2: s2-p2@dc { - reg = <0xdc 0x1>; - bits = <0 6>; - }; - - tsens_s3_p2: s3-p2@dc { - reg = <0xdc 0x2>; - bits = <6 6>; - }; - - tsens_s4_p2: s4-p2@dd { - reg = <0xdd 0x2>; - bits = <4 6>; - }; - - tsens_s5_p2: s5-p2@de { - reg = <0xde 0x2>; - bits = <2 6>; - }; - - tsens_s6_p2: s6-p2@df { - reg = <0xdf 0x1>; - bits = <0 6>; - }; - - tsens_s7_p2: s7-p2@e0 { - reg = <0xe0 0x1>; - bits = <0 6>; - }; - - tsens_s8_p2: s8-p2@e0 { - reg = <0xe0 0x2>; - bits = <6 6>; - }; - - tsens_s9_p2: s9-p2@e1 { - reg = <0xe1 0x2>; - bits = <4 6>; - }; - - tsens_s10_p2: s10-p2@e2 { - reg = <0xe2 0x2>; - bits = <2 6>; - }; - - tsens_s5_p2_backup: s5-p2-backup@e3 { - reg = <0xe3 0x2>; - bits = <0 6>; - }; - - tsens_mode_backup: mode-backup@e3 { - reg = <0xe3 0x1>; - bits = <6 2>; - }; - - tsens_s6_p2_backup: s6-p2-backup@e4 { - reg = <0xe4 0x1>; - bits = <0 6>; - }; - - tsens_s7_p2_backup: s7-p2-backup@e4 { - reg = <0xe4 0x2>; - bits = <6 6>; - }; - - tsens_s8_p2_backup: s8-p2-backup@e5 { - reg = <0xe5 0x2>; - bits = <4 6>; - }; - - tsens_s9_p2_backup: s9-p2-backup@e6 { - reg = <0xe6 0x2>; - bits = <2 6>; - }; - - tsens_s10_p2_backup: s10-p2-backup@e7 { - reg = <0xe7 0x1>; - bits = <0 6>; - }; - - tsens_base1_backup: base1-backup@440 { - reg = <0x440 0x1>; - bits = <0 8>; - }; - - tsens_s0_p1_backup: s0-p1-backup@441 { - reg = <0x441 0x1>; - bits = <0 6>; - }; - - tsens_s1_p1_backup: s1-p1-backup@442 { - reg = <0x441 0x2>; - bits = <6 6>; - }; - - tsens_s2_p1_backup: s2-p1-backup@442 { - reg = <0x442 0x2>; - bits = <4 6>; - }; - - tsens_s3_p1_backup: s3-p1-backup@443 { - reg = <0x443 0x1>; - bits = <2 6>; - }; - - tsens_s4_p1_backup: s4-p1-backup@444 { - reg = <0x444 0x1>; - bits = <0 6>; - }; - - tsens_s5_p1_backup: s5-p1-backup@444 { - reg = <0x444 0x2>; - bits = <6 6>; - }; - - tsens_s6_p1_backup: s6-p1-backup@445 { - reg = <0x445 0x2>; - bits = <4 6>; - }; - - tsens_s7_p1_backup: s7-p1-backup@446 { - reg = <0x446 0x1>; - bits = <2 6>; - }; - - tsens_use_backup: use-backup@447 { - reg = <0x447 0x1>; - bits = <5 3>; - }; - - tsens_s8_p1_backup: s8-p1-backup@448 { - reg = <0x448 0x1>; - bits = <0 6>; - }; - - tsens_s9_p1_backup: s9-p1-backup@448 { - reg = <0x448 0x2>; - bits = <6 6>; - }; - - tsens_s10_p1_backup: s10-p1-backup@449 { - reg = <0x449 0x2>; - bits = <4 6>; - }; - - tsens_base2_backup: base2-backup@44a { - reg = <0x44a 0x2>; - bits = <2 8>; - }; - - tsens_s0_p2_backup: s0-p2-backup@44b { - reg = <0x44b 0x3>; - bits = <2 6>; - }; - - tsens_s1_p2_backup: s1-p2-backup@44c { - reg = <0x44c 0x1>; - bits = <0 6>; - }; - - tsens_s2_p2_backup: s2-p2-backup@44c { - reg = <0x44c 0x2>; - bits = <6 6>; - }; - - tsens_s3_p2_backup: s3-p2-backup@44d { - reg = <0x44d 0x2>; - bits = <4 6>; - }; - - tsens_s4_p2_backup: s4-p2-backup@44e { - reg = <0x44e 0x1>; - bits = <2 6>; - }; - }; - - tsens: thermal-sensor@fc4a9000 { - compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; - reg = <0xfc4a9000 0x1000>, /* TM */ - <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_mode>, - <&tsens_base1>, <&tsens_base2>, - <&tsens_use_backup>, - <&tsens_mode_backup>, - <&tsens_base1_backup>, <&tsens_base2_backup>, - <&tsens_s0_p1>, <&tsens_s0_p2>, - <&tsens_s1_p1>, <&tsens_s1_p2>, - <&tsens_s2_p1>, <&tsens_s2_p2>, - <&tsens_s3_p1>, <&tsens_s3_p2>, - <&tsens_s4_p1>, <&tsens_s4_p2>, - <&tsens_s5_p1>, <&tsens_s5_p2>, - <&tsens_s6_p1>, <&tsens_s6_p2>, - <&tsens_s7_p1>, <&tsens_s7_p2>, - <&tsens_s8_p1>, <&tsens_s8_p2>, - <&tsens_s9_p1>, <&tsens_s9_p2>, - <&tsens_s10_p1>, <&tsens_s10_p2>, - <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, - <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, - <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, - <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, - <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, - <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, - <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, - <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, - <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, - <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, - <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; - nvmem-cell-names = "mode", - "base1", "base2", - "use_backup", - "mode_backup", - "base1_backup", "base2_backup", - "s0_p1", "s0_p2", - "s1_p1", "s1_p2", - "s2_p1", "s2_p2", - "s3_p1", "s3_p2", - "s4_p1", "s4_p2", - "s5_p1", "s5_p2", - "s6_p1", "s6_p2", - "s7_p1", "s7_p2", - "s8_p1", "s8_p2", - "s9_p1", "s9_p2", - "s10_p1", "s10_p2", - "s0_p1_backup", "s0_p2_backup", - "s1_p1_backup", "s1_p2_backup", - "s2_p1_backup", "s2_p2_backup", - "s3_p1_backup", "s3_p2_backup", - "s4_p1_backup", "s4_p2_backup", - "s5_p1_backup", "s5_p2_backup", - "s6_p1_backup", "s6_p2_backup", - "s7_p1_backup", "s7_p2_backup", - "s8_p1_backup", "s8_p2_backup", - "s9_p1_backup", "s9_p2_backup", - "s10_p1_backup", "s10_p2_backup"; - #qcom,sensors = <11>; - interrupts = ; - interrupt-names = "uplow"; - #thermal-sensor-cells = <1>; - }; - timer@f9020000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xf9020000 0x1000>; - clock-frequency = <19200000>; - - frame@f9021000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xf9021000 0x1000>, - <0xf9022000 0x1000>; - }; - - frame@f9023000 { - frame-number = <1>; - interrupts = ; - reg = <0xf9023000 0x1000>; - status = "disabled"; - }; - - frame@f9024000 { - frame-number = <2>; - interrupts = ; - reg = <0xf9024000 0x1000>; - status = "disabled"; - }; - - frame@f9025000 { - frame-number = <3>; - interrupts = ; - reg = <0xf9025000 0x1000>; - status = "disabled"; - }; - - frame@f9026000 { - frame-number = <4>; - interrupts = ; - reg = <0xf9026000 0x1000>; - status = "disabled"; - }; - - frame@f9027000 { - frame-number = <5>; - interrupts = ; - reg = <0xf9027000 0x1000>; - status = "disabled"; - }; - - frame@f9028000 { - frame-number = <6>; - interrupts = ; - reg = <0xf9028000 0x1000>; - status = "disabled"; - }; - }; - - saw0: power-manager@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; - - saw1: power-manager@f9099000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; - }; - - saw2: power-manager@f90a9000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw3: power-manager@f90b9000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; - }; - - saw_l2: power-manager@f9012000 { - compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2"; - reg = <0xf9012000 0x1000>; - }; - - acc0: power-manager@f9088000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9088000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc1: power-manager@f9098000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf9098000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc2: power-manager@f90a8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90a8000 0x1000>, - <0xf9008000 0x1000>; - }; - - acc3: power-manager@f90b8000 { - compatible = "qcom,kpss-acc-v2"; - reg = <0xf90b8000 0x1000>, - <0xf9008000 0x1000>; - }; - - restart@fc4ab000 { - compatible = "qcom,pshold"; - reg = <0xfc4ab000 0x4>; - }; - - gcc: clock-controller@fc400000 { - compatible = "qcom,gcc-apq8084"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - reg = <0xfc400000 0x4000>; - clocks = <&xo_board>, - <&sleep_clk>, - <0>, /* ufs */ - <0>, - <0>, - <0>, - <0>, /* sata */ - <0>, - <0>; /* pcie */ - clock-names = "xo", - "sleep_clk", - "ufs_rx_symbol_0_clk_src", - "ufs_rx_symbol_1_clk_src", - "ufs_tx_symbol_0_clk_src", - "ufs_tx_symbol_1_clk_src", - "sata_asic0_clk", - "sata_rx_clk", - "pcie_pipe"; - }; - - tcsr_mutex: hwlock@fd484000 { - compatible = "qcom,apq8084-tcsr-mutex", "qcom,tcsr-mutex"; - reg = <0xfd484000 0x1000>; - #hwlock-cells = <1>; - }; - - rpm_msg_ram: sram@fc428000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0xfc428000 0x4000>; - }; - - tlmm: pinctrl@fd510000 { - compatible = "qcom,apq8084-pinctrl"; - reg = <0xfd510000 0x4000>; - gpio-controller; - gpio-ranges = <&tlmm 0 0 147>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - - blsp2_uart2: serial@f995e000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xf995e000 0x1000>; - interrupts = ; - clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; - - sdhc_1: mmc@f9824900 { - compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; - reg-names = "hc", "core"; - interrupts = , ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - status = "disabled"; - }; - - sdhc_2: mmc@f98a4900 { - compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; - reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; - reg-names = "hc", "core"; - interrupts = , ; - interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; - clock-names = "iface", "core", "xo"; - status = "disabled"; - }; - - spmi_bus: spmi@fc4cf000 { - compatible = "qcom,spmi-pmic-arb"; - reg-names = "core", "intr", "cnfg"; - reg = <0xfc4cf000 0x1000>, - <0xfc4cb000 0x1000>, - <0xfc4ca000 0x1000>; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - }; - - rpm: remoteproc { - compatible = "qcom,apq8084-rpm-proc", "qcom,rpm-proc"; - - smd-edge { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm-requests { - compatible = "qcom,rpm-apq8084", "qcom,smd-rpm"; - qcom,smd-channels = "rpm_requests"; - - regulators-0 { - compatible = "qcom,rpm-pma8084-regulators"; - - pma8084_s1: s1 {}; - pma8084_s2: s2 {}; - pma8084_s3: s3 {}; - pma8084_s4: s4 {}; - pma8084_s5: s5 {}; - pma8084_s6: s6 {}; - pma8084_s7: s7 {}; - pma8084_s8: s8 {}; - pma8084_s9: s9 {}; - pma8084_s10: s10 {}; - pma8084_s11: s11 {}; - pma8084_s12: s12 {}; - - pma8084_l1: l1 {}; - pma8084_l2: l2 {}; - pma8084_l3: l3 {}; - pma8084_l4: l4 {}; - pma8084_l5: l5 {}; - pma8084_l6: l6 {}; - pma8084_l7: l7 {}; - pma8084_l8: l8 {}; - pma8084_l9: l9 {}; - pma8084_l10: l10 {}; - pma8084_l11: l11 {}; - pma8084_l12: l12 {}; - pma8084_l13: l13 {}; - pma8084_l14: l14 {}; - pma8084_l15: l15 {}; - pma8084_l16: l16 {}; - pma8084_l17: l17 {}; - pma8084_l18: l18 {}; - pma8084_l19: l19 {}; - pma8084_l20: l20 {}; - pma8084_l21: l21 {}; - pma8084_l22: l22 {}; - pma8084_l23: l23 {}; - pma8084_l24: l24 {}; - pma8084_l25: l25 {}; - pma8084_l26: l26 {}; - pma8084_l27: l27 {}; - - pma8084_lvs1: lvs1 {}; - pma8084_lvs2: lvs2 {}; - pma8084_lvs3: lvs3 {}; - pma8084_lvs4: lvs4 {}; - - pma8084_5vs1: 5vs1 {}; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi deleted file mode 100644 index 9d06255104c7..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-ipq8062-smb208.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "qcom-ipq8062.dtsi" - -&rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi deleted file mode 100644 index 5d3ebd3e2e51..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include "qcom-ipq8064-v2.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8062"; - compatible = "qcom,ipq8062", "qcom,ipq8064"; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi deleted file mode 100644 index ac9c44f0c164..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-smb208.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8064.dtsi" - -&rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi deleted file mode 100644 index 0442580b22de..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-v2.0-smb208.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8064-v2.0.dtsi" - -&rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = < 800000>; - regulator-max-microvolt = <1250000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi deleted file mode 100644 index 803e6ff99ef8..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-ipq8065-smb208.dtsi +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8065.dtsi" - -&rpm { - smb208_regulators: regulators { - compatible = "qcom,rpm-smb208-regulators"; - - smb208_s1a: s1a { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s1b: s1b { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1150000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2a: s2a { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; - - qcom,switch-mode-frequency = <1200000>; - }; - - smb208_s2b: s2b { - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1275000>; - - qcom,switch-mode-frequency = <1200000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi deleted file mode 100644 index ea49f6cc416d..000000000000 --- a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include "qcom-ipq8064-v2.0.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. IPQ8065"; - compatible = "qcom,ipq8065", "qcom,ipq8064"; -}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 2a82ddce94a2..95be1d2e214f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -1115,9 +1115,6 @@ bimc: interconnect@fc380000 { reg = <0xfc380000 0x6a000>; compatible = "qcom,msm8974-bimc"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_BIMC_CLK>, - <&rpmcc RPM_SMD_BIMC_A_CLK>; }; gcc: clock-controller@fc400000 { @@ -1162,45 +1159,32 @@ snoc: interconnect@fc460000 { reg = <0xfc460000 0x4000>; compatible = "qcom,msm8974-snoc"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; }; pnoc: interconnect@fc468000 { reg = <0xfc468000 0x4000>; compatible = "qcom,msm8974-pnoc"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_PNOC_CLK>, - <&rpmcc RPM_SMD_PNOC_A_CLK>; }; ocmemnoc: interconnect@fc470000 { reg = <0xfc470000 0x4000>; compatible = "qcom,msm8974-ocmemnoc"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, - <&rpmcc RPM_SMD_OCMEMGX_A_CLK>; }; mmssnoc: interconnect@fc478000 { reg = <0xfc478000 0x4000>; compatible = "qcom,msm8974-mmssnoc"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&mmcc MMSS_S0_AXI_CLK>, - <&mmcc MMSS_S0_AXI_CLK>; + clocks = <&mmcc MMSS_S0_AXI_CLK>; + clock-names = "bus"; }; cnoc: interconnect@fc480000 { reg = <0xfc480000 0x4000>; compatible = "qcom,msm8974-cnoc"; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; - clocks = <&rpmcc RPM_SMD_CNOC_CLK>, - <&rpmcc RPM_SMD_CNOC_A_CLK>; }; tsens: thermal-sensor@fc4a9000 { @@ -2223,6 +2207,7 @@ sram@fdd00000 { <0xfec00000 0x180000>; reg-names = "ctrl", "mem"; ranges = <0 0xfec00000 0x180000>; + /* core clock doesn't exist anymore, kept for ABI compliance */ clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, <&mmcc OCMEMCX_OCMEMNOC_CLK>; clock-names = "core", "iface"; diff --git a/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts index f69a7fe56b6e..55221c82ef64 100644 --- a/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts +++ b/arch/arm/boot/dts/renesas/r7s9210-rza2mevb.dts @@ -94,8 +94,7 @@ ðer1 { renesas,no-ether-link; phy-handle = <&phy1>; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c816", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c816"; reg = <0>; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts index 04d24b6d8056..1d56bdef5453 100644 --- a/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts @@ -65,6 +65,17 @@ vccq_sdhi0: regulator-vccq-sdhi0 { enable-active-high; }; + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pfc 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_5p0v: regulator-5p0v { compatible = "regulator-fixed"; regulator-name = "fixed-5.0V"; @@ -228,6 +239,7 @@ touchscreen@55 { pinctrl-0 = <&st1232_pins>; pinctrl-names = "default"; gpios = <&pfc 166 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; @@ -285,6 +297,11 @@ sdhi0_pins: sd0 { function = "sdhi0"; }; + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl", "sdhi1_cd", "sdhi1_wp"; + function = "sdhi1"; + }; + fsia_pins: sounda { groups = "fsia_sclk_in", "fsia_mclk_out", "fsia_data_in_1", "fsia_data_out_0"; @@ -302,6 +319,12 @@ lcd0-mux-hog { gpios = <176 0>; output-high; }; + + sdhi1-select-hog { + gpio-hog; + gpios = <6 0>; + input; + }; }; &tpu { @@ -336,6 +359,15 @@ &sdhi0 { status = "okay"; }; +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi1>; + bus-width = <4>; + status = "okay"; +}; + &sh_fsi2 { pinctrl-0 = <&fsia_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts index 33ac4bd1e63b..c43c08d9ff94 100644 --- a/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/renesas/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -85,8 +85,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1560", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1560"; reg = <1>; micrel,led-mode = <1>; }; diff --git a/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts b/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts index 9b16fe7ce713..60217797e534 100644 --- a/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts +++ b/arch/arm/boot/dts/renesas/r8a7743-sk-rzg1m.dts @@ -70,8 +70,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc 0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts index 571615a50620..42e82f069755 100644 --- a/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/renesas/r8a7745-sk-rzg1e.dts @@ -65,8 +65,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc 8 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7790-lager.dts b/arch/arm/boot/dts/renesas/r8a7790-lager.dts index 4f002aa7fbaf..8e7665501675 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-lager.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-lager.dts @@ -685,8 +685,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc0 0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7790-stout.dts b/arch/arm/boot/dts/renesas/r8a7790-stout.dts index b1e20579e071..8ba9d85f1038 100644 --- a/arch/arm/boot/dts/renesas/r8a7790-stout.dts +++ b/arch/arm/boot/dts/renesas/r8a7790-stout.dts @@ -208,8 +208,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc0 1 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts index 61ea438eb6af..48db62e0ff87 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-koelsch.dts @@ -676,8 +676,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc0 0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts index 81b3c5d74e9b..811e263452ac 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-porter.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts @@ -326,8 +326,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc0 0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7793-gose.dts b/arch/arm/boot/dts/renesas/r8a7793-gose.dts index 5c6928c941ac..69d9c674bb03 100644 --- a/arch/arm/boot/dts/renesas/r8a7793-gose.dts +++ b/arch/arm/boot/dts/renesas/r8a7793-gose.dts @@ -616,8 +616,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc0 0 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7794-alt.dts b/arch/arm/boot/dts/renesas/r8a7794-alt.dts index 3f06a7f67d62..5d6d0d8cc4dd 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-alt.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-alt.dts @@ -378,8 +378,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc0 8 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r8a7794-silk.dts b/arch/arm/boot/dts/renesas/r8a7794-silk.dts index 342825605768..af474b1d9676 100644 --- a/arch/arm/boot/dts/renesas/r8a7794-silk.dts +++ b/arch/arm/boot/dts/renesas/r8a7794-silk.dts @@ -412,8 +412,7 @@ ðer { status = "okay"; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupts-extended = <&irqc0 8 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <1>; diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts index 4a72aa7663f2..5626d7fd6c3e 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -185,6 +185,18 @@ fixed-link { }; }; +&gpioirqmux { + interrupt-map = <89 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* pin 147: phy@4 */ + <91 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* pin 149: phy@5 */ + status = "okay"; +}; + +&gpio2 { + pinctrl-0 = <&pins_gpio2>; + pinctrl-names = "default"; + status = "okay"; +}; + &i2c2 { pinctrl-0 = <&pins_i2c2>; pinctrl-names = "default"; @@ -237,13 +249,13 @@ &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&pins_cpld>; - pins_can0: pins_can0 { + pins_can0: pins-can0 { pinmux = , /* CAN0_TXD */ ; /* CAN0_RXD */ drive-strength = <6>; }; - pins_can1: pins_can1 { + pins_can1: pins-can1 { pinmux = , /* CAN1_TXD */ ; /* CAN1_RXD */ drive-strength = <6>; @@ -256,7 +268,7 @@ pins_cpld: pins-cpld { ; }; - pins_eth3: pins_eth3 { + pins_eth3: pins-eth3 { pinmux = , , , @@ -273,7 +285,7 @@ pins_eth3: pins_eth3 { bias-disable; }; - pins_eth4: pins_eth4 { + pins_eth4: pins-eth4 { pinmux = , , , @@ -290,16 +302,101 @@ pins_eth4: pins_eth4 { bias-disable; }; - pins_i2c2: pins_i2c2 { + pins_gpio2: pins-gpio2 { + pinmux = , + ; + drive-strength = <6>; + bias-pull-up; + }; + + pins_i2c2: pins-i2c2 { pinmux = , ; drive-strength = <12>; }; - pins_mdio1: pins_mdio1 { + pins_mdio1: pins-mdio1 { pinmux = , ; }; + + pins_qspi0: pins-qspi0 { + pinmux = , + , + , + , + , + ; + bias-disable; + }; +}; + +&qspi0 { + pinctrl-0 = <&pins_qspi0>; + pinctrl-names = "default"; + status = "okay"; + bootph-all; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <62500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <200>; + cdns,tsd2d-ns = <255>; + cdns,tchsh-ns = <20>; + cdns,tslch-ns = <20>; + bootph-all; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + /* 64KiB */ + label = "spl"; + reg = <0x0000000 0x00010000>; + }; + partition@10000 { + /* 64KiB */ + label = "pkgt"; + reg = <0x0010000 0x00010000>; + }; + partition@20000 { + /* 512KiB */ + label = "u-boot"; + reg = <0x0020000 0x00080000>; + }; + partition@a0000 { + /* 64KiB */ + label = "env"; + reg = <0x00a0000 0x00010000>; + }; + partition@b0000 { + /* 128KiB */ + label = "dtb"; + reg = <0x00b0000 0x00020000>; + }; + partition@d0000 { + /* 1MiB */ + label = "cm3"; + reg = <0x00d0000 0x00100000>; + }; + partition@1d0000 { + /* 6MiB */ + label = "kernel"; + reg = <0x01d0000 0x00600000>; + }; + partition@7d0000 { + /* Remaining */ + label = "data"; + reg = <0x07d0000 0x1830000>; + }; + }; + }; }; &rtc0 { @@ -323,11 +420,13 @@ mdio { switch0phy4: ethernet-phy@4 { reg = <4>; micrel,led-mode = <1>; + interrupts-extended = <&gpio2a 25 IRQ_TYPE_LEVEL_LOW>; }; switch0phy5: ethernet-phy@5 { reg = <5>; micrel,led-mode = <1>; + interrupts-extended = <&gpio2a 27 IRQ_TYPE_LEVEL_LOW>; }; }; }; diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index f4f760aff28b..442ea26b40f5 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -15,6 +15,39 @@ / { #size-cells = <1>; interrupt-parent = <&gic>; + /* + * The CPUs clock is based on the 'ref' clock (output of OPPDIV divisor) + * with x1, x2 or x4 ratio between the CPUs clock frequency and this + * 'ref' clock frequency. + * + * The table below is built on the assumption that the 'ref' clock + * frequency is set to 500MHz which is its default value. + * + * The table should be overridden in the board device-tree file based + * on the 'ref' clock frequency if this frequency value is not the + * default one. + */ + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + /* ~35 clocks cycles at 125mhz */ + clock-latency-ns = <300>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +57,7 @@ cpu@0 { compatible = "arm,cortex-a7"; reg = <0>; clocks = <&sysctrl R9A06G032_CLK_A7MP>; + operating-points-v2 = <&cpu_opp_table>; }; cpu@1 { @@ -33,6 +67,7 @@ cpu@1 { clocks = <&sysctrl R9A06G032_CLK_A7MP>; enable-method = "renesas,r9a06g032-smp"; cpu-release-addr = <0 0x4000c204>; + operating-points-v2 = <&cpu_opp_table>; }; }; @@ -66,6 +101,18 @@ soc { #size-cells = <1>; ranges; + qspi0: spi@40005000 { + compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi"; + reg = <0x40005000 0x1000>, <0x10000000 0x10000000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>, + <&sysctrl R9A06G032_HCLK_QSPI0>; + clock-names = "ref", "ahb", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rtc0: rtc@40006000 { compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; reg = <0x40006000 0x1000>; @@ -507,6 +554,7 @@ gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller; #interrupt-cells = <3>; + #address-cells = <0>; reg = <0x44101000 0x1000>, /* Distributer */ <0x44102000 0x2000>, /* CPU interface */ <0x44104000 0x2000>, /* Virt interface control */ diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile index 716f5540e438..d0154fd7ff24 100644 --- a/arch/arm/boot/dts/rockchip/Makefile +++ b/arch/arm/boot/dts/rockchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rv1103b-omega4-evb.dtb \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ rv1109-relfor-saib.dtb \ diff --git a/arch/arm/boot/dts/rockchip/rk3036-evb.dts b/arch/arm/boot/dts/rockchip/rk3036-evb.dts index becdc0b664bf..c8100dc4c7ce 100644 --- a/arch/arm/boot/dts/rockchip/rk3036-evb.dts +++ b/arch/arm/boot/dts/rockchip/rk3036-evb.dts @@ -16,8 +16,6 @@ memory@60000000 { &emac { phy = <&phy0>; - phy-reset-duration = <10>; /* millisecond */ - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ pinctrl-names = "default"; pinctrl-0 = <&emac_xfer>, <&emac_mdio>; status = "okay"; @@ -28,6 +26,8 @@ mdio { phy0: ethernet-phy@0 { reg = <0>; + reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts index ae2f84a4e922..bc6e6468fcc4 100644 --- a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts @@ -102,8 +102,6 @@ &acodec { &emac { phy = <&phy0>; - phy-reset-duration = <10>; /* millisecond */ - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ pinctrl-names = "default"; pinctrl-0 = <&emac_xfer>, <&emac_mdio>; status = "okay"; @@ -114,6 +112,8 @@ mdio { phy0: ethernet-phy@0 { reg = <0>; + reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts index edc2b7f9112d..b56095fc2441 100644 --- a/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts @@ -262,7 +262,7 @@ lis3de: accelerometer@29 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&gsensor_int>; - rotation-matrix = "1", "0", "0", + mount-matrix = "1", "0", "0", "0", "-1", "0", "0", "0", "1"; vdd-supply = <&vcc_io>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts index a55270672732..8b491b002992 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts @@ -197,11 +197,10 @@ &hdmi { }; &i2c0 { - hym8563: hym8563@51 { + hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "xin32k"; interrupt-parent = <&gpio7>; interrupts = ; diff --git a/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts index 10ce0554d4fc..46362e804daf 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts @@ -86,6 +86,10 @@ &i2c1 { touchscreen@44 { compatible = "st,stmpe811"; reg = <0x44>; + interrupt-parent = <&gpio5>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq_pin>; }; adc@64 { @@ -94,7 +98,7 @@ adc@64 { }; i2c_rtc: rtc@68 { - compatible = "rv4162"; + compatible = "microcrystal,rv4162"; reg = <0x68>; pinctrl-names = "default"; pinctrl-0 = <&i2c_rtc_int>; @@ -121,25 +125,25 @@ leddim: leddimmer@62 { compatible = "nxp,pca9533"; reg = <0x62>; - led1 { + led-1 { label = "red:user1"; linux,default-trigger = "none"; type = ; }; - led2 { + led-2 { label = "green:user2"; linux,default-trigger = "none"; type = ; }; - led3 { + led-3 { label = "blue:user3"; linux,default-trigger = "none"; type = ; }; - led4 { + led-4 { label = "red:user4"; linux,default-trigger = "none"; type = ; @@ -199,7 +203,7 @@ sdmmc_pwr: sdmmc-pwr { touchscreen { ts_irq_pin: ts-irq-pin { - rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <5 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi index 12ab10c4adde..0816e388852f 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi @@ -100,7 +100,7 @@ &gmac { tx_delay = <0x0>; rx_delay = <0x0>; - mdio0 { + mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts index ade9cc291813..d7790eebfdcd 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts @@ -91,14 +91,12 @@ vdd10_lcd: LDO_REG7 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; }; vcc18_hdmi: SWITCH_REG2 { regulator-always-on; regulator-boot-on; regulator-name = "vcc18_hdmi"; - regulator-suspend-mem-disabled; }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts index 6a0844e16279..3da105060302 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts @@ -98,9 +98,8 @@ &gmac { snps,reset-gpio = <&gpio4 RK_PB0 0>; snps,reset-active-low; snps,reset-delays-us = <0 10000 30000>; - wakeup-source; - mdio0 { + mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; @@ -177,7 +176,7 @@ &sdio0 { #address-cells = <1>; #size-cells = <0>; - btmrvl: btmrvl@2 { + btmrvl: bluetooth@2 { compatible = "marvell,sd8897-bt"; reg = <2>; interrupt-parent = <&gpio4>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts index 0d4c50e05558..cba2898f8b7d 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts @@ -48,7 +48,7 @@ &sdio0 { #address-cells = <1>; #size-cells = <0>; - btmrvl: btmrvl@2 { + btmrvl: bluetooth@2 { compatible = "marvell,sd8897-bt"; reg = <2>; interrupt-parent = <&gpio4>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts index 6894763979f0..0bf03b1ff2ab 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts @@ -488,7 +488,7 @@ trackpad@2c { interrupts = ; reg = <0x2c>; hid-descr-addr = <0x0020>; - vcc-supply = <&vcc33_io>; + vdd-supply = <&vcc33_io>; wakeup-source; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts index d665c3e8862c..20fe84683928 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts @@ -246,7 +246,6 @@ vdd10_lcd: LDO_REG7 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; }; vcc18_lcd: LDO_REG8 { @@ -255,7 +254,6 @@ vcc18_lcd: LDO_REG8 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-name = "vcc18_lcd"; - regulator-suspend-mem-disabled; }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts index cc27d116d025..e241f93b2310 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts @@ -47,6 +47,7 @@ &lid_switch { key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + linux,code = ; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 4e5e7509de48..4f2c048aee54 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -551,7 +551,6 @@ tsadc: tsadc@ff280000 { pinctrl-1 = <&otp_out>; pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <1>; - rockchip,grf = <&grf>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts b/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts new file mode 100644 index 000000000000..c6472f933aa5 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2025 plan44.ch/luz + * Copyright (c) 2026 Onion Corporation + */ + +/dts-v1/; + +#include +#include +#include "rv1103b-omega4.dtsi" + +/ { + model = "Onion Omega4 Evaluation Board"; + compatible = "onion,omega4-evb", "onion,omega4", "rockchip,rv1103b"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "sys"; + pinctrl-names = "default"; + pinctrl-0 = <&led>; + }; + }; +}; + +&fspi0 { + status = "okay"; +}; + +&pinctrl { + leds { + led: led { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc0 { + status = "okay"; +}; + +&sdmmc1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi new file mode 100644 index 000000000000..6a8e8e0f80c5 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2025 plan44.ch/luz + * Copyright (c) 2026 Onion Corporation + */ + +/dts-v1/; + +#include "rv1103b.dtsi" + +/ { + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <300>; + reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_volt>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1 1800000 0>; + }; +}; + +&uart0 { + bootph-all; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&fspi0 { + spi_nand: flash@0 { + compatible = "spi-nand"; + reg = <0>; + bootph-pre-ram; + bootph-some-ram; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x00000000 0x00040000>; + label = "env"; + }; + + partition@40000 { + reg = <0x00040000 0x00100000>; + label = "idblock"; + read-only; + }; + + partition@140000 { + reg = <0x00140000 0x00100000>; + label = "uboot"; + read-only; + }; + + partition@240000 { + reg = <0x00240000 0x00800000>; + label = "boot"; + }; + + partition@a40000 { + reg = <0x00a40000 0x0f5c0000>; + label = "ubi"; + }; + }; + }; +}; + +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "disabled"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_cmd &sdmmc1_clk &sdmmc1_bus4>; + status = "disabled"; +}; + +&pinctrl { + sdio-pwrseq { + /omit-if-no-ref/ + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc_volt: sdmmc-volt { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + /omit-if-no-ref/ + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi new file mode 100644 index 000000000000..15516c384139 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi @@ -0,0 +1,816 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Rockchip Electronics Co., Ltd. + */ + +#include +#include + +&pinctrl { + cam-clk0 { + /omit-if-no-ref/ + cam_clk0: cam-clk0 { + rockchip,pins = + /* cam_clk0_out */ + <1 RK_PB5 1 &pcfg_pull_none>; + }; + }; + + cam-clk1 { + /omit-if-no-ref/ + cam_clk1: cam-clk1 { + rockchip,pins = + /* cam_clk1_out */ + <1 RK_PB6 1 &pcfg_pull_none>; + }; + }; + + cam-spi { + /omit-if-no-ref/ + cam_spi_bus4: cam-spi-bus4 { + rockchip,pins = + /* cam_spi_d0 */ + <0 RK_PB5 4 &pcfg_pull_up_drv_level_2>, + /* cam_spi_d1 */ + <0 RK_PB2 4 &pcfg_pull_up_drv_level_2>, + /* cam_spi_d2 */ + <0 RK_PB1 4 &pcfg_pull_up_drv_level_2>, + /* cam_spi_d3 */ + <0 RK_PB0 4 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + cam_spi_clk: cam-spi-clk { + rockchip,pins = + /* cam_spi_clk */ + <0 RK_PB4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + cam_spi_cs0n: cam-spi-cs0n { + rockchip,pins = + /* cam_spi_cs0n */ + <0 RK_PB3 4 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clk_32k: clk-32k { + rockchip,pins = + /* clk_32k */ + <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + clk-24m { + /omit-if-no-ref/ + clk_24m_out: clk-24m-out { + rockchip,pins = + /* clk_24m_out */ + <0 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu: cpu { + rockchip,pins = + /* cpu_avs */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_bus4: emmc-bus4 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_bus4: fspi-bus4 { + rockchip,pins = + /* fspi_d0 */ + <1 RK_PA1 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PA2 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PA3 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PA0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs0: fspi-cs0 { + rockchip,pins = + /* fspi_cs0n */ + <1 RK_PA5 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + fspi_clk: fspi-clk { + rockchip,pins = + /* fspi_clk */ + <1 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <0 RK_PA5 3 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <0 RK_PA6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <1 RK_PB4 5 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <1 RK_PB3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m2_xfer: i2c0m2-xfer { + rockchip,pins = + /* i2c0_scl_m2 */ + <1 RK_PB5 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m2 */ + <1 RK_PB6 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB0 1 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <2 RK_PA4 4 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <2 RK_PA5 4 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB2 1 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PB3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <2 RK_PA6 4 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <2 RK_PA7 4 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <0 RK_PB4 1 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <2 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <2 RK_PB2 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <2 RK_PB0 4 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <2 RK_PB1 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <1 RK_PB7 2 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <1 RK_PC0 2 &pcfg_pull_none_smt>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0: jtagm0 { + rockchip,pins = + /* jtag_tck_m0 */ + <0 RK_PA5 5 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <0 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1: jtagm1 { + rockchip,pins = + /* jtag_tck_m1 */ + <0 RK_PB4 3 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm2: jtagm2 { + rockchip,pins = + /* jtag_tck_m2 */ + <1 RK_PB4 3 &pcfg_pull_none>, + /* jtag_tms_m2 */ + <1 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + psram-spi { + /omit-if-no-ref/ + psram_spi_bus4: psram-spi-bus4 { + rockchip,pins = + /* psram_spi_d0 */ + <0 RK_PA2 4 &pcfg_pull_none>, + /* psram_spi_d1 */ + <0 RK_PA1 4 &pcfg_pull_none>, + /* psram_spi_d2 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* psram_spi_d3 */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + psram_spi_clk: psram-spi-clk { + rockchip,pins = + /* psram_spi_clk */ + <0 RK_PA0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + psram_spi_cs0n: psram-spi-cs0n { + rockchip,pins = + /* psram_spi_cs0n */ + <0 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_ch0: pwm0m0-ch0 { + rockchip,pins = + /* pwm0m0_ch0 */ + <0 RK_PA1 1 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m0_ch1: pwm0m0-ch1 { + rockchip,pins = + /* pwm0m0_ch1 */ + <0 RK_PA5 2 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m0_ch2: pwm0m0-ch2 { + rockchip,pins = + /* pwm0m0_ch2 */ + <0 RK_PA6 2 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m0_ch3: pwm0m0-ch3 { + rockchip,pins = + /* pwm0m0_ch3 */ + <0 RK_PA2 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m1_ch0: pwm0m1-ch0 { + rockchip,pins = + /* pwm0m1_ch0 */ + <2 RK_PA0 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m1_ch1: pwm0m1-ch1 { + rockchip,pins = + /* pwm0m1_ch1 */ + <2 RK_PA1 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m1_ch2: pwm0m1-ch2 { + rockchip,pins = + /* pwm0m1_ch2 */ + <2 RK_PA2 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m1_ch3: pwm0m1-ch3 { + rockchip,pins = + /* pwm0m1_ch3 */ + <2 RK_PB0 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m2_ch1: pwm0m2-ch1 { + rockchip,pins = + /* pwm0m2_ch1 */ + <1 RK_PB7 1 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m2_ch2: pwm0m2-ch2 { + rockchip,pins = + /* pwm0m2_ch2 */ + <1 RK_PC0 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_ch0: pwm1m0-ch0 { + rockchip,pins = + /* pwm1m0_ch0 */ + <0 RK_PB0 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m0_ch1: pwm1m0-ch1 { + rockchip,pins = + /* pwm1m0_ch1 */ + <0 RK_PB1 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m0_ch2: pwm1m0-ch2 { + rockchip,pins = + /* pwm1m0_ch2 */ + <0 RK_PB2 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m0_ch3: pwm1m0-ch3 { + rockchip,pins = + /* pwm1m0_ch3 */ + <0 RK_PB3 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm1m1_ch0: pwm1m1-ch0 { + rockchip,pins = + /* pwm1m1_ch0 */ + <2 RK_PA3 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m1_ch1: pwm1m1-ch1 { + rockchip,pins = + /* pwm1m1_ch1 */ + <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m1_ch2: pwm1m1-ch2 { + rockchip,pins = + /* pwm1m1_ch2 */ + <2 RK_PA5 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m1_ch3: pwm1m1-ch3 { + rockchip,pins = + /* pwm1m1_ch3 */ + <2 RK_PB1 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_ch0: pwm2m0-ch0 { + rockchip,pins = + /* pwm2m0_ch0 */ + <1 RK_PB0 4 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m0_ch1: pwm2m0-ch1 { + rockchip,pins = + /* pwm2m0_ch1 */ + <1 RK_PA7 4 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m0_ch2: pwm2m0-ch2 { + rockchip,pins = + /* pwm2m0_ch2 */ + <1 RK_PB4 4 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m0_ch3: pwm2m0-ch3 { + rockchip,pins = + /* pwm2m0_ch3 */ + <1 RK_PB3 4 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm2m1_ch0: pwm2m1-ch0 { + rockchip,pins = + /* pwm2m1_ch0 */ + <2 RK_PA6 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m1_ch1: pwm2m1-ch1 { + rockchip,pins = + /* pwm2m1_ch1 */ + <2 RK_PA7 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m1_ch2: pwm2m1-ch2 { + rockchip,pins = + /* pwm2m1_ch2 */ + <2 RK_PB2 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m1_ch3: pwm2m1-ch3 { + rockchip,pins = + /* pwm2m1_ch3 */ + <2 RK_PB3 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr: pwr { + rockchip,pins = + /* pwr_ctrl0 */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; + + rtc_32k { + /omit-if-no-ref/ + rtc_32k: rtc-32k { + rockchip,pins = + /* rtc_32k_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sai { + /omit-if-no-ref/ + sai: sai { + rockchip,pins = + /* sai_lrck */ + <2 RK_PB1 5 &pcfg_pull_none>, + /* sai_mclk */ + <2 RK_PB0 5 &pcfg_pull_none>, + /* sai_sclk */ + <2 RK_PA7 5 &pcfg_pull_none>, + /* sai_sdi */ + <2 RK_PA6 5 &pcfg_pull_none>, + /* sai_sdo */ + <2 RK_PB2 5 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <1 RK_PA6 1 &pcfg_pull_up>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_clk: spi0m0-clk { + rockchip,pins = + /* spi0_clk_m0 */ + <2 RK_PB0 2 &pcfg_pull_none>, + /* spi0_miso_m0 */ + <2 RK_PB3 2 &pcfg_pull_none>, + /* spi0_mosi_m0 */ + <2 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0n_m0 */ + <2 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1n_m0 */ + <2 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_clk: spi0m1-clk { + rockchip,pins = + /* spi0_clk_m1 */ + <2 RK_PA2 5 &pcfg_pull_none>, + /* spi0_miso_m1 */ + <2 RK_PA4 5 &pcfg_pull_none>, + /* spi0_mosi_m1 */ + <2 RK_PA1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0n_m1 */ + <2 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + /* spi0_cs1n_m1 */ + <2 RK_PA0 5 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PA6 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PA5 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <0 RK_PB5 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <0 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m2_xfer: uart0m2-xfer { + rockchip,pins = + /* uart0_rx_m2 */ + <1 RK_PB3 2 &pcfg_pull_up>, + /* uart0_tx_m2 */ + <1 RK_PB4 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB2 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB3 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <0 RK_PB5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <0 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <1 RK_PA7 2 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <1 RK_PB0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_xfer: uart1m2-xfer { + rockchip,pins = + /* uart1_rx_m2 */ + <2 RK_PA7 1 &pcfg_pull_up>, + /* uart1_tx_m2 */ + <2 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m2_ctsn: uart1m2-ctsn { + rockchip,pins = + /* uart1m2_ctsn */ + <2 RK_PA5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m2_rtsn: uart1m2-rtsn { + rockchip,pins = + /* uart1m2_rtsn */ + <2 RK_PA4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m3_xfer: uart1m3-xfer { + rockchip,pins = + /* uart1_rx_m3 */ + <2 RK_PA3 2 &pcfg_pull_up>, + /* uart1_tx_m3 */ + <2 RK_PA2 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m3_ctsn: uart1m3-ctsn { + rockchip,pins = + /* uart1m3_ctsn */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m3_rtsn: uart1m3-rtsn { + rockchip,pins = + /* uart1m3_rtsn */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PB1 2 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PB0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <0 RK_PB3 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <0 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <2 RK_PB1 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <2 RK_PB0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <2 RK_PB3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + /* uart2_rx_m2 */ + <1 RK_PB6 3 &pcfg_pull_up>, + /* uart2_tx_m2 */ + <1 RK_PB5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m2_ctsn: uart2m2-ctsn { + rockchip,pins = + /* uart2m2_ctsn */ + <1 RK_PC0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m2_rtsn: uart2m2-rtsn { + rockchip,pins = + /* uart2m2_rtsn */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1103b.dtsi b/arch/arm/boot/dts/rockchip/rv1103b.dtsi new file mode 100644 index 000000000000..39f78e0733c9 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1103b.dtsi @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1103b"; + + interrupt-parent = <&gic>; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&cru ARMCLK>; + device_type = "cpu"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + clock-frequency = <24000000>; + interrupts = , + ; + }; + + xin24m: oscillator-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1103b-pinctrl"; + rockchip,grf = <&ioc>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + gpio0: gpio@20520000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20520000 0x200>; + clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; + gpio-controller; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@20d80000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20d80000 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20840000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20840000 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + interrupts = ; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cru: clock-controller@20000000 { + compatible = "rockchip,rv1103b-cru"; + reg = <0x20000000 0x81000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pmu_grf: syscon@20160000 { + compatible = "rockchip,rv1103b-pmu-grf", "syscon", "simple-mfd"; + reg = <0x20160000 0x1000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; + }; + + ioc: syscon@20170000 { + compatible = "rockchip,rv1103b-ioc", "syscon"; + reg = <0x20170000 0x60000>; + }; + + gic: interrupt-controller@20411000 { + compatible = "arm,gic-400"; + reg = <0x20411000 0x1000>, + <0x20412000 0x2000>, + <0x20414000 0x2000>, + <0x20416000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + uart0: serial@20540000 { + compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; + reg = <0x20540000 0x100>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + sdmmc1: mmc@20650000 { + compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; + reg = <0x20650000 0x4000>; + clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + status = "disabled"; + }; + + uart1: serial@20870000 { + compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; + reg = <0x20870000 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@20880000 { + compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; + reg = <0x20880000 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + sdmmc0: mmc@20d20000 { + compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; + reg = <0x20d20000 0x4000>; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_det &sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>; + status = "disabled"; + }; + + emmc: mmc@20d30000 { + compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; + reg = <0x20d30000 0x4000>; + clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = ; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>; + status = "disabled"; + }; + + fspi0: spi@20d40000 { + compatible = "rockchip,sfc"; + reg = <0x20d40000 0x4000>; + clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fspi_bus4 &fspi_cs0 &fspi_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + system_sram: sram@210f6000 { + compatible = "mmio-sram"; + reg = <0x210f6000 0x8000>; + ranges = <0 0x210f6000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +#include "rv1103b-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/samsung/Makefile b/arch/arm/boot/dts/samsung/Makefile index 7becf36656b1..e0143ee8c82d 100644 --- a/arch/arm/boot/dts/samsung/Makefile +++ b/arch/arm/boot/dts/samsung/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \ exynos4412-trats2.dtb dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5250-arndale.dtb \ + exynos5250-manta.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ exynos5250-snow-rev5.dtb \ diff --git a/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi b/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi index 3fdd922e635c..059c0f44e164 100644 --- a/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi @@ -74,8 +74,6 @@ &gpu { }; &i2c_0 { - #address-cells = <1>; - #size-cells = <0>; samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; samsung,i2c-max-bus-freq = <100000>; diff --git a/arch/arm/boot/dts/samsung/exynos3250-monk.dts b/arch/arm/boot/dts/samsung/exynos3250-monk.dts index 68236c7297d7..d59ed46614bd 100644 --- a/arch/arm/boot/dts/samsung/exynos3250-monk.dts +++ b/arch/arm/boot/dts/samsung/exynos3250-monk.dts @@ -191,8 +191,6 @@ &hsotg { }; &i2c_0 { - #address-cells = <1>; - #size-cells = <0>; samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; samsung,i2c-max-bus-freq = <100000>; @@ -414,8 +412,6 @@ buck5_reg: BUCK5 { }; &i2c_1 { - #address-cells = <1>; - #size-cells = <0>; samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; samsung,i2c-max-bus-freq = <400000>; diff --git a/arch/arm/boot/dts/samsung/exynos3250-rinato.dts b/arch/arm/boot/dts/samsung/exynos3250-rinato.dts index 36d2171c1ce8..fa983b732898 100644 --- a/arch/arm/boot/dts/samsung/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/samsung/exynos3250-rinato.dts @@ -263,8 +263,6 @@ &gpu { }; &i2c_0 { - #address-cells = <1>; - #size-cells = <0>; samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; samsung,i2c-max-bus-freq = <100000>; @@ -594,8 +592,6 @@ regulator-state-mem { }; &i2c_1 { - #address-cells = <1>; - #size-cells = <0>; samsung,i2c-sda-delay = <100>; samsung,i2c-slave-addr = <0x10>; samsung,i2c-max-bus-freq = <400000>; diff --git a/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts b/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts index 18f4f494093b..a6b73a8967c6 100644 --- a/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts @@ -68,8 +68,6 @@ map1 { }; &i2c_0 { - #address-cells = <1>; - #size-cells = <0>; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <100000>; status = "okay"; diff --git a/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi index 7bc6968af9c3..223907e5919c 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-itop-scp-core.dtsi @@ -130,8 +130,6 @@ &hsotg { }; &i2c_1 { - #address-cells = <1>; - #size-cells = <0>; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <400000>; pinctrl-0 = <&i2c1_bus>; diff --git a/arch/arm/boot/dts/samsung/exynos4412-origen.dts b/arch/arm/boot/dts/samsung/exynos4412-origen.dts index 10ab7bc90f50..c5fb551ab352 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-origen.dts +++ b/arch/arm/boot/dts/samsung/exynos4412-origen.dts @@ -113,8 +113,6 @@ &fimd { }; &i2c_0 { - #address-cells = <1>; - #size-cells = <0>; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; pinctrl-0 = <&i2c0_bus>; diff --git a/arch/arm/boot/dts/samsung/exynos5250-manta.dts b/arch/arm/boot/dts/samsung/exynos5250-manta.dts new file mode 100644 index 000000000000..24a27b342227 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos5250-manta.dts @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google Manta (Nexus 10) board device tree source + * + * Copyright (c) 2023-2026 Alexandre Marquet + * Copyright (c) 2025-2026 Lukas Timmermann + */ + +/dts-v1/; +#include "exynos5250.dtsi" +#include "exynos-pinctrl.h" +#include "exynos-mfc-reserved-memory.dtsi" + +#include +#include +#include +#include + +/ { + model = "Google Nexus 10"; + compatible = "google,manta", "samsung,exynos5250", "samsung,exynos5"; + + aliases { + mmc0 = &mmc_0; /* eMMC */ + mmc1 = &mmc_1; /* WiFi */ + }; + + /* Voltage source unknown */ + bmp180_vdda_reg: regulator-bmp180-vdda { + compatible = "regulator-fixed"; + regulator-name = "BMP180_VDDA"; + }; + + /* Voltage source unknown */ + bmp180_vddd_reg: regulator-bmp180-vddd { + compatible = "regulator-fixed"; + regulator-name = "BMP180_VDDD"; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + flash-controller { + compatible = "gpio-leds"; + + led-flash { + function = LED_FUNCTION_FLASH; + color = ; + linux,default-trigger = "flash"; + gpios = <&gpe0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys>; + pinctrl-names = "default"; + + button-volume-down { + label = "Volume Down"; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <5>; + }; + + button-volume-up { + label = "Volume Up"; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <5>; + }; + + button-power { + label = "Power"; + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <5>; + wakeup-source; + }; + + lid-switch { + label = "Hall Effect Sensor"; + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + multi-led { + compatible = "leds-group-multicolor"; + color = ; + function = LED_FUNCTION_STATUS; + leds = <&status_red>, <&status_green>, <&status_blue>, <&status_white>; + }; + + pwrseq: mmc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpv1 0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&wlan_pmena>; + pinctrl-names = "default"; + + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; + + post-power-on-delay-ms = <300>; + power-off-delay-us = <50>; + }; + + firmware@204efff { + compatible = "samsung,secure-firmware"; + reg = <0x0204efff 0x1000>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>, + <0x60000000 0x20000000>, + <0x80000000 0x20000000>, + <0xa0000000 0x1ff00000>; + }; +}; + +&clock { + assigned-clocks = <&clock CLK_FOUT_APLL>; + assigned-clock-rates = <1000000000>; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu1 { + cpu-supply = <&buck2_reg>; +}; + +&ehci { + status = "disabled"; +}; + +&i2c_1 { + status = "okay"; + + pressure-sensor@77 { + compatible = "bosch,bmp180"; + reg = <0x77>; + vddd-supply = <&bmp180_vddd_reg>; + vdda-supply = <&bmp180_vdda_reg>; + }; + + accelerometer@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + + pinctrl-0 = <&acc_int>; + pinctrl-names = "default"; + + interrupt-parent = <&gpx1>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "asahi-kasei,ak8963"; + reg = <0x0c>; + + pinctrl-0 = <&msense_reset>; + pinctrl-names = "default"; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + }; + }; + + led-controller@42 { + compatible = "ams,as3668"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x42>; + + status_red: led@0 { + reg = <0>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + status_green: led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + status_blue: led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + status_white: led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = ; + }; + }; +}; + +&i2c_2 { + status = "okay"; + + light-sensor@23 { + compatible = "rohm,bh1721"; + reg = <0x23>; + + pinctrl-0 = <&bh1721fvc_reset>; + pinctrl-names = "default"; + + reset-gpios = <&gph1 2 GPIO_ACTIVE_LOW>; + }; + + onewire@18 { + compatible = "maxim,ds2484"; + reg = <0x18>; + + pinctrl-0 = <&onewire_sleep>; + pinctrl-names = "default"; + }; +}; + +&i2c_5 { + samsung,i2c-sda-delay = <100>; + status = "okay"; + + max77686: pmic@9 { + compatible = "maxim,max77686"; + reg = <0x09>; + + interrupt-parent = <&gpx0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&max77686_irq>; + pinctrl-names = "default"; + + #clock-cells = <1>; + wakeup-source; + + voltage-regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "TOUCH_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "VHSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "5M_CORE_1.5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "CAM_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "TA_CHECK_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "TSP_AVDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo24_reg: LDO24 { + regulator-name = "CAM_AF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "VADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&mixer { + status = "okay"; +}; + +/* eMMC */ +&mmc_0 { + non-removable; + max-frequency = <200000000>; + sd-uhs-ddr50; + mmc-ddr-1_8v; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + bus-width = <8>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 2>; + samsung,dw-mshc-ddr-timing = <2 3>; + + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + pinctrl-names = "default"; + + status = "okay"; +}; + +/* WiFi */ +&mmc_1 { + non-removable; + max-frequency = <100000000>; + sd-uhs-sdr50; + cap-sd-highspeed; + keep-power-in-suspend; + bus-width = <4>; + card-detect-delay = <0>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 4>; + samsung,dw-mshc-ddr-timing = <2 3>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; + mmc-pwrseq = <&pwrseq>; + + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-0 = <&wlan_irq>; + pinctrl-names = "default"; + }; +}; + +&ohci { + status = "disabled"; +}; + +&pinctrl_0 { + acc_int: acc-int-pins { + samsung,pins = "gpx1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + max77686_irq: max77686-irq-pins { + samsung,pins = "gpx0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + gpio_keys: gpio-keys-pins { + samsung,pins = "gpx2-0", "gpx2-1", "gpx2-7", "gpx1-3"; + samsung,pin-pud = ; + }; + + wlan_irq: wlan-irq-pins { + samsung,pins = "gpx2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_1 { + bh1721fvc_reset: bh1721fvc-reset-pins { + samsung,pins = "gph1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + msense_reset: msense-reset-pins { + samsung,pins = "gpg2-0"; + samsung,pin-function = ; + }; + + onewire_sleep: onewire-sleep-pins { + samsung,pins = "gpg0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&pinctrl_2 { + wlan_pmena: wlan-pmena-pins { + samsung,pins = "gpv1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-val = <0>; + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_FIN_PLL>; +}; + +&rtc { + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&sd1_bus4 { + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; +}; + +&sd1_cmd { + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; +}; + +/* Bluetooth */ +&serial_0 { + status = "disabled"; +}; + +/* GPS */ +&serial_1 { + status = "disabled"; +}; + +&serial_2 { + pinctrl-0 = <&uart2_data>; + pinctrl-1 = <&uart2_data>, <&uart2_fctl>; + pinctrl-names = "default", "flow-control"; + status = "okay"; +}; + +&usbdrd { + status = "disabled"; +}; + +&usbdrd_dwc3 { + status = "disabled"; +}; + +&usbdrd_phy { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index e906bf6ba004..10c5d75f6169 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -16,6 +16,91 @@ dtb-$(CONFIG_ARCH_STI) += \ stih410-b2260.dtb \ stih418-b2199.dtb \ stih418-b2264.dtb + +stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2-dtbs := \ + stm32mp135f-dhcor-dhsbc.dtb \ + stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtbo + +stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtbo + +stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtbo + +stm32mp15xx-avenger96-overlay-fdcan1-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-fdcan1-x6.dtbo + +stm32mp15xx-avenger96-overlay-fdcan2-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-fdcan2-x6.dtbo + +stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtbo + +stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtbo + +stm32mp15xx-avenger96-overlay-ov5640-x7-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-ov5640-x7.dtbo + +stm32mp15xx-avenger96-overlay-spi2-eeprom-x6-dtbs := \ + stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtbo + +stm32mp15xx-dhcom-drc02-overlay-wifi-rsi-dtbs := \ + stm32mp153c-dhcom-drc02.dtb \ + stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtbo + +stm32mp15xx-dhcom-pdk2-overlay-460-200-x11-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-497-200-x12-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-531-100-x21-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-531-100-x22-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-560-200-x12-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo \ + +stm32mp15xx-dhcom-pdk2-overlay-672-100-x18-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtbo \ + +stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6-dtbs := \ + stm32mp157c-dhcom-picoitx.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtbo \ + +stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtbo \ + +stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh-dtbs := \ + stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \ + dtb-$(CONFIG_ARCH_STM32) += \ stm32f429-disco.dtb \ stm32f469-disco.dtb \ @@ -30,6 +115,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h750i-art-pi.dtb \ stm32mp133c-prihmb.dtb \ stm32mp135f-dhcor-dhsbc.dtb \ + stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtb \ + stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtbo \ stm32mp135f-dk.dtb \ stm32mp151a-prtt1a.dtb \ stm32mp151a-prtt1c.dtb \ @@ -39,12 +126,30 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151c-mect1s.dtb \ stm32mp151c-plyaqm.dtb \ stm32mp153c-dhcom-drc02.dtb \ + stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtb \ + stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtbo \ stm32mp153c-dhcor-drc-compact.dtb \ stm32mp153c-lxa-fairytux2-gen1.dtb \ stm32mp153c-lxa-fairytux2-gen2.dtb \ stm32mp153c-lxa-tac-gen3.dtb \ stm32mp153c-mecio1r1.dtb \ stm32mp157a-avenger96.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtbo \ + stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtb \ + stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtbo \ + stm32mp15xx-avenger96-overlay-fdcan1-x6.dtb \ + stm32mp15xx-avenger96-overlay-fdcan1-x6.dtbo \ + stm32mp15xx-avenger96-overlay-fdcan2-x6.dtb \ + stm32mp15xx-avenger96-overlay-fdcan2-x6.dtbo \ + stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtb \ + stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtbo \ + stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtb \ + stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtbo \ + stm32mp15xx-avenger96-overlay-ov5640-x7.dtb \ + stm32mp15xx-avenger96-overlay-ov5640-x7.dtbo \ + stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtb \ + stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtbo \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ stm32mp157a-dk1-scmi.dtb \ @@ -56,7 +161,29 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtbo \ + stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtb \ + stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtbo \ stm32mp157c-dhcom-picoitx.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtbo \ + stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtbo \ + stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtb \ + stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtbo \ stm32mp157c-dk2.dtb \ stm32mp157c-dk2-scmi.dtb \ stm32mp157c-ed1.dtb \ @@ -69,7 +196,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-lxa-tac-gen2.dtb \ stm32mp157c-odyssey.dtb \ stm32mp157c-osd32mp1-red.dtb \ - stm32mp157c-phycore-stm32mp1-3.dtb \ + stm32mp157c-phyboard-sargas-rdk.dtb \ stm32mp157c-ultra-fly-sbc.dtb \ stm32mp157f-dk2.dtb dtb-$(CONFIG_ARCH_U8500) += \ diff --git a/arch/arm/boot/dts/st/spear13xx.dtsi b/arch/arm/boot/dts/st/spear13xx.dtsi index 159e941708ca..0bb88f2d4ef5 100644 --- a/arch/arm/boot/dts/st/spear13xx.dtsi +++ b/arch/arm/boot/dts/st/spear13xx.dtsi @@ -332,7 +332,6 @@ wdt@ec800620 { thermal@e07008c4 { compatible = "st,thermal-spear1340"; reg = <0xe07008c4 0x4>; - thermal_flags = <0x7000>; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index b9657ff91c23..83ae59b73dd0 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -3,6 +3,7 @@ * Copyright (C) STMicroelectronics 2021 - All Rights Reserved * Author: Alexandre Torgue for STMicroelectronics. */ +#include #include #include #include @@ -469,8 +470,8 @@ i2c1: i2c@40012000 { compatible = "st,stm32mp13-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C1_K>; resets = <&rcc I2C1_R>; #address-cells = <1>; @@ -478,6 +479,7 @@ i2c1: i2c@40012000 { dmas = <&dmamux1 33 0x400 0x1>, <&dmamux1 34 0x400 0x1>; dma-names = "rx", "tx"; + wakeup-source; st,syscfg-fmp = <&syscfg 0x4 0x1>; i2c-analog-filter; status = "disabled"; @@ -487,8 +489,8 @@ i2c2: i2c@40013000 { compatible = "st,stm32mp13-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C2_K>; resets = <&rcc I2C2_R>; #address-cells = <1>; @@ -497,6 +499,7 @@ i2c2: i2c@40013000 { <&dmamux1 36 0x400 0x1>; dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; i2c-analog-filter; status = "disabled"; }; @@ -964,9 +967,125 @@ hdp: pinctrl@5002a000 { compatible = "st,stm32mp131-hdp"; reg = <0x5002a000 0x400>; clocks = <&rcc HDP>; + access-controllers = <&dbg_bus 1>; status = "disabled"; }; + dbg_bus: bus@50080000 { + compatible = "st,stm32mp131-dbg-bus"; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges = <0x50080000 0x50080000 0x3f80000>; + status = "disabled"; + + cs_etf: etf@50092000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x50092000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + }; + + cs_tpiu: tpiu@50093000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x50093000 0x1000>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + cs_cti_trace: cti@50094000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x50094000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + }; + + cs_cti_cpu0: cti@500d8000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x500d8000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <0 4 5>; + arm,trig-in-types = ; + arm,trig-out-sigs = <0 7>; + arm,trig-out-types = ; + cpu = <&cpu0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs = <2 3 6>; + arm,trig-in-types = ; + arm,trig-out-sigs = <1 2 3 4>; + arm,trig-out-types = ; + arm,cs-dev-assoc = <&cs_etm0>; + }; + }; + + cs_etm0: etm@500dc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x500dc000 0x1000>; + cpu = <&cpu0>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -1129,7 +1248,7 @@ usart1: serial@4c000000 { resets = <&rcc USART1_R>; wakeup-source; dmas = <&dmamux1 41 0x400 0x5>, - <&dmamux1 42 0x400 0x1>; + <&dmamux1 42 0x400 0x1>; dma-names = "rx", "tx"; access-controllers = <&etzpc 16>; status = "disabled"; @@ -1143,7 +1262,7 @@ usart2: serial@4c001000 { resets = <&rcc USART2_R>; wakeup-source; dmas = <&dmamux1 43 0x400 0x5>, - <&dmamux1 44 0x400 0x1>; + <&dmamux1 44 0x400 0x1>; dma-names = "rx", "tx"; access-controllers = <&etzpc 17>; status = "disabled"; @@ -1155,7 +1274,7 @@ i2s4: audio-controller@4c002000 { #sound-dai-cells = <0>; interrupts = ; dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; + <&dmamux1 84 0x400 0x01>; dma-names = "rx", "tx"; access-controllers = <&etzpc 13>; status = "disabled"; @@ -1195,8 +1314,8 @@ i2c3: i2c@4c004000 { compatible = "st,stm32mp13-i2c"; reg = <0x4c004000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C3_K>; resets = <&rcc I2C3_R>; #address-cells = <1>; @@ -1205,6 +1324,7 @@ i2c3: i2c@4c004000 { <&dmamux1 74 0x400 0x1>; dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; i2c-analog-filter; access-controllers = <&etzpc 20>; status = "disabled"; @@ -1214,8 +1334,8 @@ i2c4: i2c@4c005000 { compatible = "st,stm32mp13-i2c"; reg = <0x4c005000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C4_K>; resets = <&rcc I2C4_R>; #address-cells = <1>; @@ -1224,6 +1344,7 @@ i2c4: i2c@4c005000 { <&dmamux1 76 0x400 0x1>; dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; i2c-analog-filter; access-controllers = <&etzpc 21>; status = "disabled"; @@ -1233,8 +1354,8 @@ i2c5: i2c@4c006000 { compatible = "st,stm32mp13-i2c"; reg = <0x4c006000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C5_K>; resets = <&rcc I2C5_R>; #address-cells = <1>; @@ -1243,6 +1364,7 @@ i2c5: i2c@4c006000 { <&dmamux1 116 0x400 0x1>; dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; i2c-analog-filter; access-controllers = <&etzpc 22>; status = "disabled"; @@ -1348,9 +1470,9 @@ timers15: timer@4c00a000 { clocks = <&rcc TIM15_K>; clock-names = "int"; dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; dma-names = "ch1", "up", "trig", "com"; access-controllers = <&etzpc 26>; status = "disabled"; @@ -1383,7 +1505,7 @@ timers16: timer@4c00b000 { clocks = <&rcc TIM16_K>; clock-names = "int"; dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; + <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; access-controllers = <&etzpc 27>; status = "disabled"; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 8dcf68b212b4..4d4cec8b86ac 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -187,6 +187,30 @@ &cryp { status = "okay"; }; +&cs_cti_trace { + status = "okay"; +}; + +&cs_cti_cpu0 { + status = "okay"; +}; + +&cs_etf { + status = "okay"; +}; + +&cs_etm0 { + status = "okay"; +}; + +&cs_tpiu { + status = "okay"; +}; + +&dbg_bus { + status = "okay"; +}; + &dcmipp { pinctrl-names = "default", "sleep"; pinctrl-0 = <&dcmipp_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso new file mode 100644 index 000000000000..3801dab141e8 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-dhsbc-overlay-rb-tft32-v2.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + gpio-keys { + compatible = "gpio-keys"; + + button-1 { + label = "KEY2"; + linux,code = ; + gpios = <&gpiog 10 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + button-0 { + label = "KEY1"; + linux,code = ; + /* IRQ bank A shared with PA1 touch controller */ + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + }; + + button-2 { + label = "KEY3"; + linux,code = ; + /* IRQ line 0 taken by PI0 / SoM RTC IRQ */ + gpios = <&gpiod 0 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&m_can1 { + /* Collides with KEY2/PG10 KEY3/PD0 */ + status = "disabled"; +}; + +&m_can2 { + /* Collides with TP_CS/PE6 */ + status = "disabled"; +}; + +&usart2 { + /* Collides with TP_IRQ/PA1 */ + status = "disabled"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpiof 3 0>, <&gpioe 0 0>; + status = "okay"; + + lcd@0 { + compatible = "adafruit,yx240qv29", "ilitek,ili9341"; + reg = <0>; + spi-max-frequency = <10000000>; + dc-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; + rotation = <90>; + }; + + tp@1 { + compatible = "ti,tsc2046"; + reg = <1>; + interrupt-parent = <&gpioa>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>; + spi-max-frequency = <500000>; + ti,pressure-max = /bits/ 16 <255>; + ti,x-plate-ohms = /bits/ 16 <60>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 8613a6a17ee9..aaa91b634c12 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -231,6 +231,45 @@ pins { }; }; + /omit-if-no-ref/ + dcmi_pins_d: dcmi-3 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + dcmi_sleep_pins_d: dcmi-sleep-3 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + }; + }; + /omit-if-no-ref/ ethernet0_rgmii_pins_a: rgmii-0 { pins1 { @@ -394,6 +433,7 @@ pins1 { ethernet0_rgmii_pins_d: rgmii-3 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ , /* ETH_RGMII_TXD0 */ , /* ETH_RGMII_TXD1 */ , /* ETH_RGMII_TXD2 */ @@ -1343,6 +1383,65 @@ pins { }; }; + /omit-if-no-ref/ + ltdc_pins_f: ltdc-5 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_f: ltdc-sleep-5 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + /omit-if-no-ref/ mco1_pins_a: mco1-0 { pins { @@ -1683,6 +1782,23 @@ pins { }; }; + /omit-if-no-ref/ + pwm5_pins_c: pwm5-2 { + pins { + pinmux = ; /* TIM5_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + pwm5_sleep_pins_c: pwm5-sleep-2 { + pins { + pinmux = ; /* TIM5_CH4 */ + }; + }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { @@ -1908,6 +2024,21 @@ pins { }; }; + /omit-if-no-ref/ + sai2a_pins_d: sai2a-3 { + pins { + pinmux = ; /* SAI2_SD_A */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + sai2a_sleep_pins_d: sai2a-3 { + pins { + pinmux = ; /* SAI2_SD_A */ + }; + }; + /omit-if-no-ref/ sai2b_pins_a: sai2b-0 { pins1 { @@ -2895,6 +3026,39 @@ pins { }; }; + /omit-if-no-ref/ + uart4_pins_f: uart4-5 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_f: uart4-idle-5 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_sleep_pins_f: uart4-sleep-5 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + /omit-if-no-ref/ uart5_pins_a: uart5-0 { pins1 { diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index b1b568dfd126..84f68e8563d8 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -3,6 +3,7 @@ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved * Author: Ludovic Barre for STMicroelectronics. */ +#include #include #include #include @@ -123,6 +124,14 @@ soc { interrupt-parent = <&intc>; ranges; + sram4: sram@10050000 { + compatible = "mmio-sram"; + reg = <0x10050000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10050000 0x10000>; + }; + ipcc: mailbox@4c001000 { compatible = "st,stm32mp1-ipcc"; #mbox-cells = <1>; @@ -274,9 +283,180 @@ hdp: pinctrl@5002a000 { compatible = "st,stm32mp151-hdp"; reg = <0x5002a000 0x400>; clocks = <&rcc HDP>; + access-controllers = <&dbg_bus 1>; status = "disabled"; }; + dbg_bus: bus@50080000 { + compatible = "st,stm32mp151-dbg-bus"; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges = <0x50080000 0x50080000 0x3f80000>, + <0x90000000 0x90000000 0x1000000>; + status = "disabled"; + + cs_funnel: funnel@50091000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x50091000 0x1000>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + funnel_in_port0: endpoint { + remote-endpoint = <&stm_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel_in_port1: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + }; + + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + cs_etf: etf@50092000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x50092000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&funnel_out_port>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + }; + }; + + cs_tpiu: tpiu@50093000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x50093000 0x1000>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + cs_cti_trace: cti@50094000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x50094000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + }; + + cs_stm: stm@500a0000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x500a0000 0x00001000>, + <0x90000000 0x01000000>; + reg-names = "stm-base", "stm-stimulus-base"; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + out-ports { + port { + stm_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + + cs_cti_cpu0: cti@500d8000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x500d8000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <0 4 5>; + arm,trig-in-types = ; + arm,trig-out-sigs = <0 7>; + arm,trig-out-types = ; + cpu = <&cpu0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs = <2 3 6>; + arm,trig-in-types = ; + arm,trig-out-sigs = <1 2 3 4>; + arm,trig-out-types = ; + arm,cs-dev-assoc = <&cs_etm0>; + }; + }; + + cs_etm0: etm@500dc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x500dc000 0x1000>; + cpu = <&cpu0>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + }; + }; + mdma1: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -867,12 +1047,15 @@ i2c1: i2c@40012000 { compatible = "st,stm32mp15-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C1_K>; resets = <&rcc I2C1_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x1>, + <&dmamux1 34 0x400 0x1>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; i2c-analog-filter; @@ -884,12 +1067,15 @@ i2c2: i2c@40013000 { compatible = "st,stm32mp15-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C2_K>; resets = <&rcc I2C2_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x1>, + <&dmamux1 36 0x400 0x1>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; i2c-analog-filter; @@ -901,12 +1087,15 @@ i2c3: i2c@40014000 { compatible = "st,stm32mp15-i2c"; reg = <0x40014000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C3_K>; resets = <&rcc I2C3_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; i2c-analog-filter; @@ -918,12 +1107,15 @@ i2c5: i2c@40015000 { compatible = "st,stm32mp15-i2c"; reg = <0x40015000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C5_K>; resets = <&rcc I2C5_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; i2c-analog-filter; @@ -1083,7 +1275,7 @@ usart6: serial@44003000 { clocks = <&rcc USART6_K>; wakeup-source; dmas = <&dmamux1 71 0x400 0x15>, - <&dmamux1 72 0x400 0x11>; + <&dmamux1 72 0x400 0x11>; dma-names = "rx", "tx"; access-controllers = <&etzpc 51>; status = "disabled"; @@ -1095,7 +1287,7 @@ i2s1: audio-controller@44004000 { reg = <0x44004000 0x400>; interrupts = ; dmas = <&dmamux1 37 0x400 0x01>, - <&dmamux1 38 0x400 0x01>; + <&dmamux1 38 0x400 0x01>; dma-names = "rx", "tx"; access-controllers = <&etzpc 52>; status = "disabled"; @@ -1110,7 +1302,7 @@ spi1: spi@44004000 { clocks = <&rcc SPI1_K>; resets = <&rcc SPI1_R>; dmas = <&dmamux1 37 0x400 0x05>, - <&dmamux1 38 0x400 0x05>; + <&dmamux1 38 0x400 0x05>; dma-names = "rx", "tx"; access-controllers = <&etzpc 52>; status = "disabled"; @@ -1125,7 +1317,7 @@ spi4: spi@44005000 { clocks = <&rcc SPI4_K>; resets = <&rcc SPI4_R>; dmas = <&dmamux1 83 0x400 0x05>, - <&dmamux1 84 0x400 0x05>; + <&dmamux1 84 0x400 0x05>; dma-names = "rx", "tx"; access-controllers = <&etzpc 53>; status = "disabled"; @@ -1176,7 +1368,7 @@ timers16: timer@44007000 { clocks = <&rcc TIM16_K>; clock-names = "int"; dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; + <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; access-controllers = <&etzpc 55>; status = "disabled"; @@ -1209,7 +1401,7 @@ timers17: timer@44008000 { clocks = <&rcc TIM17_K>; clock-names = "int"; dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; + <&dmamux1 112 0x400 0x1>; dma-names = "ch1", "up"; access-controllers = <&etzpc 56>; status = "disabled"; @@ -1241,7 +1433,7 @@ spi5: spi@44009000 { clocks = <&rcc SPI5_K>; resets = <&rcc SPI5_R>; dmas = <&dmamux1 85 0x400 0x05>, - <&dmamux1 86 0x400 0x05>; + <&dmamux1 86 0x400 0x05>; dma-names = "rx", "tx"; access-controllers = <&etzpc 57>; status = "disabled"; @@ -1829,12 +2021,15 @@ i2c4: i2c@5c002000 { compatible = "st,stm32mp15-i2c"; reg = <0x5c002000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C4_K>; resets = <&rcc I2C4_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&mdma1 36 0x0 0x40008 0x0 0x0>, + <&mdma1 37 0x0 0x40002 0x0 0x0>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; i2c-analog-filter; @@ -1846,12 +2041,15 @@ i2c6: i2c@5c009000 { compatible = "st,stm32mp15-i2c"; reg = <0x5c009000 0x400>; interrupt-names = "event", "error"; - interrupts = , - ; + interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc I2C6_K>; resets = <&rcc I2C6_R>; #address-cells = <1>; #size-cells = <0>; + dmas = <&mdma1 38 0x0 0x40008 0x0 0x0>, + <&mdma1 39 0x0 0x40002 0x0 0x0>; + dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; i2c-analog-filter; diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi index 92794b942ab2..17d52d93695e 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -30,6 +30,74 @@ timer { }; }; +&cs_funnel { + in-ports { + port@2 { + reg = <2>; + funnel_in_port2: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; +}; + +&dbg_bus { + cs_cti_cpu1: cti@500d9000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x500d9000 0x1000>; + clocks = <&rcc CK_DBG>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <0 4 5>; + arm,trig-in-types = ; + arm,trig-out-sigs = <0 7>; + arm,trig-out-types = ; + cpu = <&cpu1>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs = <2 3 6>; + arm,trig-in-types = ; + arm,trig-out-sigs = <1 2 3 4>; + arm,trig-out-types = ; + arm,cs-dev-assoc = <&cs_etm1>; + }; + }; + + cs_etm1: etm@500dd000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x500dd000 0x1000>; + cpu = <&cpu1>; + clocks = <&rcc CK_DBG>, <&rcc CK_TRACE>; + clock-names = "apb_pclk", "atclk"; + access-controllers = <&dbg_bus 0>; + status = "disabled"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_in_port2>; + }; + }; + }; + }; +}; + &etzpc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts index 4e46d58bf61f..0e65a1862eb5 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -81,11 +81,59 @@ &cec { status = "okay"; }; +&cs_cti_trace { + status = "okay"; +}; + +&cs_cti_cpu0 { + status = "okay"; +}; + +&cs_cti_cpu1 { + status = "okay"; +}; + +&cs_etf { + status = "okay"; +}; + +&cs_etm0 { + status = "okay"; +}; + +&cs_etm1 { + status = "okay"; +}; + +&cs_funnel { + status = "okay"; +}; + +&cs_stm { + status = "okay"; +}; + +&cs_tpiu { + status = "okay"; +}; + +&dbg_bus { + status = "okay"; +}; + &dcmi { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&dcmi_pins_a>; pinctrl-1 = <&dcmi_sleep_pins_a>; + /* + * Enable DMA-MDMA chaining by adding a SRAM pool and + * a MDMA channel + */ + sram = <&dcmi_pool>; + + dmas = <&dmamux1 75 0x400 0x01>, <&mdma1 0 0x3 0x1200000a 0 0>; + dma-names = "tx", "mdma_tx"; port { dcmi_0: endpoint { @@ -171,6 +219,8 @@ &i2c2 { pinctrl-1 = <&i2c2_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; ov5640: camera@3c { @@ -227,6 +277,8 @@ &i2c5 { pinctrl-1 = <&i2c5_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -302,6 +354,13 @@ &spi1 { status = "disabled"; }; +&sram4 { + dcmi_pool: dcmi-sram@0 { + reg = <0x0 0x8000>; + pool; + }; +}; + &timers2 { /* spare dmas for other usage (un-delete to enable pwm capture) */ /delete-property/dmas; diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts similarity index 58% rename from arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts rename to arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts index 28d7203264ce..c18a37266083 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts @@ -6,39 +6,21 @@ /dts-v1/; -#include #include "stm32mp157.dtsi" #include "stm32mp15xc.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp157c-phycore-stm32mp15-som.dtsi" +#include "stm32mp15xx-phycore-som.dtsi" +#include "stm32mp15xx-phyboard-sargas.dtsi" / { - model = "PHYTEC phyCORE-STM32MP1-3 Dev Board"; + model = "PHYTEC phyBOARD-Sargas STM32MP157C"; compatible = "phytec,phycore-stm32mp1-3", "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; - - aliases { - mmc0 = &sdmmc1; - mmc1 = &sdmmc2; - mmc2 = &sdmmc3; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &usart1; - }; }; &cryp1 { status = "okay"; }; -&dts { - status = "okay"; -}; - -&fmc { - status = "disabled"; -}; - &gpu { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso new file mode 100644 index 000000000000..103a2f0cf57b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-otm8009a.dtso @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +#include + +/dts-v1/; +/plugin/; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + phy-dsi-supply = <®18>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel@0 { + compatible = "orisetech,otm8009a"; + reg = <0>; + reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; + status = "okay"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +<dc { + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso new file mode 100644 index 000000000000..cde2f8f68f86 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-644-100-x6-rpi7inch.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: touchscreen@38 { + }; + + attiny: regulator@45 { + }; +}; + +#include "stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi" + +<dc { + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso new file mode 100644 index 000000000000..a9916aa8df75 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan1-x6.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&m_can1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso new file mode 100644 index 000000000000..c994ff055227 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-fdcan2-x6.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&m_can2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso new file mode 100644 index 000000000000..1edfff973a81 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c1-eeprom-x6.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso new file mode 100644 index 000000000000..bb3db38e3e63 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-i2c2-eeprom-x6.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso new file mode 100644 index 000000000000..3056be6cd196 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-ov5640-x7.dtso @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + camera0_1v5_pwr: regulator-camera0-1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera0-1v5-reg"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + camera0_1v8_pwr: regulator-camera0-1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera0-1v8-reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera0_2v8_pwr: regulator-camera0-2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera0-2v8-reg"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; +}; + +&dcmi { + status = "okay"; +}; + +&dcmi_0 { + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&rcc CK_MCO1>; + clock-names = "xclk"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mco1_pins_a>; + pinctrl-1 = <&mco1_sleep_pins_a>; + assigned-clocks = <&rcc CK_MCO1>; + assigned-clock-parents = <&rcc CK_HSE>; + assigned-clock-rates = <24000000>; + AVDD-supply = <&camera0_2v8_pwr>; + DOVDD-supply = <&camera0_1v8_pwr>; + DVDD-supply = <&camera0_1v5_pwr>; + /* GPIO-J on the Dragonboard Dual-Leopard OV5640 board */ + powerdown-gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>; + /* GPIO-I on the Dragonboard Dual-Leopard OV5640 board */ + reset-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + rotation = <180>; + status = "okay"; + + port { + ov5640_0: endpoint { + remote-endpoint = <&stmipi_0>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&stmipi { + status = "okay"; +}; + +&stmipi_0 { + data-lanes = <1 2>; + remote-endpoint = <&ov5640_0>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso new file mode 100644 index 000000000000..acfd25c5bbcd --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-avenger96-overlay-spi2-eeprom-x6.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + cs-gpios = <&gpioi 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso new file mode 100644 index 000000000000..aa79f95906f8 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02-overlay-wifi-rsi.dtso @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&sdmmc3 { + broken-cd; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi new file mode 100644 index 000000000000..be9eb1e11ecd --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&{/} { + lvds-encoder { + compatible = "onnn,fin3385", "lvds-encoder"; + pclk-sample = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_bridge_in: endpoint { + remote-endpoint = <<dc_dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&display_bl { + pwms = <&pwm2 3 5000000 0>; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + ili251x@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <16384>; + touchscreen-size-y = <9600>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +<dc_dpi_out { + remote-endpoint = <&lvds_bridge_in>; +}; + +&panel { + compatible = "chefree,ch101olhlwh-002"; +}; + +&panel_in { + remote-endpoint = <&lvds_bridge_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi new file mode 100644 index 000000000000..41229ec680cc --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-overlay-panel-dpi.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Marek Vasut + */ +#include +#include +#include +#include + +&{/} { + display_bl: display-bl { + compatible = "pwm-backlight"; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; + power-supply = <®_panel_bl>; + status = "okay"; + }; + + panel: panel { + backlight = <&display_bl>; + power-supply = <®_panel_bl>; + + port { + panel_in: endpoint { + }; + }; + }; + + reg_panel_bl: regulator-panel-bl { + compatible = "regulator-fixed"; + regulator-name = "panel_backlight"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_panel_supply>; + }; + + reg_panel_supply: regulator-panel-supply { + compatible = "regulator-fixed"; + regulator-name = "panel_supply"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + }; +}; + +&timers2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pwm2: pwm { + #pwm-cells = <3>; + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@1 { + reg = <1>; + status = "okay"; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-1 = <<dc_sleep_pins_b>; + status = "okay"; + + port { + ltdc_dpi_out: endpoint { + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso new file mode 100644 index 000000000000..161e401f5e21 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-460-200-x11.dtso @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&fmc { + #address-cells = <2>; + #size-cells = <1>; + + sram@3,0 { + compatible = "mtd-ram"; + reg = <3 0x0 0x80000>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <6>; + st,fmc2-ebi-cs-address-hold-ns = <6>; + st,fmc2-ebi-cs-data-setup-ns = <127>; + st,fmc2-ebi-cs-bus-turnaround-ns = <9>; + st,fmc2-ebi-cs-data-hold-ns = <9>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso new file mode 100644 index 000000000000..1de244545054 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-497-200-x12.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&display_bl { + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; +}; + +<dc_dpi_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "dataimage,scf0700c48ggu18"; +}; + +&panel_in { + remote-endpoint = <<dc_dpi_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso new file mode 100644 index 000000000000..6ef9bcf527ad --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-505-200-x12-ch101olhlwh.dtso @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi" + +&{/} { + gpio-keys-polled { + /* BUTTON1 GPIO-B conflicts with touchscreen reset */ + button-1 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; + + led { + /* LED7 GPIO-H conflicts with touchscreen IRQ */ + led-2 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso new file mode 100644 index 000000000000..ce291736abbb --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x21.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + status = "okay"; + cs-gpios = <&gpioz 3 0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "microchip,25aa010a", "atmel,at25"; + reg = <0>; + address-width = <8>; + pagesize = <16>; + size = <128>; + spi-max-frequency = <5000000>; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso new file mode 100644 index 000000000000..7e040b2d8f24 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-531-100-x22.dtso @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; + +/* SPI2 is not connected on STM32MP1 DHCOM SoM */ diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso new file mode 100644 index 000000000000..a5cef9ba7dd2 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-560-200-x12.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&{/} { + gpio-keys { + /* + * The EXTi IRQ line 6 is shared with touchscreen IRQ, + * so operate button-1 as polled GPIO key. + */ + button-1 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; + + gpio-keys-polled { + button-1 { + label = "TA2-GPIO-B"; + linux,code = ; + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + }; + }; + + led { + /* LED5 GPIO-E conflicts with touchscreen IRQ */ + led-0 { + /* Use status as /delete-node/ does not work in DTOs */ + status = "disabled"; + }; + }; +}; + +&display_bl { + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + /* Touchscreen IRQ GPIO-E conflicts with LED5 GPIO */ + interrupt-parent = <&gpioc>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; +}; + +<dc_dpi_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "edt,etm0700g0edh6"; +}; + +&panel_in { + remote-endpoint = <<dc_dpi_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso new file mode 100644 index 000000000000..ee8a2d1a7b87 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-638-100-x12-rpi7inch.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: touchscreen@38 { + }; + + attiny: regulator@45 { + }; +}; + +#include "stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi" + +<dc { + status = "okay"; + port { + ltdc_ep_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso new file mode 100644 index 000000000000..41e473986189 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2-overlay-672-100-x18.dtso @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 5c77202ee196..0075d9391181 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -13,15 +13,6 @@ clk_ext_audio_codec: clock-codec { clock-frequency = <24000000>; }; - display_bl: display-bl { - compatible = "pwm-backlight"; - pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - default-brightness-level = <8>; - enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; - power-supply = <®_panel_bl>; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; poll-interval = <20>; @@ -75,7 +66,6 @@ led-0 { label = "green:led5"; gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; default-state = "off"; - status = "disabled"; }; led-1 { @@ -97,33 +87,6 @@ led-3 { }; }; - panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&display_bl>; - power-supply = <®_panel_bl>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - reg_panel_bl: regulator-panel-bl { - compatible = "regulator-fixed"; - regulator-name = "panel_backlight"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_panel_supply>; - }; - - reg_panel_supply: regulator-panel-supply { - compatible = "regulator-fixed"; - regulator-name = "panel_supply"; - regulator-min-microvolt = <24000000>; - regulator-max-microvolt = <24000000>; - }; - sound { compatible = "audio-graph-card"; widgets = "Headphone", "Headphone Jack", @@ -188,26 +151,6 @@ sgtl5000_rx_endpoint: endpoint@1 { }; }; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - reg = <0x38>; - interrupt-parent = <&gpioc>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_b>; - pinctrl-1 = <<dc_sleep_pins_b>; - status = "okay"; - - port { - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; }; &sai2 { @@ -259,21 +202,6 @@ sai2b_endpoint: endpoint { }; }; -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - pwm2: pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso new file mode 100644 index 000000000000..c462c6a08833 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-548-200-x2-mi0700s4t-6.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Andreas Geisreiter + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&display_bl { + pwms = <&pwm2 3 10000000 0>; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +<dc_dpi_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "multi-inno,mi0700s4t-6"; +}; + +&panel_in { + remote-endpoint = <<dc_dpi_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso new file mode 100644 index 000000000000..06338b7f7b67 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-553-100-x2-tst043015cmhx.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi.dtsi" + +&display_bl { + pwms = <&pwm2 3 10000000 0>; +}; + +&i2c5 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +<dc_dpi_out { + remote-endpoint = <&panel_in>; +}; + +&panel { + compatible = "team-source-display,tst043015cmhx"; +}; + +&panel_in { + remote-endpoint = <<dc_dpi_out>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso new file mode 100644 index 000000000000..bf5c1f6eece0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx-overlay-626-100-x2-ch101olhlwh.dtso @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "stm32mp15xx-dhcom-overlay-panel-dpi-ch101olhlwh.dtsi" diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi index aceeff6c38ba..85d93ddfa12a 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi @@ -258,15 +258,9 @@ &i2c2 { /* X6 I2C2 */ &i2c4 { stmipi: stmipi@14 { compatible = "st,st-mipid02"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mco1_pins_a>; - pinctrl-1 = <&mco1_sleep_pins_a>; reg = <0x14>; clocks = <&rcc CK_MCO1>; clock-names = "xclk"; - assigned-clocks = <&rcc CK_MCO1>; - assigned-clock-parents = <&rcc CK_HSE>; - assigned-clock-rates = <24000000>; VDDE-supply = <&v1v8>; VDDIN-supply = <&v1v8>; reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi new file mode 100644 index 000000000000..518c269a1dba --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhsom-overlay-panel-dsi-rpi7inch.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2021 Marek Vasut + */ +#include + +&{/} { + panel { + compatible = "powertip,ph800480t013-idf02"; + backlight = <&attiny>; + power-supply = <&attiny>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&attiny { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x45>; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + + phy-dsi-supply = <®18>; + status = "okay"; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + reset-gpios = <&attiny 0 GPIO_ACTIVE_HIGH>; + vddc-supply = <&attiny>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <<dc_ep_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&touchscreen { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + reset-gpios = <&attiny 1 GPIO_ACTIVE_LOW>; + /* + * Disabled, since the IRQ line is not on + * the FPC cable, so we cannot get touch + * IRQs unless its connected otherwise. In + * that case, add entry like this one and + * enable below. + * + * interrupt-parent = <&gpiog>; + * interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index 7ed2b01958fe..599ea07bdb19 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -155,6 +155,46 @@ &crc1 { status = "okay"; }; +&cs_cti_trace { + status = "okay"; +}; + +&cs_cti_cpu0 { + status = "okay"; +}; + +&cs_cti_cpu1 { + status = "okay"; +}; + +&cs_etf { + status = "okay"; +}; + +&cs_etm0 { + status = "okay"; +}; + +&cs_etm1 { + status = "okay"; +}; + +&cs_funnel { + status = "okay"; +}; + +&cs_stm { + status = "okay"; +}; + +&cs_tpiu { + status = "okay"; +}; + +&dbg_bus { + status = "okay"; +}; + &dts { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi new file mode 100644 index 000000000000..f7e7aa9b916a --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD . + */ + +#include +#include +#include +#include + +/ { + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + mmc2 = &sdmmc3; + serial0 = &uart4; + serial1 = &usart3; + serial2 = &usart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-enter { + label = "Enter"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-PHYCORE"; + routing = + "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ + "Capture", "MCLK"; + dais = <&sai2b_port>, + <&sai2a_port>; + }; +}; + +&dcmi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_d>; + pinctrl-1 = <&dcmi_sleep_pins_d>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + + codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + + ai3x-micbias-vg = <2>; + + AVDD-supply = <&v3v3>; + IOVDD-supply = <&v3v3>; + DRVDD-supply = <&v3v3>; + DVDD-supply = <&v1v8_audio>; + + clocks = <&sai2b>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tlv320_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + + tlv320_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + }; + }; + + touch@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + vio-supply = <&v3v3>; + vcc-supply = <&v3v3>; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + + touchscreen { + compatible = "st,stmpe-ts"; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + }; + }; + + leds@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-0 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-1 { + color = ; + function = LED_FUNCTION_POWER; + type = ; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + type = ; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_f>; + pinctrl-1 = <<dc_sleep_pins_f>; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_d>, <&sai2b_pins_d>; + pinctrl-1 = <&sai2a_sleep_pins_d>, <&sai2b_sleep_pins_d>; + status = "okay"; +}; + +&sai2a { + dma-names = "rx"; + clocks = <&rcc SAI2_K>, <&sai2b>; + clock-names = "sai_ck", "MCLK"; + #clock-cells = <0>; + st,sync = <&sai2b 2>; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&tlv320_rx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sai2b { + dma-names = "tx"; + #clock-cells = <0>; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&tlv320_tx_endpoint>; + mclk-fs = <256>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; + cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + vmmc-supply = <&v3v3>; + st,neg-edge; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "okay"; +}; + +&timers5 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm5: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm5_pins_c>; + pinctrl-1 = <&pwm5_sleep_pins_c>; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_f>; + pinctrl-1 = <&uart4_sleep_pins_f>; + pinctrl-2 = <&uart4_idle_pins_f>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_a>; + pinctrl-1 = <&usart3_sleep_pins_a>; + pinctrl-2 = <&usart3_idle_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + status = "okay"; +}; + +&usbh_ohci { + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi similarity index 53% rename from arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi rename to arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi index 370b2afbf15b..126446c4198f 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp15-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -1,23 +1,20 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) 2022-2023 Steffen Trumtrar * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved - * Author: Dom VOVARD . + * Author: Dom VOVARD + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Christophe Parant */ #include #include -#include -#include -#include -#include #include #include #include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" / { - model = "PHYTEC phyCORE-STM32MP15 SOM"; - compatible = "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; aliases { ethernet0 = ðernet0; @@ -25,24 +22,13 @@ aliases { rtc1 = &rtc; }; - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - key-home { - label = "Home"; - gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-enter { - label = "Enter"; - gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; }; reserved-memory { @@ -50,18 +36,6 @@ reserved-memory { #size-cells = <1>; ranges; - retram: retram@38000000 { - compatible = "shared-dma-pool"; - reg = <0x38000000 0x10000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible = "shared-dma-pool"; - reg = <0x30000000 0x40000>; - no-map; - }; - mcuram2: mcuram2@10000000 { compatible = "shared-dma-pool"; reg = <0x10000000 0x40000>; @@ -85,21 +59,23 @@ vdev0buffer: vdev0buffer@10042000 { reg = <0x10042000 0x4000>; no-map; }; - }; - sound { - compatible = "audio-graph-card"; - label = "STM32MP1-PHYCORE"; - routing = - "Playback", "MCLK", /* Set a route between "MCLK" and "playback" widgets */ - "Capture", "MCLK"; - dais = <&sai2b_port>, - <&sai2a_port>; + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; }; regulator_vin: regulator { compatible = "regulator-fixed"; - regulator-name = "vin"; + regulator-name = "VIN"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; @@ -126,101 +102,28 @@ phy0: ethernet-phy@1 { reg = <1>; interrupt-parent = <&gpiog>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,min-output-impedance; - enet-phy-lane-no-swap; ti,clk-output-sel = ; }; }; }; -&i2c1 { +&fmc { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&i2c1_pins_b>; - pinctrl-1 = <&i2c1_sleep_pins_b>; - i2c-scl-rising-time-ns = <100>; - i2c-scl-falling-time-ns = <7>; - status = "okay"; + pinctrl-0 = <&fmc_pins_a>; + pinctrl-1 = <&fmc_sleep_pins_a>; + status = "disabled"; - codec@18 { - compatible = "ti,tlv320aic3007"; - reg = <0x18>; - #sound-dai-cells = <0>; - - ai3x-micbias-vg = <2>; - - AVDD-supply = <&v3v3>; - IOVDD-supply = <&v3v3>; - DRVDD-supply = <&v3v3>; - DVDD-supply = <&v1v8_audio>; - - clocks = <&sai2b>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - tlv320_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2b_endpoint>; - frame-master; - bitclock-master; - }; - - tlv320_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2a_endpoint>; - frame-master; - bitclock-master; - }; - }; - }; - - touch@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpioi>; - vio-supply = <&v3v3>; - vcc-supply = <&v3v3>; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - - touchscreen { - compatible = "st,stmpe-ts"; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - }; - }; - - leds@62 { - compatible = "nxp,pca9533"; - reg = <0x62>; - - led-0 { - color = ; - function = LED_FUNCTION_POWER; - type = ; - }; - - led-1 { - color = ; - function = LED_FUNCTION_POWER; - type = ; - }; - - led-2 { - color = ; - function = LED_FUNCTION_HEARTBEAT; - type = ; - linux,default-trigger = "heartbeat"; + nand-controller@4,0 { + nand0: nand@0 { + reg = <0>; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; }; }; }; @@ -257,7 +160,7 @@ regulators { pwr_sw2-supply = <&bst_out>; vddcore: buck1 { - regulator-name = "vddcore"; + regulator-name = "VDD_CORE"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -265,7 +168,7 @@ vddcore: buck1 { }; vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; + regulator-name = "VDD_DDR"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -273,7 +176,7 @@ vdd_ddr: buck2 { }; vdd: buck3 { - regulator-name = "vdd"; + regulator-name = "VDD"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -282,7 +185,7 @@ vdd: buck3 { }; v3v3: buck4 { - regulator-name = "v3v3"; + regulator-name = "VDD_BUCK4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -290,7 +193,7 @@ v3v3: buck4 { }; v1v8_audio: ldo1 { - regulator-name = "v1v8_audio"; + regulator-name = "VDD_LDO1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; @@ -299,7 +202,7 @@ v1v8_audio: ldo1 { }; vdd_eth_2v5: ldo2 { - regulator-name = "dd_eth_2v5"; + regulator-name = "VDD_ETH_2V5"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; @@ -308,7 +211,7 @@ vdd_eth_2v5: ldo2 { }; vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; + regulator-name = "VTT_DDR"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <750000>; regulator-always-on; @@ -316,12 +219,12 @@ vtt_ddr: ldo3 { }; vdd_usb: ldo4 { - regulator-name = "vdd_usb"; + regulator-name = "VDD_USB"; interrupts = ; }; vdda: ldo5 { - regulator-name = "vdda"; + regulator-name = "VDDA"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = ; @@ -329,7 +232,7 @@ vdda: ldo5 { }; vdd_eth_1v0: ldo6 { - regulator-name = "vdd_eth_1v0"; + regulator-name = "VDD_ETH_1V0"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; @@ -338,23 +241,23 @@ vdd_eth_1v0: ldo6 { }; vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; + regulator-name = "VDD_REFDDR"; regulator-always-on; }; bst_out: boost { - regulator-name = "bst_out"; + regulator-name = "BST_OUT"; interrupts = ; }; vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; + regulator-name = "VBUS_OTG"; interrupts = ; regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; + regulator-name = "VBUS_SW"; interrupts = ; regulator-active-discharge = <1>; }; @@ -375,14 +278,15 @@ watchdog { }; i2c4_eeprom: eeprom@50 { - compatible = "microchip,24c32", - "atmel,24c32"; + compatible = "atmel,24c32"; reg = <0x50>; + status = "disabled"; }; i2c4_rtc: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; + status = "disabled"; }; }; @@ -395,13 +299,6 @@ &iwdg2 { status = "okay"; }; -&m_can2 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&m_can2_pins_a>; - pinctrl-1 = <&m_can2_sleep_pins_a>; - status = "okay"; -}; - &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; @@ -419,18 +316,22 @@ &pwr_regulators { &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; - status = "okay"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + reg = <0x58003000 0x1000>, + <0x70000000 0x1000000>; + status = "disabled"; flash0: flash@0 { - compatible = "winbond,w25q128", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; m25p,fast-read; - #address-cells = <1>; - #size-cells = <1>; }; }; @@ -442,56 +343,7 @@ &rtc { status = "okay"; }; -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_b>, <&sai2b_pins_d>; - pinctrl-1 = <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>; - status = "okay"; -}; - -&sai2a { - dma-names = "rx"; - st,sync = <&sai2b 2>; - clocks = <&rcc SAI2_K>, <&sai2b>; - clock-names = "sai_ck", "MCLK"; - #clock-cells = <0>; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&tlv320_rx_endpoint>; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; -}; - -&sai2b { - dma-names = "tx"; - #clock-cells = <0>; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&tlv320_tx_endpoint>; - mclk-fs = <256>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_b>; - pinctrl-1 = <&sdmmc1_b4_od_pins_b>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_b>; - cd-gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; - disable-wp; - st,neg-edge; - bus-width = <4>; - vmmc-supply = <&v3v3>; +&dts { status = "okay"; }; @@ -503,71 +355,10 @@ &sdmmc2 { non-removable; no-sd; no-sdio; - st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; vqmmc-supply = <&v3v3>; mmc-ddr-3_3v; -}; - -&spi1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&spi1_pins_a>; - pinctrl-1 = <&spi1_sleep_pins_a>; - cs-gpios = <&gpioz 3 0>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&uart4_pins_a>; - pinctrl-1 = <&uart4_sleep_pins_a>; - pinctrl-2 = <&uart4_idle_pins_a>; - pinctrl-3 = <&uart4_pins_a>; - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; -}; - -&usart1 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart1_pins_b &usart1_pins_a>; - pinctrl-1 = <&usart1_sleep_pins_b &usart1_sleep_pins_a>; - pinctrl-2 = <&usart1_idle_pins_b &usart1_idle_pins_a>; - uart-has-rtscts; - status = "okay"; -}; - -&usart3 { - pinctrl-names = "default", "sleep", "idle"; - pinctrl-0 = <&usart3_pins_a>; - pinctrl-1 = <&usart3_sleep_pins_a>; - pinctrl-2 = <&usart3_idle_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - status = "okay"; -}; - -&usbh_ohci { - status = "okay"; -}; - -&usbotg_hs { - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; + st,neg-edge; + status = "disabled"; }; diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile index 3f54b515c471..3a4d9204339b 100644 --- a/arch/arm/boot/dts/ti/omap/Makefile +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -80,8 +80,14 @@ dtb-$(CONFIG_ARCH_OMAP4) += \ omap4-sdp-es23plus.dtb \ omap4-var-dvk-om44.dtb \ omap4-var-stk-om44.dtb \ + omap4-samsung-espresso7.dtb \ + omap4-samsung-espresso10.dtb \ omap4-xyboard-mz609.dtb \ omap4-xyboard-mz617.dtb + +am335x-bonegreen-hdmi-00a0-dtbs := am335x-bonegreen-eco.dtb \ + am335x-bone-hdmi-00a0.dtbo + dtb-$(CONFIG_SOC_AM33XX) += \ am335x-baltos-ir2110.dtb \ am335x-baltos-ir3220.dtb \ @@ -93,6 +99,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-bonegreen.dtb \ am335x-bonegreen-wireless.dtb \ am335x-bonegreen-eco.dtb \ + am335x-bonegreen-hdmi-00a0.dtb \ am335x-chiliboard.dtb \ am335x-cm-t335.dtb \ am335x-evm.dtb \ @@ -174,3 +181,11 @@ dtb-$(CONFIG_SOC_TI81XX) += \ dm8148-t410.dtb \ dm8168-evm.dtb \ dra62x-j5eco-evm.dtb + +# Enable support for device-tree overlays +DTC_FLAGS_am335x-bone += -@ +DTC_FLAGS_am335x-boneblack += -@ +DTC_FLAGS_am335x-boneblack-wireless += -@ +DTC_FLAGS_am335x-bonegreen += -@ +DTC_FLAGS_am335x-bonegreen-wireless += -@ +DTC_FLAGS_am335x-bonegreen-eco += -@ diff --git a/arch/arm/boot/dts/ti/omap/am335x-bone-hdmi-00a0.dtso b/arch/arm/boot/dts/ti/omap/am335x-bone-hdmi-00a0.dtso new file mode 100644 index 000000000000..f43f44c79c96 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-bone-hdmi-00a0.dtso @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * 2017 Copyright (c) Seeed Technology Inc. All right reserved. + * Author: Baozhu Zuo + * Copyright (c) Bootlin 2026 + * + * This device tree overlay is compatible with the BeagleBone Black, Green + * and their subversions. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&it66121_out>; + }; + }; + }; + + clk_mcasp0_fixed: clk-mcasp0-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + clk_mcasp0: clk-mcasp0 { + #clock-cells = <0>; + compatible = "gpio-gate-clock"; + clocks = <&clk_mcasp0_fixed>; + enable-gpios = <&gpio1 27 0>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "TI BeagleBone Green HDMI cape"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + sound_master: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + clocks = <&clk_mcasp0>; + }; + + simple-audio-card,codec { + sound-dai = <&it66121>; + }; + }; +}; + +&am33xx_pinmux { + bb_lcd_pins: pinmux-bb-lcd-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_INPUT, MUX_MODE7) + >; + }; + mcasp0_pins: mcasp0-pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&i2c2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + it66121: it66121 { + compatible = "ite,it66121"; + reg = <0x4d>; + pinctrl-names = "default"; + pinctrl-0 = <&bb_lcd_pins>; + + #sound-dai-cells = <0>; + + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + it66121_in: endpoint { + bus-width = <24>; + remote-endpoint = <&lcdc_0>; + }; + }; + + port@1 { + reg = <1>; + it66121_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&lcdc { + status = "okay"; + blue-and-red-wiring = "straight"; + port { + lcdc_0: endpoint@0 { + remote-endpoint = <&it66121_in>; + }; + }; +}; + + +&mcasp0 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + op-mode = <0>; + tdm-slots = <2>; + serial-dir = < 0 0 1 0 >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + diff --git a/arch/arm/boot/dts/ti/omap/dm816x.dtsi b/arch/arm/boot/dts/ti/omap/dm816x.dtsi index 407d7bc5b13a..a1e0e904e0f0 100644 --- a/arch/arm/boot/dts/ti/omap/dm816x.dtsi +++ b/arch/arm/boot/dts/ti/omap/dm816x.dtsi @@ -94,8 +94,8 @@ dm816x_pinmux: pinmux@800 { #address-cells = <1>; #size-cells = <0>; #pinctrl-cells = <1>; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xf>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x1f>; }; /* Device Configuration Registers */ diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi index db6c53bbaf51..c8d325b0f57b 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -327,7 +327,7 @@ ocp2scp@0 { ranges = <0 0 0x8000>; reg = <0x0 0x20>; - pcie1_phy: pciephy@4000 { + pcie1_phy: pcie-phy@4000 { compatible = "ti,phy-pipe3-pcie"; reg = <0x4000 0x80>, /* phy_rx */ <0x4400 0x64>; /* phy_tx */ @@ -347,7 +347,7 @@ pcie1_phy: pciephy@4000 { #phy-cells = <0>; }; - pcie2_phy: pciephy@5000 { + pcie2_phy: pcie-phy@5000 { compatible = "ti,phy-pipe3-pcie"; reg = <0x5000 0x80>, /* phy_rx */ <0x5400 0x64>; /* phy_tx */ diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi index 4881dd674393..4c78a0b28fab 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi @@ -72,13 +72,13 @@ scm_conf: scm_conf@0 { #size-cells = <1>; }; - omap_control_usb2phy: control-phy@300 { + omap_control_usb2phy: phy@300 { compatible = "ti,control-phy-usb2"; reg = <0x300 0x4>; reg-names = "power"; }; - omap_control_usbotg: control-phy@33c { + omap_control_usbotg: phy@33c { compatible = "ti,control-phy-otghs"; reg = <0x33c 0x4>; reg-names = "otghs_control"; diff --git a/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso-common.dtsi b/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso-common.dtsi new file mode 100644 index 000000000000..06651072f000 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso-common.dtsi @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; +#include "dt-bindings/gpio/gpio.h" +#include +#include +#include "omap443x.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; /* 1 GB */ + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + continuous_splash: framebuffer@bef00000{ + reg = <0xbef00000 (1024 * 600 * 4)>; + no-map; + }; + }; + + chosen { + stdout-path = &uart3; + #address-cells = <1>; + }; + + i2c-gpio5 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + sda-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <10>; + #address-cells = <1>; + #size-cells = <0>; + + /* TODO: SMB136 Charger for 7" variant at 0x4d */ + }; + + i2c-gpio6 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + sda-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <10>; + #address-cells = <1>; + #size-cells = <0>; + + /* TODO: STMPE811 ADC at 0x41 */ + }; + + i2c-gpio7 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <3>; + #address-cells = <1>; + #size-cells = <0>; + + fuel-gauge@36 { + compatible = "maxim,max17042"; + reg = <0x36>; + pinctrl-0 = <&fuel_alert_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <500>; + maxim,dead-volt = <2500>; + maxim,over-volt = <4300>; + }; + }; + + reg_espresso_wlan: regulator-espresso-wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wlanen_gpio>; + compatible = "regulator-fixed"; + regulator-name = "espresso_wlan"; + regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <2000000>; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO_104 */ + startup-delay-us = <70000>; + regulator-always-on; + enable-active-high; + }; + + wlan_pwrseq: wlan-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&twl 0>; + clock-names = "ext_clock"; + }; + + reg_espresso_internal: regulator-espresso-internal { + compatible = "regulator-fixed"; + regulator-name = "eMMC_LDO"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; /* GPIO_63 */ + startup-delay-us = <100000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + }; + + reg_espresso_external: regulator-espresso-external { + compatible = "regulator-fixed"; + regulator-name = "vmmc1"; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; /* GPIO_34 */ + enable-active-high; + }; + + reg_touch_ldo_en: regulator-touch-ldo-en { + compatible = "regulator-fixed"; + regulator-name = "touch_ldo_en"; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* GPIO_54 */ + regulator-always-on; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-power { + label = "power"; + + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; /* GPIO_wk3 */ + linux,code = ; + wakeup-source; + }; + + button-volup { + linux,code = ; + label = "volume_up"; /* GPIO_wk30 */ + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + }; + + button-voldown { + linux,code = ; + label = "volume_down"; /* GPIO_wk8 */ + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "lcd_en"; + gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; /* GPIO_135 */ + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + }; + + pwm10: pwm-10 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm10_default>; + compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; + ti,timers = <&timer10>; + ti,clock-source = <0x00>; + }; + + lvds-encoder { + compatible = "doestek,dtc34lm85am", "lvds-encoder"; + powerdown-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; /* GPIO_136 */ + power-supply = <®_lcd>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; /* GPIO_38 */ + pinctrl-names = "default"; + pinctrl-0 = <&vibrator_default>; + }; + + gp2a_shunt: current-sense-shunt { + compatible = "current-sense-shunt"; + io-channels = <&gpadc 4>; + shunt-resistor-micro-ohms = <24000000>; /* 24 ohms */ + #io-channel-cells = <0>; + }; + + led-ir { + compatible = "gpio-ir-tx"; + gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* GPIO_59 */ + pinctrl-names = "default"; + pinctrl-0 = <&ledir_pins>; + }; +}; + +&omap4_pmx_wkup { + gpio_keys: gpio-keys-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x046, PIN_INPUT | MUX_MODE3) + /* sim_cd.gpio_wk3 - EXT_WAKEUP */ + OMAP4_IOPAD(0x056, PIN_INPUT | MUX_MODE3) + /* fref_clk3_req.gpio_wk30 - VOL_UP */ + OMAP4_IOPAD(0x05C, PIN_INPUT | MUX_MODE3) + /* fref_clk4_out.gpio_wk8 - VOL_DN */ + >; + }; +}; + +&omap4_pmx_core { + backlight_pins: pinmux-backlight-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0X0D8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) + /* usbb1_ulpitll_dat7.gpio_95 - LED_BACKLIGHT_RESET */ + >; + }; + + bluetooth_pins: pinmux-bluetooth-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x094, PIN_OUTPUT | MUX_MODE3) + /* gpmc_ncs6.gpio_103 - BT_EN */ + OMAP4_IOPAD(0x0be, PIN_OUTPUT | MUX_MODE3) + /* cam_strobe.gpio_82 - BT_nRST */ + OMAP4_IOPAD(0x0c0, PIN_INPUT | MUX_MODE3) + /* cam_globalreset.gpio_83 - BT_HOST_WAKE */ + OMAP4_IOPAD(0x0d4, PIN_OUTPUT | MUX_MODE3) + /* usbb1_ulpitll_dat5.gpio_93 - BT_WAKE */ + >; + }; + + dss_dpi_pins: pinmux-dss-dpi-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x162, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data23 */ + OMAP4_IOPAD(0x164, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data22 */ + OMAP4_IOPAD(0x166, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data21 */ + OMAP4_IOPAD(0x168, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data20 */ + OMAP4_IOPAD(0x16a, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data19 */ + OMAP4_IOPAD(0x16c, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data18 */ + OMAP4_IOPAD(0x16e, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data15 */ + OMAP4_IOPAD(0x170, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data14 */ + OMAP4_IOPAD(0x172, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data13 */ + OMAP4_IOPAD(0x174, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data12 */ + OMAP4_IOPAD(0x176, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data11 */ + OMAP4_IOPAD(0x1b4, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data10 */ + OMAP4_IOPAD(0x1b6, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data9 */ + OMAP4_IOPAD(0x1b8, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data16 */ + OMAP4_IOPAD(0x1ba, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data17 */ + OMAP4_IOPAD(0x1bc, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_hsync */ + OMAP4_IOPAD(0x1be, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_pclk */ + OMAP4_IOPAD(0x1c0, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_vsync */ + OMAP4_IOPAD(0x1c2, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_de */ + OMAP4_IOPAD(0x1c4, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data8 */ + OMAP4_IOPAD(0x1c6, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data7 */ + OMAP4_IOPAD(0x1c8, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data6 */ + OMAP4_IOPAD(0x1ca, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data5 */ + OMAP4_IOPAD(0x1cc, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data4 */ + OMAP4_IOPAD(0x1ce, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data3 */ + + OMAP4_IOPAD(0x1d0, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data2 */ + OMAP4_IOPAD(0x1d2, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data1 */ + OMAP4_IOPAD(0x1d4, PIN_OFF_OUTPUT_LOW | MUX_MODE5) + /* dispc2_data0 */ + >; + }; + + fuel_alert_irq: pinmux-fuel-alert-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE3) + /* gpmc_a20.gpio_44 */ + >; + }; + + i2c1_pins: pinmux-i2c1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) + /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) + /* i2c1_sda */ + >; + }; + + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) + /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) + /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux-i2c3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) + /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) + /* i2c3_sda */ + >; + }; + + i2c4_pins: pinmux-i2c4-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) + /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) + /* i2c4_sda */ + >; + }; + + i2c5_pins: pinmux-i2c5-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0de, PIN_INPUT_PULLUP | MUX_MODE3) + /* usbc1_icusb_dp.gpio_98 */ + OMAP4_IOPAD(0x0e0, PIN_INPUT_PULLUP | MUX_MODE3) + /* usbc1_icusb_dm.gpio_99 */ + >; + }; + + i2c6_pins: pinmux-i2c6-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE3) + /* hdmi_ddc_scl.gpio_65 */ + OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE3) + /* hdmi_ddc_sda.gpio_66 */ + >; + }; + + i2c7_pins: pinmux-i2c7-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x08a, PIN_INPUT_PULLUP | MUX_MODE3) + /* gpmc_wait0.gpio_61 */ + OMAP4_IOPAD(0x08c, PIN_INPUT_PULLUP | MUX_MODE3) + /* gpmc_wait1.gpio_62 */ + >; + }; + + ledir_pins: pimux-ledir-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x086, PIN_INPUT_PULLDOWN | MUX_MODE7) + /* gpmc_nbe0_cle.gpio_59 */ + OMAP4_IOPAD(0x156, PIN_INPUT_PULLDOWN | MUX_MODE7) + /* mcspi4_simo.gpio_152 */ + >; + }; + + lvds_pins: pinmux-lvds-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0X136, PIN_OUTPUT | MUX_MODE3) + /* mcspi1_simo.gpio_136 - LVDS_nSHDN */ + >; + }; + + mmc1_pins: pinmux-mmc1-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLDOWN | MUX_MODE0) + /* sdmmc1_clk */ + OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmcc1_cmd */ + OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmcc1_dat0 */ + OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmmc1_dat1 */ + OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmmc1_dat2 */ + OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmmc1_dat3 */ + >; + }; + + mmc2_pins: pinmux-mmc2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_dat0 */ + OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_dat1 */ + OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_dat2 */ + OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_dat3 */ + OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_dat4 */ + OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_dat5 */ + OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_dat6 */ + OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_dat7 */ + OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_clk */ + OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) + /* sdmmc2_cmd */ + >; + }; + + mmc5_pins: pinmux-mmc5-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x148, PIN_INPUT_PULLDOWN | MUX_MODE0) + /* sdmmc5_clk.sdmmc5_clk */ + OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmmc5_cmd.sdmmc5_cmd */ + OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmmc5_dat0.sdmmc5_dat0 */ + OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmmc5_dat1.sdmmc5_dat1 */ + OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmmc5_dat2.sdmmc5_dat2 */ + OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) + /* sdmmc5_dat3.sdmmc5_dat3 */ + >; + }; + + pwm10_default: pinmux-pwm10-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0X0D6, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE1) + /* usbb1_ulpitll_dat6.dmtimer10_pwm_evt - LED_BACKLIGHT_PWM */ + >; + }; + + touch_pins: pinmux-touch-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x06c, PIN_INPUT | MUX_MODE3) + /* gpmc_a22.gpio_46 - TSP_INT */ + >; + }; + + uart2_pins: pinmux-uart2-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) + /* uart2_cts.uart2_cts */ + OMAP4_IOPAD(0x11a, PIN_INPUT_PULLUP | MUX_MODE0) + /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) + /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_INPUT_PULLUP | MUX_MODE0) + /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux-uart3-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) + /* uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) + /* uart3_tx_irtx */ + >; + }; + + vibrator_default: pinmux-vibrator-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x05c, PIN_INPUT_PULLDOWN | MUX_MODE3) + /* gpmc_ad14.gpio_38 - MOTOR_EN */ + >; + }; + + wlanen_gpio: pinmux-wlanen-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x096, PIN_OUTPUT | MUX_MODE3) + /* gpmc_ncs7.gpio_104 */ + >; + }; + + wlan_host_wake: pinmux-wlan-host-wake-pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x0bc, PIN_INPUT | MUX_MODE3) + /* cam_shutter.gpio_81 - WLAN_HOST_WAKE */ + >; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: pmic@48 { + reg = <0x48>; + #clock-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = < + &twl6030_pins + &twl6030_wkup_pins + >; + + /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ + interrupts = ; /* IRQ_SYS_1N cascaded to gic */ + interrupt-parent = <&gic>; + system-power-controller; + }; +}; + +#include "twl6032.dtsi" +#include "twl6030_omap4.dtsi" + +&ldo1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; +}; + +&ldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; + +&ldousb { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + accelerometer@18 { + compatible = "bosch,bma254"; + reg = <0x18>; + vdd-supply = <&ldo4>; + vddio-supply = <&ldo5>; + interrupt-parent = <&gpio4>; + interrupts = <25 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>, + <26 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + }; + + magnetometer@2e { + compatible = "yamaha,yas530"; + reg = <0x2e>; + vdd-supply = <&ldo4>; + iovdd-supply = <&ldo5>; + reset-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + interrupts = <&gpio6 10 IRQ_TYPE_EDGE_RISING>; + }; + + light-sensor@44 { + compatible = "sharp,gp2ap002a00f"; + reg = <0x44>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ldo4>; + vio-supply = <&ldo4>; + io-channels = <&gp2a_shunt>; + io-channel-names = "alsout"; + sharp,proximity-far-hysteresis = /bits/ 8 <0x40>; + sharp,proximity-close-hysteresis = /bits/ 8 <0x20>; + }; +}; + +&dss { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&bridge_in>; + data-lines = <24>; + }; + }; +}; + +&twl_usb_comparator { + usb-supply = <&ldousb>; +}; + +&usb_otg_hs { + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + + vmmc-supply = <®_espresso_external>; + bus-width = <4>; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + vmmc-supply = <®_espresso_internal>; + ti,non-removable; + bus-width = <8>; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&mmc5 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + vmmc-supply = <®_espresso_wlan>; + mmc-pwrseq = <&wlan_pwrseq>; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc5_pins>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio3>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_host_wake>; + }; +}; + +&uart2 { + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART2_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_pins>; + shutdown-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + device-wakeup-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wakeup"; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso10.dts b/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso10.dts new file mode 100644 index 000000000000..558dc3c029e9 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso10.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include "omap4-samsung-espresso-common.dtsi" +#include +/ { + model = "Samsung Galaxy Tab 2 (10 inch)"; + compatible = "samsung,espresso10", "ti,omap4430", "ti,omap4"; + + i2c-gpio5 { + smb347: charger@6 { + compatible = "summit,smb347"; + reg = <0x6>; // 0x0C >> 1 + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_EDGE_BOTH>; + + summit,enable-usb-charging; + summit,enable-charge-control = ; + summit,chip-temperature-threshold-celsius = <120>; + summit,usb-current-limit-microamp = <1800000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + pwms = <&pwm10 0 1600 0>; + power-supply = <®_lcd>; + enable-gpios = <&gpio3 31 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + + panel { + compatible = "samsung,ltn101al03", "panel-lvds"; + power-supply = <®_lcd>; + width-mm = <223>; + height-mm = <125>; + data-mapping = "vesa-24"; + backlight = <&backlight>; + + panel-timing { + clock-frequency = <69818000>; + + hback-porch = <64>; + hactive = <1280>; + hfront-porch = <16>; + hsync-len = <48>; + + vback-porch = <11>; + vactive = <800>; + vfront-porch = <16>; + vsync-len = <3>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&i2c3 { + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + + //avdd-supply = <®_touch_ldo_en>; + vdd-supply = <&ldo6>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <200>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + syna,sensor-type = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso7.dts b/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso7.dts new file mode 100644 index 000000000000..cae37ff066c3 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/omap4-samsung-espresso7.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include "omap4-samsung-espresso-common.dtsi" + +/ { + model = "Samsung Galaxy Tab 2 (7 inch)"; + compatible = "samsung,espresso7", "ti,omap4430", "ti,omap4"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + pwms = <&pwm10 0 1200 0>; + power-supply = <®_lcd>; + enable-gpios = <&gpio3 31 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <2>; + }; + + panel { + compatible = "samsung,ltn070nl01", "panel-lvds"; + power-supply = <®_lcd>; + width-mm = <154>; + height-mm = <90>; + data-mapping = "vesa-24"; + backlight = <&backlight>; + + panel-timing { + clock-frequency = <47255554>; + + hback-porch = <210>; + hactive = <1024>; + hfront-porch = <186>; + hsync-len = <50>; + + vback-porch = <11>; + vactive = <600>; + vfront-porch = <24>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + syncclk-active = <0>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&i2c3 { + touchscreen@48 { + compatible = "melfas,mms136"; + reg = <0x48>; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + avdd-supply = <®_touch_ldo_en>; + vdd-supply = <&ldo6>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi index 487259132ebf..915870eb5c99 100644 --- a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi @@ -472,7 +472,7 @@ usb2_phy: usb2phy@4000 { #phy-cells = <0>; }; - usb3_phy: usb3phy@4400 { + usb3_phy: usb3-phy@4400 { compatible = "ti,omap-usb3"; reg = <0x4400 0x80>, <0x4800 0x64>, diff --git a/arch/arm/boot/dts/ti/omap/twl6032.dtsi b/arch/arm/boot/dts/ti/omap/twl6032.dtsi new file mode 100644 index 000000000000..d599a2ca62a4 --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/twl6032.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Integrated Power Management Chip + * https://www.ti.com/lit/ds/symlink/twl6032.pdf + */ + +&twl { + compatible = "ti,twl6032"; + interrupt-controller; + #interrupt-cells = <1>; + + rtc { + compatible = "ti,twl4030-rtc"; + interrupts = <11>; + }; + + vio: regulator-vio { + compatible = "ti,twl6032-vio"; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,twl6032-ldo1"; + }; + + ldo2: regulator-ldo2 { + compatible = "ti,twl6032-ldo2"; + }; + + ldo3: regulator-ldo3 { + compatible = "ti,twl6032-ldo3"; + }; + + ldo4: regulator-ldo4 { + compatible = "ti,twl6032-ldo4"; + }; + + ldo5: regulator-ldo5 { + compatible = "ti,twl6032-ldo5"; + }; + + ldo6: regulator-ldo6 { + compatible = "ti,twl6032-ldo6"; + }; + + ldoln: regulator-ldoln { + compatible = "ti,twl6032-ldoln"; + }; + + ldousb: regulator-ldousb { + compatible = "ti,twl6032-ldousb"; + }; + + smps4: regulator-smps4 { + compatible = "ti,twl6032-smps4"; + }; + + gpadc: gpadc { + compatible = "ti,twl6032-gpadc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; + + twl_usb_comparator: usb-comparator { + compatible = "ti,twl6030-usb"; + interrupts = <4>, <10>; + }; + + twl_pwm: pwm { + compatible = "ti,twl6030-pwm"; + #pwm-cells = <2>; + }; + + twl_pwmled: pwmled { + compatible = "ti,twl6030-pwmled"; + #pwm-cells = <2>; + }; +}; diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index a2bb55bc0081..9e3abb14fbc1 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -15,5 +15,3 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o - -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c deleted file mode 100644 index 3ec810b6f1a7..000000000000 --- a/arch/arm/mach-tegra/board-paz00.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-tegra/board-paz00.c - * - * Copyright (C) 2011 Marc Dietrich - * - * Based on board-harmony.c - * Copyright (C) 2010 Google, Inc. - */ - -#include -#include -#include -#include -#include -#include - -#include "board.h" - -static const struct software_node tegra_gpiochip_node = { - .name = "tegra-gpio", -}; - -static const struct property_entry wifi_rfkill_prop[] __initconst = { - PROPERTY_ENTRY_STRING("name", "wifi_rfkill"), - PROPERTY_ENTRY_STRING("type", "wlan"), - PROPERTY_ENTRY_GPIO("reset-gpios", - &tegra_gpiochip_node, 25, GPIO_ACTIVE_HIGH), - PROPERTY_ENTRY_GPIO("shutdown-gpios", - &tegra_gpiochip_node, 85, GPIO_ACTIVE_HIGH), - { } -}; - -static const struct platform_device_info wifi_rfkill_info __initconst = { - .name = "rfkill_gpio", - .id = PLATFORM_DEVID_NONE, - .properties = wifi_rfkill_prop, -}; - -void __init tegra_paz00_wifikill_init(void) -{ - struct platform_device *pd; - int err; - - err = software_node_register(&tegra_gpiochip_node); - if (err) { - pr_err("failed to register %s node: %d\n", - tegra_gpiochip_node.name, err); - return; - } - - pd = platform_device_register_full(&wifi_rfkill_info); - err = PTR_ERR_OR_ZERO(pd); - if (err) - pr_err("failed to register WiFi rfkill device: %d\n", err); -} diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 7b3ef0dc9be1..86c3ea0d6b30 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -19,6 +19,4 @@ void __init tegra_map_common_io(void); void __init tegra_init_irq(void); -void __init tegra_paz00_wifikill_init(void); - #endif diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 9ef1dfa7b926..f324a7e491d8 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -83,10 +83,6 @@ static void __init tegra_dt_init(void) static void __init tegra_dt_init_late(void) { - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && - of_machine_is_compatible("compal,paz00")) - tegra_paz00_wifikill_init(); - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("nvidia,tegra20")) platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0); diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 2edfa7bf4ab3..d116864b6c2b 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-taiqicat-a01.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 0fecf0abb204..04a26762a19a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1000,6 +1000,8 @@ uart0: serial@1c28000 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1011,6 +1013,8 @@ uart1: serial@1c28400 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1022,6 +1026,8 @@ uart2: serial@1c28800 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1033,6 +1039,8 @@ uart3: serial@1c28c00 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1044,6 +1052,8 @@ uart4: serial@1c29000 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-taiqicat-a01.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-taiqicat-a01.dts new file mode 100644 index 000000000000..225f42bd3b9e --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-taiqicat-a01.dts @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2026 Jun Yan + +/dts-v1/; + +#include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" +#include "sun50i-h6-gpu-opp.dtsi" + +#include + +/ { + model = "TaiqiCat (TQC) A01"; + compatible = "ultrapower,taiqicat-a01", "allwinner,sun50i-h6"; + + aliases { + ethernet1 = &sdio_wifi; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "taiqicat:blue:power"; + gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + default-state = "on"; + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC jack */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun50i-h6-spdif"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ + post-power-on-delay-ms = <200>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdca>; +}; + +&de { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&gpu { + mali-supply = <®_dcdcc>; + status = "okay"; +}; + +&hdmi { + hvcc-supply = <®_bldo2>; + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&mmc0 { + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + disable-wp; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_cldo3>; + vqmmc-supply = <®_bldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; + cap-mmc-hw-reset; + non-removable; + mmc-hs200-1_8v; + bus-width = <8>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_bldo3>; +}; + +&r_i2c { + status = "okay"; + + axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl-led-ir-pg-pm-ts"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + regulator-enable-ramp-delay = <100000>; + }; + + aldo3 { + /* unused */ + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18-dram-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc-emmc-efuse-hdmi"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg-wifiio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33-io-pd-emmc-sd-usb-uart"; + }; + + /* This regulator is connected with CLDO3 */ + reg_cldo2: cldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1160000>; + regulator-ramp-delay = <2500>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-enable-ramp-delay = <32000>; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-ramp-delay = <2500>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys-hdmi-usb"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&r_ir { + status = "okay"; +}; + +&r_pio { + /* + * PL0 and PL1 are used for PMIC I2C + * don't enable the pl-supply else + * it will fail at boot + * + * vcc-pl-supply = <®_aldo1>; + */ + vcc-pm-supply = <®_aldo1>; +}; + +&rtc { + clocks = <&ext_osc32k>; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43430a1-bt"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_cldo3>; + vddio-supply = <®_bldo3>; + device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ + shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + max-speed = <1500000>; + }; +}; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + usb0_vbus-supply = <®_vcc5v>; + usb3_vbus-supply = <®_vcc5v>; + status = "okay"; +}; + +&usb3phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 73e8604315c5..72ce1a75647b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -540,6 +540,8 @@ uart0: serial@5000000 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -551,6 +553,8 @@ uart1: serial@5000400 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -562,6 +566,8 @@ uart2: serial@5000800 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -573,6 +579,8 @@ uart3: serial@5000c00 { reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 8d1110c14bad..bf054869e78b 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -228,6 +228,15 @@ cpu_speed_grade: cpu-speed-grade@0 { }; }; + timer0: timer@3009000 { + compatible = "allwinner,sun50i-h616-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x03009000 0xa0>; + interrupts = , + ; + clocks = <&osc24M>; + }; + watchdog: watchdog@30090a0 { compatible = "allwinner,sun50i-h616-wdt", "allwinner,sun6i-a31-wdt"; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index a4230205c02b..5afa8d92acbf 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -153,6 +153,13 @@ i2s2_pi_pins: i2s2-pi-pins { bias-disable; }; + /omit-if-no-ref/ + ledc_ph_pin: ledc-ph-pin { + pins = "PH19"; + function = "ledc"; + allwinner,pinmux = <5>; + }; + mmc0_pins: mmc0-pins { pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; allwinner,pinmux = <2>; @@ -221,6 +228,13 @@ spi0_pc_pins: spi0-pc-pins { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_pj_pins: spi0-pj-pins { + pins = "PJ21", "PJ22", "PJ23"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + /omit-if-no-ref/ spi0_cs0_pc_pin: spi0-cs0-pc-pin { pins = "PC3"; @@ -228,6 +242,13 @@ spi0_cs0_pc_pin: spi0-cs0-pc-pin { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_cs0_pj_pin: spi0-cs0-pj-pin { + pins = "PJ20"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + /omit-if-no-ref/ spi0_cs1_pc_pin: spi0-cs1-pc-pin { pins = "PC7"; @@ -235,6 +256,13 @@ spi0_cs1_pc_pin: spi0-cs1-pc-pin { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_cs1_pj_pin: spi0-cs1-pj-pin { + pins = "PJ24"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + /omit-if-no-ref/ spi0_hold_pc_pin: spi0-hold-pc-pin { /* conflicts with eMMC D7 */ @@ -243,6 +271,13 @@ spi0_hold_pc_pin: spi0-hold-pc-pin { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_hold_pj_pin: spi0-hold-pj-pin { + pins = "PJ26"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + /omit-if-no-ref/ spi0_wp_pc_pin: spi0-wp-pc-pin { /* conflicts with eMMC D2 */ @@ -251,6 +286,13 @@ spi0_wp_pc_pin: spi0-wp-pc-pin { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_wp_pj_pin: spi0-wp-pj-pin { + pins = "PJ25"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; allwinner,pinmux = <2>; @@ -283,6 +325,21 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ledc: led-controller@2008000 { + compatible = "allwinner,sun55i-a523-ledc", + "allwinner,sun50i-a100-ledc"; + reg = <0x02008000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + wdt: watchdog@2050000 { compatible = "allwinner,sun55i-a523-wdt"; reg = <0x2050000 0x20>; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 054d0357c139..474354fbfcec 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -6,6 +6,7 @@ #include "sun55i-a523.dtsi" #include +#include / { model = "Avaota A1"; @@ -99,6 +100,46 @@ &gpu { status = "okay"; }; +&ledc { + pinctrl-names = "default"; + pinctrl-0 = <&ledc_ph_pin>; + allwinner,pixel-format = "grb"; + allwinner,t0l-ns = <800>; + allwinner,t0h-ns = <300>; + allwinner,t1l-ns = <320>; + allwinner,t1h-ns = <800>; + allwinner,treset-ns = <84>; + status = "okay"; + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + }; + + multi-led@1 { + reg = <0x1>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + multi-led@2 { + reg = <0x2>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + multi-led@3 { + reg = <0x3>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; +}; + &mdio0 { ext_rgmii0_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -362,6 +403,21 @@ &rtc { assigned-clock-rates = <32768>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pj_pins>, <&spi0_cs0_pj_pin>, + <&spi0_hold_pj_pin>, <&spi0_wp_pj_pin>; + status = "okay"; + + nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile index 1bf0c472f6b4..540bb5ae746b 100644 --- a/arch/arm64/boot/dts/altera/Makefile +++ b/arch/arm64/boot/dts/altera/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \ + socfpga_stratix10_socdk_emmc.dtb \ socfpga_stratix10_socdk_nand.dtb \ socfpga_stratix10_swvp.dtb diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 4ae18a013bbe..e2a1cea7f3da 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -3,53 +3,11 @@ * Copyright Altera Corporation (C) 2015. All rights reserved. */ -#include "socfpga_stratix10.dtsi" +#include "socfpga_stratix10_socdk.dtsi" / { model = "SoCFPGA Stratix 10 SoCDK"; compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - led-hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - led-hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - led-hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0x80000000 0 0>; - }; - - ref_033v: regulator-v-ref { - compatible = "regulator-fixed"; - regulator-name = "0.33V"; - regulator-min-microvolt = <330000>; - regulator-max-microvolt = <330000>; - }; }; &pinctrl0 { @@ -68,10 +26,6 @@ i2c1_pmx_func_gpio: i2c1-pmx-func-gpio-pins { }; }; -&gpio1 { - status = "okay"; -}; - &gmac0 { status = "okay"; phy-mode = "rgmii"; @@ -83,7 +37,7 @@ mdio0 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { + phy0: ethernet-phy@4 { reg = <4>; txd0-skew-ps = <0>; /* -420ps */ @@ -111,23 +65,6 @@ &mmc { clk-phase-sd-hs = <0>, <135>; }; -&osc1 { - clock-frequency = <25000000>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - &i2c1 { status = "okay"; clock-frequency = <100000>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtsi new file mode 100755 index 000000000000..1d50f7b21160 --- /dev/null +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright Altera Corporation (C) 2026. All rights reserved. + */ + +#include "socfpga_stratix10.dtsi" + +/ { + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led-hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led-hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led-hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; + + ref_033v: regulator-0v33-ref { + compatible = "regulator-fixed"; + regulator-name = "0.33V"; + regulator-min-microvolt = <330000>; + regulator-max-microvolt = <330000>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_emmc.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_emmc.dts new file mode 100755 index 000000000000..b2a3449638dd --- /dev/null +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_emmc.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright Altera Corporation (C) 2026. All rights reserved. + */ + +#include "socfpga_stratix10_socdk.dtsi" + +/ { + model = "SoCFPGA Stratix 10 SoCDK eMMC daughter board"; + compatible = "altr,socfpga-stratix10-socdk-emmc", + "altr,socfpga-stratix10-socdk", + "altr,socfpga-stratix10"; +}; + +&gmac2 { + status = "okay"; + /* PHY delays is configured via skew properties */ + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@4 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <100000>; + i2c-sda-falling-time-ns = <890>; /* hcnt */ + i2c-scl-falling-time-ns = <890>; /* lcnt */ + + adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&ref_033v>; + }; + + temp@4c { + compatible = "maxim,max1619"; + reg = <0x4c>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index f30ee045dc95..b35b03da2d84 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,6 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-a320-fvp.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += zena-css-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts new file mode 100644 index 000000000000..0f72af78b5e1 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000-a320.dtsi" +#include "corstone1000-fvp.dtsi" + +/ { + model = "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-a320-fvp"; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi new file mode 100644 index 000000000000..f0937914350c --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026, Arm Limited. All rights reserved. + * + */ + +#include + +#include "corstone1000.dtsi" + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a320"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a320"; + reg = <0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a320"; + reg = <0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a320"; + reg = <0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + sram: sram@2400000 { + compatible = "mmio-sram"; + reg = <0x02400000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x1c000000 0x10000>, + <0x1c040000 0x80000>; + interrupts = ; + }; + + + soc { + npu@1a050000 { + compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85"; + reg = <0x1a050000 0x1400>; + interrupts = ; + clocks = <&refclk100mhz>, <&refclk100mhz>; + clock-names = "core", "apb"; + sram = <&sram>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index 66ba6b027193..fac0999b1901 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -8,70 +8,46 @@ /dts-v1/; #include "corstone1000.dtsi" +#include "corstone1000-fvp.dtsi" / { model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; compatible = "arm,corstone1000-fvp"; - smsc: ethernet@4010000 { - compatible = "smsc,lan91c111"; - reg = <0x40100000 0x10000>; - phy-mode = "mii"; - interrupts = ; - reg-io-width = <2>; - }; + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; - vmmc_v3_3d: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc_supply"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; - sdmmc0: mmc@40300000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x40300000 0x1000>; - interrupts = ; - max-frequency = <12000000>; - vmmc-supply = <&vmmc_v3_3d>; - clocks = <&smbclk>, <&refclk100mhz>; - clock-names = "smclk", "apb_pclk"; - }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; - sdmmc1: mmc@50000000 { - compatible = "arm,pl18x", "arm,primecell"; - reg = <0x50000000 0x10000>; - interrupts = ; - max-frequency = <12000000>; - vmmc-supply = <&vmmc_v3_3d>; - clocks = <&smbclk>, <&refclk100mhz>; - clock-names = "smclk", "apb_pclk"; - }; -}; - -&cpus { - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&L2_0>; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; }; }; diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi new file mode 100644 index 000000000000..dc6d77446e8f --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/ { + smsc: ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + }; + + vmmc_v3_3d: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x40300000 0x1000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x50000000 0x10000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts index 10d265be0c02..adcfaf7c55b8 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts @@ -13,6 +13,19 @@ / { model = "ARM Corstone1000 FPGA MPS3 board"; compatible = "arm,corstone1000-mps3"; + cpus: cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + }; + smsc: ethernet@4010000 { compatible = "smsc,lan9220", "smsc,lan9115"; reg = <0x40100000 0x10000>; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index f35a5c96f3da..4d57dc197918 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -21,19 +21,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - }; - }; - memory@88200000 { device_type = "memory"; reg = <0x88200000 0x77e00000>; diff --git a/arch/arm64/boot/dts/arm/zena-css-fvp.dts b/arch/arm64/boot/dts/arm/zena-css-fvp.dts new file mode 100644 index 000000000000..53c5412d92b2 --- /dev/null +++ b/arch/arm64/boot/dts/arm/zena-css-fvp.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2025, Arm Limited. All rights reserved. + */ + +/dts-v1/; + +#include "zena-css.dtsi" + +/ { + model = "Zena CSS Fixed Virtual Platform"; + compatible = "arm,zena-css-fvp", "arm,zena-css", "arm,vexpress"; + + chosen { + stdout-path = &soc_serial0; + }; + + memory@80000000 { + device_type = "memory"; + + /* ~2GB mapped at 2GB, another 2GB at 2TB */ + reg = <0x00000000 0x80000000 0x00000000 0x7f000000>, + <0x00000200 0x00000000 0x00000000 0x80000000>; + }; +}; + +&soc { + virtio@30020000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30020000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30030000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30030000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30040000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30040000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30050000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30050000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30060000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30060000 0x0 0x10000>; + interrupts = ; + }; + + virtio@30080000 { + compatible = "virtio,mmio"; + reg = <0x0 0x30080000 0x0 0x10000>; + interrupts = ; + }; +}; diff --git a/arch/arm64/boot/dts/arm/zena-css.dtsi b/arch/arm64/boot/dts/arm/zena-css.dtsi new file mode 100644 index 000000000000..0b41ee4bf4c6 --- /dev/null +++ b/arch/arm64/boot/dts/arm/zena-css.dtsi @@ -0,0 +1,769 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2025, Arm Limited. All rights reserved. + */ + +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + soc_clk24mhz: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "refclk24mhz"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* + * The latency and residency numbers below are for illustrative + * purposes only and may vary on actual silicon. These values are + * considered just to demonstrate that the cpuidle governor logic + * works. + */ + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10000>; + entry-latency-us = <800>; + exit-latency-us = <3200>; + local-timer-stop; + min-residency-us = <4200>; + }; + + cluster_sleep: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <1000>; + exit-latency-us = <3200>; + local-timer-stop; + min-residency-us = <4500>; + }; + }; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x0000>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl0_l2_0>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl0_l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl0_l3>; + }; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x0100>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl0_l2_1>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl0_l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl0_l3>; + }; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x0200>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl0_l2_2>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl0_l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl0_l3>; + }; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x0300>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl0_l2_3>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl0_l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl0_l3>; + }; + }; + + cpu4: cpu@10000 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x10000>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl1_l2_0>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl1_l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl1_l3>; + }; + }; + + cpu5: cpu@10100 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x10100>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl1_l2_1>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl1_l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl1_l3>; + }; + }; + + cpu6: cpu@10200 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x10200>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl1_l2_2>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl1_l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl1_l3>; + }; + }; + + cpu7: cpu@10300 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x10300>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl1_l2_3>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl1_l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl1_l3>; + }; + }; + + cpu8: cpu@20000 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x20000>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl2_l2_0>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl2_l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl2_l3>; + }; + }; + + cpu9: cpu@20100 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x20100>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl2_l2_1>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl2_l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl2_l3>; + }; + }; + + cpu10: cpu@20200 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x20200>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl2_l2_2>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl2_l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl2_l3>; + }; + }; + + cpu11: cpu@20300 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x20300>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl2_l2_3>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl2_l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl2_l3>; + }; + }; + + cpu12: cpu@30000 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x30000>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl3_l2_0>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl3_l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl3_l3>; + }; + }; + + cpu13: cpu@30100 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x30100>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl3_l2_1>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl3_l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl3_l3>; + }; + }; + + cpu14: cpu@30200 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x30200>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl3_l2_2>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl3_l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl3_l3>; + }; + }; + + cpu15: cpu@30300 { + compatible = "arm,cortex-a720ae"; + device_type = "cpu"; + reg = <0x00 0x30300>; + enable-method = "psci"; + + clocks = <&scmi_dvfs 0>; + cpu-idle-states = <&cpu_sleep &cluster_sleep>; + next-level-cache = <&cl3_l2_3>; + + i-cache-line-size = <64>; + i-cache-sets = <256>; + i-cache-size = <0x10000>; + + d-cache-line-size = <64>; + d-cache-sets = <256>; + d-cache-size = <0x10000>; + + cl3_l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <0x400>; /* 8-way set */ + cache-size = <0x80000>; /* 512KB */ + cache-unified; + next-level-cache = <&cl3_l3>; + }; + }; + + cl0_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <0x1000>; /* 16-way set */ + cache-size = <0x400000>; /* 4MB */ + cache-unified; + }; + + cl1_l3: l3-cache1 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <0x1000>; /* 16-way set */ + cache-size = <0x400000>; /* 4MB */ + cache-unified; + }; + + cl2_l3: l3-cache2 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <0x1000>; /* 16-way set */ + cache-size = <0x400000>; /* 4MB */ + cache-unified; + }; + + cl3_l3: l3-cache3 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <0x1000>; /* 16-way set */ + cache-size = <0x400000>; /* 4MB */ + cache-unified; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + #address-cells = <1>; + #size-cells = <0>; + + mbox-names = "tx", "tx_reply", "rx"; + mboxes = <&mbox_db_tx 0 0 0>, + <&mbox_db_rx 0 0 0>, + <&mbox_db_rx 0 0 2>; + shmem = <&scmi_shmem_tx &scmi_shmem_rx>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + }; + }; + + dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + interrupts = ; + }; + + dsu-pmu-1 { + compatible = "arm,dsu-pmu"; + cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + interrupts = ; + }; + + dsu-pmu-2 { + compatible = "arm,dsu-pmu"; + cpus = <&cpu8 &cpu9 &cpu10 &cpu11>; + interrupts = ; + }; + + dsu-pmu-3 { + compatible = "arm,dsu-pmu"; + cpus = <&cpu12 &cpu13 &cpu14 &cpu15>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sram: sram@104000 { + compatible = "mmio-sram"; + reg = <0x0 0x00104000 0x0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x00104000 0x00001000>; + + scmi_shmem_tx: scpshmem-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + + scmi_shmem_rx: scpshmem-sram-section@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x100>; + }; + }; + + timer@1a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x1a810000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + /* + * Map child space [0x0..0x30000) to parent @ 0x1a810000 + */ + ranges = <0x0 0x0 0x1a810000 0x00030000>; + + frame@20000 { + reg = <0x20000 0x10000>; + frame-number = <0>; + interrupts = ; + }; + }; + + gic: interrupt-controller@20800000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + #redistributor-regions = <16>; + interrupt-controller; + interrupts = ; + ranges; + + /* + * With GIC-A720AE multiview enabled, GICR_TYPER.Last is + * always reported as 1 on redistributor views other than + * view 0. This breaks discovery of a single contiguous + * GICR frame region, so each core is described with its own + * redistributor region. + */ + reg = <0x0 0x20800000 0x0 0x10000>, /* GICD */ + <0x0 0x20880000 0x0 0x40000>, /* 16 * GICR */ + <0x0 0x208c0000 0x0 0x40000>, + <0x0 0x20900000 0x0 0x40000>, + <0x0 0x20940000 0x0 0x40000>, + <0x0 0x20980000 0x0 0x40000>, + <0x0 0x209c0000 0x0 0x40000>, + <0x0 0x20a00000 0x0 0x40000>, + <0x0 0x20a40000 0x0 0x40000>, + <0x0 0x20a80000 0x0 0x40000>, + <0x0 0x20ac0000 0x0 0x40000>, + <0x0 0x20b00000 0x0 0x40000>, + <0x0 0x20b40000 0x0 0x40000>, + <0x0 0x20b80000 0x0 0x40000>, + <0x0 0x20bc0000 0x0 0x40000>, + <0x0 0x20c00000 0x0 0x40000>, + <0x0 0x20c40000 0x0 0x40000>; + + its: msi-controller@20840000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x20840000 0x0 0x40000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + /* + * UART is fixed at 24MHz, both UARTCLK and PCLK. + */ + soc_serial0: serial@1a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x1a400000 0x0 0x10000>; + interrupts = ; + clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + watchdog@1a420000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x1a420000 0x0 0x10000>, + <0x0 0x1a430000 0x0 0x10000>; + interrupts = ; + }; + + rtc@300d0000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0x300d0000 0x0 0x10000>; + interrupts = ; + clocks = <&soc_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mbox_db_tx: mailbox@40020000 { + compatible = "arm,mhuv3"; + reg = <0x0 0x40020000 0x0 0x30000>; + interrupts = ; + interrupt-names = "combined"; + clocks = <&soc_clk24mhz>; + #mbox-cells = <3>; + }; + + mbox_db_rx: mailbox@40060000 { + compatible = "arm,mhuv3"; + reg = <0x0 0x40060000 0x0 0x30000>; + interrupts = ; + interrupt-names = "combined"; + clocks = <&soc_clk24mhz>; + #mbox-cells = <3>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts index 7de24d60bcd1..127be0fc27c2 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-d-rpi-5-b.dts @@ -35,3 +35,17 @@ &gio_aon { "PMIC_SCL", // AON_SGPIO_04 "PMIC_SDA"; // AON_SGPIO_05 }; + +&pinctrl { + compatible = "brcm,bcm2712d0-pinctrl"; + reg = <0x7d504100 0x20>; +}; + +&pinctrl_aon { + compatible = "brcm,bcm2712d0-aon-pinctrl"; + reg = <0x7d510700 0x1c>; +}; + +&uart10 { + interrupts = ; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi index 04738bf281eb..b7a6bc34ae1a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi @@ -44,6 +44,30 @@ power_button: power-button { }; }; + firmware { + firmware: rpi-firmware { + compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; + + mboxes = <&mailbox>; + + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; + + power: power { + compatible = "raspberrypi,bcm2835-power"; + firmware = <&firmware>; + #power-domain-cells = <1>; + }; + }; + }; + sd_io_1v8_reg: sd-io-1v8-reg { compatible = "regulator-gpio"; regulator-name = "vdd-sd-io"; @@ -189,33 +213,6 @@ wifi: wifi@1 { }; }; -&soc { - firmware: firmware { - compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - - mboxes = <&mailbox>; - dma-ranges; - - firmware_clocks: clocks { - compatible = "raspberrypi,firmware-clocks"; - #clock-cells = <1>; - }; - - reset: reset { - compatible = "raspberrypi,firmware-reset"; - #reset-cells = <1>; - }; - }; - - power: power { - compatible = "raspberrypi,bcm2835-power"; - firmware = <&firmware>; - #power-domain-cells = <1>; - }; -}; - /* uarta communicates with the BT module */ &uarta { uart-has-rtscts; @@ -252,3 +249,7 @@ &pcie1 { &pcie2 { status = "okay"; }; + +&v3d { + clocks = <&firmware_clocks 5>; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts index 285608281446..0fc57e72632e 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -68,6 +68,30 @@ usb_vbus_default_state: usb-vbus-default-state { function = "vbus1"; groups = "vbus1"; }; + + rp1_i2c4_default_state: rp1-i2c4-default-state { + function = "i2c4"; + groups = "i2c4_2"; + drive-strength = <12>; + bias-pull-up; + }; + + rp1_i2c6_default_state: rp1-i2c6-default-state { + function = "i2c6"; + groups = "i2c6_0"; + drive-strength = <12>; + bias-pull-up; + }; +}; + +&rp1_i2c4 { + pinctrl-0 = <&rp1_i2c4_default_state>; + pinctrl-names = "default"; +}; + +&rp1_i2c6 { + pinctrl-0 = <&rp1_i2c6_default_state>; + pinctrl-names = "default"; }; &rp1_usb0 { diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index d57a9b1bff70..761c59d90ffc 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) #include +#include / { compatible = "brcm,bcm2712"; @@ -508,10 +509,6 @@ axi: axi { <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; - vc4: gpu { - compatible = "brcm,bcm2712-vc6"; - }; - pcie0: pcie@1000100000 { compatible = "brcm,bcm2712-pcie"; reg = <0x10 0x00100000 0x00 0x9310>; @@ -646,6 +643,30 @@ mip1: msi-controller@1000131000 { msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>; brcm,msi-offset = <8>; }; + + isp: isp@1000880000 { + compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe"; + reg = <0x10 0x00880000 0x0 0x4000>; + interrupts = ; + clocks = <&firmware_clocks 7>; + }; + + v3d: gpu@1002000000 { + compatible = "brcm,2712-v3d"; + reg = <0x10 0x02000000 0x00 0x4000>, + <0x10 0x02008000 0x00 0x6000>, + <0x10 0x02030800 0x00 0x0700>; + reg-names = "hub", "core0", "sms"; + + power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; + resets = <&pm BCM2835_RESET_V3D>; + interrupts = , + ; + }; + }; + + vc4: gpu { + compatible = "brcm,bcm2712-vc6"; }; timer { diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi index 5a815c379794..16f535939583 100644 --- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi +++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi @@ -26,6 +26,83 @@ rp1_clocks: clocks@40018000 { <200000000>; // RP1_CLK_SYS }; + rp1_i2c0: i2c@40070000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x40070000 0x0 0x1000>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + i2c-scl-rising-time-ns = <65>; + i2c-scl-falling-time-ns = <100>; + + status = "disabled"; + }; + + rp1_i2c1: i2c@40074000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x40074000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + i2c-scl-rising-time-ns = <65>; + i2c-scl-falling-time-ns = <100>; + + status = "disabled"; + }; + + rp1_i2c2: i2c@40078000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x40078000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + i2c-scl-rising-time-ns = <65>; + i2c-scl-falling-time-ns = <100>; + + status = "disabled"; + }; + + rp1_i2c3: i2c@4007c000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x4007c000 0x0 0x1000>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + i2c-scl-rising-time-ns = <65>; + i2c-scl-falling-time-ns = <100>; + + status = "disabled"; + }; + + rp1_i2c4: i2c@40080000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x40080000 0x0 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + i2c-scl-rising-time-ns = <65>; + i2c-scl-falling-time-ns = <100>; + + status = "disabled"; + }; + + rp1_i2c5: i2c@40084000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x40084000 0x0 0x1000>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + i2c-scl-rising-time-ns = <65>; + i2c-scl-falling-time-ns = <100>; + + status = "disabled"; + }; + + rp1_i2c6: i2c@40088000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x40088000 0x0 0x1000>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>; + i2c-scl-rising-time-ns = <65>; + i2c-scl-falling-time-ns = <100>; + + status = "disabled"; + }; + rp1_gpio: pinctrl@400d0000 { compatible = "raspberrypi,rp1-gpio"; reg = <0x00 0x400d0000 0x0 0xc000>, @@ -56,6 +133,34 @@ rp1_eth: ethernet@40100000 { #size-cells = <0>; }; + rp1_csi0: csi@40110000 { + compatible = "raspberrypi,rp1-cfe"; + reg = <0x0 0x40110000 0x0 0x100>, // CSI2 DMA address + <0x0 0x40114000 0x0 0x100>, // PHY/CSI Host address + <0x0 0x40120000 0x0 0x100>, // MIPI CFG address + <0x0 0x40124000 0x0 0x1000>; // PiSP FE address + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>; + assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>; + assigned-clock-rates = <25000000>; + + status = "disabled"; + }; + + rp1_csi1: csi@40128000 { + compatible = "raspberrypi,rp1-cfe"; + reg = <0x0 0x40128000 0x0 0x100>, // CSI2 DMA address + <0x0 0x4012c000 0x0 0x100>, // PHY/CSI Host address + <0x0 0x40138000 0x0 0x100>, // MIPI CFG address + <0x0 0x4013c000 0x0 0x1000>; // PiSP FE address + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>; + assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>; + assigned-clock-rates = <25000000>; + + status = "disabled"; + }; + rp1_usb0: usb@40200000 { compatible = "snps,dwc3"; reg = <0x00 0x40200000 0x0 0x100000>; diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts index 4dee8cd0b86d..e39c87774c12 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -36,6 +36,22 @@ linux,cma { }; +&fch_gpio0 { + status = "okay"; +}; + +&fch_gpio1 { + status = "okay"; +}; + +&fch_gpio2 { + status = "okay"; +}; + +&fch_gpio3 { + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -86,6 +102,18 @@ &pcie_x1_1_rc { status = "okay"; }; +&s5_gpio0 { + status = "okay"; +}; + +&s5_gpio1 { + status = "okay"; +}; + +&s5_gpio2 { + status = "okay"; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/cix/sky1-power.h b/arch/arm64/boot/dts/cix/sky1-power.h new file mode 100644 index 000000000000..53f4a3af36b3 --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1-power.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ + +#ifndef __SKY1_POWER_H__ +#define __SKY1_POWER_H__ + +/* The Rich OS need flow the macro */ +#define SKY1_PD_AUDIO 0 +#define SKY1_PD_PCIE_CTRL0 1 +#define SKY1_PD_PCIE_DUMMY 2 +#define SKY1_PD_PCIEHUB 3 +#define SKY1_PD_MMHUB 4 +#define SKY1_PD_MMHUB_SMMU 5 +#define SKY1_PD_DPU0 6 +#define SKY1_PD_DPU1 7 +#define SKY1_PD_DPU2 8 +#define SKY1_PD_DPU3 9 +#define SKY1_PD_DPU4 10 +#define SKY1_PD_VPU_TOP 11 +#define SKY1_PD_VPU_CORE0 12 +#define SKY1_PD_VPU_CORE1 13 +#define SKY1_PD_VPU_CORE2 14 +#define SKY1_PD_VPU_CORE3 15 +#define SKY1_PD_NPU_CORE0 16 +#define SKY1_PD_NPU_CORE1 17 +#define SKY1_PD_NPU_CORE2 18 +#define SKY1_PD_NPU_TOP 19 +#define SKY1_PD_ISP0 20 +#define SKY1_PD_GPU 21 + +#endif diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index fb8c826bbc97..bb5cfb1f2113 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -6,6 +6,7 @@ #include #include +#include "sky1-power.h" / { interrupt-parent = <&gic>; @@ -168,6 +169,19 @@ scmi_clk: protocol@14 { #clock-cells = <1>; }; }; + + ap_to_tfa_scmi: scmi-1 { + compatible = "arm,scmi-smc"; + arm,smc-id = <0xc2000001>; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&ap_tfa_scmi_mem>; + + smc_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + }; }; pmu-a520 { @@ -185,6 +199,13 @@ psci { method = "smc"; }; + s5_gpio_apb_clk: clock-100000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "s5_gpio_apb_clk"; + }; + soc@0 { compatible = "simple-bus"; ranges = <0 0 0 0 0x20 0>; @@ -348,6 +369,76 @@ i3c1: i3c@4100000 { status = "disabled"; }; + fch_gpio0: gpio-controller@4120000 { + compatible = "cdns,gpio-r1p02"; + reg = <0x0 0x4120000 0x0 0x1000>; + clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + fch_gpio1: gpio-controller@4130000 { + compatible = "cdns,gpio-r1p02"; + reg = <0x0 0x4130000 0x0 0x1000>; + clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + fch_gpio2: gpio-controller@4140000 { + compatible = "cdns,gpio-r1p02"; + reg = <0x0 0x4140000 0x0 0x1000>; + clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + fch_gpio3: gpio-controller@4150000 { + compatible = "cdns,gpio-r1p02"; + reg = <0x0 0x4150000 0x0 0x1000>; + clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <17>; + + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + syscon: syscon@4160000 { + compatible = "cix,sky1-system-control", "syscon"; + reg = <0x0 0x4160000 0x0 0x100>; + #reset-cells = <1>; + }; + iomuxc: pinctrl@4170000 { compatible = "cix,sky1-pinctrl"; reg = <0x0 0x04170000 0x0 0x1000>; @@ -428,6 +519,7 @@ pcie_x8_rc: pcie@a010000 { #size-cells = <2>; bus-range = <0xc0 0xff>; device_type = "pci"; + power-domains = <&smc_devpd SKY1_PD_PCIE_CTRL0>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, @@ -568,10 +660,70 @@ ppi_partition1: interrupt-partition-1 { }; }; + s5_syscon: syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x0 0x16000000 0x0 0x1000>; + #reset-cells = <1>; + }; + + s5_gpio0: gpio-controller@16004000 { + compatible = "cdns,gpio-r1p02"; + reg = <0x0 0x16004000 0x0 0x1000>; + clocks = <&s5_gpio_apb_clk>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + s5_gpio1: gpio-controller@16005000 { + compatible = "cdns,gpio-r1p02"; + reg = <0x0 0x16005000 0x0 0x1000>; + clocks = <&s5_gpio_apb_clk>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <10>; + + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + s5_gpio2: gpio-controller@16006000 { + compatible = "cdns,gpio-r1p02"; + reg = <0x0 0x16006000 0x0 0x1000>; + clocks = <&s5_gpio_apb_clk>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <10>; + + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + iomuxc_s5: pinctrl@16007000 { compatible = "cix,sky1-pinctrl-s5"; reg = <0x0 0x16007000 0x0 0x1000>; }; + + ap_tfa_scmi_mem: shmem@84380000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x84380000 0x0 0x80>; + reg-io-width = <4>; + }; }; timer { diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index bcca63136557..76cc23acb9b2 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -8,7 +8,9 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \ exynos5433-tm2e.dtb \ exynos7-espresso.dtb \ exynos7870-a2corelte.dtb \ + exynos7870-j5y17lte.dtb \ exynos7870-j6lte.dtb \ + exynos7870-j7xelte.dtb \ exynos7870-on7xelte.dtb \ exynos7885-jackpotlte.dtb \ exynos850-e850-96.dtb \ diff --git a/arch/arm64/boot/dts/exynos/axis/Makefile b/arch/arm64/boot/dts/exynos/axis/Makefile index ccf00de64016..da6a426516fc 100644 --- a/arch/arm64/boot/dts/exynos/axis/Makefile +++ b/arch/arm64/boot/dts/exynos/axis/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ARTPEC) += \ - artpec8-grizzly.dtb + artpec8-grizzly.dtb \ + artpec9-alfred.dtb diff --git a/arch/arm64/boot/dts/exynos/axis/artpec9-alfred.dts b/arch/arm64/boot/dts/exynos/axis/artpec9-alfred.dts new file mode 100644 index 000000000000..5a779f1acf3b --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec9-alfred.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-9 Alfred board device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +/dts-v1/; +#include "artpec9.dtsi" +#include "artpec9-pinctrl.dtsi" +#include + +/ { + model = "ARTPEC-9 alfred board"; + compatible = "axis,artpec9-alfred", "axis,artpec9"; + + aliases { + serial0 = &serial_0; + }; + + chosen { + stdout-path = &serial_0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&osc_clk { + clock-frequency = <50000000>; +}; diff --git a/arch/arm64/boot/dts/exynos/axis/artpec9-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec9-pinctrl.dtsi new file mode 100644 index 000000000000..a9fbdf7734d4 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec9-pinctrl.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-9 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include "artpec-pinctrl.h" + +&pinctrl_fsys0 { + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe3: gpe3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe4: gpe4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpi0: gpi0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps0: gps0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps1: gps1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_fsys1 { + gpu0: gpu0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + serial0_bus: serial0-bus-pins { + samsung,pins = "gpu0-0", "gpu0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_peric { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi new file mode 100644 index 000000000000..f8ed43c6e825 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec9.dtsi @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-9 SoC device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include +#include + +/ { + compatible = "axis,artpec9"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + pinctrl0 = &pinctrl_fsys0; + pinctrl1 = &pinctrl_fsys1; + pinctrl2 = &pinctrl_peric; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + }; + }; + + fin_pll: clock-finpll { + compatible = "fixed-factor-clock"; + clocks = <&osc_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fin_pll"; + }; + + osc_clk: clock-osc { + /* XXTI */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc_clk"; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x0 0x0 0x17000000>; + #address-cells = <2>; + #size-cells = <2>; + + cmu_imem: clock-controller@10010000 { + compatible = "axis,artpec9-cmu-imem"; + reg = <0x0 0x10010000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_CA5>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_SSS>; + clock-names = "fin_pll", "aclk", "ca5", "jpeg", "sss"; + }; + + timer@10040000 { + compatible = "axis,artpec9-mct", "samsung,exynos4210-mct"; + reg = <0x0 0x10040000 0x0 0x1000>; + clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT0_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x10400000 0x0 0x00040000>, + <0x0 0x10440000 0x0 0x000c0000>; + #interrupt-cells = <3>; + interrupt-controller; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + }; + + cmu_cpucl: clock-controller@12810000 { + compatible = "axis,artpec9-cmu-cpucl"; + reg = <0x0 0x12810000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>; + clock-names = "fin_pll", "switch"; + }; + + cmu_cmu: clock-controller@12c00000 { + compatible = "axis,artpec9-cmu-cmu"; + reg = <0x0 0x12c00000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + cmu_core: clock-controller@12c10000 { + compatible = "axis,artpec9-cmu-core"; + reg = <0x0 0x12c10000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>; + clock-names = "fin_pll", "main"; + }; + + cmu_bus: clock-controller@13410000 { + compatible = "axis,artpec9-cmu-bus"; + reg = <0x0 0x13410000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_BUS>; + clock-names = "fin_pll", "bus"; + }; + + cmu_peri: clock-controller@14010000 { + compatible = "axis,artpec9-cmu-peri"; + reg = <0x0 0x14010000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_PERI_IP>, + <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>; + clock-names = "fin_pll", "ip", "disp"; + }; + + pinctrl_peric: pinctrl@141f0000 { + compatible = "axis,artpec9-pinctrl"; + reg = <0x0 0x141f0000 0x0 0x1000>; + interrupts = ; + }; + + cmu_fsys0: clock-controller@14410000 { + compatible = "axis,artpec9-cmu-fsys0"; + reg = <0x0 0x14410000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS0_BUS>, + <&cmu_cmu CLK_DOUT_CMU_FSYS0_IP>; + clock-names = "fin_pll", "bus", "ip"; + }; + + pinctrl_fsys0: pinctrl@14430000 { + compatible = "axis,artpec9-pinctrl"; + reg = <0x0 0x14430000 0x0 0x1000>; + interrupts = ; + }; + + cmu_fsys1: clock-controller@14c10000 { + compatible = "axis,artpec9-cmu-fsys1"; + reg = <0x0 0x14c10000 0x0 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>; + clock-names = "fin_pll", "scan0", "scan1", "bus"; + }; + + pinctrl_fsys1: pinctrl@14c30000 { + compatible = "axis,artpec9-pinctrl"; + reg = <0x0 0x14c30000 0x0 0x1000>; + interrupts = ; + }; + + pmu_system_controller: system-controller@14c40000 { + compatible = "axis,artpec9-pmu", "samsung,exynos7-pmu", "syscon"; + reg = <0x0 0x14c40000 0x0 0x10000>; + }; + + serial_0: serial@14c70000 { + compatible = "axis,artpec9-uart", "samsung,exynos8895-uart"; + reg = <0x0 0x14c70000 0x0 0x100>; + clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_UART0_PCLK>, + <&cmu_fsys1 CLK_GOUT_FSYS1_UART0_SCLK_UART>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&serial0_bus>; + samsung,uart-fifosize = <64>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts b/arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts index 6f40ca4350ed..0888cd2faca4 100644 --- a/arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7870-a2corelte.dts @@ -158,9 +158,6 @@ &gpu { }; &hsi2c0 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; pmic@66 { @@ -394,9 +391,6 @@ vdd_ldo35: ldo35 { }; &i2c5 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <400000>; @@ -428,9 +422,6 @@ proximity@48 { }; &i2c6 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <400000>; diff --git a/arch/arm64/boot/dts/exynos/exynos7870-j5y17lte.dts b/arch/arm64/boot/dts/exynos/exynos7870-j5y17lte.dts new file mode 100644 index 000000000000..36c327668db5 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos7870-j5y17lte.dts @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Galaxy J5 (2017) (j5y17lte) device tree source + * + * Copyright (c) 2024 Andras Sebok + */ + +/dts-v1/; +#include "exynos7870.dtsi" +#include +#include +#include + +/ { + model = "Samsung Galaxy J5 (2017)"; + compatible = "samsung,j5y17lte", "samsung,exynos7870"; + chassis-type = "handset"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc2; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + }; + + chosen { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + stdout-path = &serial2; + + framebuffer@67000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x67000000 (720 * 1280 * 4)>; + width = <720>; + height = <1280>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_power &key_voldown &key_volup>; + + key-home { + interrupt-parent = <&gpa1>; + linux,code = ; + label = "gpio-keys: KEY_HOMEPAGE"; + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>; + }; + + key-power { + interrupt-parent = <&gpa0>; + linux,code = ; + label = "gpio-keys: KEY_POWER"; + gpios = <&gpa0 0 GPIO_ACTIVE_LOW>; + }; + + key-voldown { + interrupt-parent = <&gpa2>; + linux,code = ; + label = "gpio-keys: KEY_VOLUMEDOWN"; + gpios = <&gpa2 1 GPIO_ACTIVE_LOW>; + }; + + key-volup { + interrupt-parent = <&gpa2>; + linux,code = ; + label = "gpio-keys: KEY_VOLUMEUP"; + gpios = <&gpa2 0 GPIO_ACTIVE_LOW>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x3e400000>, + <0x0 0x80000000 0x40000000>; + }; + + pwrseq_mmc1: pwrseq-mmc1 { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpd3 6 GPIO_ACTIVE_LOW>; + }; + + vdd_fixed_mmc2: regulator-fixed-mmc2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed_mmc2"; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + + gpio = <&gpc0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + ramoops@46e00000 { + compatible = "ramoops"; + reg = <0x0 0x46e00000 0x8000>; + console-size = <0x4000>; + pmsg-size = <0x4000>; + }; + + framebuffer@67000000 { + reg = <0x0 0x67000000 (720 * 1280 * 4)>; + no-map; + }; + }; + + vibrator { + compatible = "regulator-haptic"; + haptic-supply = <&vdd_ldo32>; + min-microvolt = <3300000>; + max-microvolt = <3300000>; + }; +}; + +&gpu { + status = "okay"; +}; + +&hsi2c0 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mpu05-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpa0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq>; + + regulators { + vdd_buck1: buck1 { + regulator-name = "vdd_buck1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_buck2: buck2 { + regulator-name = "vdd_buck2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_buck3: buck3 { + regulator-name = "vdd_buck3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_buck4: buck4 { + regulator-name = "vdd_buck4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_buck5: buck5 { + regulator-name = "vdd_buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo1: ldo1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo2: ldo2 { + regulator-name = "vdd_ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12000>; + }; + + vdd_ldo3: ldo3 { + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo4: ldo4 { + regulator-name = "vdd_ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo5: ldo5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo6: ldo6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo7: ldo7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo8: ldo8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3375000>; + regulator-ramp-delay = <12000>; + }; + + vdd_ldo9: ldo9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo10: ldo10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo25: ldo25 { + regulator-name = "vdd_ldo25"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo26: ldo26 { + regulator-name = "vdd_ldo26"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3375000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo27: ldo27 { + regulator-name = "vdd_ldo27"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo29: ldo29 { + regulator-name = "vdd_ldo29"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo30: ldo30 { + regulator-name = "vdd_ldo30"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo31: ldo31 { + regulator-name = "vdd_ldo31"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ldo32: ldo32 { + regulator-name = "vdd_ldo32"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12000>; + }; + + vdd_ldo33: ldo33 { + regulator-name = "vdd_ldo33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12000>; + }; + + vdd_ldo34: ldo34 { + regulator-name = "vdd_ldo34"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_ldo35: ldo35 { + regulator-name = "vdd_ldo35"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + + status = "okay"; + + touchscreen@50 { + compatible = "imagis,ist3038h"; + reg = <0x50>; + + interrupt-parent = <&gpa0>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_irq>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + vdd-supply = <&vdd_ldo34>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_rdqs &sd0_bus1 &sd0_bus4 &sd0_bus8>; + + vmmc-supply = <&vdd_ldo26>; + vqmmc-supply = <&vdd_ldo27>; + + fifo-depth = <64>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + non-removable; + + status = "okay"; +}; + +&mmc1 { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>; + + mmc-pwrseq = <&pwrseq_mmc1>; + + bus-width = <4>; + fifo-depth = <64>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + non-removable; + cap-sd-highspeed; + cap-sdio-irq; + + status = "okay"; + + wifi@0 { + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; + reg = <0x0>; + + interrupt-names = "host-wake"; + interrupt-parent = <&gpa2>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&gpd3 6 GPIO_ACTIVE_LOW>; + }; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + accel_irq: accel-irq-pins { + samsung,pins = "gpa2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + dwmmc2_irq: dwmmc2-irq-pins { + samsung,pins = "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fuel_irq: fuel-irq-pins { + samsung,pins = "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hall_irq: hall-irq-pins { + samsung,pins = "gpa1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_power: key-power-pins { + samsung,pins = "gpa0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_voldown: key-voldown-pins { + samsung,pins = "gpa2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_volup: key-volup-pins { + samsung,pins = "gpa2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_irq: pmic-irq-pins { + samsung,pins = "gpa0-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touch_irq: touch-irq-pins { + samsung,pins = "gpa0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + wlan_hostwake: wlan-hostwake-pins { + samsung,pins = "gpa2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_top { + wlan_enable: wlan-enable-pins { + samsung,pins = "gpd3-6"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; +}; + +&serial2 { + status = "okay"; +}; + +&usbdrd { + vdd33-supply = <&vdd_ldo8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts b/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts index 09f2367cfec9..de30d0970336 100644 --- a/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts @@ -383,9 +383,6 @@ vdd_ldo35: ldo35 { }; &i2c5 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <400000>; @@ -409,9 +406,6 @@ accelerometer@1d { }; &i2c6 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <400000>; diff --git a/arch/arm64/boot/dts/exynos/exynos7870-j7xelte.dts b/arch/arm64/boot/dts/exynos/exynos7870-j7xelte.dts new file mode 100644 index 000000000000..079b2b581307 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos7870-j7xelte.dts @@ -0,0 +1,494 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Galaxy J7 (2016) (j7xelte) device tree source + * + * Copyright (c) 2025 Rayan Marzouk + */ + +/dts-v1/; +#include "exynos7870.dtsi" +#include +#include +#include + +/ { + model = "Samsung Galaxy J7 (2016)"; + compatible = "samsung,j7xelte", "samsung,exynos7870"; + chassis-type = "handset"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc2; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + }; + + chosen { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + stdout-path = &serial2; + + framebuffer@67000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x67000000 (720 * 1280 * 4)>; + width = <720>; + height = <1280>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "GPIO Keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_home &key_power &key_voldown &key_volup>; + + key-home { + label = "Home Key"; + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-power { + label = "Power Key"; + gpios = <&gpa0 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-voldown { + label = "Volume Down Key"; + gpios = <&gpa2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volup { + label = "Volume Up Key"; + gpios = <&gpa2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x3e400000>, + <0x0 0x80000000 0x40000000>; + }; + + pwrseq_mmc1: pwrseq-mmc1 { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpd3 6 GPIO_ACTIVE_LOW>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + ramoops@46e00000 { + compatible = "ramoops"; + reg = <0x0 0x46e00000 0x8000>; + console-size = <0x4000>; + pmsg-size = <0x4000>; + }; + + cont_splash_mem: framebuffer@67000000 { + reg = <0x0 0x67000000 0x00384000>; + no-map; + }; + }; + + vdd_fixed_mmc2: regulator-fixed-mmc2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed_mmc2"; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + gpio = <&gpc0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vibrator { + compatible = "regulator-haptic"; + haptic-supply = <&vdd_ldo32>; + min-microvolt = <3300000>; + max-microvolt = <3300000>; + }; +}; + +&gpu { + status = "okay"; +}; + +&hsi2c0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mpu05-pmic"; + reg = <0x66>; + interrupt-parent = <&gpa0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq>; + + regulators { + vdd_buck1: buck1 { + regulator-name = "vdd_buck1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_buck2: buck2 { + regulator-name = "vdd_buck2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_buck3: buck3 { + regulator-name = "vdd_buck3"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_buck4: buck4 { + regulator-name = "vdd_buck4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_buck5: buck5 { + regulator-name = "vdd_buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo1: ldo1 { + regulator-name = "vdd_ldo1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo2: ldo2 { + regulator-name = "vdd_ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + }; + + vdd_ldo3: ldo3 { + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo4: ldo4 { + regulator-name = "vdd_ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo5: ldo5 { + regulator-name = "vdd_ldo5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo6: ldo6 { + regulator-name = "vdd_ldo6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo7: ldo7 { + regulator-name = "vdd_ldo7"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo8: ldo8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_ldo9: ldo9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo10: ldo10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo25: ldo25 { + regulator-name = "vdd_ldo25"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo26: ldo26 { + regulator-name = "vdd_ldo26"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3375000>; + }; + + vdd_ldo27: ldo27 { + regulator-name = "vdd_ldo27"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2375000>; + }; + + vdd_ldo29: ldo29 { + regulator-name = "vdd_ldo29"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo30: ldo30 { + regulator-name = "vdd_ldo30"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo31: ldo31 { + regulator-name = "vdd_ldo31"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo32: ldo32 { + regulator-name = "vdd_ldo32"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_ldo33: ldo33 { + regulator-name = "vdd_ldo33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo34: ldo34 { + regulator-name = "vdd_ldo34"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ldo35: ldo35 { + regulator-name = "vdd_ldo35"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <400000>; + + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mip4_ts"; + reg = <0x48>; + + interrupt-parent = <&gpc3>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_irq>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_rdqs &sd0_bus1 &sd0_bus4 &sd0_bus8>; + + vmmc-supply = <&vdd_ldo26>; + vqmmc-supply = <&vdd_ldo27>; + + fifo-depth = <64>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + non-removable; + + status = "okay"; +}; + +&mmc1 { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>; + + mmc-pwrseq = <&pwrseq_mmc1>; + + bus-width = <4>; + fifo-depth = <64>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + non-removable; + cap-sd-highspeed; + cap-sdio-irq; + + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; + reg = <0x1>; + + interrupt-names = "host-wake"; + interrupt-parent = <&gpa2>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&gpd3 6 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &dwmmc2_irq>; + + vmmc-supply = <&vdd_fixed_mmc2>; + vqmmc-supply = <&vdd_ldo2>; + + bus-width = <4>; + card-detect-delay = <200>; + fifo-depth = <64>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + sd-uhs-sdr50; + sd-uhs-sdr104; + broken-cd; + disable-wp; + + status = "okay"; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + dwmmc2_irq: dwmmc2-irq-pins { + samsung,pins = "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fuel_irq: fuel-irq-pins { + samsung,pins = "gpa0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_home: key-home-pins { + samsung,pins = "gpa1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_power: key-power-pins { + samsung,pins = "gpa0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_voldown: key-voldown-pins { + samsung,pins = "gpa2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_volup: key-volup-pins { + samsung,pins = "gpa2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_irq: pmic-irq-pins { + samsung,pins = "gpa0-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_touch { + touch_irq: touch-irq-pins { + samsung,pins = "gpc3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&serial2 { + status = "okay"; +}; + +&usbdrd { + vdd33-supply = <&vdd_ldo8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts b/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts index 29e124c72e9d..29be4764f84d 100644 --- a/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts @@ -398,9 +398,6 @@ vdd_ldo35: ldo35 { }; &i2c1 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <400000>; @@ -438,9 +435,6 @@ rmi4-f12@12 { }; &i2c7 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <400000>; @@ -464,9 +458,6 @@ accelerometer@1d { }; &i2c8 { - #address-cells = <1>; - #size-cells = <0>; - samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <400000>; diff --git a/arch/arm64/boot/dts/exynos/exynos7870.dtsi b/arch/arm64/boot/dts/exynos/exynos7870.dtsi index 2827e10d6962..19f9ae783587 100644 --- a/arch/arm64/boot/dts/exynos/exynos7870.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7870.dtsi @@ -220,6 +220,9 @@ hsi2c0: i2c@10510000 { clock-names = "hsi2c"; clocks = <&cmu_mif CLK_GOUT_MIF_HSI2C_IPCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -422,6 +425,9 @@ i2c0: i2c@13830000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C0_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -437,6 +443,9 @@ i2c1: i2c@13840000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C1_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -452,6 +461,9 @@ i2c2: i2c@13850000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C2_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -467,6 +479,9 @@ i2c3: i2c@13860000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C3_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -482,6 +497,9 @@ i2c4: i2c@13870000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C4_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -497,6 +515,9 @@ i2c5: i2c@13880000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C5_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -512,6 +533,9 @@ i2c6: i2c@13890000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C6_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -527,6 +551,9 @@ hsi2c1: i2c@138a0000 { clock-names = "hsi2c"; clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C1_IPCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -542,6 +569,9 @@ hsi2c2: i2c@138b0000 { clock-names = "hsi2c"; clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C2_IPCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -557,6 +587,9 @@ hsi2c3: i2c@138c0000 { clock-names = "hsi2c"; clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C3_IPCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -572,6 +605,9 @@ i2c7: i2c@138d0000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C7_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -587,6 +623,9 @@ i2c8: i2c@138e0000 { clock-names = "i2c"; clocks = <&cmu_peri CLK_GOUT_PERI_I2C8_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -602,6 +641,9 @@ hsi2c4: i2c@138f0000 { clock-names = "hsi2c"; clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C4_IPCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -617,6 +659,9 @@ hsi2c5: i2c@13950000 { clock-names = "hsi2c"; clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C5_IPCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -632,6 +677,9 @@ hsi2c6: i2c@13960000 { clock-names = "hsi2c"; clocks = <&cmu_peri CLK_GOUT_PERI_HSI2C6_IPCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts b/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts index 61e064af3337..305dc72f93d8 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts @@ -103,8 +103,6 @@ reg_placeholder: regulator-0 { }; &hsi2c_23 { - #address-cells = <1>; - #size-cells = <0>; status = "okay"; touchscreen@48 { diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index f92d2a8a20a2..ff114cd6c9ea 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -266,6 +266,10 @@ hsi2c_5: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c5_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -305,6 +309,10 @@ hsi2c_6: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c6_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -328,6 +336,10 @@ hsi2c_7: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c5_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -367,6 +379,10 @@ hsi2c_8: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c8_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -390,6 +406,10 @@ hsi2c_9: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c9_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -429,6 +449,10 @@ hsi2c_10: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c10_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -452,6 +476,10 @@ hsi2c_11: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c11_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -491,6 +519,10 @@ hsi2c_12: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c12_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -565,6 +597,10 @@ hsi2c_13: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c13_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -604,6 +640,10 @@ hsi2c_14: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c14_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -627,6 +667,10 @@ hsi2c_15: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c15_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -666,6 +710,10 @@ hsi2c_16: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c16_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -689,6 +737,10 @@ hsi2c_17: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c17_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -728,6 +780,10 @@ hsi2c_18: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c18_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -751,6 +807,10 @@ hsi2c_19: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c19_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -790,6 +850,10 @@ hsi2c_20: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c20_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -813,6 +877,10 @@ hsi2c_21: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c21_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -852,6 +920,10 @@ hsi2c_22: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c22_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -875,6 +947,10 @@ hsi2c_23: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c23_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -914,6 +990,10 @@ hsi2c_24: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c24_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -937,6 +1017,10 @@ hsi2c_25: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c25_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -976,6 +1060,10 @@ hsi2c_26: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c26_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -999,6 +1087,10 @@ hsi2c_27: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c27_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -1038,6 +1130,10 @@ hsi2c_28: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c28_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -1061,6 +1157,10 @@ hsi2c_29: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c29_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -1100,6 +1200,10 @@ hsi2c_30: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c30_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -1123,6 +1227,10 @@ hsi2c_31: i2c@0 { interrupts = ; pinctrl-0 = <&hsi2c31_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -1162,6 +1270,10 @@ hsi2c_32: i2c@10000 { interrupts = ; pinctrl-0 = <&hsi2c32_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; }; @@ -1180,6 +1292,10 @@ hsi2c_1: i2c@10990000 { interrupts = ; pinctrl-0 = <&hsi2c1_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -1191,6 +1307,10 @@ hsi2c_2: i2c@109a0000 { interrupts = ; pinctrl-0 = <&hsi2c2_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -1202,6 +1322,10 @@ hsi2c_3: i2c@109b0000 { interrupts = ; pinctrl-0 = <&hsi2c3_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; @@ -1213,6 +1337,10 @@ hsi2c_4: i2c@109c0000 { interrupts = ; pinctrl-0 = <&hsi2c4_bus>; pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 02bf2ca52fdc..0bf7c4cb9846 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1473,6 +1473,19 @@ cmu_mfd: clock-controller@19e00000 { "noc"; }; + cmu_g3d: clock-controller@1a000000 { + compatible = "samsung,exynosautov920-cmu-g3d"; + reg = <0x1a000000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_G3D_SWITCH>, + <&cmu_top DOUT_CLKCMU_G3D_NOCP>; + clock-names = "oscclk", + "switch", + "nocp"; + }; + pinctrl_aud: pinctrl@1a460000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 8df42bedbc03..36721adcaa23 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include #include "gs101-pixel-common.dtsi" / { @@ -15,6 +16,27 @@ / { compatible = "google,gs101-oriole", "google,gs101"; }; +&acpm_ipc { + pmic-1 { + regulators { + ldo14m { + /* PLL */ + regulator-name = "avdd18_tcxo"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo31m { + regulator-name = "nfc"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + }; + }; + }; +}; + &cont_splash_mem { reg = <0x0 0xfac00000 (1080 * 2400 * 4)>; status = "okay"; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi index 93892adaa679..5227cd4e314b 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi @@ -10,6 +10,7 @@ #include #include +#include #include #include "gs101-pinctrl.h" #include "gs101.dtsi" @@ -28,6 +29,8 @@ chosen { framebuffer0: framebuffer-0 { compatible = "simple-framebuffer"; memory-region = <&cont_splash_mem>; + vci-supply = <&s2mpg10_ldo22m>; + vddi-supply = <&s2mpg11_bucka>; /* format properties to be added by actual board */ status = "disabled"; }; @@ -101,7 +104,7 @@ cont_splash_mem: splash@fac00000 { }; &acpm_ipc { - pmic { + pmic-1 { compatible = "samsung,s2mpg10-pmic"; interrupts-extended = <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; @@ -109,6 +112,22 @@ pmic { system-power-controller; wakeup-source; + vinl1m-supply = <&s2mpg11_buck3s>; + vinl2m-supply = <&s2mpg11_buck3s>; + vinl3m-supply = <&s2mpg10_buck8m>; + vinl4m-supply = <&s2mpg10_buck9m>; + vinl5m-supply = <&s2mpg10_buck9m>; + vinl6m-supply = <&s2mpg10_buck9m>; + vinl7m-supply = <&s2mpg11_buck6s>; + vinl8m-supply = <&s2mpg11_buck6s>; + vinl9m-supply = <&s2mpg11_buck7s>; + vinl10m-supply = <&s2mpg11_buck7s>; + vinl11m-supply = <&s2mpg11_buck7s>; + vinl12m-supply = <&s2mpg11_bucka>; + vinl13m-supply = <&s2mpg11_bucka>; + vinl14m-supply = <&s2mpg11_buckboost>; + vinl15m-supply = <&s2mpg11_buckboost>; + clocks { compatible = "samsung,s2mpg10-clk"; #clock-cells = <1>; @@ -117,6 +136,489 @@ clocks { }; regulators { + buck1m { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + samsung,ext-control = ; + }; + + buck2m { + regulator-name = "vdd_cpucl2"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + buck3m { + regulator-name = "vdd_cpucl1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + buck4m { + regulator-name = "vdd_cpucl0"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + buck5m { + regulator-name = "vdd_int"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + buck6m { + regulator-name = "vdd_cpucl2_m"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + buck7m { + /* GPU */ + regulator-name = "vdd_int_m"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + samsung,ext-control = ; + }; + + s2mpg10_buck8m: buck8m { + regulator-name = "lldo2"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + }; + + s2mpg10_buck9m: buck9m { + regulator-name = "lldo3"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + }; + + buck10m { + regulator-name = "vdd_tpu"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo1m { + /* ALIVE, AOC PLL */ + regulator-name = "vdd_l1m_alive"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + }; + + ldo2m { + /* lots, DDR */ + regulator-name = "vdd_l2m_alive"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + }; + + ldo3m { + /* AVDD: MIPI CSI & DSI, PLL: CPUCL SHARED TPU UFS */ + regulator-name = "ldo3m"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo4m { + /* AVDD: MIPI CSI & DSI, UFS, OTP, TS_SUB, TS_TOP, XOTP */ + regulator-name = "ldo4m"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo5m { + /* VDD: ADD, AVDD: TCXO & TCXO_FAR */ + regulator-name = "avdd075_tcxo"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo6m { + /* PLL CPUCL & MIFx, UFS clk, MIPI DSI */ + regulator-name = "vdd_pll"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo7m { + /* IO (HSI (USB)) */ + regulator-name = "vdd_hsi"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6250>; + /* + * TODO: link to HSI power domain, without this, + * Linux hangs during USB access. + */ + regulator-always-on; + }; + + ldo8m { + regulator-name = "vdd085_usb"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + ldo9m { + regulator-name = "vdd18_usb"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + }; + + ldo10m { + regulator-name = "vdd33_usb"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo11m { + regulator-name = "vdd_cpucl1_m"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo12m { + regulator-name = "vdd_cpucl0_m"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo13m { + regulator-name = "vdd_tpu_m"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + /* ldo14m is board specific */ + + ldo15m { + regulator-name = "vdd_slc_m"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + ldo16m { + regulator-name = "vdd085_pcie0"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + }; + + ldo17m { + regulator-name = "vdd085_pcie1"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + }; + + ldo18m { + regulator-name = "vdd18_pcie0"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + }; + + ldo19m { + regulator-name = "vdd18_pcie1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + }; + + ldo20m { + /* DMIC, memory power */ + regulator-name = "vddq_aoc_pdm"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo21m { + /* Dauntless */ + regulator-name = "vdd_dtls"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + s2mpg10_ldo22m: ldo22m { + /* display */ + regulator-name = "vci_disp"; + regulator-min-microvolt = <3025000>; + regulator-max-microvolt = <3025000>; + }; + + /* ldo23m & ldo24m are unused */ + + ldo25m { + /* touch */ + regulator-name = "dvdd_tsp"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + }; + + ldo26m { + /* touch */ + regulator-name = "avdd_ts"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + ldo27m { + /* under-display fingerprint scanner */ + regulator-name = "avdd_udfps"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + /* + *ldo28m .. ldo30m are unused, ldo31m is board specific + */ + }; + }; + + pmic-2 { + compatible = "samsung,s2mpg11-pmic"; + interrupts-extended = <&gpa0 7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sub_pmic_int>; + wakeup-source; + + vinl1s-supply = <&s2mpg10_buck8m>; + vinl2s-supply = <&s2mpg11_buck6s>; + vinl3s-supply = <&s2mpg11_buck7s>; + vinl4s-supply = <&s2mpg11_buck7s>; + vinl5s-supply = <&s2mpg11_buckboost>; + vinl6s-supply = <&s2mpg11_buckboost>; + vinbd-supply = <&s2mpg11_buckboost>; + + regulators { + buck1s { + /* multimedia */ + regulator-name = "vdd_cam"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + buck2s { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + s2mpg11_buck3s: buck3s { + regulator-name = "lldo1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + }; + + buck4s { + /* DDR */ + regulator-name = "vdd2h_mem"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + }; + + buck5s { + /* DDR */ + regulator-name = "vddq_mem"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + samsung,ext-control = ; + }; + + s2mpg11_buck6s: buck6s { + regulator-name = "lldo4"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6250>; + }; + + s2mpg11_buck7s: buck7s { + regulator-name = "mldo"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2200000>; + regulator-ramp-delay = <6250>; + }; + + buck8s { + regulator-name = "vdd_g3d_l2"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + samsung,ext-control = ; + }; + + buck9s { + regulator-name = "vdd_aoc"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + buck10s { + /* DDR */ + regulator-name = "vdd2l_mem"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + }; + + buckd { + regulator-name = "vcc_ufs"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + samsung,ext-control = ; + }; + + s2mpg11_bucka: bucka { + /* lots, IO */ + regulator-name = "bucka"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2100000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + }; + + s2mpg11_buckboost: buckboost { + regulator-name = "buckboost"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + }; + + ldo1s { + regulator-name = "vdd_g3d_m"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo2s { + regulator-name = "vdd_aoc_ret"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + /* ldo3s & ldo5s are unused, ldo4s is board specific */ + + ldo6s { + /* sensors */ + regulator-name = "vdd_prox"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7s { + /* sensors */ + regulator-name = "vdd_sensors"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + }; + + ldo8s { + regulator-name = "vccq_ufs"; + regulator-min-microvolt = <1130400>; + regulator-max-microvolt = <1281200>; + regulator-always-on; + samsung,ext-control = ; + }; + + ldo9s { + regulator-name = "vdd_gnss"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + }; + + ldo10s { + regulator-name = "vdd_gnss_rf"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + }; + + ldo11s { + regulator-name = "vdd_gnss_aux"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + }; + + /* ldo12s is unused */ + + ldo13s { + regulator-name = "vddq_mmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + samsung,ext-control = ; + }; + + /* ldo14s is board specific, ldo15s is unused */ }; }; }; @@ -225,6 +727,17 @@ usbc0_role_sw: endpoint { }; }; + fuel-gauge@36 { + compatible = "maxim,max77759-fg"; + reg = <0x36>; + + pinctrl-0 = <&if_pmic_fg_int>; + pinctrl-names = "default"; + interrupts-extended = <&gpa9 3 IRQ_TYPE_LEVEL_LOW>; + + shunt-resistor-micro-ohms = <5000>; + }; + pmic@66 { compatible = "maxim,max77759"; reg = <0x66>; @@ -317,6 +830,19 @@ pmic_int: pmic-int-pins { samsung,pin-pud = ; }; + sub_pmic_int: sub-pmic-int-pins { + samsung,pins = "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + if_pmic_fg_int: if-pmic-fg-int-pins { + samsung,pins = "gpa9-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + key_power: key-power-pins { samsung,pins = "gpa10-1"; samsung,pin-function = ; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-raven.dts b/arch/arm64/boot/dts/exynos/google/gs101-raven.dts index 1e7e6b34b864..a422542715f2 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-raven.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-raven.dts @@ -15,6 +15,24 @@ / { compatible = "google,gs101-raven", "google,gs101"; }; +&acpm_ipc { + pmic-2 { + regulators { + ldo4s { + regulator-name = "vdd2_uwb"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + ldo14s { + regulator-name = "vdd3_uwb"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + }; + }; + }; +}; + &cont_splash_mem { reg = <0x0 0xfac00000 (1440 * 3120 * 4)>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 700bab4d3e60..711e36cc2c99 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -126,6 +126,8 @@ imx8mm-evk-pcie-ep-dtbs += imx8mm-evk.dtb imx-pcie0-ep.dtbo imx8mm-evkb-pcie-ep-dtbs += imx8mm-evkb.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-pcie-ep.dtb imx8mm-evkb-pcie-ep.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-hummingboard-ripple.dtb +DTC_FLAGS_imx8mm-hummingboard-ripple += -@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb @@ -158,7 +160,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb @@ -178,7 +183,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb +imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb @@ -189,6 +196,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-rve-gateway.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb +DTC_FLAGS_imx8mn-solidsense-n8-compact += -@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb @@ -212,17 +221,21 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-vhip4-evalboard-v1.dtb \ imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtb \ imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo +imx8mn-tqma8mqnl-mba8mx-lvds-g133han01-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-usbotg.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-usbotg.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-ab2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-adpismarc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios.dtb imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-aristainetos3-helios-lvds.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb +DTC_FLAGS_imx8mp-cubox-m := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb @@ -234,9 +247,27 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb +DTC_FLAGS_imx8mp-hummingboard-iiot := -@ +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo +imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtbo +imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-a.dtbo +imx8mp-hummingboard-iiot-rs485-a-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-rs485-a.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-a.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-b.dtbo +imx8mp-hummingboard-iiot-rs485-b-dtbs += imx8mp-hummingboard-iiot.dtb imx8mp-hummingboard-iiot-rs485-b.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot-rs485-b.dtb +DTC_FLAGS_imx8mp-hummingboard-mate := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb +DTC_FLAGS_imx8mp-hummingboard-pro := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb +DTC_FLAGS_imx8mp-hummingboard-pulse := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb +DTC_FLAGS_imx8mp-hummingboard-ripple := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb @@ -339,8 +370,11 @@ imx8mp-tqma8mpql-mba8mp-ras314-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219-dtbs += imx8mp-tqma8mpql-mba8mp-ras314.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb @@ -406,17 +440,31 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb + +imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo +imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-lvds-tm070jvhg33.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca-rgb-cdtech-dc44.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-var-dart-sonata.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo +imx93-9x9-qsb-ontat-kd50g21-40nt-a1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb + +imx93-11x11-frdm-pixpaper-dtbs += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm-pixpaper.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb @@ -425,12 +473,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb imx93-phyboard-nash-jtag-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-jtag.dtbo imx93-phyboard-nash-peb-wlbt-07-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-peb-wlbt-07.dtbo imx93-phyboard-nash-pwm-fan-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-nash-pwm-fan.dtbo +imx93-phyboard-segin-peb-av-02-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-av-02.dtbo imx93-phyboard-segin-peb-eval-01-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-eval-01.dtbo imx93-phyboard-segin-peb-wlbt-05-dtbs += imx93-phyboard-segin.dtb imx93-phyboard-segin-peb-wlbt-05.dtbo imx93-phycore-rpmsg-dtbs += imx93-phyboard-nash.dtb imx93-phyboard-segin.dtb imx93-phycore-rpmsg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-jtag.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-peb-wlbt-07.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash-pwm-fan.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-av-02.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-eval-01.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin-peb-wlbt-05.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb @@ -438,7 +488,19 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-rpmsg.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini.dtb + +imx93-tqma9352-mba91xxca-lvds-tm070jvhg33-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo +imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb + +imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb @@ -446,6 +508,17 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-mallow.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-yavia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb @@ -501,4 +574,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb +dtb-$(CONFIG_ARCH_S32) += s32n79-rdb.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index e7f9c9319319..f4ba3d16ab86 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -114,14 +114,10 @@ optee: optee { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; pmu { @@ -138,8 +134,7 @@ gic: interrupt-controller@6000000 { <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ #interrupt-cells = <3>; interrupt-controller; - interrupts = ; + interrupts = ; its: msi-controller@6020000 { compatible = "arm,gic-v3-its"; msi-controller; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index eec2cd6c6d32..90956ffb8ea9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -14,6 +14,7 @@ / { aliases { crypto = &crypto; + rtc0 = &com_rtc; }; sb_3v3: regulator-sb3v3 { @@ -154,7 +155,7 @@ &i2c2 { &i2c4 { status = "okay"; - rtc@51 { + com_rtc: rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>; @@ -162,6 +163,8 @@ rtc@51 { }; &fspi { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>; status = "okay"; flash@0 { @@ -177,6 +180,11 @@ flash@0 { }; }; +&pinmux_i2crv { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_14_12_pins>; +}; + &usb0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index af6258b2fe82..580ee9b3026e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -89,6 +89,8 @@ &emdio2 { }; &esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>; sd-uhs-sdr104; sd-uhs-sdr50; sd-uhs-sdr25; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 853b01452813..479982948ee5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -750,9 +750,10 @@ i2c0: i2c@2000000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c0_scl>; - pinctrl-1 = <&i2c0_scl_gpio>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&gpio0_3_2_pins>; scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -766,9 +767,10 @@ i2c1: i2c@2010000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c1_scl>; - pinctrl-1 = <&i2c1_scl_gpio>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&gpio0_31_30_pins>; scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -782,9 +784,10 @@ i2c2: i2c@2020000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c2_scl>; - pinctrl-1 = <&i2c2_scl_gpio>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&gpio0_29_28_pins>; scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -798,9 +801,10 @@ i2c3: i2c@2030000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c3_scl>; - pinctrl-1 = <&i2c3_scl_gpio>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-1 = <&gpio0_27_26_pins>; scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -814,9 +818,10 @@ i2c4: i2c@2040000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c4_scl>; - pinctrl-1 = <&i2c4_scl_gpio>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&gpio0_25_24_pins>; scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -830,9 +835,10 @@ i2c5: i2c@2050000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c5_scl>; - pinctrl-1 = <&i2c5_scl_gpio>; + pinctrl-0 = <&i2c5_pins>; + pinctrl-1 = <&gpio0_23_22_pins>; scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -846,9 +852,10 @@ i2c6: i2c@2060000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c6_scl>; - pinctrl-1 = <&i2c6_scl_gpio>; + pinctrl-0 = <&i2c6_i2c7_pins>; + pinctrl-1 = <&gpio1_18_15_pins>; scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -862,9 +869,10 @@ i2c7: i2c@2070000 { clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>; pinctrl-names = "default", "gpio"; - pinctrl-0 = <&i2c7_scl>; - pinctrl-1 = <&i2c7_scl_gpio>; + pinctrl-0 = <&i2c6_i2c7_pins>; + pinctrl-1 = <&gpio1_18_15_pins>; scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -1713,68 +1721,159 @@ pinmux_i2crv: pinmux@70010012c { pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x7>; - i2c1_scl: i2c1-scl-pins { - pinctrl-single,bits = <0x0 0 0x7>; + /* RCWSR12 */ + i2c1_pins: iic2-i2c-pins { + pinctrl-single,bits = <0x0 0x0 0x7>; }; - i2c1_scl_gpio: i2c1-scl-gpio-pins { + gpio0_31_30_pins: iic2-gpio-pins { pinctrl-single,bits = <0x0 0x1 0x7>; }; - i2c2_scl: i2c2-scl-pins { - pinctrl-single,bits = <0x0 0 (0x7 << 3)>; + ftm0_ch10_pins: iic2-ftm-pins { + pinctrl-single,bits = <0x0 0x2 0x7>; }; - i2c2_scl_gpio: i2c2-scl-gpio-pins { + esdhc0_cd_wp_pins: iic2-sdhc-pins { + pinctrl-single,bits = <0x0 0x6 0x7>; + }; + + i2c2_pins: iic3-i2c-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 3)>; + }; + + gpio0_29_28_pins: iic3-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>; }; - i2c3_scl: i2c3-scl-pins { - pinctrl-single,bits = <0x0 0 (0x7 << 6)>; + can0_pins: iic3-can-pins { + pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>; }; - i2c3_scl_gpio: i2c3-scl-gpio-pins { + event65_pins: iic3-event-pins { + pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>; + }; + + i2c3_pins: iic4-i2c-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>; + }; + + gpio0_27_26_pins: iic4-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>; }; - i2c4_scl: i2c4-scl-pins { - pinctrl-single,bits = <0x0 0 (0x7 << 9)>; + can1_pins: iic4-can-pins { + pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>; }; - i2c4_scl_gpio: i2c4-scl-gpio-pins { + event87_pins: iic4-event-pins { + pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>; + }; + + i2c4_pins: iic5-i2c-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>; + }; + + gpio0_25_24_pins: iic5-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>; }; - i2c5_scl: i2c5-scl-pins { - pinctrl-single,bits = <0x0 0 (0x7 << 12)>; + esdhc0_clksync_pins: iic5-sdhc-clk-pins { + pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>; }; - i2c5_scl_gpio: i2c5-scl-gpio-pins { + dspi2_miso_mosi_pins: iic5-spi3-pins { + pinctrl-single,bits = <0x3 (0x2 << 9) (0x7 << 9)>; + }; + + i2c5_pins: iic6-i2c-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>; + }; + + gpio0_23_22_pins: iic6-gpio-pins { pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; }; - i2c6_scl: i2c6-scl-pins { - pinctrl-single,bits = <0x4 0x2 0x7>; + esdhc1_clksync_pins: iic6-sdhc-clk-pins { + pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>; }; - i2c6_scl_gpio: i2c6-scl-gpio-pins { + fspi_data74_pins: xspi1-data74-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>; + }; + + gpio1_31_28_pins: xspi1-data74-gpio-pins { + pinctrl-single,bits = <0x0 0x1 (0x7 << 15)>; + }; + + fspi_data30_pins: xspi1-data30-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>; + }; + + gpio1_27_24_pins: xspi1-data30-gpio-pins { + pinctrl-single,bits = <0x0 0x1 (0x7 << 18)>; + }; + + fspi_dqs_sck_cs10_pins: xspi1-base-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>; + }; + + gpio1_23_20_pins: xspi1-base-gpio-pins { + pinctrl-single,bits = <0x0 0x1 (0x7 << 21)>; + }; + + esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>; + }; + + gpio0_21_15_pins: sdhc1-base-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>; + }; + + dspi0_pins: sdhc1-base-spi1-pins { + pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>; + }; + + esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins { + pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>; + }; + + esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins { + pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>; + }; + + esdhc0_dir_pins: sdhc1-dir-pins { + pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>; + }; + + gpio0_14_12_pins: sdhc1-dir-gpio-pins { + pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>; + }; + + dspi2_cs31_pins: sdhc1-dir-spi3-pins { + pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>; + }; + + esdhc0_data75_pins: sdhc1-dir-sdhc-pins { + pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>; + }; + + /* RCWSR13 */ + gpio1_18_15_pins: iic8-iic7-gpio-pins { pinctrl-single,bits = <0x4 0x1 0x7>; }; - i2c7_scl: i2c7-scl-pins { + i2c6_i2c7_pins: iic8-iic7-i2c-pins { pinctrl-single,bits = <0x4 0x2 0x7>; }; - i2c7_scl_gpio: i2c7-scl-gpio-pins { - pinctrl-single,bits = <0x4 0x1 0x7>; + /* RCWSR14 */ + i2c0_pins: iic1-i2c-pins { + pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>; }; - i2c0_scl: i2c0-scl-pins { - pinctrl-single,bits = <0x8 0 (0x7 << 10)>; - }; - - i2c0_scl_gpio: i2c0-scl-gpio-pins { - pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>; + gpio0_3_2_pins: iic1-gpio-pins { + pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index eafef8718a0f..9d50d3e2761d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -41,21 +41,29 @@ leds { led_sfp_at: led-sfp-at { gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */ default-state = "off"; + linux,default-trigger = "netdev"; + trigger-sources = <&dpmac3>; }; led_sfp_ab: led-sfp-ab { gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */ default-state = "off"; + linux,default-trigger = "netdev"; + trigger-sources = <&dpmac4>; }; led_sfp_bt: led-sfp-bt { gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */ default-state = "off"; + linux,default-trigger = "netdev"; + trigger-sources = <&dpmac5>; }; led_sfp_bb: led-sfp-bb { gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */ default-state = "off"; + linux,default-trigger = "netdev"; + trigger-sources = <&dpmac6>; }; }; @@ -223,6 +231,8 @@ ethernet_phy8: ethernet-phy@15 { }; &esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>; sd-uhs-sdr104; sd-uhs-sdr50; sd-uhs-sdr25; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi index e914291e63a1..3ad908d52a18 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi @@ -5,6 +5,16 @@ // Copyright 2021 Rabeeh Khoury // Copyright 2023 Josua Mayer +/ { + model = "SolidRun LX2162A System on Module"; + compatible = "solidrun,lx2162a-som", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + rtc0 = &som_rtc; + }; +}; + &crypto { status = "okay"; }; @@ -30,6 +40,8 @@ &esdhc1 { }; &fspi { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>; status = "okay"; flash@0 { @@ -75,8 +87,13 @@ variable_eeprom: eeprom@54 { &i2c5 { status = "okay"; - rtc@6f { + som_rtc: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; }; + +&pinmux_i2crv { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_14_12_pins>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi index 06790255a764..6f5af37ba9af 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi @@ -22,10 +22,6 @@ &adc1 { status = "okay"; }; -&amix { - status = "okay"; -}; - &asrc0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index 7022de46b8bf..93f485140b20 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -21,6 +21,7 @@ led-1 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <1>; gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>; }; @@ -29,6 +30,7 @@ led-2 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <1>; gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>; }; @@ -37,6 +39,7 @@ led-3 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <2>; gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; }; @@ -45,6 +48,7 @@ led-4 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <2>; gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; }; }; @@ -62,10 +66,6 @@ &adc1 { status = "okay"; }; -&amix { - status = "okay"; -}; - &asrc0 { status = "okay"; }; @@ -89,8 +89,6 @@ &flexcan2 { status = "okay"; }; -/* TODO: GPU */ - /* Apalis I2C1 */ &i2c2 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi index 12732ed7f811..5c86bcee55fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -21,6 +21,7 @@ led-1 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <1>; gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>; }; @@ -29,6 +30,7 @@ led-2 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <1>; gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>; }; @@ -37,6 +39,7 @@ led-3 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <2>; gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; }; @@ -45,6 +48,7 @@ led-4 { color = ; default-state = "off"; function = LED_FUNCTION_STATUS; + function-enumerator = <2>; gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; }; }; @@ -94,10 +98,6 @@ &adc1 { status = "okay"; }; -&amix { - status = "okay"; -}; - &asrc0 { status = "okay"; }; @@ -123,8 +123,6 @@ &flexcan2 { status = "okay"; }; -/* TODO: GPU */ - /* Apalis I2C1 */ &i2c2 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 5c68d33e19f2..bc62ae5ca812 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -259,33 +259,37 @@ sound-wm8960-1 { }; sound-wm8960-2 { - compatible = "fsl,imx-audio-wm8960"; - model = "wm8960-audio-2"; - audio-cpu = <&sai2>; - audio-codec = <&wm8960_2>; - audio-routing = "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT1", "Mic Jack", - "Mic Jack", "MICB"; + compatible = "audio-graph-card2"; + label = "wm8960-audio-2"; + links = <&sai2_port2>; + routing = "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + widgets = "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; }; sound-wm8960-3 { - compatible = "fsl,imx-audio-wm8960"; - model = "wm8960-audio-3"; - audio-cpu = <&sai3>; - audio-codec = <&wm8960_3>; - audio-routing = "Headphone Jack", "HP_L", - "Headphone Jack", "HP_R", - "Ext Spk", "SPK_LP", - "Ext Spk", "SPK_LN", - "Ext Spk", "SPK_RP", - "Ext Spk", "SPK_RN", - "LINPUT1", "Mic Jack", - "Mic Jack", "MICB"; + compatible = "audio-graph-card2"; + label = "wm8960-audio-3"; + links = <&sai3_port2>; + routing = "Headphones", "HP_L", + "Headphones", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + widgets = "Headphone", "Headphones", + "Speaker", "Ext Spk", + "Microphone", "Mic Jack"; }; }; @@ -481,6 +485,16 @@ wm8960_2: audio-codec@1a { DCVDD-supply = <®_audio_1v8>; SPKVDD1-supply = <®_audio_5v>; SPKVDD2-supply = <®_audio_5v>; + + port { + capture-only; + + wm8960_2_ep: endpoint { + bitclock-master; + frame-master; + remote-endpoint = <&sai2_endpoint2>; + }; + }; }; }; @@ -510,6 +524,16 @@ wm8960_3: audio-codec@1a { DCVDD-supply = <®_audio_1v8>; SPKVDD1-supply = <®_audio_5v>; SPKVDD2-supply = <®_audio_5v>; + + port { + capture-only; + + wm8960_3_ep: endpoint { + bitclock-master; + frame-master; + remote-endpoint = <&sai3_endpoint2>; + }; + }; }; }; @@ -700,6 +724,27 @@ &sai2 { pinctrl-0 = <&pinctrl_sai2>; fsl,sai-asynchronous; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + sai2_port1: port@1 { + reg = <1>; + endpoint { /* not used */ }; + }; + + sai2_port2: port@2 { + reg = <2>; + capture-only; + + sai2_endpoint2: endpoint { + dai-format = "i2s"; + remote-endpoint = <&wm8960_2_ep>; + system-clock-direction-out; + }; + }; + }; }; &sai3 { @@ -712,6 +757,27 @@ &sai3 { pinctrl-0 = <&pinctrl_sai3>; fsl,sai-asynchronous; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + sai3_port1: port@1 { + reg = <1>; + endpoint { /* not used */ }; + }; + + sai3_port2: port@2 { + reg = <2>; + capture-only; + + sai3_endpoint2: endpoint { + dai-format = "i2s"; + remote-endpoint = <&wm8960_3_ep>; + system-clock-direction-out; + }; + }; + }; }; &thermal_zones { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6eab8a6001db..8be44eaf4e1e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -608,12 +608,34 @@ &spdif1 { status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &usbphynop1 { wakeup-source; }; @@ -691,7 +713,7 @@ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 pinctrl_ir: irgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f >; }; @@ -724,26 +746,26 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 pinctrl_pcie0: pcie0grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 - MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 >; }; pinctrl_pcie0_reg: pcie0reggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 >; }; pinctrl_pdm: pdmgrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 - MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 - MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 - MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 - MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 - MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 - MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 >; }; @@ -761,19 +783,19 @@ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 pinctrl_sai2: sai2grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 >; }; pinctrl_sai3: sai3grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 >; }; @@ -790,6 +812,15 @@ MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 @@ -797,6 +828,15 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts b/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts new file mode 100644 index 000000000000..18b58634d3c2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-hummingboard-ripple.dts @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include + +#include "imx8mm-sr-som.dtsi" + +/ { + compatible = "solidrun,imx8mm-hummingboard-ripple", + "solidrun,imx8mm-sr-som", "fsl,imx8mm"; + model = "SolidRun i.MX8MM HummingBoard Ripple"; + + aliases { + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "c"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led-0 { + color = ; + default-state = "on"; + gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + label = "D30"; + }; + + led-1 { + color = ; + default-state = "on"; + gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + label = "D31"; + }; + + led-2 { + color = ; + default-state = "on"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + label = "D32"; + }; + + led-3 { + color = ; + default-state = "on"; + gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + label = "D33"; + }; + + led-4 { + color = ; + default-state = "on"; + gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + label = "D34"; + }; + }; + + v_1_2: regulator-1-2 { + compatible = "regulator-fixed"; + regulator-name = "1v2"; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + }; + + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + pinctrl-0 = <&vmmc_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + startup-delay-us = <250>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; + }; + + vbus1: regulator-vbus-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus1"; + pinctrl-0 = <&vbus1_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus2: regulator-vbus-2 { + compatible = "regulator-fixed"; + regulator-name = "vbus2"; + pinctrl-0 = <&vbus2_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rfkill-mpcie-wifi { + compatible = "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + label = "mpcie WiFi"; + pinctrl-0 = <&pcie_rfkill_pins>; + pinctrl-names = "default"; + radio-type = "wlan"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; + + hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + a2vdd-supply = <&v_1_8>; + avdd-supply = <&v_1_8>; + dvdd-supply = <&v_1_8>; + pd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmi_pins>; + pinctrl-names = "default"; + pvdd-supply = <&v_1_8>; + v3p3-supply = <&v_3_3>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_from_dsim: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; + + carrier_rtc: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + }; +}; + +&iomuxc { + hdmi_pins: pinctrl-hdmi-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0 + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x0 + >; + }; + + i2c3_pins: pinctrl-i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + led_pins: pinctrl-led-grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x0 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0 + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x0 + MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x0 + MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x0 + >; + }; + + pcie_rfkill_pins: pinctrl-pcie-rfkill-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x0 + >; + }; + + usb_hub_pins: pinctrl-usb-hub-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x0 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + >; + }; + + vbus1_pins: pinctrl-vbus-1-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x20 + >; + }; + + vbus2_pins: pinctrl-vbus-2-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x20 + >; + }; + + vmmc_pins: pinctrl-vmmc-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&adv7535_from_dsim>; +}; + +&usbotg1 { + dr_mode = "host"; + vbus-supply = <&vbus2>; + status = "okay"; +}; + +&usbotg2 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + pinctrl-0 = <&usb_hub_pins>; + pinctrl-names = "default"; + vbus-supply = <&vbus1>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb4b4,6502", "usb4b4,6506"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + vdd2-supply = <&v_3_3>; + vdd-supply = <&v_1_2>; + }; + + /* this device is not visible because host supports 2.0 only */ + hub_3_0: hub@2 { + compatible = "usb4b4,6500", "usb4b4,6504"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>; + vdd2-supply = <&v_3_3>; + vdd-supply = <&v_1_2>; + }; +}; + +&usdhc2 { + bus-width = <4>; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h index b1f11098d248..31557b7b9ccc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h @@ -6,6 +6,39 @@ #ifndef __DTS_IMX8MM_PINFUNC_H #define __DTS_IMX8MM_PINFUNC_H +/* Drive Strength */ +#define MX8MM_DSE_X1 0x0 +#define MX8MM_DSE_X2 0x4 +#define MX8MM_DSE_X4 0x2 +#define MX8MM_DSE_X6 0x6 + +/* Slew Rate */ +#define MX8MM_FSEL_FAST 0x10 +#define MX8MM_FSEL_SLOW 0x0 + +/* Open Drain */ +#define MX8MM_ODE_ENABLE 0x20 +#define MX8MM_ODE_DISABLE 0x0 + +#define MX8MM_PULL_DOWN 0x0 +#define MX8MM_PULL_UP 0x40 + +/* Hysteresis */ +#define MX8MM_HYS_CMOS 0x0 +#define MX8MM_HYS_SCHMITT 0x80 + +#define MX8MM_PULL_ENABLE 0x100 +#define MX8MM_PULL_DISABLE 0x0 + +/* SION force input mode */ +#define MX8MM_SION 0x40000000 + +/* long defaults */ +#define MX8MM_USDHC_DATA_DEFAULT (MX8MM_FSEL_FAST | MX8MM_PULL_UP | \ + MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) +#define MX8MM_I2C_DEFAULT (MX8MM_DSE_X6 | MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | \ + MX8MM_PULL_ENABLE | MX8MM_SION) + /* * The pin function ID is a tuple of * diff --git a/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi new file mode 100644 index 000000000000..8d0249f1e92d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-sr-som.dtsi @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +#include + +#include "imx8mm.dtsi" + +/ { + compatible = "solidrun,imx8mm-sr-som", "fsl,imx8mm"; + model = "SolidRun i.MX8MM SoM"; + + chosen { + bootargs = "earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + v_1_8: regulator-1-8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + v_3_3: regulator-3-3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + memory@40000000 { + reg = <0x0 0x40000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&fec1 { + phy = <&phy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&fec1_pins>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x4>; + phy-reset-duration = <10>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + vddio-supply = <&vddio>; + qca,smarteee-tw-us-1g = <24>; + + vddio: vddio-regulator { + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + clocks = <&osc_32k>; + #clock-cells = <0>; + clock-output-names = "clk-32k-out"; + pinctrl-0 = <&pmic_pins>; + pinctrl-names = "default"; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + rohm,dvs-idle-voltage = <900000>; + rohm,dvs-run-voltage = <1000000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <700000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1995000>; + regulator-min-microvolt = <1605000>; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <800000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <800000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + }; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c01", "atmel,24c01"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&iomuxc { + fec1_pins: pinctrl-fec1-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + i2c1_pins: pinctrl-i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pcie_pins: pinctrl-pcie-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0 + >; + }; + + pmic_pins: pinctrl-pmic-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 + >; + }; + + uart1_pins: pinctrl-uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + /* BT_REG_ON */ + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 + /* BT_WAKE_DEV */ + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0 + /* BT_WAKE_HOST */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100 + >; + }; + + uart2_pins: pinctrl-uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + usdhc1_pins: pinctrl-usdhc1-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + /* wifi refclk */ + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0 + /* WL_REG_ON */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0 + /* WL_WAKE_HOST */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100 + >; + }; + + usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + usdhc3_pins: pinctrl-usdhc3-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + wdog1_pins: pinctrl-wdog1-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 + >; + }; +}; + +/* assembly-option for AI accelerator on SoM, otherwise routed to carrier */ +&pcie0 { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pcie_phy { + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&uart1 { + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usdhc1 { + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + pinctrl-0 = <&usdhc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&usdhc3_pins>; + pinctrl-1 = <&usdhc3_100mhz_pins>; + pinctrl-2 = <&usdhc3_200mhz_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&wdog1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso new file mode 100644 index 000000000000..ce12bc46553d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtso @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2019-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&backlight_lvds { + status = "okay"; +}; + +&dsi_lvds_bridge { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + lvds_bridge_out0: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + + port@3 { + reg = <3>; + + lvds_bridge_out1: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&expander0 { + dsi-mux-oe-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-high; + line-name = "DSI_MUX_OE#"; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +&panel { + compatible = "auo,g133han01"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds_bridge_out0>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds_bridge_out1>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso index e44249c6d8a0..046399a455ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , + * Copyright (c) 2022-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -10,10 +10,6 @@ #include -&{/} { - compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; -}; - &backlight_lvds { status = "okay"; }; @@ -36,7 +32,8 @@ &lcdif { }; &mipi_dsi { - status = "okay"; + samsung,burst-clock-frequency = <600000000>; + status = "okay"; }; &panel { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index 8dcc5cbcb8f6..8490b7b04e9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -76,7 +76,6 @@ expander2: gpio@27 { }; &mipi_dsi { - samsung,burst-clock-frequency = <891000000>; samsung,esc-clock-frequency = <20000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts new file mode 100644 index 000000000000..6cc04aa90f21 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-iv-306-d.dts @@ -0,0 +1,799 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Maud Spierings + */ + +/dts-v1/; + +#include + +#include "imx8mm-tx8m-1610.dtsi" + +/ { + chassis-type = "embedded"; + compatible = "gocontroll,moduline-iv-306-d", "karo,tx8m-1610", "fsl,imx8mm"; + hardware = "Moduline IV V3.06-D"; + model = "GOcontroll Moduline IV"; + + aliases { + spi0 = &ecspi2; /* spidev number compatibility */ + spi1 = &ecspi3; /* spidev number compatibility */ + spi2 = &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + mcp_clock: mcp-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + reg_3v3_m2: regulator-3v3-m2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_m2>; + pinctrl-names = "default"; + power-supply = <®_6v4>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3-m.2"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + power-supply = <®_6v4>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5v0"; + }; + + reg_6v4: regulator-6v4 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <6400000>; + regulator-min-microvolt = <6400000>; + regulator-name = "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 16 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can1_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 17 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can2_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + reg_can3_stby: regulator-can3-stby { + compatible = "regulator-fixed"; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can3_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can3-stby"; + }; + + reg_can4_stby: regulator-can4-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 8 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can4_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can4-stby"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_wl_reg>; + pinctrl-names = "default"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <500000>; + reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI 2 */ +&ecspi1 { + cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>, + <&gpio1 0 GPIO_ACTIVE_LOW>, + <&gpio5 2 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio3 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + slot-number = <3>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + slot-number = <4>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@2 { + compatible = "gocontroll,moduline-module-slot"; + reg = <2>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + slot-number = <5>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@3 { + compatible = "gocontroll,moduline-module-slot"; + reg = <3>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + slot-number = <6>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + adc@4 { + compatible = "microchip,mcp3004"; + reg = <4>; + spi-max-frequency = <2300000>; + vref-supply = <®_vdd_3v3>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>, + <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio3 2 GPIO_ACTIVE_LOW>, + <&gpio5 25 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + slot-number = <7>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + slot-number = <8>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + can@2 { + compatible = "microchip,mcp25625"; + reg = <2>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can1>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can1_stby>; + }; + + can@3 { + compatible = "microchip,mcp25625"; + reg = <3>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can2>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can2_stby>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>, + <&gpio5 5 GPIO_ACTIVE_LOW>, + <&gpio5 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + slot-number = <1>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio5>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + slot-number = <2>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + can@2 { + compatible = "microchip,mcp25625"; + reg = <2>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can3>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can3_stby>; + }; + + can@3 { + compatible = "microchip,mcp25625"; + reg = <3>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can4>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can4_stby>; + }; +}; + +&gpu_2d { + status = "disabled"; +}; + +&gpu_3d { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + vled-supply = <®_6v4>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = ; + label = "case-led1"; + + led@0 { + color = ; + reg = <0>; + }; + + led@1 { + color = ; + reg = <1>; + }; + + led@2 { + color = ; + reg = <2>; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = ; + label = "case-led2"; + + led@0 { + color = ; + reg = <0>; + }; + + led@1 { + color = ; + reg = <1>; + }; + + led@2 { + color = ; + reg = <2>; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + label = "case-led3"; + + led@0 { + color = ; + reg = <0>; + }; + + led@1 { + color = ; + reg = <1>; + }; + + led@2 { + color = ; + reg = <2>; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = ; + label = "case-led4"; + + led@0 { + color = ; + reg = <0>; + }; + + led@1 { + color = ; + reg = <1>; + }; + + led@2 { + color = ; + reg = <2>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 + MX8MM_DSE_X1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can1_reg: can1reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can2_reg: can2reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can3: can3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can3_reg: can3reggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can4: can4grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can4_reg: can4reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 + MX8MM_DSE_X1 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 + MX8MM_DSE_X1 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 + MX8MM_DSE_X1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_reg_m2: reg-m2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 + MX8MM_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 + MX8MM_DSE_X1 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + device-wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio3>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + max-speed = <921600>; + pinctrl-0 = <&pinctrl_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3v3_m2>; + vddio-supply = <®_3v3_m2>; + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&pinctrl_uart4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + sd-uhs-sdr25; + vmmc-supply = <®_3v3_m2>; + status = "okay"; + + wifi@1 { + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wl_int>; + pinctrl-names = "default"; + interrupt-names = "host-wake"; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + brcm,board-type = "GOcontroll,moduline"; + }; +}; + +&vpu_blk_ctrl { + status = "disabled"; +}; + +&vpu_g1 { + status = "disabled"; +}; + +&vpu_g2 { + status = "disabled"; +}; + +&wdog1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts new file mode 100644 index 000000000000..39b7d9077e8e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610-moduline-mini-111.dts @@ -0,0 +1,687 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Maud Spierings + */ + +/dts-v1/; + +#include + +#include "imx8mm-tx8m-1610.dtsi" + +/ { + chassis-type = "embedded"; + compatible = "gocontroll,moduline-mini-111", "karo,tx8m-1610", "fsl,imx8mm"; + hardware = "Moduline Mini V1.11"; + model = "GOcontroll Moduline Mini"; + + aliases { + spi0 = &ecspi2; /* spidev number compatibility */ + spi1 = &ecspi3; /* spidev number compatibility */ + spi2 = &ecspi1; /* spidev number compatibility */ + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + mcp_clock: mcp-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + reg_3v3_comm: regulator-3v3-communication { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_comm>; + pinctrl-names = "default"; + power-supply = <®_6v4>; + /* also powers the cellular modem which can't vote on the regulator */ + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_comm"; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + power-supply = <®_6v4>; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "5v0"; + }; + + reg_6v4: regulator-6v4 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <6400000>; + regulator-min-microvolt = <6400000>; + regulator-name = "6v4"; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + gpio = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can1_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_can2_reg>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_wl_reg>; + pinctrl-names = "default"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <500000>; + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>, + <&gpio3 23 GPIO_ACTIVE_LOW>, + <&gpio3 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + slot-number = <3>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + slot-number = <4>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + adc@2 { + compatible = "microchip,mcp3004"; + reg = <2>; + spi-max-frequency = <2300000>; + vref-supply = <®_vdd_3v3>; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, + <&gpio3 9 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi2>; + pinctrl-names = "default"; + status = "okay"; + + can@0 { + compatible = "microchip,mcp25625"; + reg = <0>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can1>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can1_stby>; + }; + + can@1 { + compatible = "microchip,mcp25625"; + reg = <1>; + clocks = <&mcp_clock>; + interrupt-parent = <&gpio3>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_can2>; + pinctrl-names = "default"; + spi-max-frequency = <10000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_can2_stby>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>, + <&gpio1 2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi3>; + pinctrl-names = "default"; + status = "okay"; + + connector@0 { + compatible = "gocontroll,moduline-module-slot"; + reg = <0>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + slot-number = <1>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; + + connector@1 { + compatible = "gocontroll,moduline-module-slot"; + reg = <1>; + i2c-bus = <&i2c2>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; + slot-number = <2>; + spi-max-frequency = <54000000>; + sync-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + vddhpp-supply = <®_6v4>; + vddp-supply = <®_5v0>; + vdd-supply = <®_vdd_3v3>; + }; +}; + +&gpu_2d { + status = "disabled"; +}; + +&gpu_3d { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + vled-supply = <®_6v4>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = ; + label = "case-led1"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = ; + label = "case-led2"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + label = "case-led3"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = ; + label = "case-led4"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + }; + + accelerometer@18 { + compatible = "st,lis2dw12"; + reg = <0x18>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>, <5 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&pinctrl_lis_int>; + pinctrl-names = "default"; + vddio-supply = <®_vdd_3v3>; + vdd-supply = <®_vdd_3v3>; + }; + + humidity-sensor@5f { + compatible = "st,hts221"; + reg = <0x5f>; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_EDGE_RISING>; + pinctrl-0 = <&pinctrl_hts_int>; + pinctrl-names = "default"; + vdd-supply = <®_vdd_3v3>; + }; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 + MX8MM_DSE_X1 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can1_reg: can1reggrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_can2_reg: can2reggrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 + MX8MM_DSE_X1 + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 + MX8MM_DSE_X1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI + MX8MM_DSE_X4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO + (MX8MM_DSE_X4 | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK + MX8MM_DSE_X4 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 + MX8MM_DSE_X1 + >; + }; + + pinctrl_hts_int: htsintgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_lis_int: lisintgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 + (MX8MM_PULL_ENABLE | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_reg_comm: reg_commgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 + MX8MM_DSE_X1 + >; + }; + + pinctrl_sysfs_gpios: sysfsgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 + MX8MM_DSE_X1 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 + MX8MM_DSE_X1 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 + MX8MM_DSE_X1 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 + MX8MM_DSE_X1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 + MX8MM_DSE_X1 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + device-wakeup-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio3>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + max-speed = <921600>; + pinctrl-0 = <&pinctrl_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3v3_comm>; + vddio-supply = <®_3v3_comm>; + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <0>; + cap-power-off-card; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + sd-uhs-sdr25; + vmmc-supply = <®_3v3_comm>; + status = "okay"; + + wifi@1 { + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wl_int>; + pinctrl-names = "default"; + interrupt-names = "host-wake"; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + brcm,board-type = "GOcontroll,moduline"; + }; +}; + +&vpu_blk_ctrl { + status = "disabled"; +}; + +&vpu_g1 { + status = "disabled"; +}; + +&vpu_g2 { + status = "disabled"; +}; + +&wdog1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi new file mode 100644 index 000000000000..ba00f7063476 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tx8m-1610.dtsi @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 Lothar Waßmann + * 2025 Maud Spierings + */ + +#include "imx8mm.dtsi" + +/ { + model = "Ka-Ro Electronics TX8M-1610"; + compatible = "karo,tx8m-1610", "fsl,imx8mm"; + + reg_3v3_etn: regulator-3v3-etn { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pinctrl_reg_3v3_etn>; + pinctrl-names = "default"; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3-etn"; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; +}; + +&fec1 { + assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>, + <&clk IMX8MM_CLK_ENET_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>, <50000000>; + clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET1_ROOT>, + <&clk IMX8MM_CLK_ENET_TIMER>, + <&clk IMX8MM_CLK_ENET_REF>; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + phy-reset-duration = <25>; + phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + phy-reset-post-delay = <1>; + phy-supply = <®_3v3_etn>; + pinctrl-0 = <&pinctrl_fec1>, <&pinctrl_ethphy_rst>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + clocks = <&clk IMX8MM_CLK_ENET_REF>; + interrupt-parent = <&gpio1>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_ethphy_int>; + pinctrl-names = "default"; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names = "SODIMM_152", "SODIMM_42", "SODIMM_153", "PMIC_IRQ_B", + "SODIMM_154", "SODIMM_155", "SODIMM_156", "SODIMM_157", + "SODIMM_158", "SODIMM_159", "SODIMM_161", "SODIMM_162", + "SODIMM_34", "SODIMM_36", "SODIMM_27", "SODIMM_28", + "", "", "", "", + "", "", "", "ENET_POWER", + "", "", "", "", + "ENET_nINT", "ENET_nRST", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "SODIMM_51", "SODIMM_57", "SODIMM_56", "SODIMM_52", + "SODIMM_53", "SODIMM_54", "SODIMM_55", "SODIMM_15", + "SODIMM_45", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "SODIMM_103", "SODIMM_104", "SODIMM_105", "SODIMM_106", + "SODIMM_107", "SODIMM_112", "SODIMM_108", "SODIMM_109", + "SODIMM_95", "SODIMM_110", "SODIMM_96", "SODIMM_97", + "SODIMM_98", "SODIMM_99", "SODIMM_113", "SODIMM_114", + "SODIMM_115", "SODIMM_101", "SODIMM_100", "SODIMM_77", + "SODIMM_72", "SODIMM_73", "SODIMM_74", "SODIMM_75", + "SODIMM_76", "SODIMM_43", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "SODIMM_178", "SODIMM_180", "SODIMM_184", "SODIMM_185", + "SODIMM_186", "SODIMM_187", "SODIMM_188", "SODIMM_189", + "SODIMM_190", "SODIMM_191", "SODIMM_179", "SODIMM_181", + "SODIMM_192", "SODIMM_193", "SODIMM_194", "SODIMM_195", + "SODIMM_196", "SODIMM_197", "SODIMM_198", "SODIMM_199", + "SODIMM_182", "SODIMM_79", "SODIMM_78", "SODIMM_84", + "SODIMM_87", "SODIMM_86", "SODIMM_85", "SODIMM_83", + "SODIMM_81", "SODIMM_80", "SODIMM_90", "SODIMM_93"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_92", "SODIMM_91", "SODIMM_89", "SODIMM_144", + "SODIMM_143", "SODIMM_146", "SODIMM_68", "SODIMM_67", + "SODIMM_70", "SODIMM_69", "SODIMM_48", "SODIMM_46", + "SODIMM_47", "SODIMM_44", "PMIC_SCL", "PMIC_SDA", + "SODIMM_41", "SODIMM_40", "SODIMM_148", "SODIMM_149", + "SODIMM_150", "SODIMM_151", "SODIMM_60", "SODIMM_59", + "SODIMM_64", "SODIMM_63", "SODIMM_62", "SODIMM_61", + "SODIMM_66", "SODIMM_65", "", ""; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + pinctrl-names = "default"; + rohm,reset-snvs-powered; + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <780000>; + regulator-name = "buck1"; + regulator-ramp-delay = <1250>; + }; + + reg_vdd_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <805000>; + regulator-name = "buck2"; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <950000>; + rohm,dvs-idle-voltage = <810000>; + }; + + BUCK3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <805000>; + regulator-name = "buck3"; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "buck4"; + }; + + reg_vdd_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1700000>; + regulator-name = "buck5"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <(1350000 + 100000)>; + regulator-min-microvolt = <(1350000 - 67000)>; + regulator-name = "buck6"; + rohm,fb-pull-up-microvolt = <0>; + rohm,feedback-pull-up-r1-ohms = <2200>; + rohm,feedback-pull-up-r2-ohms = <499>; + }; + + LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1980000>; + regulator-min-microvolt = <1620000>; + regulator-name = "ldo1"; + }; + + LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <760000>; + regulator-name = "ldo2"; + }; + + LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <1710000>; + regulator-name = "ldo3"; + }; + + LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <855000>; + regulator-name = "ldo4"; + }; + + LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "ldo5"; + }; + + LDO6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1260000>; + regulator-min-microvolt = <1140000>; + regulator-name = "ldo6"; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ethphy_int: etnphy-intgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + >; + }; + + pinctrl_ethphy_rst: etnphy-rstgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 + (MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK + (MX8MM_FSEL_FAST | MX8MM_SION) + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT) + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER + MX8MM_FSEL_FAST + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL + MX8MM_FSEL_FAST + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST) + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 + MX8MM_I2C_DEFAULT + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 + MX8MM_I2C_DEFAULT + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 + (MX8MM_PULL_UP | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_reg_3v3_etn: reg-3v3-etngrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 + (MX8MM_DSE_X4 | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + MX8MM_USDHC_DATA_DEFAULT + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + (MX8MM_DSE_X2 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_DSE_X2 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 + (MX8MM_DSE_X6 | MX8MM_USDHC_DATA_DEFAULT) + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_HYS_SCHMITT | MX8MM_PULL_ENABLE) + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B + (MX8MM_DSE_X6 | MX8MM_FSEL_FAST | MX8MM_PULL_UP | MX8MM_PULL_ENABLE) + >; + }; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts new file mode 100644 index 000000000000..faa707402de9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony-legacy.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +#include "imx8mm-var-som-symphony.dts" +#include "imx8mm-var-som-wifi-brcm-legacy.dtsi" + +&bluetooth_iw61x { + status = "disabled"; +}; + +&iw61x_pwrseq { + status = "disabled"; +}; + +&usdhc1 { + /delete-property/ mmc-pwrseq; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index affbc67c2ef6..857325ef4461 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -5,12 +5,25 @@ /dts-v1/; +#include +#include #include "imx8mm-var-som.dtsi" +#include "imx8mm-var-som-wifi-bt-iw61x.dtsi" / { model = "Variscite VAR-SOM-MX8MM Symphony evaluation board"; compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm"; + chosen { + stdout-path = &uart4; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -18,7 +31,8 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -26,6 +40,7 @@ reg_usb_otg2_vbus: regulator-usb-otg2-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>; + pinctrl-1 = <&pinctrl_reg_usb_otg2_vbus_sleep>; regulator-name = "usb_otg2_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -67,7 +82,24 @@ led { }; ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; &i2c2 { @@ -110,17 +142,38 @@ enet-sel-hog { }; }; - extcon_usbotg1: typec@3d { + /* USB Type-C Controller */ + ptn5150: typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; interrupt-parent = <&gpio1>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; }; }; &i2c3 { + pca6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>; + }; + /* Capacitive touch controller */ ft5x06_ts: touchscreen@38 { compatible = "edt,edt-ft5406"; @@ -142,6 +195,39 @@ rtc@68 { }; }; +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + fsl,clkreq-unsupported; + status = "okay"; +}; + +&pcie0 { + reset-gpio = <&pca6408 1 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; @@ -156,28 +242,49 @@ &uart3 { status = "okay"; }; +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usbotg1 { - disable-over-current; - extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; }; &usbotg2 { dr_mode = "host"; vbus-supply = <®_usb_otg2_vbus>; - srp-disable; - hnp-disable; - adp-disable; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; disable-over-current; - /delete-property/ usb-role-switch; - /* - * FIXME: having USB2 enabled hangs the boot just after: - * [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller - * [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1 - * [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00 - * [ 1.977203] hub 1-0:1.0: USB hub found - * [ 1.980987] hub 1-0:1.0: 1 port detected - */ - status = "disabled"; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; }; &pinctrl_fec1 { @@ -214,6 +321,20 @@ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 @@ -232,9 +353,15 @@ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16 >; }; + pinctrl_reg_usb_otg2_vbus_sleep: regusbotg2vbus-sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x120 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 >; }; @@ -251,4 +378,53 @@ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-brcm-legacy.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-brcm-legacy.dtsi new file mode 100644 index 000000000000..f44a846ea6f9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-brcm-legacy.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/* WIFI */ +&usdhc1 { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-bt-iw61x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-bt-iw61x.dtsi new file mode 100644 index 000000000000..15990d141d2a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-wifi-bt-iw61x.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/ { + iw61x_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_bt>; + + bluetooth_iw61x: bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + mmc-pwrseq = <&iw61x_pwrseq>; +}; + +&iomuxc { + pinctrl_bt: bluetoothgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 190bde4edcd7..d05b1ab17fed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -9,15 +9,26 @@ / { model = "Variscite VAR-SOM-MX8MM module"; - chosen { - stdout-path = &uart4; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x80000000>; }; + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_eth_phy: regulator-eth-phy { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -28,6 +39,41 @@ reg_eth_phy: regulator-eth-phy { gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + }; }; &A53_0 { @@ -100,15 +146,33 @@ touchscreen@0 { ti,keep-vref-on; wakeup-source; }; + + /* CAN controller */ + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + clocks = <&clk40m>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <20000000>; + microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + }; }; &fec1 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ phy-mode = "rgmii"; phy-handle = <ðphy>; phy-supply = <®_eth_phy>; - fsl,magic-packet; status = "okay"; mdio { @@ -120,7 +184,8 @@ ethphy: ethernet-phy@4 { reg = <4>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - reset-deassert-us = <10000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; }; }; }; @@ -248,18 +313,57 @@ ldo6_reg: LDO6 { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - /* TODO: configure audio, as of now just put a placeholder */ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - status = "disabled"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MM_CLK_SAI5_ROOT>; + clock-names = "mclk"; + AVDD-supply = <&ldo5_reg>; + CPVDD-supply = <&ldo5_reg>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <&ldo5_reg>; + MICVDD-supply = <&ldo5_reg>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; }; }; +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <1536000>; + #sound-dai-cells = <0>; + dmas = <&sdma2 8 25 0>, <&sdma2 9 25 0>; + dma-names = "rx", "tx"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -274,26 +378,6 @@ &uart2 { status = "okay"; }; -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - -/* WIFI */ &usdhc1 { #address-cells = <1>; #size-cells = <0>; @@ -305,11 +389,6 @@ &usdhc1 { non-removable; keep-power-in-suspend; status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; }; /* SD */ @@ -347,6 +426,13 @@ &wdog1 { }; &iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x16 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 @@ -377,180 +463,212 @@ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 >; }; + pinctrl_fec1_sleep: fec1sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 + MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 + MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 + MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 + MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 + MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 + MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 + MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 + MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 + MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 + MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 >; }; pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 >; }; pinctrl_reg_eth_phy: regethphygrp { fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 >; }; pinctrl_restouch: restouchgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 9f49c0b386d3..4cc5ad01d0e2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -220,16 +220,15 @@ psci { pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; timer { compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ clock-frequency = <8000000>; arm,no-tick-in-suspend; }; @@ -400,7 +399,7 @@ micfil: audio-controller@30080000 { }; spdif1: spdif@30090000 { - compatible = "fsl,imx35-spdif"; + compatible = "fsl,imx8mm-spdif"; reg = <0x30090000 0x10000>; interrupts = ; clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ @@ -1149,8 +1148,10 @@ mipi_dsi: dsi@32e10000 { clocks = <&clk IMX8MM_CLK_DSI_CORE>, <&clk IMX8MM_CLK_DSI_PHY_REF>; clock-names = "bus_clk", "sclk_mipi"; - assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; interrupts = ; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 145355ff91b4..3e590afa4fab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -415,6 +415,10 @@ &uart1 { /* BT */ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; }; &uart2 { /* console */ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts b/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts new file mode 100644 index 000000000000..c8c6760524db --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-solidsense-n8-compact.dts @@ -0,0 +1,851 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for SolidSense N8 Compact + * + * Copyright 2024 Josua Mayer + */ + +/dts-v1/; + +#include + +#include "imx8mn.dtsi" + +/ { + compatible = "solidrun,solidsense-n8-compact", "fsl,imx8mn"; + model = "SolidRun SolidSense N8 Compact"; + + /* LED labels based on enclosure, schematic names differ. */ + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + /* D20 */ + led1 { + default-state = "off"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + label = "led1"; + }; + + /* D18 */ + led2 { + default-state = "off"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + label = "led2"; + }; + + /* D19 */ + led3 { + default-state = "off"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + label = "led3"; + }; + }; + + aliases { + gpio5 = &expander; + rtc0 = &rtc; + rtc1 = &snvs_rtc; + usb0 = &usbotg1; + watchdog0 = &wdog1; + watchdog1 = &rtc; + }; + + chosen { + stdout-path = &uart2; + }; + + reg_modem_vbat: regulator-modem-vbat { + compatible = "regulator-fixed"; + regulator-name = "modem-vbat"; + pinctrl-0 = <®ulator_modem_vbat_pins>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <3800000>; + regulator-min-microvolt = <3800000>; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power to lte modems behind hub ports 2/3 */ + reg_modem_vbus: regulator-modem-vbus { + compatible = "regulator-fixed"; + regulator-name = "modem-vbus"; + pinctrl-0 = <®ulator_modem_vbus_pins>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power to usb hub, and type-a behind hub port 1 */ + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + pinctrl-0 = <®ulator_usb1_vbus_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "usdhc2-vmmc"; + off-on-delay-us = <250>; + pinctrl-0 = <®ulator_usdhc2_vmmc_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + vin-supply = <®_vdd_3v3>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd-1v8"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_vdd_3v3: regulator-vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd-3v3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + rfkill { + compatible = "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + label = "rfkill-wwan"; + pinctrl-0 = <&modem_pins>; + pinctrl-names = "default"; + radio-type = "wwan"; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + + memory@40000000 { + reg = <0x0 0x40000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-266500000 { + opp-hz = /bits/ 64 <266500000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + +&ecspi2 { + /* native chip-select causes reading 0xffffffff */ + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + num-cs = <1>; + pinctrl-0 = <&ecspi2_pins>; + pinctrl-names = "default"; + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clk IMX8MN_CLK_CLKOUT1>; + /* generate 8MHz clock from soc-internal 24mhz reference */ + assigned-clock-parents = <&clk IMX8MN_CLK_24M>, <0>; + assigned-clock-rates = <0>, <8000000>; + assigned-clocks = <&clk IMX8MN_CLK_CLKOUT1_SEL>, + <&clk IMX8MN_CLK_CLKOUT1_DIV>; + pinctrl-0 = <&can_pins>; + pinctrl-names = "default"; + spi-max-frequency = <20000000>; + }; +}; + +&fec1 { + phy-handle = <&phy4>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&fec1_pins>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* + * Depending on board revision two different phys are used: + * - v1.1: atheros phy at address 4 + * - v1.2+: analog devices phy at address 0 + * Configure first version by default. + * On v1.2 and later, U-Boot will enable the correct phy + * based on runtime detection and patch dtb accordingly. + */ + + /* ADIN1300 */ + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + adi,led-polarity = ; + adi,link-st-polarity = ; + status = "disabled"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + active-low; + color = ; + default-state = "keep"; + function = LED_FUNCTION_LAN; + }; + }; + }; + + /* AR8035 */ + phy4: ethernet-phy@4 { + reg = <4>; + reset-assert-us = <10000>; + reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + }; +}; + +&gpio5 { + usb-hub-reset-hog { + line-name = "usb-hub-reset"; + gpios = <3 GPIO_ACTIVE_LOW>; + gpio-hog; + /* deasserted */ + output-low; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + clocks = <&osc_32k>; + #clock-cells = <0>; + clock-output-names = "clk-32k-out"; + pinctrl-0 = <&pmic_pins>; + pinctrl-names = "default"; + rohm,reset-snvs-powered; + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + // supplies soc vdd, soc mipi vdd @ 0.9V + regulator-name = "buck1"; + rohm,dvs-run-voltage = <850000>; + rohm,dvs-suspend-voltage = <750000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + rohm,dvs-idle-voltage = <900000>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-suspend-voltage = <0>; + }; + + BUCK3 { + // BUCK5 in datasheet + // output floating + regulator-name = "buck3"; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <700000>; + }; + + BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + // BUCK6 in datasheet + // supplies ldo3, ldo5, muxsw + regulator-name = "buck4"; + }; + + BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1995000>; + regulator-min-microvolt = <1605000>; + // BUCK7 in datasheet + // supplies ldo4, ldo6, muxsw + // enables dram vpp @ 2.5V + regulator-name = "buck5"; + }; + + BUCK6 { + // BUCK8 in datasheet + // supplies dram @ 1.2V + regulator-name = "buck6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <800000>; + }; + + LDO1 { + // supplies soc snvs @ 1.8V + regulator-name = "ldo1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + }; + + LDO2 { + // supplies soc snvs @ 0.8V + regulator-name = "ldo2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <800000>; + }; + + LDO3 { + // supplies soc vdd @ 1.8V + regulator-name = "ldo3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + LDO4 { + // output floating + regulator-name = "ldo4"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + + LDO5 { + // output floating + regulator-name = "ldo5"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + }; + + LDO6 { + // supplies soc vdd mipi @ 1.2V + regulator-name = "ldo6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + }; + }; +}; + +&i2c2 { + /* + * routed to various connectors: + * - basler camera (CON2) + * - touchscreen (J3) + * - expansion connector (J14) + */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; + + expander: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "SYSGD", "PFO#", "CAPGD", "CAPFLT#", + "CHGEN#", "BSTEN#", "", ""; + pinctrl-0 = <&gpio_expander_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; + }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + }; + + accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + }; + + /* battery-charger@68 */ + + rtc: rtc@69 { + compatible = "abracon,abx80x"; + reg = <0x69>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&rtc_pins>; + pinctrl-names = "default"; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + }; +}; + +&i2c4 { + /* routed to expansion connector (J14) */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&tamper_pins>, <&usb_hub_pins>; + pinctrl-names = "default"; + + can_pins: pinctrl-can-grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x140 + >; + }; + + ecspi2_pins: pinctrl-ecspi2-grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x96 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x1d6 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1d6 + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1d6 + >; + }; + + fec1_pins: pinctrl-fec1-grp { + /* + * Some pins are sampled at phy reset to apply configuration: + * - AR803x PHY (revision 1.1) + * - RXD[1:0]: phy address bits [1:0] + * - RXD[3:2],RX_CTL: mac interface select bits 3,1,0 + * - ADIN1300 PHY (revision 1.2 or later) + * - RXD[3:0]: phy address bits [3:0] + * - RX_CTL,RXC: mac interface select bits 1,0 + * SoC enables pull-down at reset, PHYs have internal + * pull-down, so pinmux may unset pull-enable. + */ + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x2 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1e + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1e + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1e + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1e + /* RD[3:0] sampled at phy reset for address bits [3:0] */ + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x10 + /* phy reset */ + MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0 + /* phy interrupt */ + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 + >; + }; + + gpio_expander_pins: pinctrl-gpio-expander-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x140 + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 + >; + }; + + i2c1_pins: pinctrl-i2c1-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c2 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c2 + >; + }; + + i2c2_pins: pinctrl-i2c2-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 + >; + }; + + i2c3_pins: pinctrl-i2c3-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + i2c4_pins: pinctrl-i2c4-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 + >; + }; + + ieee802151_radio_pins: pinctrl-ieee802151-radio-grp { + fsl,pins = < + /* RESETN */ + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x0 + /* VDD_EN */ + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0 + /* SWDCLK */ + MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0 + /* SDIO */ + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0 + >; + }; + + led_pins: pinctrl-led-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x100 + MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x100 + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x100 + >; + }; + + modem_pins: pinctrl-modem-grp { + fsl,pins = < + /* RESET_N: modem-internal pull-down */ + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0 + /* PWRKEY: pull-down ensures always-on */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x100 + >; + }; + + pmic_pins: pinctrl-pmic-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 + >; + }; + + regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0 + >; + }; + + regulator_modem_vbus_pins: pinctrl-regulator-modem-vbus-grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0 + >; + }; + + regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x0 + >; + }; + + regulator_usdhc2_vmmc_pins: pinctrl-regulator-usdhc2-vmmc-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0 + >; + }; + + rtc_pins: pinctrl-rtc-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x100 + >; + }; + + tamper_pins: pinctrl-tamper-grp { + /* + * Routed to physical tamper input (J12), + * accelerometer and light-sensor interrupts. + */ + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x140 + >; + }; + + uart1_pins: pinctrl-uart1-grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + /* BT_REG_ON */ + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 + /* BT_WAKE_DEV */ + MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0 + /* BT_WAKE_HOST */ + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x100 + >; + }; + + uart2_pins: pinctrl-uart2-grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + uart3_pins: pinctrl-uart3-grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x140 + >; + }; + + uart4_pins: pinctrl-uart4-grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + usb_hub_pins: pinctrl-usb-hub-grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x0 + >; + }; + + usdhc1_pins: pinctrl-usdhc1-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + /* wifi refclk */ + MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0 + /* WL_WAKE_HOST */ + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x100 + /* WL_REG_ON */ + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + /* usdhc2 signalling voltage pmic control */ + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + /* usdhc2 signalling voltage pmic control */ + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 + /* usdhc2 signalling voltage pmic control */ + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x140 + >; + }; + + usdhc3_pins: pinctrl-usdhc3-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + wdog1_pins: pinctrl-wdog1-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140 + >; + }; +}; + +/* Bluetooth */ +&uart1 { + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +/* console */ +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* RS485 */ +&uart3 { + pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + fsl,dte-mode; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* 802.15.1 radio */ +&uart4 { + pinctrl-0 = <&uart4_pins &ieee802151_radio_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +/* WiFi */ +&usdhc1 { + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + pinctrl-0 = <&usdhc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + broken-cd; + bus-width = <4>; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&usdhc3_pins>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + /* + * Use lowest drive strength for all high-speed modes to minimise + * electro-magnetic emissions. + * In this particular design HS-400 still works okay, no extra + * pinctrl for 100mhz and 200mhz are required. + */ + pinctrl-names = "default"; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&wdog1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso index 29235e390a5d..046399a455ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , + * Copyright (c) 2022-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -10,10 +10,6 @@ #include -&{/} { - compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; -}; - &backlight_lvds { status = "okay"; }; @@ -36,6 +32,7 @@ &lcdif { }; &mipi_dsi { + samsung,burst-clock-frequency = <600000000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index 664f4a6950a8..01d565cdbfea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -65,7 +65,6 @@ expander2: gpio@27 { }; &mipi_dsi { - samsung,burst-clock-frequency = <891000000>; samsung,esc-clock-frequency = <20000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 3199bc0966b0..79b169b07c4f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -215,8 +215,7 @@ clk_ext4: clock-ext4 { pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -258,10 +257,10 @@ map0 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts new file mode 100644 index 000000000000..dbbc0df0e3d1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts @@ -0,0 +1,912 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2026 NXP + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + compatible = "fsl,imx8mp-ab2", "fsl,imx8mp"; + model = "NXP i.MX8MP SOM on AB2"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_gpio_led>; + pinctrl-names = "default"; + + status { + default-state = "on"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + label = "yellow:status"; + }; + }; + + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + reg_ab2_ana_pwr: regulator-ab2-ana-pwr { + compatible = "regulator-fixed"; + regulator-name = "ab2_ana_pwr"; + pinctrl-0 = <&pinctrl_ab2_ana_pwr>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 { + compatible = "regulator-fixed"; + regulator-name = "ab2_vdd_pwr_5v0"; + pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>; + pinctrl-names = "default"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + }; + + sound-ak4458 { + compatible = "fsl,imx-audio-card"; + model = "ak4458-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "akcodec"; + fsl,mclk-equal-bclk; + + codec { + sound-dai = <&ak4458_1>, <&ak4458_2>; + }; + + cpu { + sound-dai = <&sai1>; + }; + }; + }; + + sound-ak5552 { + compatible = "fsl,imx-audio-card"; + model = "ak5552-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "akcodec"; + fsl,mclk-equal-bclk; + + codec { + sound-dai = <&ak5552>; + }; + + cpu { + sound-dai = <&sai3>; + }; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + model = "audio-hdmi"; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + + memory@40000000 { + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + device_type = "memory"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&aud2htx { + status = "okay"; +}; + +&dsp { + memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status = "okay"; +}; + +&dsp_reserved { + status = "okay"; +}; + +&easrc { + #sound-dai-cells = <0>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&eqos { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&flexspi { + pinctrl-0 = <&pinctrl_flexspi0>; + pinctrl-names = "default"; + status = "okay"; + + mt25qu256aba: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&hdmi_pai { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-0 = <&pinctrl_hdmi>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-names = "default"; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_pmic>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-names = "default"; + status = "okay"; + + pca6408: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + pca6416_2: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-names = "default"; + status = "okay"; + + ak4458_1: audio-codec@10 { + compatible = "asahi-kasei,ak4458"; + reg = <0x10>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + sound-name-prefix = "0"; + }; + + ak4458_2: audio-codec@11 { + compatible = "asahi-kasei,ak4458"; + reg = <0x11>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + sound-name-prefix = "1"; + }; + + ak4458_3: audio-codec@12 { + compatible = "asahi-kasei,ak4458"; + reg = <0x12>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 4 GPIO_ACTIVE_LOW>; + }; + + ak5552: audio-codec@13 { + compatible = "asahi-kasei,ak5552"; + reg = <0x13>; + #sound-dai-cells = <0>; + AVDD-supply = <®_ab2_ana_pwr>; + DVDD-supply = <®_ab2_ana_pwr>; + reset-gpios = <&pca6416 2 GPIO_ACTIVE_LOW>; + }; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + pinctrl-names = "default"; + + pinctrl_ab2_ana_pwr: ab2anapwrgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0xd6 + >; + }; + + pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xd6 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x10 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6 + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0xd6 + MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0xd6 + MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0xd6 + MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0xd6 + MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0xd6 + MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0xd6 + MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_xcvr: xcvrgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0xd6 + MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0xd6 + MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0xd6 + >; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +&micfil { + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <196608000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm4 { + pinctrl-0 = <&pinctrl_pwm4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sai1 { + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-names = "default"; + fsl,dataline = <2 0xff 0xff>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-names = "default"; + fsl,sai-asynchronous; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sdma2 { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart3 { + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&pinctrl_wdog>; + pinctrl-names = "default"; + fsl,ext-reset-output; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_xcvr>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index 31c33acb560c..385aa6bae520 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -266,8 +266,7 @@ mdio { #size-cells = <0>; ethphy1: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <3>; reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi index 6a62cb32e22e..1007f7db85e9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi @@ -60,8 +60,7 @@ mdio { #size-cells = <0>; ethphy0: ethernet-phy@3 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <3>; reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts index 8290f187b79f..7bc213499f09 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts @@ -68,7 +68,7 @@ vmmc: regulator-mmc { regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; startup-delay-us = <250>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index ef012e8365b1..6ad824a7e07e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -345,7 +345,7 @@ &pinctrl_dhcom_l pinctrl_ptn5150: ptn5150grp { fsl,pins = < - MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000 + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 MX8MP_SION >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index b256be710ea1..d0a2bd975a18 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -134,7 +134,7 @@ reg_audio_pwr: regulator-audio-pwr { enable-active-high; }; - reg_pcie0: regulator-pcie { + reg_m2_wlan: reg_pcie0: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0_reg>; @@ -250,6 +250,13 @@ cpu { }; }; + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_pwrseq>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -595,7 +602,8 @@ ov5640_mipi_0_ep: endpoint { hdmi@3d { compatible = "adi,adv7535"; - reg = <0x3d>; + reg = <0x3d>, <0x3f>, <0x3b>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; @@ -825,6 +833,10 @@ &uart1 { /* BT */ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; }; &uart2 { @@ -858,6 +870,19 @@ &uart3 { status = "okay"; }; +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + keep-power-in-suspend; + non-removable; + wakeup-source; + mmc-pwrseq = <&usdhc1_pwrseq>; + vmmc-supply = <®_m2_wlan>; + status = "okay"; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; @@ -965,33 +990,33 @@ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 - MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 - MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 >; }; pinctrl_flexcan_phy: flexcanphygrp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 - MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 - MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 - MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 - MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 - MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 >; }; @@ -1044,8 +1069,8 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 pinctrl_i2c5: i2c5grp { fsl,pins = < - MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 - MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2 >; }; @@ -1064,7 +1089,7 @@ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40 pinctrl_pcie0_reg: pcie0reggrp { fsl,pins = < - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40 + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140 >; }; @@ -1164,6 +1189,45 @@ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc1_pwrseq: usdhc1pwrseqgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x140 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts index 55690f5e53d7..5fb9714215bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -42,6 +42,67 @@ memory@40000000 { reg = <0x0 0x40000000 0 0xc0000000>, <0x1 0x00000000 0 0x40000000>; }; + + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + reg_usdhc2_vmmc: regulator-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pcal6416_1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc1_vmmc: regulator-wifi-vmmc { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6416_1 10 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + enable-active-high; + startup-delay-us = <20000>; + }; + + reg_usdhc1_vqmmc: regulator-wifi-vqmmc { + compatible = "regulator-fixed"; + regulator-name = "regulator-wifi-vqmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + }; + + sdio_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + }; }; &A53_0 { @@ -60,6 +121,146 @@ &A53_3 { cpu-supply = <®_arm>; }; +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + eee-broken-1000t; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,aldps-enable; + realtek,clkout-disable; + }; + }; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -218,6 +419,10 @@ &i2c3 { status = "okay"; }; +&lcdif3 { + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -237,6 +442,58 @@ &uart3 { status = "okay"; }; +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <®_usdhc1_vmmc>; + vqmmc-supply = <®_usdhc1_vqmmc>; + bus-width = <4>; + non-removable; + no-sd; + no-mmc; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + &usdhc3 { assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; assigned-clock-rates = <400000000>; @@ -250,106 +507,291 @@ &usdhc3 { }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + >; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + >; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* Pin might be required by multiple drivers + * (e. g. HDMI Audio and HDMI TX) + */ + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) >; }; pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 + (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) >; }; pinctrl_pcal6416_0_int: pcal6416-0-int-grp { fsl,pins = < - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146 + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) >; }; pinctrl_pcal6416_1_int: pcal6416-1-int-grp { fsl,pins = < - MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146 + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 - MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 - MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 - MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 MX8MP_USDHC_DATA_DEFAULT + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | + MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso new file mode 100644 index 000000000000..6c41f2633f14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-dsi-WJ70N3TYJHMNG0.dtso @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT MIPI-DSI connector + * with Winstar WJ70N3TYJHMNG0 panel. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + dsi_backlight: dsi-backlight { + compatible = "gpio-backlight"; + gpios = <&tca6408_u48 3 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c_dsi { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili2130"; + reg = <0x41>; + interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6408_u48 6 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + panel@0 { + /* This is a Winstar panel, but the ronbo panel uses same controls. */ + compatible = "ronbo,rb070d30"; + reg = <0>; + /* reset is active-low but driver inverts it internally */ + reset-gpios = <&tca6408_u48 1 GPIO_ACTIVE_HIGH>; + backlight = <&dsi_backlight>; + power-gpios = <&tca6408_u48 2 GPIO_ACTIVE_HIGH>; + shlr-gpios = <&tca6408_u48 4 GPIO_ACTIVE_LOW>; + updn-gpios = <&tca6408_u48 5 GPIO_ACTIVE_HIGH>; + vcc-lcd-supply = <®_dsi_panel>; + + port { + panel_from_dsim: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; +}; + +&mipi_dsi_out { + data-lanes = <1 2 3 4>; + remote-endpoint = <&panel_from_dsim>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso new file mode 100644 index 000000000000..ca4e7b8fee8e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-panel-lvds-WF70A8SYJHLNGA.dtso @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT LVDS connector + * with Winstar WF70A8SYJHLNGA panel. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + lvds_backlight: lvds-backlight { + compatible = "gpio-backlight"; + gpios = <&tca6408_u37 3 GPIO_ACTIVE_LOW>; + }; + + panel-lvds { + compatible = "winstar,wf70a8syjhlnga", "panel-lvds"; + backlight = <&lvds_backlight>; + data-mapping = "vesa-24"; + enable-gpios = <&tca6408_u37 2 GPIO_ACTIVE_HIGH>; + height-mm = <86>; + power-supply = <®_dsi_panel>; + reset-gpios = <&tca6408_u37 1 GPIO_ACTIVE_HIGH>; + width-mm = <154>; + + panel-timing { + /* + * Note: NXP BSP hard-codes 74MHz clock in ldb driver: + * drivers/gpu/drm/imx/imx8mp-ldb.c + * SolidRun BSP carries patch. + */ + clock-frequency = <49500000>; + de-active = <1>; + hactive = <1024>; + hback-porch = <144>; + hfront-porch = <40>; + hsync-active = <0>; + hsync-len = <104>; + vactive = <600>; + vback-porch = <11>; + vfront-porch = <3>; + vsync-active = <1>; + vsync-len = <10>; + }; + + port { + panel_from_lvds: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&i2c_lvds { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili2130"; + reg = <0x41>; + interrupts-extended = <&tca6416_u21 13 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6408_u37 6 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&ldb_lvds_ch0 { + remote-endpoint = <&panel_from_lvds>; +}; + +&lvds_bridge { + status = "okay"; +}; + +&tca6408_u37 { + lvds-lr-hog { + gpios = <4 GPIO_ACTIVE_HIGH>; + gpio-hog; + line-name = "lvds-l/r"; + output-high; + }; + + lvds-ud-hog { + gpios = <5 GPIO_ACTIVE_HIGH>; + gpio-hog; + line-name = "lvds-u/d"; + output-high; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso new file mode 100644 index 000000000000..ae64d6efad9d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-a.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT on-board RS485 Port A on connector J5004. + */ + +/dts-v1/; +/plugin/; + +&uart3 { + linux,rs485-enabled-at-boot-time; +}; + +&uart3_rs_232_485_mux { + /* select rs485 */ + idle-state = <1>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso new file mode 100644 index 000000000000..2718fa5b2c66 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot-rs485-b.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + * + * Overlay for enabling HummingBoard IIoT on-board RS485 Port B on connector J5004. + */ + +/dts-v1/; +/plugin/; + +&uart4 { + linux,rs485-enabled-at-boot-time; +}; + +&uart4_rs_232_485_mux { + /* select rs485 */ + idle-state = <1>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts new file mode 100644 index 000000000000..7c5b77c928d3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-iiot.dts @@ -0,0 +1,716 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Yazan Shhady + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include +#include + +#include "imx8mp-sr-som.dtsi" + +/ { + compatible = "solidrun,imx8mp-hummingboard-iiot", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + model = "SolidRun i.MX8MP HummingBoard IIoT"; + + /* power for M.2 B-Key connector (J6) */ + regulator-m2-b { + compatible = "regulator-fixed"; + regulator-name = "m2-b"; + gpios = <&tca6416_u20 5 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + enable-active-high; + }; + + /* power for M.2 M-Key connector (J4) */ + regulator-m2-m { + compatible = "regulator-fixed"; + regulator-name = "m2-m"; + gpios = <&tca6416_u20 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + enable-active-high; + }; + + /* power for USB-A J27 behind USB Hub Port 3 */ + regulator-vbus-2 { + compatible = "regulator-fixed"; + regulator-name = "vbus2"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&tca6416_u20 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power for USB-A J27 behind USB Hub Port 4 */ + regulator-vbus-3 { + compatible = "regulator-fixed"; + regulator-name = "vbus3"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&tca6416_u20 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + aliases { + /* J10 */ + ethernet0 = &eqos; + /* J11 */ + ethernet1 = &fec; + gpio5 = &tca6408_u48; + gpio6 = &tca6408_u37; + gpio7 = &tca6416_u20; + gpio8 = &tca6416_u21; + i2c6 = &i2c_exp; + i2c7 = &i2c_csi; + i2c8 = &i2c_dsi; + i2c9 = &i2c_lvds; + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + + gpio-keys { + compatible = "gpio-keys"; + + wakeup-event { + interrupts-extended = <&tca6416_u21 11 IRQ_TYPE_EDGE_FALLING>; + label = "m2-m-wakeup"; + wakeup-source; + linux,code = ; + }; + }; + + can_mux: mux-controller-0 { + compatible = "gpio-mux"; + /* + * Mux routes CAN bus signals between SoM connector pins, + * expansion connector (J22) and on-board transceivers using + * two GPIO: + * - IO3: 0 = on-board transceivers, 1 = expansion connector + * - IO4: 0 = J9-55/57/59/61, 1 = J7-12/16 & J9-54/56 + */ + mux-gpios = <&tca6416_u20 3 GPIO_ACTIVE_HIGH>, + <&tca6416_u20 4 GPIO_ACTIVE_HIGH>; + /* default J7-12/16 & J9-54/56 to on-board transceivers */ + idle-state = <2>; + #mux-control-cells = <0>; + }; + + spi_mux: mux-controller-1 { + compatible = "gpio-mux"; + /* default on-board */ + idle-state = <0>; + /* + * Mux switches spi bus between on-board tpm + * and expansion connector (J22). + */ + mux-gpios = <&tca6416_u21 0 GPIO_ACTIVE_HIGH>; + #mux-control-cells = <0>; + }; + + uart3_uart4_b2b_mux: mux-controller-2 { + compatible = "gpio-mux"; + /* default on-board */ + idle-state = <0>; + /* + * Mux switches both uart3 and uart4 tx/rx between expansion + * connector (J22) and on-board rs232/rs485 transceivers + * using one GPIO: 0 = on-board, 1 = connector. + */ + mux-gpios = <&tca6416_u20 0 GPIO_ACTIVE_HIGH>; + #mux-control-cells = <0>; + }; + + uart3_rs_232_485_mux: mux-controller-3 { + compatible = "gpio-mux"; + /* default rs232 */ + idle-state = <0>; + /* + * Mux switches uart3 tx/rx between rs232 and rs485 + * transceivers. using one GPIO: 0 = rs232, 1 = rs485. + */ + mux-gpios = <&tca6416_u20 1 GPIO_ACTIVE_HIGH>; + #mux-control-cells = <0>; + }; + + uart4_rs_232_485_mux: mux-controller-4 { + compatible = "gpio-mux"; + /* default rs232 */ + idle-state = <0>; + /* + * Mux switches uart4 tx/rx between rs232 and rs485 + * transceivers. using one GPIO: 0 = rs232, 1 = rs485. + */ + mux-gpios = <&tca6416_u20 2 GPIO_ACTIVE_HIGH>; + #mux-control-cells = <0>; + }; + + v_1_2: regulator-1-2 { + compatible = "regulator-fixed"; + regulator-name = "1v2"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; + + reg_dsi_panel: regulator-dsi-panel { + compatible = "regulator-fixed"; + regulator-name = "dsi-panel"; + gpios = <&tca6416_u20 15 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <11200000>; + regulator-min-microvolt = <11200000>; + enable-active-high; + }; + + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + pinctrl-0 = <&vmmc_pins>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + startup-delay-us = <250>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* power for USB-A J5003 */ + vbus1: regulator-vbus-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus1"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + gpio = <&tca6416_u20 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rfkill-m2-b-gnss { + compatible = "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&tca6416_u20 10 GPIO_ACTIVE_HIGH>; + label = "m2-b gnss"; + radio-type = "gps"; + }; + + rfkill-m2-b-wwan { + compatible = "rfkill-gpio"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&tca6416_u20 9 GPIO_ACTIVE_HIGH>; + label = "m2-b radio"; + radio-type = "wwan"; + }; +}; + +&ecspi2 { + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + num-cs = <1>; + pinctrl-0 = <&ecspi2_pins>; + pinctrl-names = "default"; + status = "okay"; + + ecspi2_muxed: spi@0 { + compatible = "spi-mux"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mux-controls = <&spi_mux>; + /* mux bandwidth is 2GHz, soc max. spi clock is 166MHz */ + spi-max-frequency = <166000000>; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + interrupts-extended = <&tca6416_u21 9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tca6416_u21 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + spi-max-frequency = <43000000>; + }; + }; +}; + +&flexcan1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&flexcan2 { + pinctrl-0 = <&can2_pins>; + pinctrl-names = "default"; + status = "okay"; + + can-transceiver { + max-bitrate = <8000000>; + }; +}; + +&i2c2 { + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + /* + * This reset is open drain, + * but reset core does not support GPIO_OPEN_DRAIN flag. + */ + reset-gpios = <&tca6416_u21 2 GPIO_ACTIVE_LOW>; + + /* channel 0 routed to expansion connector (J22) */ + i2c_exp: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* channel 1 routed to mipi-csi connector (J23) */ + i2c_csi: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* channel 2 routed to mipi-dsi connector (J25) */ + i2c_dsi: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + tca6408_u48: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "CAM_RST#", "DSI_RESET", + "DSI_STBYB", "DSI_PWM_BL", + "DSI_L/R", "DSI_U/D", + "DSI_CTP_/RST", "CAM_TRIG"; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + * + * reset-gpios = <&tca6416_u21 4 + * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + */ + }; + + }; + + /* channel 2 routed to lvds connector (J24) */ + i2c_lvds: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + tca6408_u37: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "SELB", "LVDS_RESET", + "LVDS_STBYB", "LVDS_PWM_BL", + "LVDS_L/R", "LVDS_U/D", + "LVDS_CTP_/RST", ""; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + * + * reset-gpios = <&tca6416_u21 4 + * (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + */ + }; + + }; + }; +}; + +&i2c3 { + /* highest i2c clock supported by all peripherals is 400kHz */ + clock-frequency = <400000>; + + tca6416_u20: gpio@20 { + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "TCA_INT/EXT_UART", "TCA_UARTA_232/485", + "TCA_UARTB_232/485", "TCA_INT/EXT_CAN", + "TCA_NXP/REN", "TCA_M.2B_3V3_EN", + "TCA_M.2M_3V3_EN", "TCA_M.2M_RESET#", + "TCA_M.2B_RESET#", "TCA_M.2B_W_DIS#", + "TCA_M.2B_GPS_EN#", "TCA_USB-HUB_RST#", + "TCA_USB_HUB3_PWR_EN", "TCA_USB_HUB4_PWR_EN", + "TCA_USB1_PWR_EN", "TCA_VIDEO_PWR_EN"; + /* + * This is a TI TCAL6416 using same programming model as + * NXP PCAL6416, not to be confused with TI TCA6416. + */ + compatible = "nxp,pcal6416"; + + m2-b-reset-hog { + gpios = <8 GPIO_ACTIVE_LOW>; + gpio-hog; + line-name = "m2-b-reset"; + output-low; + }; + }; + + tca6416_u21: gpio@21 { + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "TCA_SPI_TPM/EXT", "TCA_TPM_RST#", + "TCA_I2C_RST", "TCA_RS232_SHTD#", + "TCA_LCD_I2C_RST", "TCA_DIG_OUT1", + "TCA_bDIG_IN1", "TCA_SENS_INT", + "TCA_ALERT#", "TCA_TPM_PIRQ#", + "TCA_RTC_INT", "TCA_M.2M_WAKW_ON_LAN", + "TCA_M.2M_CLKREQ#", "TCA_LVDS_INT#", + "", "TCA_POE_AT"; + interrupts-extended = <&gpio1 15 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&tca6416_u21_int_pins>; + pinctrl-names = "default"; + /* + * This is a TI TCAL6416 using same programming model as + * NXP PCAL6416, not to be confused with TI TCA6416. + */ + compatible = "nxp,pcal6416"; + + lcd-i2c-reset-hog { + gpios = <4 (GPIO_ACTIVE_LOW|GPIO_PULL_UP|GPIO_OPEN_DRAIN)>; + line-name = "lcd-i2c-reset"; + output-low; + /* + * reset shared between U37 and U48, to be + * supported once gpio-pca953x switches to + * reset framework. + */ + gpio-hog; + }; + + m2-m-clkreq-hog { + gpios = <12 GPIO_ACTIVE_LOW>; + gpio-hog; + input; + line-name = "m2-m-clkreq"; + }; + + rs232_shutdown: rs232-shutdown-hog { + gpios = <3 GPIO_ACTIVE_LOW>; + gpio-hog; + line-name = "rs232-shutdown"; + output-low; + }; + }; + + led-controller@30 { + compatible = "ti,lp5562"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + /* use internal clock, could use external generated by rtc */ + clock-mode = /bits/ 8 <1>; + + multi-led@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + color = ; + label = "D7"; + + led@0 { + reg = <0x0>; + color = ; + led-cur = /bits/ 8 <0x32>; + max-cur = /bits/ 8 <0x64>; + }; + + led@1 { + reg = <0x1>; + color = ; + led-cur = /bits/ 8 <0x19>; + max-cur = /bits/ 8 <0x32>; + }; + + led@2 { + reg = <0x2>; + color = ; + led-cur = /bits/ 8 <0x19>; + max-cur = /bits/ 8 <0x32>; + }; + }; + + led@3 { + reg = <0x3>; + chan-name = "D8"; + color = ; + label = "D8"; + led-cur = /bits/ 8 <0x19>; + max-cur = /bits/ 8 <0x64>; + }; + }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */ + interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>; + }; + + accelerometer@53 { + compatible = "adi,adxl345"; + reg = <0x53>; + /* IRQ shared between accelerometer, light-sensor and Tamper input (J5007) */ + interrupts-extended = <&tca6416_u21 7 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "INT1"; + }; + + carrier_eeprom: eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + pagesize = <8>; + }; + + carrier_rtc: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + /* + * AM1805 RTC used on this board has only nTIRQ pins wired, + * which is for countdown timer irqs only. + * Driver does not support this, disable for now. + * + * interrupts-extended = <&tca6416_u21 10 IRQ_TYPE_EDGE_FALLING>; + */ + }; +}; + +&iomuxc { + can1_pins: pinctrl-can1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + can2_pins: pinctrl-can2-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + ecspi2_pins: pinctrl-ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + tca6416_u21_int_pins: pinctrl-tca6416-u21-int-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x0 + >; + }; + + /* UARTA */ + uart3_pins: pinctrl-uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 + >; + }; + + /* UARTB */ + uart4_pins: pinctrl-uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + vmmc_pins: pinctrl-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0 + >; + }; +}; + +&pcie { + reset-gpio = <&tca6416_u20 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* M.2 M-Key (J4) */ +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&phy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = ; + default-state = "keep"; + function = LED_FUNCTION_LAN; + }; + }; +}; + +&phy1 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = ; + default-state = "keep"; + function = LED_FUNCTION_LAN; + }; + }; +}; + +&uart3 { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; + rts-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart4 { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + pinctrl-0 = <&uart4_pins>; + pinctrl-names = "default"; + rts-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <&vbus1>; + fsl,phy-tx-preemp-amp-tune-microamp = <1200>; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; +}; + +&usb_dwc3_1 { + #address-cells = <1>; + #size-cells = <0>; + dr_mode = "host"; + + hub_2_0: hub@1 { + compatible = "usb4b4,6502", "usb4b4,6506"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>; + vdd2-supply = <&v_3_3>; + vdd-supply = <&v_1_2>; + }; + + hub_3_0: hub@2 { + compatible = "usb4b4,6500", "usb4b4,6504"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&tca6416_u20 11 GPIO_ACTIVE_LOW>; + vdd2-supply = <&v_3_3>; + vdd-supply = <&v_1_2>; + }; +}; + +&usdhc2 { + bus-width = <4>; + cap-power-off-card; + full-pwr-cycle; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi index fa7cb9759d01..0b4e5f300eb1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi @@ -73,7 +73,7 @@ vmmc: regulator-mmc { regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + gpio = <&gpio2 19 GPIO_ACTIVE_LOW>; startup-delay-us = <250>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi index 46916ddc0533..0e5f4607c7c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi @@ -41,7 +41,7 @@ port@0 { reg = <0>; adv7535_from_dsim: endpoint { - remote-endpoint = <&dsim_to_adv7535>; + remote-endpoint = <&mipi_dsi_out>; }; }; @@ -71,11 +71,8 @@ &lcdif1 { &mipi_dsi { samsung,esc-clock-frequency = <10000000>; status = "okay"; - - port@1 { - dsim_to_adv7535: endpoint { - remote-endpoint = <&adv7535_from_dsim>; - attach-bridge; - }; - }; +}; + +&mipi_dsi_out { + remote-endpoint = <&adv7535_from_dsim>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso index a3cba41d2b53..41a2bb74f156 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso @@ -7,6 +7,7 @@ /plugin/; #include +#include #include "imx8mp-pinfunc.h" &{/} { @@ -77,12 +78,14 @@ &i2c1 { touchscreen@5d { compatible = "goodix,gt928"; reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; interrupt-parent = <&gpio1>; - interrupts = <6 8>; - irq-gpios = <&gpio1 6 0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; AVDD28-supply = <®_vcc_panel>; VDDIO-supply = <®_vcc_panel>; - reset-gpios = <&gpio1 7 0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; }; @@ -98,6 +101,16 @@ &lvds_bridge { status = "okay"; }; +/* redefine to remove touch controller GPIOs */ +&pinctrl_gpio1 { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x19 /* GPIO_A_0 */ + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x19 /* GPIO_A_1 */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 /* GPIO_A_2 */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19 /* GPIO_A_5 */ + >; +}; + &pwm1 { status = "okay"; }; @@ -108,4 +121,11 @@ pinctrl_panel_stby: panelstbygrp { MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x19 >; }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi index b97bfeb1c30f..bc1a261bb000 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi @@ -330,6 +330,12 @@ rv3028: rtc@52 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc>; interrupts-extended = <&gpio3 24 IRQ_TYPE_LEVEL_LOW>; + /* + * While specifying the vdd-supply is normally not strictly necessary, + * here it also makes sure that the PMIC driver enables the level- + * shifter for the RTC before the RTC is probed. + */ + vdd-supply = <®_vdd_3v3>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts index 2173a36ff691..74d620dd06b7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts @@ -249,6 +249,5 @@ &usb3_phy1 { }; &usdhc2 { - vmmc-supply = <®_vdd_3v3>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h index 16f5899de415..26e7a9428c4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h @@ -36,7 +36,7 @@ /* long defaults */ #define MX8MP_USDHC_DATA_DEFAULT (MX8MP_FSEL_FAST | MX8MP_PULL_UP | \ MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) -#define MX8MP_I2C_DEFAULT (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | \ +#define MX8MP_I2C_DEFAULT (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | \ MX8MP_PULL_ENABLE | MX8MP_SION) /* diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index b7f69c92b774..90d6b5ae215f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -184,6 +184,9 @@ &eqos { pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = <ðphy3>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; mdio { @@ -209,6 +212,70 @@ ethphy3: ethernet-phy@3 { ti,clk-output-sel = ; }; }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; }; &fec { @@ -520,6 +587,7 @@ &uart2 { bluetooth { compatible = "nxp,88w8987-bt"; + vcc-supply = <®_vcc_3v3>; }; }; @@ -848,8 +916,8 @@ pinctrl_tlv320aic3x04: tlv320aic3x04grp { pinctrl_uart1: uart1grp { fsl,pins = , , - , - ; + , + ; }; pinctrl_uart1_gpio: uart1gpiogrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso index 5058cd9409c7..129b02a69ccf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2023 TQ-Systems GmbH , + * Copyright (c) 2023-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -10,10 +10,6 @@ #include -&{/} { - compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; -}; - &backlight_lvds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso index ea44d605342b..f6aaad91d7f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-tm070jvhg33.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022 TQ-Systems GmbH , + * Copyright (c) 2022-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -8,10 +8,6 @@ /dts-v1/; /plugin/; -&{/} { - compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; -}; - &backlight_lvds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ad49bf85a04d..890d1e525a48 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -336,6 +336,9 @@ &eqos { pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>; phy-mode = "rgmii-id"; phy-handle = <ðphy3>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; mdio { @@ -359,6 +362,70 @@ ethphy3: ethernet-phy@3 { interrupts = <3 IRQ_TYPE_LEVEL_LOW>; }; }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; }; &fec { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso index e3965caca6be..c6fc5d5b1e5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso @@ -77,6 +77,7 @@ connector { compatible = "usb-c-connector"; data-role = "host"; pd-disable; + typec-power-opmode = "default"; vbus-supply = <®_vbus>; port { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts index 399230144ce3..87b20b856458 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts @@ -302,36 +302,36 @@ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c2_gpio: i2c2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c4_gpio: i2c4-gpiogrp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi index 761ee046eb72..bf49ae942d41 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi @@ -425,18 +425,18 @@ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; pinctrl_i2c1_gpio: i2c1-gpiogrp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 - MX8MP_I2C_DEFAULT + (MX8MP_DSE_X6 | MX8MP_I2C_DEFAULT) >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9b2b3a9bf9e8..90d7bb8f5619 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -310,8 +310,7 @@ dsp_reserved: dsp@92400000 { pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -397,10 +396,10 @@ map0 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso index 306977d6ba0c..78f24f72cc69 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2019-2023 TQ-Systems GmbH , + * Copyright (c) 2019-2026 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Alexander Stein */ @@ -10,10 +10,6 @@ #include -&{/} { - compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq"; -}; - &backlight_lvds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index dadc136aec6e..011a89d85961 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -611,9 +611,17 @@ ptn5110: tcpc@51 { usb_con1: connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "source"; + power-role = "dual"; data-role = "dual"; + try-power-role = "sink"; source-pdos = ; + /* + * Set operational current to 0mA as we don't want EN_SNK + * enable 12V VBUS switch when it work as a sink. + */ + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index bd6e0aa27efe..f2c94cdb682b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -20,8 +20,9 @@ pcie0: pciea: pcie@5f000000 { ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>, <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; + interrupt-names = "msi", "dma"; #address-cells = <3>; #size-cells = <2>; clocks = <&pciea_lpcg IMX_LPCG_CLK_6>, diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 40a0bc9f4e84..623169f7ddb5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -566,9 +566,17 @@ ptn5110: tcpc@50 { usb_con1: connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "source"; + power-role = "dual"; data-role = "dual"; + try-power-role = "sink"; source-pdos = ; + /* + * Set operational current to 0mA as we don't want EN_SNK + * enable 12V VBUS switch when it work as a sink. + */ + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 9b5d98766512..1de3ad60c6aa 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -86,8 +86,7 @@ gic: interrupt-controller@2d400000 { pmu { compatible = "arm,cortex-a35-pmu"; interrupt-parent = <&gic>; - interrupts = ; + interrupts = ; interrupt-affinity = <&A35_0>, <&A35_1>; }; diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 03f460d62f7a..c083b97476a5 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -23,6 +23,7 @@ aliases { i2c2 = &lpi2c3; mmc0 = &usdhc1; mmc1 = &usdhc2; + mmc2 = &usdhc3; rtc0 = &bbnsm_rtc; serial0 = &lpuart1; serial1 = &lpuart2; @@ -57,6 +58,15 @@ reg_audio_pwr: regulator-audio-pwr { enable-active-high; }; + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; off-on-delay-us = <12000>; @@ -69,6 +79,23 @@ reg_usdhc2_vmmc: regulator-usdhc2 { enable-active-high; }; + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + enable-active-high; + }; + reserved-memory { ranges; #address-cells = <2>; @@ -144,6 +171,11 @@ cpu { }; }; }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; }; &adc1 { @@ -246,6 +278,12 @@ pcal6524: gpio@22 { interrupt-parent = <&gpio3>; pinctrl-0 = <&pinctrl_pcal6524>; pinctrl-names = "default"; + + m2-pcm-level-shifter-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + }; }; pmic@25 { @@ -514,6 +552,7 @@ &usdhc1 { pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; + fsl,tuning-step = <1>; status = "okay"; }; @@ -528,6 +567,22 @@ &usdhc2 { pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; status = "okay"; }; @@ -850,4 +905,47 @@ MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e >; }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts new file mode 100644 index 000000000000..62dc1dedfb0e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm-s.dts @@ -0,0 +1,769 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-11x11-frdm-s", "fsl,imx91"; + model = "NXP FRDM-IMX91S board"; + + aliases { + ethernet0 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf2131; + rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan1_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio_key>; + pinctrl-names = "default"; + + button { + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + gpios = <&gpio3 26 GPIO_PULL_UP>; + label = "User Button"; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + default-state = "on"; + gpios = <&pcal6524 7 GPIO_ACTIVE_LOW>; + label = "green:status"; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_usdhc1_vmmc: regulator-usdhc1 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + startup-delay-us = <20000>; + gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + bootph-pre-ram; + bootph-some-ram; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_VBUS"; + gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x20000000>; + reusable; + size = <0 0x2000000>; + linux,cma-default; + }; + }; + + soc@0 { + bootph-all; + bootph-pre-ram; + }; + + sound-mqs { + compatible = "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-codec = <&mqs1>; + audio-cpu = <&sai1>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 18 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&clk { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&flexcan1 { + phys = <&flexcan1_phy>; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-1 = <&pinctrl_flexcan1_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x000000 0x800000>; + label = "bootloader"; + }; + + partition@1 { + reg = <0x800000 0x800000>; + label = "env"; + }; + + partition@2 { + reg = <0x1000000 0x2800000>; + label = "kernel"; + }; + + partition@3 { + reg = <0x3800000 0x20000>; + label = "dtb"; + }; + + partition@4 { + reg = <0x3820000 0xc7e0000>; + label = "rootfs"; + linux,rootfs; + }; + }; + }; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__CAN1_TX 0x139e + MX91_PAD_GPIO_IO29__CAN1_RX 0x139e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_flexcan1_sleep: flexcan1sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x31e + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x31e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x3fe + MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x3fe + MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x3fe + MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x3fe + >; + }; + + pinctrl_gpio_key: gpiokeysgrp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + MX91_PAD_SD1_DATA5__GPIO3_IO15 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + bootph-pre-ram; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e + MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e + MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__GPIO3_IO14 0x31e + MX91_PAD_SD1_STROBE__GPIO3_IO18 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + }; + + pmic@32 { + compatible = "nxp,pf9453"; + reg = <0x32>; + interrupt-parent = <&pcal6524>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3775000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK1"; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <12500>; + }; + + buck3: BUCK3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3775000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK3"; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3775000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK4"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO1"; + }; + + ldo2: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <500000>; + regulator-name = "LDO2"; + }; + + ldo_snvs: LDO-SNVS { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1200000>; + regulator-name = "LDO-SNVS"; + }; + }; + }; + + ptn5110: tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&mqs1 { + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + pinctrl-0 = <&pinctrl_mqs1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&sai1 { + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc1_vmmc>; + wakeup-source; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&wdog3 { + pinctrl-0 = <&pinctrl_wdog>; + pinctrl-names = "default"; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts new file mode 100644 index 000000000000..afa39dab240a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX91 + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx91-var-dart.dtsi" + +/ { + model = "Variscite DART-MX91 on Sonata-Board"; + compatible = "variscite,var-dart-mx91-sonata", + "variscite,var-dart-mx91", + "fsl,imx91"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + }; + + chosen { + stdout-path = &lpuart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label = "Up"; + linux,code = ; + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label = "Down"; + linux,code = ; + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-emmc { + label = "eMMC"; + gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x40000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +/* Use external instead of internal RTC */ +&bbnsm_rtc { + status = "disabled"; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1_gpio>; + pinctrl-2 = <&pinctrl_lpi2c1_gpio>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + /* USB Type-C Controller */ + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +/* Console (J10) */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header (J12.4, J12.6) */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIO Expanders shared IRQ */ + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins = < + MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x37e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__CAN1_TX 0x139e + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp { + fsl,pins = < + MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e + MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX91_PAD_GPIO_IO05__LPUART6_RX 0x31e + MX91_PAD_GPIO_IO04__LPUART6_TX 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi new file mode 100644 index 000000000000..a9e44efad13f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX91 + * + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx91.dtsi" + +/ { + model = "Variscite DART-MX91 Module"; + compatible = "variscite,var-dart-mx91", "fsl,imx91"; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + snps,clk-csr = <5>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + pinctrl-2 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_GATE>; + clock-names = "mclk"; + AVDD-supply = <&buck5>; + CPVDD-supply = <&buck5>; + DBVDD-supply = <&buck4>; + DCVDD-supply = <&buck5>; + MICVDD-supply = <&buck5>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + /* DMIC is connected to IN1L */ + wlf,in1l-as-dmicdat1; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +/* BT module */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* WiFi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq = <&wifi_pwrseq>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e + >; + }; + + pinctrl_eqos_sleep: eqos-sleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e + MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e + MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e + MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1-sleepgrp { + fsl,pins = < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e + MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e + MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi index f075592bfc01..d63569b39bbc 100644 --- a/arch/arm64/boot/dts/freescale/imx91.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -11,7 +11,7 @@ thermal-zones { cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; - thermal-sensors = <&tmu 0>; + thermal-sensors = <&tmu>; trips { cpu_alert: cpu-alert { diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi index 7958cef35376..46a5d2df074d 100644 --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -69,7 +69,7 @@ clk_ext1: clock-ext1 { pmu { compatible = "arm,cortex-a55-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -79,10 +79,10 @@ psci { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <24000000>; arm,no-tick-in-suspend; interrupt-parent = <&gic>; @@ -1122,8 +1122,62 @@ media_blk_ctrl: system-controller@4ac10000 { <&clk IMX93_CLK_MIPI_DSI_GATE>; clock-names = "apb", "axi", "nic", "disp", "cam", "pxp", "lcdif", "isi", "csi", "dsi"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <400000000>, <133333333>; #power-domain-cells = <1>; status = "disabled"; + + dpi_bridge: dpi-bridge { + compatible = "nxp,imx93-pdfc"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dpi>; + }; + }; + + port@1 { + reg = <1>; + + dpi_to_panel: endpoint { + }; + }; + }; + }; + }; + + lcdif: display-controller@4ae30000 { + compatible = "fsl,imx93-lcdif"; + reg = <0x4ae30000 0x23c>; + interrupts = ; + clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_MEDIA_AXI>; + clock-names = "pix", "axi", "disp_axi"; + power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + lcdif_to_dpi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dpi_from_lcdif>; + }; + }; }; usbotg1: usb@4c100000 { diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi new file mode 100644 index 000000000000..7d3fc4ad7b8b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi @@ -0,0 +1,861 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022,2026 NXP + */ + +#include + +/ { + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4010000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + + }; + + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-name = "VDD_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&adp5585 0 100000 0>; + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <100>; + power-supply = <®_vdd_12v>; + enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cm33 { + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + realtek,clkout-disable; + }; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + phys = <&flexcan_phy>; + status = "okay"; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + wm8962: codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + DCVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + inertial-meter@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <670000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1140000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <840000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + adp5585: io-expander@34 { + compatible = "adi,adp5585-00", "adi,adp5585"; + reg = <0x34>; + vdd-supply = <&buck4>; + gpio-controller; + #gpio-cells = <2>; + gpio-reserved-ranges = <5 1>; + #pwm-cells = <3>; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + adp5585_isp: io-expander@34 { + compatible = "adi,adp5585-01", "adi,adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <3>; + }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-1 = <&pinctrl_sai3_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + fsl,tuning-step = <1>; + status = "okay"; + no-mmc; +}; + +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&xcvr { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-1 = <&pinctrl_spdif_sleep>; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3sleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e + MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e + MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e + MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + + pinctrl_spdif_sleep: spdifsleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e + MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 8dd5340e8141..c6db9c85f2ac 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -1,116 +1,19 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2022 NXP + * Copyright 2022,2026 NXP */ /dts-v1/; -#include #include "imx93.dtsi" +#include "imx93-11x11-evk-common.dtsi" / { model = "NXP i.MX93 11X11 EVK board"; compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; aliases { - ethernet0 = &fec; - ethernet1 = &eqos; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - rtc0 = &bbnsm_rtc; - serial0 = &lpuart1; - serial1 = &lpuart2; - serial2 = &lpuart3; - serial3 = &lpuart4; - serial4 = &lpuart5; - }; - - chosen { - stdout-path = &lpuart1; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - alloc-ranges = <0 0x80000000 0 0x40000000>; - size = <0 0x10000000>; - linux,cma-default; - }; - - vdev0vring0: vdev0vring0@a4000000 { - reg = <0 0xa4000000 0 0x8000>; - no-map; - }; - - vdev0vring1: vdev0vring1@a4008000 { - reg = <0 0xa4008000 0 0x8000>; - no-map; - }; - - vdev1vring0: vdev1vring0@a4010000 { - reg = <0 0xa4010000 0 0x8000>; - no-map; - }; - - vdev1vring1: vdev1vring1@a4018000 { - reg = <0 0xa4018000 0 0x8000>; - no-map; - }; - - rsc_table: rsc-table@2021e000 { - reg = <0 0x2021e000 0 0x1000>; - no-map; - }; - - vdevbuffer: vdevbuffer@a4020000 { - compatible = "shared-dma-pool"; - reg = <0 0xa4020000 0 0x100000>; - no-map; - }; - - }; - - flexcan_phy: can-phy { - compatible = "nxp,tja1057"; - #phy-cells = <0>; - max-bitrate = <5000000>; - silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>; - }; - - reg_vdd_12v: regulator-vdd-12v { - compatible = "regulator-fixed"; - regulator-name = "VDD_12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-name = "vref_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_audio_pwr: regulator-audio-pwr { - compatible = "regulator-fixed"; - regulator-name = "audio-pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; - enable-active-high; + mmc2 = &usdhc3; }; reg_m2_pwr: regulator-m2-pwr { @@ -122,18 +25,6 @@ reg_m2_pwr: regulator-m2-pwr { enable-active-high; }; - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <12000>; - enable-active-high; - }; - reg_usdhc3_vmmc: regulator-usdhc3 { compatible = "regulator-fixed"; regulator-name = "WLAN_EN"; @@ -156,17 +47,6 @@ usdhc3_pwrseq: usdhc3_pwrseq { reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; }; - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - pwms = <&adp5585 0 100000 0>; - brightness-levels = <0 100>; - num-interpolated-steps = <100>; - default-brightness-level = <100>; - power-supply = <®_vdd_12v>; - enable-gpios = <&adp5585 9 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - bt_sco_codec: bt-sco-codec { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -204,348 +84,6 @@ cpu { }; }; }; - - sound-wm8962 { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC", - "IN1R", "AMIC"; - }; - - sound-xcvr { - compatible = "fsl,imx-audio-card"; - model = "imx-audio-xcvr"; - - pri-dai-link { - link-name = "XCVR PCM"; - - cpu { - sound-dai = <&xcvr>; - }; - }; - }; -}; - -&adc1 { - vref-supply = <®_vref_1v8>; - status = "okay"; -}; - -&cm33 { - mbox-names = "tx", "rx", "rxdb"; - mboxes = <&mu1 0 1>, - <&mu1 1 1>, - <&mu1 3 1>; - memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, - <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; - status = "okay"; -}; - -&eqos { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_eqos>; - pinctrl-1 = <&pinctrl_eqos_sleep>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - realtek,clkout-disable; - }; - }; -}; - -&fec { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec>; - pinctrl-1 = <&pinctrl_fec_sleep>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy2>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - reg = <2>; - reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <80000>; - realtek,clkout-disable; - }; - }; -}; - -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - phys = <&flexcan_phy>; - status = "okay"; -}; - -&lpi2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1>; - status = "okay"; - - wm8962: codec@1a { - compatible = "wlf,wm8962"; - reg = <0x1a>; - clocks = <&clk IMX93_CLK_SAI3_GATE>; - DCVDD-supply = <®_audio_pwr>; - DBVDD-supply = <®_audio_pwr>; - AVDD-supply = <®_audio_pwr>; - CPVDD-supply = <®_audio_pwr>; - MICVDD-supply = <®_audio_pwr>; - PLLVDD-supply = <®_audio_pwr>; - SPKVDD1-supply = <®_audio_pwr>; - SPKVDD2-supply = <®_audio_pwr>; - gpio-cfg = < - 0x0000 /* 0:Default */ - 0x0000 /* 1:Default */ - 0x0000 /* 2:FN_DMICCLK */ - 0x0000 /* 3:Default */ - 0x0000 /* 4:FN_DMICCDAT */ - 0x0000 /* 5:Default */ - >; - }; - - inertial-meter@6a { - compatible = "st,lsm6dso"; - reg = <0x6a>; - }; -}; - -&lpi2c2 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c2>; - status = "okay"; - - pcal6524: gpio@22 { - compatible = "nxp,pcal6524"; - reg = <0x22>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6524>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - }; - - pmic@25 { - compatible = "nxp,pca9451a"; - reg = <0x25>; - interrupt-parent = <&pcal6524>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <610000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <670000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1140000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <840000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - adp5585: io-expander@34 { - compatible = "adi,adp5585-00", "adi,adp5585"; - reg = <0x34>; - vdd-supply = <&buck4>; - gpio-controller; - #gpio-cells = <2>; - gpio-reserved-ranges = <5 1>; - #pwm-cells = <3>; - }; -}; - -&lpi2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c3>; - status = "okay"; - - adp5585_isp: io-expander@34 { - compatible = "adi,adp5585-01", "adi,adp5585"; - reg = <0x34>; - gpio-controller; - #gpio-cells = <2>; - #pwm-cells = <3>; - }; - - ptn5110: tcpc@50 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x50>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - typec1_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - }; - }; - }; - - ptn5110_2: tcpc@51 { - compatible = "nxp,ptn5110", "tcpci"; - reg = <0x51>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - typec2_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - data-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <15000000>; - self-powered; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - typec2_dr_sw: endpoint { - remote-endpoint = <&usb2_drd_sw>; - }; - }; - }; - }; - }; - - pcf2131: rtc@53 { - compatible = "nxp,pcf2131"; - reg = <0x53>; - interrupt-parent = <&pcal6524>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&lpuart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&lpuart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; - - bluetooth { - compatible = "nxp,88w8987-bt"; - }; }; &micfil { @@ -558,12 +96,12 @@ &micfil { status = "okay"; }; -&mu1 { - status = "okay"; -}; - -&mu2 { - status = "okay"; +&pcal6524 { + m2-pcm-level-shifter-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + }; }; &sai1 { @@ -577,76 +115,6 @@ &sai1 { status = "okay"; }; -&sai3 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_sai3>; - pinctrl-1 = <&pinctrl_sai3_sleep>; - assigned-clocks = <&clk IMX93_CLK_SAI3>; - assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb1_drd_sw: endpoint { - remote-endpoint = <&typec1_dr_sw>; - }; - }; -}; - -&usbotg2 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - usb-role-switch; - disable-over-current; - samsung,picophy-pre-emp-curr-control = <3>; - samsung,picophy-dc-vol-level-adjust = <7>; - status = "okay"; - - port { - usb2_drd_sw: endpoint { - remote-endpoint = <&typec2_dr_sw>; - }; - }; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; - no-mmc; -}; - &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; @@ -662,152 +130,7 @@ &usdhc3 { status = "okay"; }; -&wdog3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&xcvr { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_spdif>; - pinctrl-1 = <&pinctrl_spdif_sleep>; - assigned-clocks = <&clk IMX93_CLK_SPDIF>, - <&clk IMX93_CLK_AUDIO_XCVR>; - assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <12288000>, <200000000>; - status = "okay"; -}; - &iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e - MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e - MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e - MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e - MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e - MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e - MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e - MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e - MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e - MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e - MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_eqos_sleep: eqossleepgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e - MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e - MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e - MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e - MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e - MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e - MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e - MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e - MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e - MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e - MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e - MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e - MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e - MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e - MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e - MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e - MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e - MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e - MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_fec_sleep: fecsleepgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e - MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e - MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e - MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e - MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e - MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e - MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e - MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e - MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e - MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e - MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e - MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e - MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e - MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX93_PAD_GPIO_IO25__CAN2_TX 0x139e - MX93_PAD_GPIO_IO27__CAN2_RX 0x139e - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x31e - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e - MX93_PAD_DAP_TDI__LPUART5_RX 0x31e - MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e - MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e - MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = < - MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e - MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c3: lpi2c3grp { - fsl,pins = < - MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e - MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e - >; - }; - - pinctrl_pcal6524: pcal6524grp { - fsl,pins = < - MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e - >; - }; - pinctrl_pdm: pdmgrp { fsl,pins = < MX93_PAD_PDM_CLK__PDM_CLK 0x31e @@ -842,160 +165,6 @@ MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e >; }; - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 - MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e - >; - }; - - pinctrl_sai3: sai3grp { - fsl,pins = < - MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e - MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e - MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e - MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e - MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e - >; - }; - - pinctrl_sai3_sleep: sai3sleepgrp { - fsl,pins = < - MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e - MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e - MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e - MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e - MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e - >; - }; - - pinctrl_spdif: spdifgrp { - fsl,pins = < - MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e - MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e - >; - }; - - pinctrl_spdif_sleep: spdifsleepgrp { - fsl,pins = < - MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e - MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 - MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e - MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_sleep: usdhc2sleepgrp { - fsl,pins = < - MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e - MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e - MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e - MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e - MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e - MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e - MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e - >; - }; - /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc3: usdhc3grp { fsl,pins = < @@ -1048,10 +217,4 @@ pinctrl_usdhc3_wlan: usdhc3wlangrp { MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e >; }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e - >; - }; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-pixpaper.dtso b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-pixpaper.dtso new file mode 100644 index 000000000000..d220d7e07df2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-pixpaper.dtso @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Overlay for Mayqueen (Open-EP Community) pixpaper display + * support on NXP FRDM i.MX 93 Development Board + * + * Copyright (C) 2026 Wig Cheng + */ + +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +&iomuxc { + pinctrl_epd_ctrl: epdctrlgrp { + fsl,pins = < + MX93_PAD_GPIO_IO05__GPIO2_IO05 0x31e /* DC pin */ + MX93_PAD_GPIO_IO06__GPIO2_IO06 0x31e /* RESET pin */ + MX93_PAD_GPIO_IO26__GPIO2_IO26 0x31e /* BUSY pin */ + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__GPIO2_IO08 0x3fe /* SPI3 CE0 */ + MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe /* SPI3 MISO */ + MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe /* SPI3 MOSI */ + MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe /* SPI3 CLK */ + >; + }; +}; + +&lpspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_lpspi3>, <&pinctrl_epd_ctrl>; + pinctrl-names = "default"; + status = "okay"; + + display@0 { + compatible = "mayqueen,pixpaper"; + reg = <0>; + busy-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + dc-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <1000000>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index 61843b2c1b1b..ec78c03f4788 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -25,6 +25,7 @@ aliases { mmc1 = &usdhc2; rtc0 = &bbnsm_rtc; serial0 = &lpuart1; + serial4 = &lpuart5; }; bt_sco_codec: bt-sco-codec { @@ -400,6 +401,17 @@ &lpuart1 { /* console */ status = "okay"; }; +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &mu1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso new file mode 100644 index 000000000000..d167c9fc3b8f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtso @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx93-pinfunc.h" + +&{/} { + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + }; + + panel { + compatible = "ontat,kd50g21-40nt-a1"; + backlight = <&backlight>; + power-supply = <®_rpi_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_to_panel>; + }; + }; + }; +}; + +&dpi_bridge { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dpi_to_panel: endpoint { + remote-endpoint = <&panel_in>; + bus-width = <18>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e + >; + }; +}; + +&lcdif { + status = "okay"; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&pcal6524 { + /* + * exp-sel-hog has property 'output-low' while DT overlay doesn't + * support /delete-property/. Both 'output-low' and 'output-high' + * will exist under hog nodes if DT overlay file sets 'output-high'. + * Workaround is to disable this hog and create new hog with + * 'output-high'. + */ + exp-sel-hog { + status = "disabled"; + }; + + exp-high-sel-hog { + gpio-hog; + gpios = <22 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&sai3 { + /* disable due to GPIO12 and GPIO17~20 pin conflicts with LCDIF */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts index 197c8f8b7f66..7bcebd702106 100644 --- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts @@ -349,6 +349,12 @@ mic-can-sel-hog { gpios = <17 GPIO_ACTIVE_HIGH>; output-low; }; + + m2-pcm-level-shifter-hog { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + output-high; + }; }; pmic@25 { diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts index 9e875e082ee8..eac389ed30f3 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -144,8 +144,11 @@ &flexcan1 { /* I2C2 */ &lpi2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; /* RTC */ @@ -277,6 +280,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e >; }; + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = < + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e + >; + }; + pinctrl_lpspi6: lpspi6grp { fsl,pins = < MX93_PAD_GPIO_IO00__GPIO2_IO00 0x386 diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso new file mode 100644 index 000000000000..af330756abfd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin-peb-av-02.dtso @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Copyright (C) 2025 Pengutronix + * + * Author: Andrej Picej + * Author: Marco Felsch + */ + +#include +#include +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + power-supply = <®_vcc_3v3_con>; + pwms = <&pwm7 0 5000000 0>; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + + backlight = <&backlight>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_vcc_3v3_con>; + + port { + panel_in: endpoint { + remote-endpoint = <&dpi_to_panel>; + }; + }; + }; + + /* TODO: Convert to FlexIO PWM once supported */ + pwm7: pwm-7 { + compatible = "pwm-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + #pwm-cells = <3>; + }; + + reg_vcc_3v3_con: regulator-vcc-3v3-con { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_CON"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; +}; + +&dpi_bridge { + status = "okay"; +}; + +&dpi_to_panel { + remote-endpoint = <&panel_in>; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <332600000>; + status = "okay"; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + vcc-supply = <®_vcc_3v3_con>; + iovcc-supply = <®_vcc_3v3_con>; + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + wakeup-source; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x50e + MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x50e + MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x50e + MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x50e + MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x50e + MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x50e + MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x50e + MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x50e + MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x50e + MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x51e + MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x50e + MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x50e + MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x50e + MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x50e + MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x50e + MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x50e + MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x506 + MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x506 + MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x506 + MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x506 + MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x506 + MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x506 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1133e + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x1133e + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x11e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x1133e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index ac64abacc4a2..a982606de1ee 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -148,8 +148,11 @@ &flexcan1 { /* I2C2 */ &lpi2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; /* Codec */ @@ -262,6 +265,13 @@ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e >; }; + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = < + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 3f069905cf0b..ebc57841f27f 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -93,8 +93,11 @@ ethphy1: ethernet-phy@1 { /* I2C3 */ &lpi2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@25 { @@ -234,6 +237,13 @@ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e >; }; + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + MX93_PAD_GPIO_IO28__GPIO2_IO28 0x31e + MX93_PAD_GPIO_IO29__GPIO2_IO29 0x31e + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso new file mode 100644 index 000000000000..40a519e9c91e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtso @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include + +/dts-v1/; +/plugin/; + +&backlight { + status = "okay"; +}; + +&display { + compatible = "tianma,tm070jvhg33"; + status = "okay"; +}; + +&dpi_bridge { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgbdisp>; + status = "okay"; +}; + +&dpi_to_panel { + remote-endpoint = <&lvds_encoder_input>; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <477400000>; + status = "okay"; +}; + +&lvds_encoder { + status = "okay"; +}; + +&lvds_encoder_input { + remote-endpoint = <&dpi_to_panel>; +}; + +&lvds_encoder_output { + remote-endpoint = <&panel_in>; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&panel_in { + remote-endpoint = <&lvds_encoder_output>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso new file mode 100644 index 000000000000..869e3ad1d828 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&backlight { + status = "okay"; +}; + +&display { + compatible = "cdtech,s070swv29hg-dc44"; + status = "okay"; +}; + +&dpi_bridge { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgbdisp>; + status = "okay"; +}; + +&dpi_to_panel { + remote-endpoint = <&panel_in>; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <333333333>; + status = "okay"; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + + polytouch: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&expander2 0 GPIO_ACTIVE_LOW>; + iovcc-supply = <®_3v3>; + vcc-supply = <®_3v3>; + gain = <20>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + }; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&panel_in { + remote-endpoint = <&dpi_to_panel>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts index 2673d9dccbf4..737326ba1b2a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts @@ -232,7 +232,7 @@ ethphy_eqos: ethernet-phy@0 { reset-assert-us = <500000>; reset-deassert-us = <50000>; interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; @@ -265,7 +265,7 @@ ethphy_fec: ethernet-phy@0 { reset-assert-us = <500000>; reset-deassert-us = <50000>; interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 4760d07ea24b..9108181e6592 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -242,7 +242,7 @@ ethphy_eqos: ethernet-phy@0 { reset-assert-us = <500000>; reset-deassert-us = <50000>; interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; @@ -275,7 +275,7 @@ ethphy_fec: ethernet-phy@0 { reset-assert-us = <500000>; reset-deassert-us = <50000>; interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; enet-phy-lane-no-swap; ti,rx-internal-delay = ; ti,tx-internal-delay = ; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtso new file mode 100644 index 000000000000..12a14d871103 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&lpuart7 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4329-bt"; + vbat-supply = <®_3v3>; + vddio-supply = <®_3v3>; + shutdown-gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf_sdio: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts new file mode 100644 index 000000000000..4afd6b650d9d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + */ +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "imx93-tqma9352.dtsi" + +/{ + model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA-MINI SBC"; + compatible = "tq,imx93-tqma9352-mba93xxla-mini", + "tq,imx93-tqma9352", "fsl,imx93"; + chassis-type = "embedded"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0_usb: regulator-5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&expander1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&expander0 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +/* deactivated because pins are used for SDIO */ +&flexspi1 { + status = "disabled"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_m2_key_b>, <&pinctrl_m2_key_e>; + + gpio-line-names = + /* 00 */ "", "", "M2_KEYE_ALERT#", "", + /* 04 */ "", "", "M2_KEYE_UART_WAKE#", "BM1_M2_KEYE_SDIO_WAKE#", + /* 08 */ "", "", "", "BM2_M2_KEYE_SDIO_RST#", + /* 12 */ "M2_KEYB_WOWWAN#", "BM3_M2_KEYB_PEWAKE#", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "LVDS_RESET#", "LVDS_BLT_EN", "", "LVDS_PWR_EN", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "X1_9", "X1_19", "X1_15", "X1_11", + /* 20 */ "X1_13", "X1_7", "", "CAM_TRIGGER", + /* 24 */ "CAM_SYNC", "", "X1_5", "", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "DSI_GPIO", "", ""; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "M2_KEYE_PERST#", "M2_KEYB_PERST#", + "M2_KEYE_W_DISABLE1#", "M2_KEYE_W_DISABLE2#", + "M2_KEYA_W_DISABLE1#", "12V_EN"; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "USB_HUB_PWR", "DSI_RST#", + "CAM_PWR#", "CAMRST#", + "M2_KEYB_FULL_CARD_PWR_OFF#", "M2_KEYB_W_DISABLE2#", + "M2_KEYB_RST#", "M2_KEYB_DPR"; + + /* + * Controls the LTE card FULL_CARD_PWR_OFF pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + full-card-power-off-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_FULL_CARD_PWR_OFF#"; + }; + + /* + * Controls the LTE card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_RST#"; + }; + }; +}; + +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* disabled per default, console for M33 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "disabled"; +}; + +/* disabled per default, used for bluetooth on M.2 slot */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; + status = "disabled"; +}; + +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&usbotg1 { + disable-over-current; + dr_mode = "peripheral"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_5v0_usb>; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + hub_2_0: usb-hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + disable-wp; + no-sdio; + no-mmc; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_3v3>; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X5 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_fec: fecgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X5 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + , + ; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp { + fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_lpspi6: lpspi6grp { + fsl,pins = /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + ; + }; + + pinctrl_lpspi6_cs: lpspi6csgrp { + fsl,pins = /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_m2_key_b: m2keybgrp { + fsl,pins = , + ; + }; + + pinctrl_m2_key_e: m2keyegrp { + fsl,pins = , + , + , + ; + }; + + /*CAM_MCLK, DSI_GPIO, CAM_TRIGGER, CAM_SYNC*/ + pinctrl_mipi_csi_dsi: mipi_csi_dsigrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usbhub: usbhubgrp { + fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X5 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + /* HYS | PU | FSEL_3 | DSE X3 */ + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X6 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = /* PD | FSEL_3 | DSE X6 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index 8a88c98ac05a..a78bbc46c59b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -172,7 +172,7 @@ ethphy_eqos: ethernet-phy@0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos_phy>; interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; reset-assert-us = <500000>; reset-deassert-us = <50000>; @@ -205,7 +205,7 @@ ethphy_fec: ethernet-phy@0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec_phy>; interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; reset-assert-us = <500000>; reset-deassert-us = <50000>; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 7b27012dfcb5..b9abe143cb56 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -43,6 +43,30 @@ map0 { }; }; }; + + soc@0 { + npu@4a900000 { + compatible = "fsl,imx93-npu", "arm,ethos-u65"; + reg = <0x4a900000 0x1000>; + interrupts = ; + power-domains = <&mlmix>; + clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>; + clock-names = "core", "apb"; + sram = <&sram>; + assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <800000000>, <133000000>; + }; + }; + + sram: sram@20480000 { + compatible = "mmio-sram"; + reg = <0x0 0x20480000 0x0 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x20480000 0x18000>; + }; }; &aips1 { @@ -150,6 +174,18 @@ l3_cache: l3-cache { }; }; +&lcdif { + port { + lcdif_to_ldb: endpoint@1 { + reg = <1>; + }; + + lcdif_to_dsi: endpoint@2 { + reg = <2>; + }; + }; +}; + &src { mlmix: power-domain@44461800 { compatible = "fsl,imx93-src-slice"; diff --git a/arch/arm64/boot/dts/freescale/imx93w-evk.dts b/arch/arm64/boot/dts/freescale/imx93w-evk.dts new file mode 100644 index 000000000000..8e53e7384013 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93w-evk.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; + +#include "imx93w.dtsi" +#include "imx93-11x11-evk-common.dtsi" + +/ { + model = "NXP i.MX93W EVK board"; + compatible = "fsl,imx93-wireless-evk", "fsl,imx93"; +}; + +&lpi2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; +}; + +&iomuxc { + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93w.dtsi b/arch/arm64/boot/dts/freescale/imx93w.dtsi new file mode 100644 index 000000000000..95fb025c3949 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93w.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +#include "imx93.dtsi" + +/ { + aliases { + mmc2 = &usdhc3; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc3_vmmc>; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + mmc-pwrseq = <&usdhc3_pwrseq>; + vmmc-supply = <®_usdhc3_vmmc>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_reg_usdhc3_vmmc: regusdhc3vmmcgrp { + fsl,pins = < + /* + * Enable open drain and internal pull-up to allow the IW610 JTAG + * connector to control the PDn status. + */ + MX93_PAD_GPIO_IO29__GPIO2_IO29 0xb9e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x39e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx94-pinfunc.h b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h index 00255db89185..d5056e917140 100644 --- a/arch/arm64/boot/dts/freescale/imx94-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx94-pinfunc.h @@ -233,6 +233,7 @@ #define IMX94_PAD_GPIO_IO17__GPT_MUX_INOUT3 0x0054 0x0358 0x0704 0x05 0x01 #define IMX94_PAD_GPIO_IO17__FLEXPWM4_PWMB0 0x0054 0x0358 0x06e4 0x06 0x00 #define IMX94_PAD_GPIO_IO17__XBAR1_XBAR_INOUT31 0x0054 0x0358 0x08b4 0x07 0x00 +#define IMX94_PAD_GPIO_IO17__XSPI1_IPP_IND_INTFA_B 0x0054 0x0358 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x035c 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO18__LPI2C4_SDA 0x0058 0x035c 0x0738 0x01 0x00 @@ -242,6 +243,7 @@ #define IMX94_PAD_GPIO_IO18__GPT_MUX_INOUT6 0x0058 0x035c 0x0710 0x05 0x01 #define IMX94_PAD_GPIO_IO18__FLEXPWM4_PWMA1 0x0058 0x035c 0x06d8 0x06 0x00 #define IMX94_PAD_GPIO_IO18__XBAR1_XBAR_INOUT32 0x0058 0x035c 0x08b8 0x07 0x00 +#define IMX94_PAD_GPIO_IO18__USB1_OTG_OC 0x0058 0x035c 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x0360 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO19__LPI2C4_SCL 0x005c 0x0360 0x0734 0x01 0x00 @@ -251,6 +253,7 @@ #define IMX94_PAD_GPIO_IO19__GPT_MUX_INOUT9 0x005c 0x0360 0x071c 0x05 0x01 #define IMX94_PAD_GPIO_IO19__FLEXPWM4_PWMB1 0x005c 0x0360 0x06e8 0x06 0x00 #define IMX94_PAD_GPIO_IO19__XBAR1_XBAR_INOUT33 0x005c 0x0360 0x08bc 0x07 0x00 +#define IMX94_PAD_GPIO_IO19__USB2_OTG_OC 0x005c 0x0360 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0364 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO20__PCIE1_CLKREQ_B 0x0060 0x0364 0x0000 0x01 0x00 @@ -413,6 +416,7 @@ #define IMX94_PAD_GPIO_IO37__FLEXPWM3_PWMB2 0x00a4 0x03a8 0x06c0 0x05 0x00 #define IMX94_PAD_GPIO_IO37__FLEXPWM2_PWMX1 0x00a4 0x03a8 0x06a4 0x06 0x00 #define IMX94_PAD_GPIO_IO37__XBAR1_XBAR_INOUT13 0x00a4 0x03a8 0x0890 0x07 0x00 +#define IMX94_PAD_GPIO_IO37__XSPI1_IPP_IND_INTFA_B 0x00a4 0x03a8 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO38__GPIO3_IO6 0x00a8 0x03ac 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO38__NETC_1588MUX_INOUT0 0x00a8 0x03ac 0x064c 0x01 0x00 @@ -574,6 +578,7 @@ #define IMX94_PAD_GPIO_IO55__TPM4_CH3 0x00ec 0x03f0 0x083c 0x05 0x01 #define IMX94_PAD_GPIO_IO55__SINC3_EMBIT0 0x00ec 0x03f0 0x0000 0x06 0x00 #define IMX94_PAD_GPIO_IO55__XBAR1_XBAR_INOUT19 0x00ec 0x03f0 0x08a8 0x07 0x00 +#define IMX94_PAD_GPIO_IO55__XSPI1_IPP_IND_INTFA_B 0x00ec 0x03f0 0x0000 0x0100 0x00 #define IMX94_PAD_GPIO_IO56__GPIO3_IO24 0x00f0 0x03f4 0x0000 0x00 0x00 #define IMX94_PAD_GPIO_IO56__NETC_1588MUX_INOUT6 0x00f0 0x03f4 0x0664 0x01 0x00 @@ -592,6 +597,8 @@ #define IMX94_PAD_GPIO_IO57__TPM6_CH3 0x00f4 0x03f8 0x084c 0x05 0x01 #define IMX94_PAD_GPIO_IO57__SINC3_EMBIT1 0x00f4 0x03f8 0x0000 0x06 0x00 #define IMX94_PAD_GPIO_IO57__ENET_REF_CLK_ROOT 0x00f4 0x03f8 0x0000 0x07 0x00 +#define IMX94_PAD_GPIO_IO57__XBAR1_XBAR_INOUT21 0x00f4 0x03f8 0x0000 0x0100 0x00 +#define IMX94_PAD_GPIO_IO57__SAI3_RX_SYNC 0x00f4 0x03f8 0x0000 0x0200 0x00 #define IMX94_PAD_CCM_CLKO1__CLKO_1 0x00f8 0x03fc 0x0000 0x00 0x00 #define IMX94_PAD_CCM_CLKO1__NETC_1588MUX_INOUT8 0x00f8 0x03fc 0x066c 0x01 0x00 @@ -619,6 +626,7 @@ #define IMX94_PAD_CCM_CLKO3__GPIO4_IO2 0x0100 0x0404 0x0000 0x05 0x00 #define IMX94_PAD_CCM_CLKO3__SINC3_EMCLK3 0x0100 0x0404 0x0000 0x06 0x00 #define IMX94_PAD_CCM_CLKO3__ENET_REF_CLK_ROOT 0x0100 0x0404 0x0000 0x07 0x00 +#define IMX94_PAD_CCM_CLKO3__XBAR1_XBAR_INOUT24 0x0100 0x0404 0x0000 0x0105 0x00 #define IMX94_PAD_CCM_CLKO4__CLKO_4 0x0104 0x0408 0x0000 0x00 0x00 #define IMX94_PAD_CCM_CLKO4__NETC_1588MUX_INOUT11 0x0104 0x0408 0x0000 0x01 0x00 @@ -872,6 +880,7 @@ #define IMX94_PAD_ETH4_MDIO_GPIO2__GPIO6_IO29 0x017c 0x0480 0x0000 0x05 0x00 #define IMX94_PAD_ETH4_MDIO_GPIO2__FLEXPWM4_PWMX1 0x017c 0x0480 0x06f8 0x06 0x02 #define IMX94_PAD_ETH4_MDIO_GPIO2__SINC_FILTER_GLUE4_BREAK 0x017c 0x0480 0x0000 0x07 0x00 +#define IMX94_PAD_ETH4_MDIO_GPIO2__XSPI2_IPP_IND_INTFA_B 0x017c 0x0480 0x0000 0x0105 0x00 #define IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x0180 0x0484 0x0648 0x00 0x00 #define IMX94_PAD_ETH4_TX_CLK__USDHC3_CLK 0x0180 0x0484 0x0000 0x01 0x00 @@ -917,6 +926,7 @@ #define IMX94_PAD_ETH4_TXD2__GPIO7_IO2 0x0190 0x0494 0x0000 0x05 0x00 #define IMX94_PAD_ETH4_TXD2__FLEXPWM4_PWMA2 0x0190 0x0494 0x06dc 0x06 0x01 #define IMX94_PAD_ETH4_TXD2__ETH4_RMII_REF50_CLK 0x0190 0x0494 0x0000 0x07 0x00 +#define IMX94_PAD_ETH4_TXD2__XBAR1_XBAR_INOUT34 0x0190 0x0494 0x0000 0x0105 0x00 #define IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x0194 0x0498 0x0000 0x00 0x00 #define IMX94_PAD_ETH4_TXD3__USDHC3_DATA3 0x0194 0x0498 0x0868 0x01 0x01 @@ -965,6 +975,7 @@ #define IMX94_PAD_ETH4_RX_CTL__GPIO7_IO8 0x01a8 0x04ac 0x0000 0x05 0x00 #define IMX94_PAD_ETH4_RX_CTL__DIG_ENCODER2_DATA_OUT 0x01a8 0x04ac 0x0000 0x06 0x00 #define IMX94_PAD_ETH4_RX_CTL__XBAR1_XBAR_INOUT6 0x01a8 0x04ac 0x0874 0x07 0x01 +#define IMX94_PAD_ETH4_RX_CTL__XSPI2_IPP_IND_INTFA_B 0x01a8 0x04ac 0x0000 0x0105 0x00 #define IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x01ac 0x04b0 0x0630 0x00 0x00 #define IMX94_PAD_ETH4_RX_CLK__XSPI2_A_DQS 0x01ac 0x04b0 0x0000 0x02 0x00 @@ -1344,6 +1355,7 @@ #define IMX94_PAD_XSPI1_SS1_B__GPIO7_IO27 0x028c 0x0590 0x0000 0x05 0x00 #define IMX94_PAD_XSPI1_SS1_B__SINC1_MOD_CLK0 0x028c 0x0590 0x0000 0x06 0x00 #define IMX94_PAD_XSPI1_SS1_B__SINC_FILTER_GLUE1_BREAK 0x028c 0x0590 0x0000 0x07 0x00 +#define IMX94_PAD_XSPI1_SS1_B__XSPI1_IPP_IND_INTFA_B 0x028c 0x0590 0x0000 0x0105 0x00 #define IMX94_PAD_SD2_CD_B__USDHC2_CD_B 0x0290 0x0594 0x0000 0x00 0x00 #define IMX94_PAD_SD2_CD_B__NETC_PINMUX_ETH4_RX_CTL 0x0290 0x0594 0x0634 0x01 0x01 diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index d2f31c8caf6e..c460ece6070f 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include "imx94-clock.h" #include "imx94-pinfunc.h" @@ -94,14 +95,27 @@ scmi_clk: protocol@14 { #clock-cells = <1>; }; + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + scmi_iomuxc: protocol@19 { reg = <0x19>; }; + scmi_lmm: protocol@80 { + reg = <0x80>; + }; + scmi_bbm: protocol@81 { reg = <0x81>; }; + scmi_cpu: protocol@82 { + reg = <0x82>; + }; + scmi_misc: protocol@84 { reg = <0x84>; }; @@ -120,7 +134,7 @@ mqs2: mqs2 { pmu { compatible = "arm,cortex-a55-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -130,15 +144,22 @@ psci { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <24000000>; interrupt-parent = <&gic>; arm,no-tick-in-suspend; }; + usbphynop: usbphynop { + compatible = "usb-nop-xceiv"; + clocks = <&scmi_clk IMX94_CLK_HSIO>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + gic: interrupt-controller@48000000 { compatible = "arm,gic-v3"; reg = <0 0x48000000 0 0x10000>, @@ -1205,6 +1226,48 @@ a55_irqsteer: interrupt-controller@446a0000 { }; }; + mailbox@47300000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47300000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47310000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47310000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47330000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47330000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47340000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47340000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47350000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47350000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47550000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47550000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + aips4: bus@49000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x0 0x49000000 0x0 0x800000>; @@ -1223,6 +1286,60 @@ wdog3: watchdog@49220000 { }; }; + usb3: usb@4c100000 { + compatible = "nxp,imx94-dwc3", "nxp,imx8mp-dwc3"; + reg = <0x0 0x4c100000 0x0 0x10000>, + <0x0 0x4c010010 0x0 0x04>, + <0x0 0x4c1f0000 0x0 0x20>; + reg-names = "core", "blkctl", "glue"; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_24M>, + <&scmi_clk IMX94_CLK_32K>; + clock-names = "hsio", "bus_early", "ref", "suspend"; + interrupts = , + ; + interrupt-names = "dwc_usb3", "wakeup"; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + + usb3_phy: phy@4c1f0040 { + compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; + reg = <0x0 0x4c1f0040 0x0 0x40>, + <0x0 0x4c1fc000 0x0 0x100>; + clocks = <&scmi_clk IMX94_CLK_HSIO>; + clock-names = "phy"; + #phy-cells = <0>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + status = "disabled"; + }; + + usb2: usb@4c200000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c200000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + phys = <&usbphynop>; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbmisc: usbmisc@4c200200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x4c200200 0x0 0x200>, + <0x0 0x4c010014 0x0 0x04>; + #index-cells = <1>; + }; + netc_blk_ctrl: system-controller@4ceb0000 { compatible = "nxp,imx94-netc-blk-ctrl"; reg = <0x0 0x4ceb0000 0x0 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 31fa9675cee1..52f7ef7dbf27 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -6,6 +6,14 @@ /dts-v1/; #include "imx943.dtsi" +#include +#include + +#define BRD_SM_CTRL_BT_WAKE 0x8000 /*!< PCAL6416A-3 */ +#define BRD_SM_CTRL_SD3_WAKE 0x8001 /*!< PCAL6416A-4 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8002 /*!< PCAL6416A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6416A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6416A-7 */ / { compatible = "fsl,imx943-evk", "fsl,imx94"; @@ -20,7 +28,9 @@ aliases { i2c5 = &lpi2c6; mmc0 = &usdhc1; mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &lpuart1; + serial5 = &lpuart6; }; bt_sco_codec: bt-sco-codec { @@ -53,6 +63,32 @@ dmic: dmic { #sound-dai-cells = <0>; }; + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-name = "M.2-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6416_i2c3_u46 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * M.2 device only can be enabled(W_DISABLE1#) after all Power + * Rails reach their minimum operating voltage (PCI Express M.2 + * Specification r5.1 3.1.4 Power-up Timing). + * Set a delay equal to the max value of Tsettle here. + */ + startup-delay-us = <5000>; + }; + + reg_m2_wlan: regulator-wlan { + compatible = "regulator-fixed"; + regulator-name = "WLAN_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6416_i2c3_u46 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; off-on-delay-us = <12000>; @@ -140,6 +176,11 @@ sound-wm8962 { model = "wm8962-audio"; }; + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6416_i2c3_u46 4 GPIO_ACTIVE_LOW>; + }; + memory@80000000 { reg = <0x0 0x80000000 0x0 0x80000000>; device_type = "memory"; @@ -197,6 +238,48 @@ pca9670_i2c3: gpio@23 { gpio-controller; }; + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + pca9548_i2c3: i2c-mux@77 { compatible = "nxp,pca9548"; reg = <0x77>; @@ -253,6 +336,28 @@ wm8962: codec@1a { SPKVDD1-supply = <®_audio_pwr>; SPKVDD2-supply = <®_audio_pwr>; }; + + fan_controller: pwm@2f { + compatible = "microchip,emc2301", "microchip,emc2305"; + reg = <0x2f>; + #pwm-cells = <3>; + #address-cells = <1>; + #size-cells = <0>; + + fan0: fan@0 { + reg = <0x0>; + pwms = <&fan_controller 26000 1 PWM_POLARITY_INVERTED>; + #cooling-cells = <2>; + }; + }; + + ptn5150: tcpc@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + interrupt-parent = <&pcal6408_i2c3_u172>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; }; i2c@5 { @@ -437,6 +542,17 @@ &lpuart1 { status = "okay"; }; +&lpuart6 { + /* BT */ + pinctrl-0 = <&pinctrl_uart6>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &micfil { assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>, @@ -636,6 +752,12 @@ IMX94_PAD_GPIO_IO47__SAI3_TX_DATA0 0x31e >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + IMX94_PAD_GPIO_IO44__GPIO3_IO12 0x30e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < IMX94_PAD_UART1_TXD__LPUART1_TX 0x31e @@ -643,6 +765,15 @@ IMX94_PAD_UART1_RXD__LPUART1_RX 0x31e >; }; + pinctrl_uart6: uart6grp { + fsl,pins = < + IMX94_PAD_GPIO_IO04__LPUART6_TX 0x31e + IMX94_PAD_GPIO_IO05__LPUART6_RX 0x31e + IMX94_PAD_GPIO_IO06__LPUART6_CTS_B 0x31e + IMX94_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e + >; + }; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < IMX94_PAD_SD1_CLK__USDHC1_CLK 0x158e @@ -739,6 +870,18 @@ IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e >; }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX94_PAD_GPIO_IO48__USDHC3_CLK 0x158e + /* Need to config the SION for CMD pad, refer to ERR053138 */ + IMX94_PAD_GPIO_IO49__USDHC3_CMD 0x4000138e + IMX94_PAD_GPIO_IO50__USDHC3_DATA0 0x138e + IMX94_PAD_GPIO_IO51__USDHC3_DATA1 0x138e + IMX94_PAD_GPIO_IO52__USDHC3_DATA2 0x138e + IMX94_PAD_GPIO_IO53__USDHC3_DATA3 0x138e + >; + }; + pinctrl_xspi1: xspi1grp { fsl,pins = < IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe @@ -756,6 +899,138 @@ IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe }; }; +&scmi_misc { + nxp,ctrl-ids = ; +}; + +&thermal_zones { + a55-thermal { + trips { + atrip2: trip2 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + atrip3: trip3 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + + atrip4: trip4 { + temperature = <75000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&atrip2>; + cooling-device = <&fan0 4 6>; + }; + + map2 { + trip = <&atrip3>; + cooling-device = <&fan0 6 8>; + }; + + map3 { + trip = <&atrip4>; + cooling-device = <&fan0 8 10>; + }; + }; + }; + + pf09-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + temperature = <140000>; + hysteresis = <2000>; + type = "passive"; + }; + + pf09_crit: trip1 { + temperature = <155000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + temperature = <140000>; + hysteresis = <2000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + temperature = <155000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; +}; + +&usb2 { + dr_mode = "otg"; + disable-over-current; + adp-disable; + hnp-disable; + srp-disable; + samsung,picophy-dc-vol-level-adjust = <10>; + status = "okay"; +}; + +&usb3 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; @@ -781,6 +1056,23 @@ &usdhc2 { status = "okay"; }; +&usdhc3 { + /* + * Only enable SDIO2.0 mode as the corresponding GPIO pads are 3.3V, the + * max frequency is 50MHz. + */ + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "sleep"; + bus-width = <4>; + vmmc-supply = <®_m2_wlan>; + mmc-pwrseq = <&usdhc3_pwrseq>; + keep-power-in-suspend; + non-removable; + wakeup-source; + status = "okay"; +}; + &wdog3 { fsl,ext-reset-output; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi index 45b8da758e87..dfd956ece2e3 100644 --- a/arch/arm64/boot/dts/freescale/imx943.dtsi +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -145,4 +145,68 @@ l3_cache: l3-cache { cache-unified; }; }; + + thermal_zones: thermal-zones { + a55-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 1>; + + trips { + cpu_alert0: trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + ana-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 0>; + + trips { + ana_alert: trip0 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + ana_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&ana_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index d4184fb8b28c..7eb12e7d5014 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -116,7 +116,6 @@ flexcan2_phy: can-phy { reg_m2_pwr: regulator-m2-pwr { compatible = "regulator-fixed"; - regulator-always-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "M.2-power"; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts index ca1c4966c867..0f43e3be7058 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts @@ -243,6 +243,12 @@ codec { }; }; + sound-mqs { + compatible = "audio-graph-card2"; + links = <&sai1_port1>; + label = "mqs-audio"; + }; + usdhc3_pwrseq: usdhc3-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>; @@ -473,6 +479,21 @@ &mu7 { status = "okay"; }; +&mqs1 { + clocks = <&scmi_clk IMX95_CLK_SAI1>; + clock-names = "mclk"; + pinctrl-0 = <&pinctrl_mqs1>; + pinctrl-names = "default"; + status = "okay"; + + mqs1_port: port { + mqs1_ep: endpoint { + dai-format = "left_j"; + remote-endpoint = <&sai1_port1_ep>; + }; + }; +}; + &netc_blk_ctrl { status = "okay"; }; @@ -534,6 +555,51 @@ &pcie0 { status = "okay"; }; +&sai1 { + clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, + <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, + <&dummy>, <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, + <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* leave unconnected - no RX in the context of MQS */ + port@0 { + reg = <0>; + + endpoint { + }; + }; + + sai1_port1: port@1 { + reg = <1>; + mclk-fs = <512>; + + sai1_port1_ep: endpoint { + dai-format = "left_j"; + system-clock-direction-out; + bitclock-master; + frame-master; + remote-endpoint = <&mqs1_ep>; + }; + }; + }; +}; + &scmi_iomuxc { pinctrl_emdio: emdiogrp { fsl,pins = < @@ -618,6 +684,13 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e >; }; + pinctrl_mqs1: mqs1grp { + fsl,pins = < + IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x31e + IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x31e + >; + }; + pinctrl_pcal6524: pcal6524grp { fsl,pins = < IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts index 808a9fe3ebb2..264703f6eef6 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk-sof.dts @@ -55,8 +55,11 @@ sound-wm8962 { }; &edma2 { - /* channels 30 and 31 reserved for FW usage */ - dma-channel-mask = <0xc0000000>, <0x0>; + /* + * channels 0 and 1 reserved for V2X fast hash, + * channels 30 and 31 reserved for FW usage + */ + dma-channel-mask = <0xc0000003>, <0x0>; }; &sai3 { diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index aaa0da55a22b..041fd838fabb 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -475,7 +475,7 @@ &lpuart1 { &lpuart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; - status = "disabled"; + status = "okay"; bluetooth { compatible = "nxp,88w8987-bt"; diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index 5932ba238a8a..7a73958f6eec 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -144,6 +144,14 @@ reg_wifi_en: regulator-wifi-en { startup-delay-us = <2000>; }; + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -156,6 +164,42 @@ linux_cma: linux,cma { alloc-ranges = <0 0x80000000 0 0x7f000000>; linux,cma-default; }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; }; }; @@ -262,7 +306,6 @@ &gpio3 { "", "", "", - "", "PMIC_SD2_VSEL"; status = "okay"; }; @@ -572,6 +615,10 @@ &lpuart3 { pinctrl-0 = <&pinctrl_uart3>; }; +&mu7 { + status = "okay"; +}; + /* SMARC MDIO, shared between all ethernet ports */ &netc_emdio { pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts new file mode 100644 index 000000000000..0f3d2e488f4a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX95 + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +#include "imx95-var-dart.dtsi" + +/ { + model = "Variscite DART-MX95 on Sonata-Board"; + compatible = "variscite,var-dart-mx95-sonata", + "variscite,var-dart-mx95", + "fsl,imx95"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + ethernet2 = &enetc_port2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + clk_osc_can0: clock-osc-40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-back { + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + label = "Back"; + wakeup-source; + linux,code = ; + }; + + button-down { + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + label = "Down"; + wakeup-source; + linux,code = ; + }; + + button-home { + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + label = "Home"; + wakeup-source; + linux,code = ; + }; + + button-up { + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + label = "Up"; + wakeup-source; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-heartbeat { + label = "Heartbeat"; + gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_phy1_supply: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "SUPPLY_PHY1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; + + sfp0: sfp { + compatible = "sff,sfp"; + i2c-bus = <&lpi2c3>; + los-gpios = <&pca9534 1 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <2000>; + }; +}; + +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; + phy-handle = <ðphy1>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + status = "okay"; +}; + +&enetc_port2 { + phy-mode = "10gbase-r"; + sfp = <&sfp0>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + pinctrl-2 = <&pinctrl_lpi2c3_gpio>; + scl-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + pcie2-sel-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "pcie-clk-sw"; + }; + + sfp-sel-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "sfp-sw"; + }; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio5>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; + + /* DS1337 RTC module */ + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio5>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; +}; + +&lpi2c8 { + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; +}; + +&lpspi7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi7>; + cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + pendown-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + spi-max-frequency = <1500000>; + wakeup-source; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + }; +}; + +/* Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header (J12.4, J12.6) */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&netc_emdio { + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; +}; + +&pcie0 { + reset-gpio = <&pca6408_2 3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1 { + reset-gpio = <&pca6408_2 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usb2 { + dr_mode = "host"; + adp-disable; + hnp-disable; + srp-disable; + disable-over-current; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; + + port@1 { + reg = <1>; + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; +}; + +&usb3_phy { + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIO Expanders shared IRQ */ + IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x31e + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x57e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x57e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x37e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x31e + IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x31e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_lpspi7: lpspi7grp { + fsl,pins = < + /* j16.4 ADS7846 */ + IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe + /* j14.4 MCP2518FDT */ + IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x3fe + /* j25.2 spidev */ + IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x3fe + IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe + IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe + IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe + >; + }; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x31e + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e + IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi new file mode 100644 index 000000000000..a20fadacaa6d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX95 + * + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx95.dtsi" + +/ { + model = "Variscite DART-MX95 Module"; + compatible = "variscite,var-dart-mx95", "fsl,imx95"; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_audio: regulator-audio-vdd { + compatible = "regulator-fixed"; + regulator-name = "wm8904_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + }; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 27 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + status = "okay"; +}; + +&lpi2c8 { + clock-frequency = <400000>; + pinctrl-names = "default","gpio","sleep"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8_gpio>; + pinctrl-2 = <&pinctrl_lpi2c8_gpio>; + scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + DCVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +/* BT */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&mu7 { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>; + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +/* WiFi */ +&usdhc3 { + pinctrl-names = "default","state_100mhz","state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-3 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + wakeup-source; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e + >; + }; + + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = < + IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x40000b9e + IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { + fsl,pins = < + IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e + IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e + >; + }; + + pinctrl_phy0res: phy0resgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e + IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e + IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e + IMX95_PAD_GPIO_IO01__LPUART5_RX 0x31e + IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e + IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc3_gpio: usdhc3gpiogrp { + fsl,pins = < + IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x31e + IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x31e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi new file mode 100644 index 000000000000..889b71aa3de0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Dahlia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + reg_1v8_sw: regulator-1v8-sw { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier +V1.8_SW"; + }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-name = "PCIE_1_PWR_EN"; + }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-name = "HUB_PWR_EN"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3_mclk>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_1v8_sw>; + CPVDD-supply = <®_1v8_sw>; + DBVDD-supply = <®_1v8_sw>; + DCVDD-supply = <®_1v8_sw>; + MICVDD-supply = <®_1v8_sw>; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + vpcie-supply = <®_pcie>; + + status = "okay"; +}; + +/* We support turning off sleep moci on Dahlia */ +®_force_sleep_moci { + status = "disabled"; +}; + +/* Verdin I2S_1 */ +&sai3 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_dwc3 { + #address-cells = <1>; + #size-cells = <0>; + + usb_hub_3_0: usb-hub@1 { + compatible = "usb424,5744"; + reg = <1>; + peer-hub = <&usb_hub_2_0>; + vdd-supply = <®_usb_hub>; + }; + + usb_hub_2_0: usb-hub@2 { + compatible = "usb424,2744"; + reg = <2>; + peer-hub = <&usb_hub_3_0>; + vdd-supply = <®_usb_hub>; + }; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi new file mode 100644 index 000000000000..2848f9adf152 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + clocks = <&scmi_clk IMX95_CLK_SAI3>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3_mclk>; + #sound-dai-cells = <0>; + }; + + carrier_gpio_expander: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&lpuart7 { + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +&netc_emdio { + ethphy2: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&sai3 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi new file mode 100644 index 000000000000..8337c8b25f05 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi @@ -0,0 +1,515 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Ivy carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +#include +#include +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + ain1-current { + compatible = "io-channel-mux"; + channels = "", "ain1_current"; + io-channels = <&ain1_current_unmanaged>; + io-channel-names = "parent"; + mux-controls = <&ain1_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain1-voltage { + compatible = "io-channel-mux"; + channels = "ain1_voltage", ""; + io-channels = <&ain1_voltage_unmanaged 0>; + io-channel-names = "parent"; + mux-controls = <&ain1_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain2-current { + compatible = "io-channel-mux"; + channels = "", "ain2_current"; + io-channels = <&ain2_current_unmanaged>; + io-channel-names = "parent"; + mux-controls = <&ain2_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + ain2-voltage { + compatible = "io-channel-mux"; + channels = "ain2_voltage", ""; + io-channels = <&ain2_voltage_unmanaged 0>; + io-channel-names = "parent"; + mux-controls = <&ain2_mode_mux_ctrl>; + settle-time-us = <1000>; + }; + + /* AIN1 Current w/o AIN1_MODE gpio control */ + ain1_current_unmanaged: current-sense-shunt-ain1 { + compatible = "current-sense-shunt"; + #io-channel-cells = <0>; + io-channels = <&ivy_adc1 1>; + shunt-resistor-micro-ohms = <100000000>; + }; + + /* AIN2 Current w/o AIN2_MODE gpio control */ + ain2_current_unmanaged: current-sense-shunt-ain2 { + compatible = "current-sense-shunt"; + #io-channel-cells = <0>; + io-channels = <&ivy_adc2 1>; + shunt-resistor-micro-ohms = <100000000>; + }; + + /* Ivy Power Supply Input Voltage */ + ivy-1v8-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_4 */ + io-channels = <&adc1 3>; + full-ohms = <39000>; /* 12k + 27k */ + output-ohms = <27000>; + }; + + ivy-3v3-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_3 */ + io-channels = <&adc1 2>; + full-ohms = <54000>; /* 27k + 27k */ + output-ohms = <27000>; + }; + + ivy-5v-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_2 */ + io-channels = <&adc1 1>; + full-ohms = <39000>; /* 27k + 12k */ + output-ohms = <12000>; + }; + + ivy-input-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_1 */ + io-channels = <&adc1 0>; + full-ohms = <204700>; /* 200k + 4.7k */ + output-ohms = <4700>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ivy_leds>; + + /* D7 Blue - SODIMM 30 - LEDs.GPIO1 */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + }; + + /* D7 Green - SODIMM 32 - LEDs.GPIO2 */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + }; + + /* D7 Red - SODIMM 34 - LEDs.GPIO3 */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Blue - SODIMM 36 - LEDs.GPIO4 */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Green - SODIMM 54 - LEDs.GPIO5 */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + + /* D8 Red - SODIMM 44 - LEDs.GPIO6 */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + }; + + /* D9 Blue - SODIMM 46 - LEDs.GPIO7 */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + /* D9 Red - SODIMM 48 - LEDs.GPIO8 */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; + }; + }; + + /* AIN1_MODE - SODIMM 216 */ + ain1_mode_mux_ctrl: mux-controller-0 { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + #mux-control-cells = <0>; + mux-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + /* AIN2_MODE - SODIMM 218 */ + ain2_mode_mux_ctrl: mux-controller-1 { + compatible = "gpio-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; + #mux-control-cells = <0>; + mux-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + }; + + reg_3v2_ain1: regulator-3v2-ain1 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3200000>; + regulator-min-microvolt = <3200000>; + regulator-name = "+3V2_AIN1"; + }; + + reg_3v2_ain2: regulator-3v2-ain2 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3200000>; + regulator-min-microvolt = <3200000>; + regulator-name = "+3V2_AIN2"; + }; + + /* AIN1 Voltage w/o AIN1_MODE gpio control */ + ain1_voltage_unmanaged: voltage-divider-ain1 { + compatible = "voltage-divider"; + #io-channel-cells = <1>; + io-channels = <&ivy_adc1 0>; + full-ohms = <19>; + output-ohms = <1>; + }; + + /* AIN2 Voltage w/o AIN2_MODE gpio control */ + ain2_voltage_unmanaged: voltage-divider-ain2 { + compatible = "voltage-divider"; + #io-channel-cells = <1>; + io-channels = <&ivy_adc2 0>; + full-ohms = <19>; + output-ohms = <1>; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + gpio-line-names = ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>, + <&pinctrl_gpio3>; + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "GPIO2", /* Verdin GPIO_2 - SODIMM 208 */ + "", + "", /* 20 */ + "", + "", + "", + "GPIO3", /* Verdin GPIO_3 - SODIMM 210 */ + "", + "", + "", + "", + "", + "", /* 30 */ + ""; +}; + +&gpio3 { + gpio-line-names = ""; +}; + +&gpio4 { + gpio-line-names = ""; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_cs2_gpio>, + <&pinctrl_qspi1_dqs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + gpio-line-names = + "DIGI_1", /* SODIMM 56 */ + "DIGI_2", /* SODIMM 58 */ + "REL1", /* SODIMM 60 */ + "REL2", /* SODIMM 62 */ + "", + "", + "", + "", + "REL4", /* SODIMM 66 */ + "", + "", /* 10 */ + "REL3", /* SODIMM 64 */ + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; + + ivy_adc1: adc@40 { + compatible = "ti,ads1119"; + reg = <0x40>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <®_3v2_ain1>; + dvdd-supply = <®_3v2_ain1>; + vref-supply = <®_3v2_ain1>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + + /* AIN1 0-33V Voltage Input */ + channel@0 { + reg = <0>; + diff-channels = <0 1>; + }; + + /* AIN1 0-20mA Current Input */ + channel@1 { + reg = <1>; + diff-channels = <2 3>; + }; + }; + + ivy_adc2: adc@41 { + compatible = "ti,ads1119"; + reg = <0x41>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <®_3v2_ain2>; + dvdd-supply = <®_3v2_ain2>; + vref-supply = <®_3v2_ain2>; + #address-cells = <1>; + #io-channel-cells = <1>; + #size-cells = <0>; + + /* AIN2 0-33V Voltage Input */ + channel@0 { + reg = <0>; + diff-channels = <0 1>; + }; + + /* AIN2 0-20mA Current Input */ + channel@1 { + reg = <1>; + diff-channels = <2 3>; + }; + }; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, + <&pinctrl_spi1_cs>, + <&pinctrl_gpio1>, + <&pinctrl_gpio4>; + cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>, + <&gpio2 0 GPIO_ACTIVE_LOW>, + <&gpio5 12 GPIO_ACTIVE_LOW>; + + tpm@2 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <2>; + spi-max-frequency = <18500000>; + }; + + fram@3 { + compatible = "fujitsu,mb85rs256", "atmel,at25"; + reg = <3>; + address-width = <16>; + size = <32768>; + spi-max-frequency = <33000000>; + pagesize = <1>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2, through RS485 transceiver */ +&lpuart8 { + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; + +&netc_emdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +&som_gpio_expander { + gpio-line-names = ""; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_ivy_leds: ivyledsgrp { + fsl,pins = , /* SODIMM 30 */ + , /* SODIMM 32 */ + , /* SODIMM 34 */ + , /* SODIMM 36 */ + , /* SODIMM 44 */ + , /* SODIMM 46 */ + , /* SODIMM 48 */ + ; /* SODIMM 54 */ + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi new file mode 100644 index 000000000000..53506b7550f5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Mallow carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>; + + /* SODIMM 52 - USER_LED_1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 54 - USER_LED_1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 56 - USER_LED_2_RED */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 58 - USER_LED_2_GREEN */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, + <&pinctrl_spi1_cs>, + <&pinctrl_qspi1_cs2_gpio>; + cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>, + <&gpio5 11 GPIO_ACTIVE_LOW>; + + tpm@2 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; + interrupt-parent = <&gpio5>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..16975ae12fcb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Dahlia Board"; + compatible = "toradex,verdin-imx95-nonwifi-dahlia", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..97636ec7c26a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Verdin Development Board"; + compatible = "toradex,verdin-imx95-nonwifi-dev", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts new file mode 100644 index 000000000000..ebe1aec1ffa4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-ivy.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Ivy Board"; + compatible = "toradex,verdin-imx95-nonwifi-ivy", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts new file mode 100644 index 000000000000..5a9c0e4a79c9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Mallow Board"; + compatible = "toradex,verdin-imx95-nonwifi-mallow", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts new file mode 100644 index 000000000000..4f7b4e3a518b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-nonwifi.dtsi" +#include "imx95-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin iMX95 on Yavia Board"; + compatible = "toradex,verdin-imx95-nonwifi-yavia", + "toradex,verdin-imx95-nonwifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..7aba22067de5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM non-WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +/* SDIO on MSP 30, 31, 32, 33, 34, 35 */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..bafbe1179ec8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Dahlia Board"; + compatible = "toradex,verdin-imx95-wifi-dahlia", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts new file mode 100644 index 000000000000..345d37247025 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Verdin Development Board"; + compatible = "toradex,verdin-imx95-wifi-dev", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts new file mode 100644 index 000000000000..7ff2d03a254d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/ivy-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-ivy.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Ivy Board"; + compatible = "toradex,verdin-imx95-wifi-ivy", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts new file mode 100644 index 000000000000..eaa67a39be1c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Mallow Board"; + compatible = "toradex,verdin-imx95-wifi-mallow", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts new file mode 100644 index 000000000000..43d35b770db2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "imx95-verdin.dtsi" +#include "imx95-verdin-wifi.dtsi" +#include "imx95-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin iMX95 WB on Yavia Board"; + compatible = "toradex,verdin-imx95-wifi-yavia", + "toradex,verdin-imx95-wifi", + "toradex,verdin-imx95", + "fsl,imx95"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi new file mode 100644 index 000000000000..256c9ed04605 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + /* PMIC_EN_WIFI */ + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PDn_MAYA-W260"; + startup-delay-us = <2000>; + }; +}; + +/* On-module Bluetooth */ +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + uart-has-rtscts; + + status = "okay"; + + som_bt: bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_wifi_en>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi new file mode 100644 index 000000000000..6403ae584e70 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM on Yavia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/yavia + */ + +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + + /* SODIMM 52 - LD1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 54 - LD1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 56 - LD1_BLUE */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 58 - LD2_RED */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 60 - LD2_GREEN */ + led-4 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 62 - LD2_BLUE */ + led-5 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, + <&pinctrl_gpio2>, + <&pinctrl_gpio3>; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio6>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>, + <&pinctrl_qspi1_cs2_gpio>, + <&pinctrl_qspi1_dqs_gpio>; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&lpuart7 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&lpuart8 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&tpm4 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&tpm5 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb2 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,permanently-attached; + + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi new file mode 100644 index 000000000000..d3737956e2f9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi @@ -0,0 +1,1162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin iMX95 SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95 + */ + +#include +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + i2c0 = &lpi2c2; + i2c1 = &lpi2c4; + i2c2 = &lpi2c3; + i2c3 = &i3c2; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart7; + serial1 = &lpuart8; + serial2 = &lpuart1; + serial3 = &lpuart2; + serial4 = &lpuart6; + usb0 = &usb2; + usb1 = &usb3; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + /* Verdin USB_1_ID (SODIMM 161) */ + id-gpios = <&som_gpio_expander 5 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb1_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_id>; + }; + }; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + verdin_key_wakeup: key-wakeup { + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + /* + * By default we enable CTRL_SLEEP_MOCI#, this is required to have + * peripherals on the carrier board powered. + * If more granularity or power saving is required this can be disabled + * in the carrier board device tree files. + */ + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Verdin USB_1_EN (SODIMM 155) */ + gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Verdin USB_2_EN (SODIMM 185) */ + gpios = <&som_gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_EN"; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vsel>; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "PMIC_SD2_VSEL"; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + cm7: remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu7 0 1 + &mu7 1 1 + &mu7 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + }; +}; + +/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Verdin ETH_2_RGMII */ +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Verdin QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; +}; + +&gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153", + "SODIMM_20", + "SODIMM_22", + "SODIMM_252", /* 10 */ + "", + "SODIMM_189", + "IO_EXP_INT", + "SODIMM_256", + ""; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = + "SODIMM_206", /* 0 */ + "SODIMM_198", + "SODIMM_200", + "SODIMM_196", + "", + "SODIMM_15", + "SODIMM_16", + "", + "SODIMM_131", + "SODIMM_129", + "SODIMM_135", /* 10 */ + "SODIMM_133", + "SODIMM_139", + "SODIMM_137", + "SODIMM_143", + "SODIMM_141", + "SODIMM_30", + "SODIMM_38", + "SODIMM_208", + "SODIMM_19", + "SODIMM_36", /* 20 */ + "SODIMM_34", + "SODIMM_93", + "SODIMM_95", + "SODIMM_210", + "SODIMM_24", + "SODIMM_32", + "SODIMM_26", + "SODIMM_53", + "SODIMM_55", + "SODIMM_12", /* 30 */ + "SODIMM_14"; +}; + +&gpio3 { + gpio-line-names = + "SODIMM_84", /* 0 */ + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72", + "SODIMM_76", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "PMIC_SD2_VSEL", + "", /* 20 */ + "", + "", + "", + "", + "", + "SODIMM_91", + "SODIMM_218", + "", + "", + "", /* 30 */ + ""; +}; + +&gpio4 { + gpio-line-names = + "SODIMM_59", /* 0 */ + "SODIMM_57", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "SODIMM_193", + "SODIMM_191", + "SODIMM_215", + "SODIMM_217", + "SODIMM_219", + "SODIMM_221", + "SODIMM_211", /* 20 */ + "SODIMM_213", + "SODIMM_199", + "SODIMM_197", + "SODIMM_201", + "SODIMM_203", + "SODIMM_205", + "SODIMM_207", + "SODIMM_216", + "SODIMM_202"; +}; + +&gpio5 { + gpio-line-names = + "SODIMM_56", /* 0 */ + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "SODIMM_46", + "SODIMM_44", + "SODIMM_42", + "SODIMM_48", + "SODIMM_66", + "SODIMM_52", + "SODIMM_54", /* 10 */ + "SODIMM_64", + "SODIMM_212", + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_3_HDMI */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <400000>; +}; + +/* CTRL_I2C (On-module I2C) */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>, <&pinctrl_io_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>, <&pinctrl_io_exp_int>; + clock-frequency = <400000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; + + status = "okay"; + + som_gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "SODIMM_220", /* 0 */ + "SODIMM_222", + "SODIMM_17", + "SODIMM_21", + "SODIMM_244", + "SODIMM_161", + "SODIMM_157", + "SODIMM_155", + "SODIMM_185", + "SODIMM_187", + "USB_RECOV_CTRL#", /* 10 */ + "ENET1_INT#", + "TPM_INT#", + "TPM_CS#", + "", + ""; + + /* + * Switch USB to default position: + * - SoC USB2 -> Verdin USB_1 + * - SoC USB1 -> Verdin USB_2 + * Reset configuration: + * - SoC USB1 -> Verdin USB_1 (USB recovery) + * - SoC USB2 not connected + */ + usb_recov_ctrl: usb-recov-ctrl-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "USB_RECOV_CTRL#"; + output-high; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin I2C_1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin I2C_4_CSI */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + single-master; +}; + +/* Verdin SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_spi1_cs>; + cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, + <&som_gpio_expander 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi6's per-clock (twice the max speed) is 24 MHz + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Verdin UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Verdin UART_1 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_bus0 { + msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map = <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x50 &smmu 0x25 0x1>, + <0x60 &smmu 0x26 0x1>, + <0x80 &smmu 0x24 0x1>, + <0xc0 &smmu 0x27 0x1>; +}; + +/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&som_gpio_expander>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_LOW>; +}; + +/* Verdin I2S_1 */ +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = ; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Verdin PWM_1 */ +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm4>; +}; + +/* Verdin PWM_2 */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +/* Verdin PWM_3_DSI */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; +}; + +/* Verdin USB_1 */ +&usb2 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; + vbus-supply = <®_usb1_vbus>; + + port { + usb1_id: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +/* Verdin USB_2 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "host"; +}; + +&usb3_phy { + vbus-supply = <®_usb2_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* On-module Bluetooth on WB SKUs, module-specific UART otherwise */ + pinctrl_bt_uart: btuartgrp { + fsl,pins = , /* WiFi_UART_SoC_TXD */ + , /* WiFi_UART_SoC_RXD */ + , /* WiFi_UART_SoC_CTS */ + ; /* WiFi_UART_SoC_RTS */ + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_csi1_mclk: csi1mclkgrp { + fsl,pins = ; /* SODIMM 91 */ + }; + + /* Verdin CTRL_SLEEP_MOCI# */ + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = ; /* SODIMM 256 */ + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = ; /* SODIMM 252 */ + }; + + /* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */ + pinctrl_emdio: emdiogrp { + fsl,pins = , /* ENET2_MDC, SODIMM 193 */ + ; /* ENET2_MDIO, SODIMM 191 */ + }; + + /* Verdin ETH_1 (On-module PHY) */ + pinctrl_enetc0: enetc0grp { + fsl,pins = , /* ENET1_TX_CTL */ + , /* ENET1_TXC */ + , /* ENET1_TDO */ + , /* ENET1_TD1 */ + , /* ENET1_TD2 */ + , /* ENET1_TD3 */ + , /* ENET1_RX_CTL */ + , /* ENET1_RXC */ + , /* ENET1_RD0 */ + , /* ENET1_RD1 */ + , /* ENET1_RD2 */ + ; /* ENET1_RD3 */ + }; + + /* Verdin ETH_2_RGMII */ + pinctrl_enetc1: enetc1grp { + fsl,pins = , /* ENET2_TX_CTL */ + , /* ENET2_TXC */ + , /* ENET2_TD0 */ + , /* ENET2_TD1 */ + , /* ENET2_TD2 */ + , /* ENET2_TD3 */ + , /* ENET2_RX_CTL */ + , /* ENET2_RXC */ + , /* ENET2_RD0 */ + , /* ENET2_RD1 */ + , /* ENET2_RD2 */ + ; /* ENET2_RD3 */ + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: eth2rgmiiintgrp { + fsl,pins = ; /* SODIMM 189 */ + }; + + /* Verdin CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , /* SODIMM 20 */ + ; /* SODIMM 22 */ + }; + + /* Verdin CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , /* SODIMM 24 */ + ; /* SODIMM 26 */ + }; + + /* Verdin QSPI_1 */ + pinctrl_flexspi1: flexspi1grp { + fsl,pins = , /* SODIMM 54 */ + , /* SODIMM 64 */ + , /* SODIMM 52 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + , /* SODIMM 62 */ + ; /* SODIMM 66 */ + }; + + /* Verdin GPIO_1 */ + pinctrl_gpio1: gpio1grp { + fsl,pins = ; /* SODIMM 206 */ + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio2: gpio2grp { + fsl,pins = ; /* SODIMM 208 */ + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio3: gpio3grp { + fsl,pins = ; /* SODIMM 210 */ + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = ; /* SODIMM 212 */ + }; + + /* Verdin GPIO_5_CSI */ + pinctrl_gpio5: gpio5grp { + fsl,pins = ; /* SODIMM 216 */ + }; + + /* Verdin GPIO_6_CSI */ + pinctrl_gpio6: gpio6grp { + fsl,pins = ; /* SODIMM 218 */ + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_bclk_gpio: i2s2bclkgpiogrp { + fsl,pins = ; /* SODIMM 42 */ + }; + + /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_d_in_gpio: i2s2dingpiogrp { + fsl,pins = ; /* SODIMM 48 */ + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_d_out_gpio: i2s2doutgpiogrp { + fsl,pins = ; /* SODIMM 46 */ + }; + + /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2) */ + pinctrl_i2s_2_sync_gpio: i2s2syncgpiogrp { + fsl,pins = ; /* SODIMM 44 */ + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = , /* SODIMM 59 */ + ; /* SODIMM 57 */ + }; + + pinctrl_io_exp_int: ioexpintgrp { + fsl,pins = ; /* IO_EXP_INT */ + }; + + /* CTRL_I2C (On-module I2C) */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = , /* CTRL_I2C_SCL */ + ; /* CTRL_I2C_SDA */ + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , /* CTRL_I2C_SCL */ + ; /* CTRL_I2C_SDA */ + }; + + /* Verdin I2C_2_DSI */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = , /* SODIMM 53 */ + ; /* SODIMM 55 */ + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = , /* SODIMM 53 */ + ; /* SODIMM 55 */ + }; + + /* Verdin I2C_1 */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + /* Verdin I2C_4_CSI */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = , /* SODIMM 93 */ + ; /* SODIMM 95 */ + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = , /* SODIMM 93 */ + ; /* SODIMM 95 */ + }; + + /* Verdin SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = , /* SODIMM 198 */ + , /* SODIMM 200 */ + ; /* SODIMM 196 */ + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: qspi1clkgpiogrp { + fsl,pins = ; /* SODIMM 52 */ + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: qspi1cs2gpiogrp { + fsl,pins = ; /* SODIMM 64 */ + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: qspi1csgpiogrp { + fsl,pins = ; /* SODIMM 54 */ + }; + + /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_dqs_gpio: qspi1dqsgpiogrp { + fsl,pins = ; /* SODIMM 66 */ + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: qspi1io0gpiogrp { + fsl,pins = ; /* SODIMM 56 */ + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: qspi1io1gpiogrp { + fsl,pins = ; /* SODIMM 58 */ + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: qspi1io2gpiogrp { + fsl,pins = ; /* SODIMM 60 */ + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: qspi1io3gpiogrp { + fsl,pins = ; /* SODIMM 62 */ + }; + + /* Verdin I2S_1 */ + pinctrl_sai3: sai3grp { + fsl,pins = , /* SODIMM 30 */ + , /* SODIMM 36 */ + , /* SODIMM 34 */ + ; /* SODIMM 32 */ + }; + + /* Verdin I2S_1_MCLK */ + pinctrl_sai3_mclk: sai3mclkgrp { + fsl,pins = ; /* SODIMM 38 */ + }; + + /* Verdin I2S_2 */ + pinctrl_sai5: sai5grp { + fsl,pins = , /* SODIMM 46 */ + , /* SODIMM 44 */ + , /* SODIMM 42 */ + ; /* SODIMM 48 */ + }; + + /* Verdin SPI_1_CS */ + pinctrl_spi1_cs: spi1csgrp { + fsl,pins = ; /* SODIMM 202 */ + }; + + /* Verdin PWM_1 */ + pinctrl_tpm4: tpm4grp { + fsl,pins = ; /* SODIMM 15 */ + }; + + /* Verdin PWM_2 */ + pinctrl_tpm5: tpm5grp { + fsl,pins = ; /* SODIMM 16 */ + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_tpm6_gpio: tpm6gpiogrp { + fsl,pins = ; /* SODIMM 19 */ + }; + + /* Verdin PWM_3_DSI */ + pinctrl_tpm6: tpm6grp { + fsl,pins = ; /* SODIMM 19 */ + }; + + /* Verdin UART_3, used as the Linux Console */ + pinctrl_uart1: uart1grp { + fsl,pins = , /* SODIMM 147 */ + ; /* SODIMM 149 */ + }; + + /* Verdin UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = , /* SODIMM 151 */ + ; /* SODIMM 153 */ + }; + + /* Verdin UART_1 */ + pinctrl_uart7: uart7grp { + fsl,pins = , /* SODIMM 131 */ + , /* SODIMM 129 */ + , /* SODIMM 135 */ + ; /* SODIMM 133 */ + }; + + /* Verdin UART_2 */ + pinctrl_uart8: uart8grp { + fsl,pins = , /* SODIMM 139 */ + , /* SODIMM 137 */ + , /* SODIMM 143 */ + ; /* SODIMM 141 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , /* SD1_CLK */ + , /* SD1_CMD */ + , /* SD1_DATA0 */ + , /* SD1_DATA1 */ + , /* SD1_DATA2 */ + , /* SD1_DATA3 */ + , /* SD1_DATA4 */ + , /* SD1_DATA5 */ + , /* SD1_DATA6 */ + , /* SD1_DATA7 */ + ; /* SD1_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , /* SD1_CLK */ + , /* SD1_CMD */ + , /* SD1_DATA0 */ + , /* SD1_DATA1 */ + , /* SD1_DATA2 */ + , /* SD1_DATA3 */ + , /* SD1_DATA4 */ + , /* SD1_DATA5 */ + , /* SD1_DATA6 */ + , /* SD1_DATA7 */ + ; /* SD1_STROBE */ + }; + + /* Verdin SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + ; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + ; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + ; /* SODIMM 72 */ + }; + + /* Verdin SD_1_CD# */ + pinctrl_usdhc2_cd: usdhc2-cdgrp { + fsl,pins = ; /* SODIMM 84 */ + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { + fsl,pins = ; /* SODIMM 76 */ + }; + + pinctrl_usdhc2_vsel: usdhc2-vselgrp { + fsl,pins = ; /* PMIC_SD2_VSEL */ + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , /* SD3_CLK */ + , /* SD3_CMD */ + , /* SD3_DATA0 */ + , /* SD3_DATA1 */ + , /* SD3_DATA2 */ + ; /* SD3_DATA3 */ + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , /* SD3_CLK */ + , /* SD3_CMD */ + , /* SD3_DATA1 */ + , /* SD3_DATA2 */ + , /* SD3_DATA3 */ + ; /* SD3_DATA4 */ + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = ; /* PMIC_EN_WIFI */ + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 55e2da094c88..71394871d8dd 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -391,9 +391,60 @@ scmi_misc: protocol@84 { }; }; + funnel0: funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + port { + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + + funnel1: funnel-sys { + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + port { + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + mqs1: mqs-1 { + compatible = "fsl,imx95-aonmix-mqs"; + status = "disabled"; + }; + pmu { compatible = "arm,cortex-a55-pmu"; - interrupts = ; + interrupts = ; }; thermal_zones: thermal-zones { @@ -470,10 +521,10 @@ psci { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <24000000>; arm,no-tick-in-suspend; interrupt-parent = <&gic>; @@ -532,52 +583,6 @@ etm0_out_port: endpoint { }; }; - funnel0: funnel { - /* - * non-configurable funnel don't show up on the AMBA - * bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-funnel"; - status = "disabled"; - - in-ports { - port { - ca_funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - }; - - out-ports { - port { - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - }; - }; - - funnel1: funnel-sys { - compatible = "arm,coresight-static-funnel"; - status = "disabled"; - - in-ports { - port { - hugo_funnel_in_port0: endpoint { - remote-endpoint = <&ca_funnel_out_port0>; - }; - }; - }; - - out-ports { - port { - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - }; - }; - etf: etf@41030000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x0 0x41030000 0x0 0x1000>; @@ -631,6 +636,8 @@ edma2: dma-controller@42000000 { reg = <0x42000000 0x210000>; #dma-cells = <3>; dma-channels = <64>; + /* channels 0 and 1 reserved for V2X fast hash */ + dma-channel-mask = <0x3>; interrupts = , , , diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index b838323468d4..62d1c1c7c501 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -43,10 +43,21 @@ aliases { spi6 = &lpspi7; }; + bt_sco_codec: audio-codec-bt-sco { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + chosen { stdout-path = &lpuart1; }; + dmic: dmic { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <2>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; @@ -110,6 +121,15 @@ reg_vref_1v8: regulator-adc-vref { regulator-max-microvolt = <1800000>; }; + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-pwr"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + gpio = <&i2c4_pcal6408 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -131,6 +151,88 @@ reg_usb_vbus: regulator-vbus { enable-active-high; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master = <&btcpu>; + simple-audio-card,format = "dsp_a"; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,name = "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + sound-dai = <&sai1>; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + codec { + sound-dai = <&dmic>; + }; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + audio-asrc = <&asrc1>; + audio-codec = <&wm8962>; + audio-cpu = <&sai3>; + audio-routing = "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + model = "wm8962-audio"; + pinctrl-0 = <&pinctrl_hp>; + pinctrl-names = "default"; + }; +}; + +&asrc1 { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_ASRC1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc2 { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_ASRC2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + fsl,asrc-rate = <48000>; + status = "okay"; }; /* pin conflict with PDM */ @@ -185,6 +287,27 @@ &lpi2c4 { pinctrl-0 = <&pinctrl_lpi2c4>; status = "okay"; + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&scmi_clk IMX952_CLK_SAI3>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + DCVDD-supply = <®_audio_pwr>; + gpio-cfg = < 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + }; + i2c4_pcal6408: gpio@21 { compatible = "nxp,pcal6408"; reg = <0x21>; @@ -312,6 +435,57 @@ &lpspi7 { status = "okay"; }; +&micfil { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <49152000>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-1 = <&pinctrl_pdm_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <12288000>; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + pinctrl-names = "default", "sleep"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&scmi_clk IMX952_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, <12288000>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-1 = <&pinctrl_sai3_sleep>; + pinctrl-names = "default", "sleep"; + fsl,sai-amix-mode = "bypass"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &scmi_misc { nxp,ctrl-ids = ; }; + pinctrl_hp: hpgrp { + fsl,pins = < + IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x31e + >; + }; + pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e @@ -464,6 +644,20 @@ IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins = < + IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x31e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x31e + >; + }; + pinctrl_ptn5110: ptn5110grp { fsl,pins = < IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e @@ -476,6 +670,44 @@ IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x31e + IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e + IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e + IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1sleepgrp { + fsl,pins = < + IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x51e + IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x51e + IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x51e + IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x51e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x31e + IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x31e + IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x31e + IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x31e + IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3sleepgrp { + fsl,pins = < + IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x31e + IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x31e + IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x31e + IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x31e + IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x31e + >; + }; + pinctrl_tpm3: tpm3grp { fsl,pins = < IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e @@ -593,4 +825,45 @@ pinctrl_usdhc2_gpio: usdhc2gpiogrp { IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e >; }; + + pinctrl_xspi1: xspi1grp { + fsl,pins = < + IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x39e + IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x39e + IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x39e + IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x39e + IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x39e + IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x39e + IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x39e + IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x39e + IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x39e + IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x39e + IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x39e + >; + }; + + pinctrl_xspi1_reset: xspi1-reset-grp { + fsl,pins = < + IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x39e + >; + }; +}; + +&xspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xspi1>; + status = "okay"; + + mt35xu01gbba: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_xspi1_reset>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <200000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi index 91fe4916ac04..b30707837f35 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -285,7 +285,7 @@ its: msi-controller@48040000 { pmu { compatible = "arm,cortex-a55-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -295,10 +295,10 @@ psci { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <24000000>; arm,no-tick-in-suspend; interrupt-parent = <&gic>; @@ -672,6 +672,25 @@ mu8: mailbox@42350000 { #mbox-cells = <2>; status = "disabled"; }; + + xspi1: spi@42400000 { + compatible = "nxp,imx952-xspi", "nxp,imx94-xspi"; + reg = <0x42400000 0x50000>, <0x28000000 0x8000000>; + reg-names = "base", "mmap"; + interrupts = , + , + , + , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_XSPI1>; + clock-names = "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_XSPI1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <200000000>; + status = "disabled"; + }; }; aips3: bus@42800000 { @@ -804,6 +823,160 @@ usdhc3: mmc@42c40000 { }; }; + aips5: bus@43000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x43000000 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x43000000 0x0 0x43000000 0x800000>; + + asrc1: asrc@43000000 { + compatible = "fsl,imx952-asrc"; + reg = <0x43000000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_ASRC1>, + <&scmi_clk IMX952_CLK_ASRC2>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma2 97 0 0>, <&edma2 98 0 0>, <&edma2 99 0 0>, + <&edma2 100 0 FSL_EDMA_RX>, <&edma2 101 0 FSL_EDMA_RX>, + <&edma2 102 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + #sound-dai-cells = <0>; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + status = "disabled"; + }; + + asrc2: asrc@430f0000 { + compatible = "fsl,imx952-asrc"; + reg = <0x430f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_ASRC1>, + <&scmi_clk IMX952_CLK_ASRC2>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "mem", "ipg", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma2 103 0 0>, <&edma2 104 0 0>, <&edma2 105 0 0>, + <&edma2 106 0 FSL_EDMA_RX>, <&edma2 107 0 FSL_EDMA_RX>, + <&edma2 108 0 FSL_EDMA_RX>; + /* tx* is output channel of asrc, it is rx channel for eDMA */ + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + #sound-dai-cells = <0>; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + status = "disabled"; + }; + + amix: amix@431f0000 { + compatible = "fsl,imx952-audmix"; + reg = <0x431f0000 0x10000>; + clocks = <&scmi_clk IMX952_CLK_AUDMIX1>; + clock-names = "ipg"; + status = "disabled"; + }; + + sai3: sai@433e0000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x433e0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI3>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai4: sai@433f0000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x433f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI4>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai5: sai@43400000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x43400000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI5>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai6: sai@43410000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x43410000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI3>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 96 0 FSL_EDMA_RX>, <&edma2 95 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + }; + gpio2: gpio@43810000 { compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; reg = <0x0 0x43810000 0x0 0x1000>; @@ -1043,6 +1216,40 @@ flexcan1: can@443a0000 { status = "disabled"; }; + sai1: sai@443b0000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x443b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI1>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + micfil: micfil@44520000 { + compatible = "fsl,imx943-micfil"; + reg = <0x44520000 0x10000>; + interrupts = , + , + , + ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_PDM>, + <&scmi_clk IMX952_CLK_AUDIOPLL1>, + <&scmi_clk IMX952_CLK_AUDIOPLL2>, + <&clk_dummy>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&edma1 6 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>; + dma-names = "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + adc1: adc@44530000 { compatible = "nxp,imx93-adc"; reg = <0x44530000 0x10000>; @@ -1262,5 +1469,20 @@ usbmisc2: usbmisc@4c200200 { reg = <0x0 0x4c200200 0x0 0x200>, <0x0 0x4c010014 0x0 0x4>; }; + + sai2: sai@4c880000 { + compatible = "fsl,imx952-sai", "fsl,imx95-sai"; + reg = <0x0 0x4c880000 0x0 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSNETCMIX>, <&clk_dummy>, + <&scmi_clk IMX952_CLK_SAI2>, <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + power-domains = <&scmi_devpd IMX952_PD_NETC>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 10d5c211b1c9..c24ae953cbc2 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -209,7 +209,7 @@ expander0: gpio@23 { interrupt-controller; #interrupt-cells = <2>; gpio-line-names = "", "", "", "", - "", "", "LVDS_BRIDGE_EN", "", + "", "", "LVDS_BRIDGE_EN", "LVDS_BRIDGE_IRQ", "", "", "", "", "", "", "", ""; @@ -298,6 +298,8 @@ dsi_lvds_bridge: bridge@2d { reg = <0x2d>; enable-gpios = <&gpio_delays 0 130000 0>; vcc-supply = <®_sn65dsi83_1v8>; + interrupt-parent = <&expander0>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; status = "disabled"; ports { diff --git a/arch/arm64/boot/dts/freescale/s32n79-rdb.dts b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts new file mode 100644 index 000000000000..1feccd61258e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2026 NXP + * + * NXP S32N79 Reference Design Board (S32N79-RDB) + */ + +/dts-v1/; +#include "s32n79.dtsi" + +/ { + compatible = "nxp,s32n79-rdb", "nxp,s32n79"; + model = "NXP S32N79-RDB"; + + aliases { + serial0 = &uart0; + serial1 = &uart5; + serial2 = &uart6; + serial3 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + scmi_shbuf: memory@93000000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x93000000 0x0 0x80>; + no-map; + }; + }; + + memory@80000000 { + reg = <0x00 0x80000000 0x00 0x80000000>, + <0x88 0x00000000 0x03 0x40000000>, + <0xc0 0x00000000 0x03 0x40000000>; + device_type = "memory"; + }; +}; + +&irqsteer_coss { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart6 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&usdhc0 { + disable-wp; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi new file mode 100644 index 000000000000..94ab58783fdc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * NXP S32N79 SoC + * + * Copyright 2026 NXP + */ + +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cis-bus { + compatible = "simple-bus"; + ranges = <0x4f200000 0x0 0x4f200000 0xc00000>; + #address-cells = <1>; + #size-cells = <1>; + + gic: interrupt-controller@4f200000 { + compatible = "arm,gic-v3"; + reg = <0x4f200000 0x10000>, /* GIC Dist */ + <0x4f260000 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + /* GICR (RD_base + SGI_base) */ + ranges; + + its: msi-controller@4f240000 { + compatible = "arm,gic-v3-its"; + reg = <0x4f240000 0x20000>; + #msi-cells = <1>; + msi-controller; + }; + }; + + smmu: iommu@4fc00000 { + compatible = "arm,smmu-v3"; + reg = <0x4fc00000 0x200000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + dma-coherent; + status = "disabled"; + }; + }; + + coss-bus { + compatible = "simple-bus"; + ranges = <0x4a000000 0x0 0x4a000000 0xff0000>, + <0x4e000000 0x0 0x4e000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@4a030000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x4a030000 0x1000>; + interrupt-parent = <&irqsteer_coss>; + interrupts = <264>; + clocks = <&clks 0x9a>, <&clks 0x9a>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart5: serial@4a060000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x4a060000 0x1000>; + interrupt-parent = <&irqsteer_coss>; + interrupts = <269>; + clocks = <&clks 0x9a>, <&clks 0x9a>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart6: serial@4aa30000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x4aa30000 0x1000>; + interrupt-parent = <&irqsteer_coss>; + interrupts = <270>; + clocks = <&clks 0x9a>, <&clks 0x9a>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart7: serial@4aa40000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x4aa40000 0x1000>; + interrupt-parent = <&irqsteer_coss>; + interrupts = <271>; + clocks = <&clks 0x9a>, <&clks 0x9a>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + irqsteer_coss: interrupt-controller@4ed00000 { + compatible = "nxp,s32n79-irqsteer"; + reg = <0x4ed00000 0x10000>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clks 0x9a>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <512>; + status = "disabled"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + }; + + cluster3 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <524288>; + cache-unified; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <524288>; + cache-unified; + next-level-cache = <&l3_1>; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <524288>; + cache-unified; + next-level-cache = <&l3_2>; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <524288>; + cache-unified; + next-level-cache = <&l3_3>; + }; + + l3_0: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-size = <1048576>; + cache-unified; + }; + + l3_1: l3-cache1 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-size = <1048576>; + cache-unified; + }; + + l3_2: l3-cache2 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-size = <1048576>; + cache-unified; + }; + + l3_3: l3-cache3 { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-size = <1048576>; + cache-unified; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a78ae"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_0>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a78ae"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_0>; + }; + + cpu2: cpu@10000 { + compatible = "arm,cortex-a78ae"; + reg = <0x10000>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_1>; + }; + + cpu3: cpu@10100 { + compatible = "arm,cortex-a78ae"; + reg = <0x10100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_1>; + }; + + cpu4: cpu@20000 { + compatible = "arm,cortex-a78ae"; + reg = <0x20000>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_2>; + }; + + cpu5: cpu@20100 { + compatible = "arm,cortex-a78ae"; + reg = <0x20100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_2>; + }; + + cpu6: cpu@30000 { + compatible = "arm,cortex-a78ae"; + reg = <0x30000>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_3>; + }; + + cpu7: cpu@30100 { + compatible = "arm,cortex-a78ae"; + reg = <0x30100>; + device_type = "cpu"; + enable-method = "psci"; + next-level-cache = <&l2_3>; + }; + }; + + firmware { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + #address-cells = <1>; + #size-cells = <0>; + shmem = <&scmi_shbuf>; + arm,smc-id = <0xc20000fe>; + status = "okay"; + + clks: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + fss-bus { + compatible = "simple-bus"; + ranges = <0x5b490000 0x0 0x5b490000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + usdhc0: mmc@5b490000 { + compatible = "nxp,s32n79-usdhc"; + reg = <0x5b490000 0x1000>; + interrupts = ; + clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>; + clock-names = "ipg", "ahb", "per"; + bus-width = <8>; + status = "disabled"; + }; + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 957a1b41f19b..374aa173bec6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1057,7 +1057,7 @@ ufs: ufs@ff3b0000 { }; /* SD */ - dwmmc1: dwmmc1@ff37f000 { + dwmmc1: mmc@ff37f000 { compatible = "hisilicon,hi3660-dw-mshc"; reg = <0x0 0xff37f000 0x0 0x1000>; #address-cells = <1>; @@ -1075,7 +1075,7 @@ dwmmc1: dwmmc1@ff37f000 { }; /* SDIO */ - dwmmc2: dwmmc2@ff3ff000 { + dwmmc2: mmc@ff3ff000 { compatible = "hisilicon,hi3660-dw-mshc"; reg = <0x0 0xff3ff000 0x0 0x1000>; #address-cells = <0x1>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 886b93c5893a..0db1849a2878 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -679,7 +679,7 @@ ufs: ufs@ff3c0000 { }; /* SD */ - dwmmc1: dwmmc1@ff37f000 { + dwmmc1: mmc@ff37f000 { compatible = "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc"; reg = <0x0 0xff37f000 0x0 0x1000>; @@ -698,7 +698,7 @@ dwmmc1: dwmmc1@ff37f000 { }; /* SDIO */ - dwmmc2: dwmmc2@fc183000 { + dwmmc2: mmc@fc183000 { compatible = "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc"; reg = <0x0 0xfc183000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index f8b56d443850..61eaa7f8c1c9 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -799,7 +799,7 @@ mailbox: mailbox@f7510000 { #mbox-cells = <3>; }; - dwmmc_0: dwmmc0@f723d000 { + dwmmc_0: mmc@f723d000 { compatible = "hisilicon,hi6220-dw-mshc"; reg = <0x0 0xf723d000 0x0 0x1000>; interrupts = <0x0 0x48 0x4>; @@ -812,7 +812,7 @@ dwmmc_0: dwmmc0@f723d000 { &emmc_cfg_func &emmc_rst_cfg_func>; }; - dwmmc_1: dwmmc1@f723e000 { + dwmmc_1: mmc@f723e000 { compatible = "hisilicon,hi6220-dw-mshc"; hisilicon,peripheral-syscon = <&ao_ctrl>; reg = <0x0 0xf723e000 0x0 0x1000>; @@ -828,7 +828,7 @@ dwmmc_1: dwmmc1@f723e000 { pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; }; - dwmmc_2: dwmmc2@f723f000 { + dwmmc_2: mmc@f723f000 { compatible = "hisilicon,hi6220-dw-mshc"; reg = <0x0 0xf723f000 0x0 0x1000>; interrupts = <0x0 0x4a 0x4>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 352c96d144a8..02e62d954e94 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -152,10 +152,10 @@ qspi_clk: qspi-clk { timer { compatible = "arm,armv8-timer"; interrupt-parent = <&intc>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; usbphy0: usbphy { diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index 467d8a4c2aa7..45ad69ee49ed 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -205,7 +205,7 @@ mt6359_vrfck_ldo_reg: ldo_vrfck { regulator-max-microvolt = <1700000>; }; mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 { - regulator-name = "vrfck"; + regulator-name = "vrfck_1"; regulator-min-microvolt = <1240000>; regulator-max-microvolt = <1600000>; }; @@ -227,7 +227,7 @@ mt6359_vemc_ldo_reg: ldo_vemc { regulator-max-microvolt = <3300000>; }; mt6359_vemc_1_ldo_reg: ldo_vemc_1 { - regulator-name = "vemc"; + regulator-name = "vemc_1"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index ae2aaa51c9ad..134cfa77e3b1 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -371,7 +371,7 @@ pio: pinctrl@10005000 { ; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 196>; + gpio-ranges = <&pio 0 0 197>; interrupt-controller; #interrupt-cells = <2>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 4084f4dfa3e5..1bbe219380f9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -332,7 +332,7 @@ pio: pinctrl@11d00000 { interrupt-controller; interrupts = ; interrupt-parent = <&gic>; - gpio-ranges = <&pio 0 0 56>; + gpio-ranges = <&pio 0 0 57>; gpio-controller; #gpio-cells = <2>; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 9693f62fd013..9ebc196107e5 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -187,7 +187,7 @@ pio: pinctrl@1001f000 { "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 100>; + gpio-ranges = <&pio 0 0 101>; interrupt-controller; interrupts = ; interrupt-parent = <&gic>; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts index c7ea6e88c4f4..621d01e3cd89 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-4e.dts @@ -9,7 +9,7 @@ #include "mt7988a-bananapi-bpi-r4-pro.dtsi" / { - model = "Bananapi BPI-R4"; + model = "Bananapi BPI-R4 Pro 4E"; compatible = "bananapi,bpi-r4-pro-4e", "bananapi,bpi-r4-pro", "mediatek,mt7988a"; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts index c9a0e69e9dd5..bb15bfa5e6ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-pro-8x.dts @@ -9,7 +9,7 @@ #include "mt7988a-bananapi-bpi-r4-pro.dtsi" / { - model = "Bananapi BPI-R4"; + model = "Bananapi BPI-R4 Pro 8X"; compatible = "bananapi,bpi-r4-pro-8x", "bananapi,bpi-r4-pro", "mediatek,mt7988a"; diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 2374c0953057..27cf32d7ae35 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -29,12 +29,6 @@ infracfg: infracfg@10001000 { #clock-cells = <1>; }; - apmixedsys: apmixedsys@10018000 { - compatible = "mediatek,mt8167-apmixedsys", "syscon"; - reg = <0 0x10018000 0 0x710>; - #clock-cells = <1>; - }; - scpsys: syscon@10006000 { compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; @@ -101,18 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_CONN { }; }; - imgsys: syscon@15000000 { - compatible = "mediatek,mt8167-imgsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - vdecsys: syscon@16000000 { - compatible = "mediatek,mt8167-vdecsys", "syscon"; - reg = <0 0x16000000 0 0x1000>; - #clock-cells = <1>; - }; - pio: pinctrl@1000b000 { compatible = "mediatek,mt8167-pinctrl"; reg = <0 0x1000b000 0 0x1000>; @@ -124,21 +106,26 @@ pio: pinctrl@1000b000 { interrupts = ; }; + apmixedsys: apmixedsys@10018000 { + compatible = "mediatek,mt8167-apmixedsys", "syscon"; + reg = <0 0x10018000 0 0x710>; + #clock-cells = <1>; + }; + + iommu: m4u@10203000 { + compatible = "mediatek,mt8167-m4u"; + reg = <0 0x10203000 0 0x1000>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; + interrupts = ; + #iommu-cells = <1>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; - smi_common: smi@14017000 { - compatible = "mediatek,mt8167-smi-common"; - reg = <0 0x14017000 0 0x1000>; - clocks = <&mmsys CLK_MM_SMI_COMMON>, - <&mmsys CLK_MM_SMI_COMMON>; - clock-names = "apb", "smi"; - power-domains = <&spm MT8167_POWER_DOMAIN_MM>; - }; - larb0: larb@14016000 { compatible = "mediatek,mt8167-smi-larb"; reg = <0 0x14016000 0 0x1000>; @@ -149,6 +136,21 @@ larb0: larb@14016000 { power-domains = <&spm MT8167_POWER_DOMAIN_MM>; }; + smi_common: smi@14017000 { + compatible = "mediatek,mt8167-smi-common"; + reg = <0 0x14017000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8167_POWER_DOMAIN_MM>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt8167-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + larb1: larb@15001000 { compatible = "mediatek,mt8167-smi-larb"; reg = <0 0x15001000 0 0x1000>; @@ -159,6 +161,12 @@ larb1: larb@15001000 { power-domains = <&spm MT8167_POWER_DOMAIN_ISP>; }; + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8167-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + larb2: larb@16010000 { compatible = "mediatek,mt8167-smi-larb"; reg = <0 0x16010000 0 0x1000>; @@ -168,13 +176,5 @@ larb2: larb@16010000 { clock-names = "apb", "smi"; power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>; }; - - iommu: m4u@10203000 { - compatible = "mediatek,mt8167-m4u"; - reg = <0 0x10203000 0 0x1000>; - mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; - interrupts = ; - #iommu-cells = <1>; - }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts index 49664de99b88..57cc329f49c4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts @@ -11,6 +11,28 @@ / { compatible = "google,dojo-sku7", "google,dojo-sku5", "google,dojo-sku3", "google,dojo-sku1", "google,dojo", "mediatek,mt8195"; + + nvme-connector { + compatible = "pcie-m2-m-connector"; + /* power is controlled by EC */ + vpcie3v3-supply = <&pp3300_z2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + nvme_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie0_ep>; + }; + }; + }; + }; }; &audio_codec { @@ -72,6 +94,22 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pcie0_pins_default>; status = "okay"; + + pcie@0 { + compatible = "pciclass,0604"; + reg = <0 0 0 0 0>; + device_type = "pci"; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + port { + pcie0_ep: endpoint { + remote-endpoint = <&nvme_ep>; + }; + }; + }; }; &pciephy { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index b3761b80cac7..f1ff64a84267 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -83,6 +83,17 @@ pp3300_s3: regulator-pp3300-s3 { vin-supply = <&pp3300_z2>; }; + pp3300_wlan: regulator-pp3300-wlan { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_wlan_en_pin>; + regulator-name = "pp3300_wlan"; + /* load switch */ + enable-active-high; + gpio = <&pio 58 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_z2>; + }; + /* system wide 3.3V power rail */ pp3300_z2: regulator-pp3300-z2 { compatible = "regulator-fixed"; @@ -760,10 +771,25 @@ &ovl0_in { }; &pcie1 { - status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_pins_default>; + status = "okay"; + + pcie@0 { + compatible = "pciclass,0604"; + reg = <0 0 0 0 0>; + device_type = "pci"; + num-lanes = <1>; + vpcie3v3-supply = <&pp3300_wlan>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@0 { + reg = <0 0 0 0 0>; + wakeup-source; + }; + }; }; &pio { @@ -1179,12 +1205,6 @@ pins-vreg-en { }; pio_default: pio-default-pins { - pins-wifi-enable { - pinmux = ; - output-high; - drive-strength = <14>; - }; - pins-low-power-pd { pinmux = , , @@ -1222,6 +1242,12 @@ pins-low-power-pupd { }; }; + pp3300_wlan_en_pin: pp3300-wlan-en-pins { + pins-en { + pinmux = ; + }; + }; + rt1019p_pins_default: rt1019p-default-pins { pins-amp-sdb { pinmux = ; @@ -1495,6 +1521,7 @@ &u3phy0 { }; &u3phy1 { + /* shared between xhci1 and pcie1. */ status = "okay"; }; @@ -1563,27 +1590,16 @@ &xhci0 { vbus-supply = <&usb_vbus>; }; -&xhci1 { - status = "okay"; - - phys = <&u2port1 PHY_TYPE_USB2>; - rx-fifo-depth = <3072>; - vusb33-supply = <&mt6359_vusb_ldo_reg>; - vbus-supply = <&usb_vbus>; - mediatek,u3p-dis-msk = <1>; -}; - &xhci2 { status = "okay"; vbus-supply = <&usb_vbus>; }; &xhci3 { - status = "okay"; - /* MT7921's USB Bluetooth has issues with USB2 LPM */ usb2-lpm-disable; - vbus-supply = <&usb_vbus>; + vbus-supply = <&pp3300_wlan>; + status = "okay"; }; #include diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index b5dd5ef9fa11..a30ee523b0b5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -20,8 +20,10 @@ / { compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; aliases { - serial0 = &uart0; ethernet = ðernet; + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; }; chosen { diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index a5ca3cda6ef3..2e782558fb77 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -536,10 +536,9 @@ iommu: iommu@10205000 { #iommu-cells = <1>; }; - infracfg_nao: infracfg@1020e000 { - compatible = "mediatek,mt8365-infracfg", "syscon"; + infracfg_nao: syscon@1020e000 { + compatible = "mediatek,mt8365-infracfg-nao", "syscon"; reg = <0 0x1020e000 0 0x1000>; - #clock-cells = <1>; }; rng: rng@1020f000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index d849af4d3613..62c336e21500 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -18,8 +18,10 @@ / { aliases { - serial0 = &uart0; ethernet0 = ð + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; }; chosen { diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 1cd4b84e9861..bf91305e8e4a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -21,12 +21,14 @@ / { compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195"; aliases { + ethernet0 = ð i2c0 = &i2c2; i2c1 = &i2c3; i2c2 = &i2c4; i2c3 = &i2c0; i2c4 = &i2c1; - ethernet0 = ð + mmc0 = &mmc0; + mmc1 = &mmc1; serial0 = &uart0; serial1 = &uart1; spi0 = &spi1; diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile index c6e0313eea0f..09d16fc1ce9a 100644 --- a/arch/arm64/boot/dts/microchip/Makefile +++ b/arch/arm64/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_LAN969X) += lan9696-ev23x71a.dtb dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/clk-lan9691.h b/arch/arm64/boot/dts/microchip/clk-lan9691.h new file mode 100644 index 000000000000..0f2d7a0f881e --- /dev/null +++ b/arch/arm64/boot/dts/microchip/clk-lan9691.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ + +#ifndef _DTS_CLK_LAN9691_H +#define _DTS_CLK_LAN9691_H + +#define GCK_ID_QSPI0 0 +#define GCK_ID_QSPI2 1 +#define GCK_ID_SDMMC0 2 +#define GCK_ID_SDMMC1 3 +#define GCK_ID_MCAN0 4 +#define GCK_ID_MCAN1 5 +#define GCK_ID_FLEXCOM0 6 +#define GCK_ID_FLEXCOM1 7 +#define GCK_ID_FLEXCOM2 8 +#define GCK_ID_FLEXCOM3 9 +#define GCK_ID_TIMER 10 +#define GCK_ID_USB_REFCLK 11 + +/* Gate clocks */ +#define GCK_GATE_USB_DRD 12 +#define GCK_GATE_MCRAMC 13 +#define GCK_GATE_HMATRIX 14 + +#endif diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/dts/microchip/lan9691.dtsi new file mode 100644 index 000000000000..235e56bebbdb --- /dev/null +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include +#include +#include + +#include "clk-lan9691.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "Microchip LAN969x"; + compatible = "microchip,lan9691"; + interrupt-parent = <&gic>; + + clocks { + fx100_clk: fx100-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <320000000>; + }; + + cpu_clk: cpu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + ddr_clk: ddr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + fabric_clk: fabric-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&l2_0>; + }; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Secure Phys IRQ */ + , /* Non-secure Phys IRQ */ + , /* Virt IRQ */ + ; /* Hyp IRQ */ + }; + + axi: axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb: usb@300000 { + compatible = "microchip,lan9691-dwc3", "snps,dwc3"; + reg = <0x300000 0x80000>; + interrupts = ; + clocks = <&clks GCK_GATE_USB_DRD>, + <&clks GCK_ID_USB_REFCLK>; + clock-names = "bus_early", "ref"; + assigned-clocks = <&clks GCK_ID_USB_REFCLK>; + assigned-clock-rates = <60000000>; + maximum-speed = "high-speed"; + dr_mode = "host"; + status = "disabled"; + }; + + flx0: flexcom@e0040000 { + compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe0040000 0x100>; + ranges = <0x0 0xe0040000 0x800>; + clocks = <&clks GCK_ID_FLEXCOM0>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usart0: serial@200 { + compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flx1: flexcom@e0044000 { + compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe0044000 0x100>; + ranges = <0x0 0xe0044000 0x800>; + clocks = <&clks GCK_ID_FLEXCOM1>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usart1: serial@200 { + compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + trng: rng@e0048000 { + compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng"; + reg = <0xe0048000 0x100>; + clocks = <&fabric_clk>; + status = "disabled"; + }; + + aes: crypto@e004c000 { + compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes"; + reg = <0xe004c000 0x100>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(12)>, + <&dma AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "aes_clk"; + status = "disabled"; + }; + + flx2: flexcom@e0060000 { + compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe0060000 0x100>; + ranges = <0x0 0xe0060000 0x800>; + clocks = <&clks GCK_ID_FLEXCOM2>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usart2: serial@200 { + compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flx3: flexcom@e0064000 { + compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe0064000 0x100>; + ranges = <0x0 0xe0064000 0x800>; + clocks = <&clks GCK_ID_FLEXCOM3>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usart3: serial@200 { + compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + dma: dma-controller@e0068000 { + compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma"; + reg = <0xe0068000 0x1000>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <1>; + clocks = <&fabric_clk>; + clock-names = "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha"; + reg = <0xe006c000 0xec>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(14)>; + dma-names = "tx"; + clocks = <&fabric_clk>; + clock-names = "sha_clk"; + status = "disabled"; + }; + + timer: timer@e008c000 { + compatible = "snps,dw-apb-timer"; + reg = <0xe008c000 0x400>; + clocks = <&fabric_clk>; + clock-names = "timer"; + interrupts = ; + status = "disabled"; + }; + + watchdog: watchdog@e0090000 { + compatible = "snps,dw-wdt"; + reg = <0xe0090000 0x1000>; + interrupts = ; + clocks = <&fabric_clk>; + }; + + cpu_ctrl: syscon@e00c0000 { + compatible = "microchip,lan966x-cpu-syscon", "syscon"; + reg = <0xe00c0000 0x350>; + }; + + switch: switch@e00c0000 { + compatible = "microchip,lan9691-switch"; + reg = <0xe00c0000 0x0010000>, + <0xe2010000 0x1410000>; + reg-names = "cpu", "devices"; + interrupt-names = "xtr", "fdma", "ptp"; + interrupts = , + , + ; + resets = <&reset 0>; + reset-names = "switch"; + status = "disabled"; + }; + + clks: clock-controller@e00c00b4 { + compatible = "microchip,lan9691-gck"; + reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>; + clock-names = "cpu", "ddr", "sys"; + }; + + reset: reset-controller@e201000c { + compatible = "microchip,lan9691-switch-reset", + "microchip,lan966x-switch-reset"; + reg = <0xe201000c 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + + gpio: pinctrl@e20100d4 { + compatible = "microchip,lan9691-pinctrl"; + reg = <0xe20100d4 0xd4>, + <0xe2010370 0xa8>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 66>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + mdio0: mdio@e20101a8 { + compatible = "microchip,lan9691-miim", "mscc,ocelot-miim"; + reg = <0xe20101a8 0x24>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&fx100_clk>; + status = "disabled"; + }; + + mdio1: mdio@e20101cc { + compatible = "microchip,lan9691-miim", "mscc,ocelot-miim"; + reg = <0xe20101cc 0x24>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&fx100_clk>; + status = "disabled"; + }; + + sgpio: gpio@e2010230 { + compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio"; + reg = <0xe2010230 0x118>; + clocks = <&fx100_clk>; + resets = <&reset 0>; + reset-names = "switch"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgpio_in: gpio@0 { + compatible = "microchip,lan9691-sgpio-bank", + "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sgpio_out: gpio@1 { + compatible = "microchip,lan9691-sgpio-bank", + "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + }; + }; + + tmon: hwmon@e2020100 { + compatible = "microchip,lan9691-temp", "microchip,sparx5-temp"; + reg = <0xe2020100 0xc>; + clocks = <&fx100_clk>; + #thermal-sensor-cells = <0>; + }; + + serdes: serdes@e3410000 { + compatible = "microchip,lan9691-serdes"; + reg = <0xe3410000 0x150000>; + #phy-cells = <1>; + clocks = <&fabric_clk>; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,gic-400"; + reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */ + <0xe8c12000 0x2000>, /* CPU interface GICC_ */ + <0xe8c14000 0x2000>, /* Virt interface control */ + <0xe8c16000 0x2000>; /* Virt CPU interface */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts new file mode 100644 index 000000000000..4012ea7d07bb --- /dev/null +++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts @@ -0,0 +1,756 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include "lan9691.dtsi" + +/ { + model = "Microchip EV23X71A"; + compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691"; + + aliases { + serial0 = &usart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 60 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c3>; + idle-state = <0x8>; + mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>, + <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>, + <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>; + settle-time-us = <100>; + + i2c_sfp0: i2c@0 { + reg = <0x0>; + }; + + i2c_sfp1: i2c@1 { + reg = <0x1>; + }; + + i2c_sfp2: i2c@2 { + reg = <0x2>; + }; + + i2c_sfp3: i2c@3 { + reg = <0x3>; + }; + + i2c_poe: i2c@7 { + reg = <0x7>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-status { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio 61 GPIO_ACTIVE_LOW>; + }; + + led-sfp1-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp1-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp2-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp2-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp3-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp3-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp4-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp4-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>, + <&sgpio_out 1 3 GPIO_ACTIVE_LOW>; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp0>; + tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>; + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio { + emmc_sd_pins: emmc-sd-pins { + /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ + pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", + "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", + "GPIO_22", "GPIO_23", "GPIO_24"; + function = "emmc_sd"; + }; + + fan_pins: fan-pins { + pins = "GPIO_25", "GPIO_26"; + function = "fan"; + }; + + fc0_pins: fc0-pins { + pins = "GPIO_3", "GPIO_4"; + function = "fc"; + }; + + fc2_pins: fc2-pins { + pins = "GPIO_64", "GPIO_65", "GPIO_66"; + function = "fc"; + }; + + fc3_pins: fc3-pins { + pins = "GPIO_55", "GPIO_56"; + function = "fc"; + }; + + mdio_irq_pins: mdio-irq-pins { + pins = "GPIO_11"; + function = "miim_irq"; + }; + + mdio_pins: mdio-pins { + pins = "GPIO_9", "GPIO_10"; + function = "miim"; + }; + + ptp_ext_pins: ptp-ext-pins { + pins = "GPIO_59"; + function = "ptpsync_5"; + }; + + ptp_out_pins: ptp-out-pins { + pins = "GPIO_58"; + function = "ptpsync_4"; + }; + + sgpio_pins: sgpio-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; + function = "sgpio_a"; + }; + + usb_over_pins: usb-over-pins { + pins = "GPIO_13"; + function = "usb_over_detect"; + }; + + usb_power_pins: usb-power-pins { + pins = "GPIO_1"; + function = "usb_power"; + }; + + usb_rst_pins: usb-rst-pins { + pins = "GPIO_12"; + function = "usb2phy_rst"; + }; + + usb_ulpi_pins: usb-ulpi-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", + "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", + "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; + function = "usb_ulpi"; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&flx2 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&fc3_pins>; + pinctrl-names = "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; +}; + +&mdio0 { + pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>; + status = "okay"; + + phy3: phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy4: phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy5: phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy7: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy8: phy@8 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <8>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy9: phy@9 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <9>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy10: phy@10 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <10>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy11: phy@11 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <11>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy12: phy@12 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <12>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy13: phy@13 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <13>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy14: phy@14 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <14>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy15: phy@15 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <15>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy16: phy@16 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <16>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy17: phy@17 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <17>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy18: phy@18 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <18>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy19: phy@19 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <19>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy20: phy@20 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <20>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy21: phy@21 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <21>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy22: phy@22 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <22>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy23: phy@23 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <23>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy24: phy@24 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <24>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy25: phy@25 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <25>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy26: phy@26 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <26>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy27: phy@27 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <27>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + microchip,sgpio-port-ranges = <0 1>, <6 9>; + status = "okay"; + + gpio@0 { + ngpios = <128>; + }; + gpio@1 { + ngpios = <128>; + }; +}; + +&spi2 { + pinctrl-0 = <&fc2_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&switch { + pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + phy-handle = <&phy4>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + microchip,bandwidth = <1000>; + }; + + port1: port@1 { + reg = <1>; + phy-handle = <&phy5>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + microchip,bandwidth = <1000>; + }; + + port2: port@2 { + reg = <2>; + phy-handle = <&phy6>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + microchip,bandwidth = <1000>; + }; + + port3: port@3 { + reg = <3>; + phy-handle = <&phy7>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + microchip,bandwidth = <1000>; + }; + + port4: port@4 { + reg = <4>; + phy-handle = <&phy8>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + microchip,bandwidth = <1000>; + }; + + port5: port@5 { + reg = <5>; + phy-handle = <&phy9>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + microchip,bandwidth = <1000>; + }; + + port6: port@6 { + reg = <6>; + phy-handle = <&phy10>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + microchip,bandwidth = <1000>; + }; + + port7: port@7 { + reg = <7>; + phy-handle = <&phy11>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + microchip,bandwidth = <1000>; + }; + + port8: port@8 { + reg = <8>; + phy-handle = <&phy12>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + microchip,bandwidth = <1000>; + }; + + port9: port@9 { + reg = <9>; + phy-handle = <&phy13>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + microchip,bandwidth = <1000>; + }; + + port10: port@10 { + reg = <10>; + phy-handle = <&phy14>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + microchip,bandwidth = <1000>; + }; + + port11: port@11 { + reg = <11>; + phy-handle = <&phy15>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + microchip,bandwidth = <1000>; + }; + + port12: port@12 { + reg = <12>; + phy-handle = <&phy16>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + microchip,bandwidth = <1000>; + }; + + port13: port@13 { + reg = <13>; + phy-handle = <&phy17>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + microchip,bandwidth = <1000>; + }; + + port14: port@14 { + reg = <14>; + phy-handle = <&phy18>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + microchip,bandwidth = <1000>; + }; + + port15: port@15 { + reg = <15>; + phy-handle = <&phy19>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + microchip,bandwidth = <1000>; + }; + + port16: port@16 { + reg = <16>; + phy-handle = <&phy20>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + microchip,bandwidth = <1000>; + }; + + port17: port@17 { + reg = <17>; + phy-handle = <&phy21>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + microchip,bandwidth = <1000>; + }; + + port18: port@18 { + reg = <18>; + phy-handle = <&phy22>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + microchip,bandwidth = <1000>; + }; + + port19: port@19 { + reg = <19>; + phy-handle = <&phy23>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + microchip,bandwidth = <1000>; + }; + + port20: port@20 { + reg = <20>; + phy-handle = <&phy24>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + microchip,bandwidth = <1000>; + }; + + port21: port@21 { + reg = <21>; + phy-handle = <&phy25>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + microchip,bandwidth = <1000>; + }; + + port22: port@22 { + reg = <22>; + phy-handle = <&phy26>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + microchip,bandwidth = <1000>; + }; + + port23: port@23 { + reg = <23>; + phy-handle = <&phy27>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + microchip,bandwidth = <1000>; + }; + + port24: port@24 { + reg = <24>; + phys = <&serdes 6>; + phy-mode = "10gbase-r"; + sfp = <&sfp0>; + managed = "in-band-status"; + microchip,bandwidth = <10000>; + microchip,sd-sgpio = <24>; + }; + + port25: port@25 { + reg = <25>; + phys = <&serdes 7>; + phy-mode = "10gbase-r"; + sfp = <&sfp1>; + managed = "in-band-status"; + microchip,bandwidth = <10000>; + microchip,sd-sgpio = <28>; + }; + + port26: port@26 { + reg = <26>; + phys = <&serdes 8>; + phy-mode = "10gbase-r"; + sfp = <&sfp2>; + managed = "in-band-status"; + microchip,bandwidth = <10000>; + microchip,sd-sgpio = <32>; + }; + + port27: port@27 { + reg = <27>; + phys = <&serdes 9>; + phy-mode = "10gbase-r"; + sfp = <&sfp3>; + managed = "in-band-status"; + microchip,bandwidth = <10000>; + microchip,sd-sgpio = <36>; + }; + + port29: port@29 { + reg = <29>; + phy-handle = <&phy3>; + phy-mode = "rgmii-id"; + microchip,bandwidth = <1000>; + }; + }; +}; + +&tmon { + pinctrl-0 = <&fan_pins>; + pinctrl-names = "default"; +}; + +&usart0 { + pinctrl-0 = <&fc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb { + pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 24133528b8e9..c781190b42c5 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -145,7 +145,6 @@ watchdog0: watchdog@801c { reg = <0x801c 0x4>; status = "disabled"; clocks = <&refclk>; - syscon = <&gcr>; }; watchdog1: watchdog@901c { @@ -154,7 +153,6 @@ watchdog1: watchdog@901c { reg = <0x901c 0x4>; status = "disabled"; clocks = <&refclk>; - syscon = <&gcr>; }; watchdog2: watchdog@a01c { @@ -163,7 +161,6 @@ watchdog2: watchdog@a01c { reg = <0xa01c 0x4>; status = "disabled"; clocks = <&refclk>; - syscon = <&gcr>; }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index b139cbd14442..72c0cb5efa47 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -14,6 +14,7 @@ DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@ DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@ DTC_FLAGS_tegra234-p3768-0000+p3767-0005 := -@ DTC_FLAGS_tegra264-p3971-0089+p3834-0008 := -@ +DTC_FLAGS_tegra264-p4071-0000+p3834-0008 := -@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb @@ -35,3 +36,4 @@ dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3740-0002+p3701-0008.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0005.dtb dtb-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra264-p3971-0089+p3834-0008.dtb +dtb-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra264-p4071-0000+p3834-0008.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index b88428aa831e..f0b8c2c80aa5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1892,6 +1892,18 @@ interrupt-controller@702f9000 { }; }; + spi@70410000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + }; + clk32k_in: clock-32k { compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 137aa8375257..5f5e5370d709 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -309,9 +309,7 @@ tsec@54500000 { reg = <0x0 0x54500000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_TSECB>; - clock-names = "tsec"; resets = <&tegra_car 206>; - reset-names = "tsec"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi index 58bf55c0e414..c10d041c183b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi @@ -9,6 +9,7 @@ aliases { mmc0 = "/bus@0/mmc@3460000"; mmc1 = "/bus@0/mmc@3400000"; rtc0 = "/bpmp/i2c/pmic@3c"; + rtc1 = "/bus@0/rtc@c2a0000"; }; bus@0 { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi index ab391a71c3d3..9e9e80d57623 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi @@ -8,6 +8,7 @@ / { aliases { mmc0 = "/bus@0/mmc@3400000"; rtc0 = "/bpmp/i2c/pmic@3c"; + rtc1 = "/bus@0/rtc@c2a0000"; }; bus@0 { diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 850c473235e3..04a95b6658ca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3621,7 +3621,7 @@ ethernet@6800000 { snps,axi-config = <&mgbe0_axi_setup>; mgbe0_axi_setup: stmmac-axi-config { - snps,blen = <256 128 64 32>; + snps,blen = <256 128 64 32 0 0 0>; snps,rd_osr_lmt = <63>; snps,wr_osr_lmt = <63>; }; @@ -3663,7 +3663,7 @@ ethernet@6900000 { snps,axi-config = <&mgbe1_axi_setup>; mgbe1_axi_setup: stmmac-axi-config { - snps,blen = <256 128 64 32>; + snps,blen = <256 128 64 32 0 0 0>; snps,rd_osr_lmt = <63>; snps,wr_osr_lmt = <63>; }; @@ -3705,7 +3705,7 @@ ethernet@6a00000 { snps,axi-config = <&mgbe2_axi_setup>; mgbe2_axi_setup: stmmac-axi-config { - snps,blen = <256 128 64 32>; + snps,blen = <256 128 64 32 0 0 0>; snps,rd_osr_lmt = <63>; snps,wr_osr_lmt = <63>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts new file mode 100644 index 000000000000..df6555b6d0e0 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/dts-v1/; + +// module files must be included first +#include "tegra264-p3834-0008.dtsi" +#include "tegra264-p4071-0000+p3834.dtsi" + +/ { + model = "NVIDIA Jetson AGX Thor Developer Kit"; + compatible = "nvidia,p4071-0000+p3834-0008", "nvidia,p3834-0008", "nvidia,tegra264"; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi new file mode 100644 index 000000000000..45f8df9bbfd6 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + +/ { + aliases { + serial0 = &{/bus@0/serial@c4e0000}; + serial1 = &{/bus@0/serial@c5a0000}; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 7644a41d5f72..06d8357bdf52 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -32,7 +32,7 @@ bus@0 { #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>; + ranges = <0x00 0x00000000 0x00 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */ misc@100000 { compatible = "nvidia,tegra234-misc"; @@ -3277,6 +3277,50 @@ rtc: rtc@c2c0000 { status = "disabled"; }; + gpio_main: gpio@c300000 { + compatible = "nvidia,tegra264-gpio"; + reg = <0x00 0x0c300000 0x0 0x4000>, + <0x00 0x0c310000 0x0 0x4000>; + reg-names = "security", "gpio"; + wakeup-parent = <&pmc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + serial@c4e0000 { compatible = "nvidia,tegra264-utc"; reg = <0x0 0x0c4e0000 0x0 0x8000>, @@ -3347,6 +3391,22 @@ pmc: pmc@c800000 { #interrupt-cells = <2>; interrupt-controller; }; + + gpio_aon: gpio@cf00000 { + compatible = "nvidia,tegra264-gpio-aon"; + reg = <0x0 0x0cf00000 0x0 0x10000>, + <0x0 0x0cf10000 0x0 0x1000>; + reg-names = "security", "gpio"; + wakeup-parent = <&pmc>; + interrupts = , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; /* TOP_MMIO */ @@ -3356,9 +3416,10 @@ bus@8100000000 { #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */ - <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */ - <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */ + ranges = <0x00 0x00000000 0x81 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x20000000>, /* non-prefetchable memory (32-bit, 512 MiB) */ + <0x00 0x40000000 0x81 0x40000000 0x00 0x20000000>, /* MMIO (512 MiB) */ + <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ smmu1: iommu@5000000 { compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; @@ -3402,23 +3463,23 @@ cmdqv2: cmdqv@6200000 { mc: memory-controller@8020000 { compatible = "nvidia,tegra264-mc"; - reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */ - <0x00 0x8040000 0x0 0x20000>, /* MC 0 */ - <0x00 0x8060000 0x0 0x20000>, /* MC 1 */ - <0x00 0x8080000 0x0 0x20000>, /* MC 2 */ - <0x00 0x80a0000 0x0 0x20000>, /* MC 3 */ - <0x00 0x80c0000 0x0 0x20000>, /* MC 4 */ - <0x00 0x80e0000 0x0 0x20000>, /* MC 5 */ - <0x00 0x8100000 0x0 0x20000>, /* MC 6 */ - <0x00 0x8120000 0x0 0x20000>, /* MC 7 */ - <0x00 0x8140000 0x0 0x20000>, /* MC 8 */ - <0x00 0x8160000 0x0 0x20000>, /* MC 9 */ - <0x00 0x8180000 0x0 0x20000>, /* MC 10 */ - <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */ - <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */ - <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */ - <0x00 0x8200000 0x0 0x20000>, /* MC 14 */ - <0x00 0x8220000 0x0 0x20000>; /* MC 15 */ + reg = <0x000 0x8020000 0x0 0x20000>, /* MC broadcast */ + <0x000 0x8040000 0x0 0x20000>, /* MC 0 */ + <0x000 0x8060000 0x0 0x20000>, /* MC 1 */ + <0x000 0x8080000 0x0 0x20000>, /* MC 2 */ + <0x000 0x80a0000 0x0 0x20000>, /* MC 3 */ + <0x000 0x80c0000 0x0 0x20000>, /* MC 4 */ + <0x000 0x80e0000 0x0 0x20000>, /* MC 5 */ + <0x000 0x8100000 0x0 0x20000>, /* MC 6 */ + <0x000 0x8120000 0x0 0x20000>, /* MC 7 */ + <0x000 0x8140000 0x0 0x20000>, /* MC 8 */ + <0x000 0x8160000 0x0 0x20000>, /* MC 9 */ + <0x000 0x8180000 0x0 0x20000>, /* MC 10 */ + <0x000 0x81a0000 0x0 0x20000>, /* MC 11 */ + <0x000 0x81c0000 0x0 0x20000>, /* MC 12 */ + <0x000 0x81e0000 0x0 0x20000>, /* MC 13 */ + <0x000 0x8200000 0x0 0x20000>, /* MC 14 */ + <0x000 0x8220000 0x0 0x20000>; /* MC 15 */ reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", @@ -3437,12 +3498,12 @@ mc: memory-controller@8020000 { #size-cells = <2>; /* limit the DMA range for memory clients to [39:0] */ - dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + dma-ranges = <0x000 0x0 0x000 0x0 0x100 0x0>; emc: external-memory-controller@8800000 { compatible = "nvidia,tegra264-emc"; - reg = <0x00 0x8800000 0x0 0x20000>, - <0x00 0x8890000 0x0 0x20000>; + reg = <0x000 0x8800000 0x0 0x20000>, + <0x000 0x8890000 0x0 0x20000>; interrupts = ; clocks = <&bpmp TEGRA264_CLK_EMC>, <&bpmp TEGRA264_CLK_DBB_UPHY0>; @@ -3493,6 +3554,38 @@ cmdqv4: cmdqv@b200000 { status = "disabled"; }; + pci@c000000 { + compatible = "nvidia,tegra264-pcie"; + reg = <0xd0 0xb0000000 0x0 0x10000000>, + <0x00 0x0c000000 0x0 0x00004000>, + <0x00 0x0c004000 0x0 0x00001000>, + <0x00 0x0c005000 0x0 0x00001000>; + reg-names = "ecam", "xal", "xtl", "xtl-pri"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0x00>; + #interrupt-cells = <0x1>; + + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 IRQ_TYPE_LEVEL_HIGH>; + + iommu-map = <0x0 &smmu2 0x10000 0x10000>; + msi-map = <0x0 &its 0x210000 0x10000>; + dma-coherent; + + ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */ + <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */ + <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ + bus-range = <0x0 0xff>; + + nvidia,bpmp = <&bpmp 0>; + status = "disabled"; + }; + i2c14: i2c@c410000 { compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c410000 0x0 0x10000>; @@ -3720,7 +3813,7 @@ bus@8800000000 { #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; + ranges = <0x00 0x00000000 0x88 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */ smmu3: iommu@6000000 { compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; @@ -3765,8 +3858,197 @@ bus@a800000000 { #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */ - <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */ + ranges = <0x00 0x00000000 0xa8 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */ + <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ + + gpio_uphy: gpio@8300000 { + compatible = "nvidia,tegra264-gpio-uphy"; + reg = <0x00 0x08300000 0x0 0x2000>, + <0x00 0x08310000 0x0 0x2000>; + reg-names = "security", "gpio"; + wakeup-parent = <&pmc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pci@8400000 { + compatible = "nvidia,tegra264-pcie"; + reg = <0xa8 0xb0000000 0x0 0x10000000>, + <0x00 0x08400000 0x0 0x00004000>, + <0x00 0x08404000 0x0 0x00001000>, + <0x00 0x08405000 0x0 0x00001000>, + <0x00 0x08410000 0x0 0x00010000>; + reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0x01>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map = <0x0 &smmu1 0x10000 0x10000>; + msi-map = <0x0 &its 0x110000 0x10000>; + dma-coherent; + + ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>, /* I/O */ + <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-prefetchable memory */ + <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; + + nvidia,bpmp = <&bpmp 1>; + status = "disabled"; + }; + + pci@8420000 { + compatible = "nvidia,tegra264-pcie"; + reg = <0xb0 0xb0000000 0x0 0x10000000>, + <0x00 0x08420000 0x0 0x00004000>, + <0x00 0x08424000 0x0 0x00001000>, + <0x00 0x08425000 0x0 0x00001000>, + <0x00 0x08430000 0x0 0x00010000>; + reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0x02>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 917 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 918 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 919 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 920 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map = <0x0 &smmu1 0x20000 0x10000>; + msi-map = <0x0 &its 0x120000 0x10000>; + dma-coherent; + + ranges = <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>, /* I/O */ + <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-prefetchable memory */ + <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; + + nvidia,bpmp = <&bpmp 2>; + status = "disabled"; + }; + + pci@8440000 { + compatible = "nvidia,tegra264-pcie"; + reg = <0xb8 0xb0000000 0x0 0x10000000>, + <0x00 0x08440000 0x0 0x00004000>, + <0x00 0x08444000 0x0 0x00001000>, + <0x00 0x08445000 0x0 0x00001000>, + <0x00 0x08450000 0x0 0x00010000>; + reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0x03>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 926 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 927 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 928 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 929 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map = <0x0 &smmu1 0x30000 0x10000>; + msi-map = <0x0 &its 0x130000 0x10000>; + dma-coherent; + + ranges = <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>, /* I/O */ + <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-prefetchable memory */ + <0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; + + nvidia,bpmp = <&bpmp 3>; + status = "disabled"; + }; + + pci@8460000 { + compatible = "nvidia,tegra264-pcie"; + reg = <0xc0 0xb0000000 0x0 0x10000000>, + <0x00 0x08460000 0x0 0x00004000>, + <0x00 0x08464000 0x0 0x00001000>, + <0x00 0x08465000 0x0 0x00001000>, + <0x00 0x08470000 0x0 0x00010000>; + reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0x04>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 935 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 936 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 937 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 938 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map = <0x0 &smmu1 0x40000 0x10000>; + msi-map = <0x0 &its 0x140000 0x10000>; + dma-coherent; + + ranges = <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>, /* I/O */ + <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-prefetchable memory */ + <0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; + + nvidia,bpmp = <&bpmp 4>; + status = "disabled"; + }; + + pci@8480000 { + compatible = "nvidia,tegra264-pcie"; + reg = <0xc8 0xb0000000 0x0 0x10000000>, + <0x00 0x08480000 0x0 0x00004000>, + <0x00 0x08484000 0x0 0x00001000>, + <0x00 0x08485000 0x0 0x00001000>, + <0x00 0x08490000 0x0 0x00010000>; + reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0x05>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 944 IRQ_TYPE_LEVEL_HIGH>, /* INTA */ + <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 945 IRQ_TYPE_LEVEL_HIGH>, /* INTB */ + <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 946 IRQ_TYPE_LEVEL_HIGH>, /* INTC */ + <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 947 IRQ_TYPE_LEVEL_HIGH>; /* INTD */ + + iommu-map = <0x0 &smmu1 0x50000 0x10000>; + msi-map = <0x0 &its 0x150000 0x10000>; + dma-coherent; + + ranges = <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>, /* I/O */ + <0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-prefetchable memory */ + <0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */ + bus-range = <0x00 0xff>; + + nvidia,bpmp = <&bpmp 5>; + status = "disabled"; + }; }; cpus { diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f80b5d9cf1e8..4ba8e7306419 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -12,10 +12,19 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-schneider-hmibsc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb + +hamoa-iot-evk-el2-dtbs := hamoa-iot-evk.dtb x1-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += hamoa-lenovo-ideacentre-mini-01q8x10.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5210-rdp504.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb @@ -25,8 +34,8 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb ipq9574-rdp418-emmc.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb ipq9574-rdp433-emmc.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb @@ -43,8 +52,21 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb +lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb + +monaco-evk-camera-imx577-dtbs := monaco-evk.dtb monaco-evk-camera-imx577.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-camera-imx577.dtb + +monaco-evk-el2-dtbs := monaco-evk.dtb monaco-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-el2.dtb +monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb @@ -61,6 +83,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-surnia.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-coreprimeltevzw.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gprimeltecan.dtb @@ -75,11 +98,14 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-rossa.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-wiko-chuppito.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt86518.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt86528.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-riva.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-rolex.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8917-xiaomi-tiare.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8929-wingtech-wt82918hd.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8937-xiaomi-land.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-asus-z00t.dtb @@ -130,6 +156,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb +dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb @@ -137,6 +164,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb + +qcs615-ride-el2-dtbs := qcs615-ride.dtb talos-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb @@ -145,8 +176,13 @@ qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2 dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-minipc-g1iot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb + +qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb @@ -178,6 +214,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb sc7180-acer-aspire1-el2-dtbs := sc7180-acer-aspire1.dtb sc7180-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb sc7180-acer-aspire1-el2.dtb +sc7180-ecs-liva-qc710-el2-dtbs := sc7180-ecs-liva-qc710.dtb sc7180-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sc7180-ecs-liva-qc710.dtb sc7180-ecs-liva-qc710-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb @@ -294,8 +332,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-ginkgo.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-ginkgo.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-willow.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb @@ -327,14 +366,19 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-samsung-r0q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb +sm8550-hdk-display-card-dtbs := sm8550-hdk.dtb sm8550-hdk-display-card.dtbo +sm8550-hdk-display-card-rear-camera-card-dtbs := sm8550-hdk.dtb sm8550-hdk-display-card.dtbo sm8550-hdk-rear-camera-card.dtbo sm8550-hdk-rear-camera-card-dtbs := sm8550-hdk.dtb sm8550-hdk-rear-camera-card.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card-rear-camera-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-display-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk-rear-camera-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-ayaneo-pocket-s2.dtb sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo sm8650-hdk-display-card-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo sm8650-hdk-rear-camera-card.dtbo @@ -348,6 +392,15 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-evk.dtb +talos-evk-usb1-peripheral-dtbs := talos-evk.dtb talos-evk-usb1-peripheral.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-usb1-peripheral.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtbo +talos-evk-camera-imx577-dtbs := talos-evk.dtb talos-evk-camera-imx577.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtb +talos-evk-lvds-auo,g133han01-dtbs := \ + talos-evk.dtb talos-evk-lvds-auo,g133han01.dtbo +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-lvds-auo,g133han01.dtb x1e001de-devkit-el2-dtbs := x1e001de-devkit.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb x1e001de-devkit-el2.dtb x1e78100-lenovo-thinkpad-t14s-el2-dtbs := x1e78100-lenovo-thinkpad-t14s.dtb x1-el2.dtbo @@ -374,12 +427,16 @@ x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.d dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb x1e80100-medion-sprchrgd-14-s1-el2-dtbs := x1e80100-medion-sprchrgd-14-s1.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-medion-sprchrgd-14-s1.dtb x1e80100-medion-sprchrgd-14-s1-el2.dtb +x1e80100-microsoft-denali-oled-el2-dtbs := x1e80100-microsoft-denali-oled.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-denali-oled.dtb x1e80100-microsoft-denali-oled-el2.dtb x1e80100-microsoft-romulus13-el2-dtbs := x1e80100-microsoft-romulus13.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus15.dtb x1e80100-microsoft-romulus15-el2.dtb x1e80100-qcp-el2-dtbs := x1e80100-qcp.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb x1e80100-qcp-el2.dtb +x1p42100-asus-vivobook-s15-el2-dtbs := x1p42100-asus-vivobook-s15.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-vivobook-s15.dtb x1p42100-asus-vivobook-s15-el2.dtb x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb x1p42100-asus-zenbook-a14-lcd-el2-dtbs := x1p42100-asus-zenbook-a14-lcd.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 893cb0689013..8a7337239b1e 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -2834,9 +2834,9 @@ camera_crit: camera-crit { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 9fa70ff6887b..47b4568e4039 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -6,1133 +6,9 @@ /dts-v1/; #include "msm8996.dtsi" -#include "pm8994.dtsi" -#include "pmi8994.dtsi" -#include -#include -#include -#include -#include -#include -#include - -/* - * GPIO name legend: proper name = the GPIO line is used as GPIO - * NC = not connected (pin out but not routed from the chip to - * anything the board) - * "[PER]" = pin is muxed for [peripheral] (not GPIO) - * LSEC = Low Speed External Connector - * P HSEC = Primary High Speed External Connector - * S HSEC = Secondary High Speed External Connector - * J14 = Camera Connector - * TP = Test Points - * - * Line names are taken from the schematic "DragonBoard 820c", - * drawing no: LM25-P2751-1 - * - * For the lines routed to the external connectors the - * lines are named after the 96Boards CE Specification 1.0, - * Appendix "Expansion Connector Signal Description". - * - * When the 96Board naming of a line and the schematic name of - * the same line are in conflict, the 96Board specification - * takes precedence, which means that the external UART on the - * LSEC is named UART0 while the schematic and SoC names this - * UART3. This is only for the informational lines i.e. "[FOO]", - * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only - * ones actually used for GPIO. - */ +#include "apq8096-db820c.dtsi" / { model = "Qualcomm Technologies, Inc. DB820c"; compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096"; - - aliases { - serial0 = &blsp2_uart2; - serial1 = &blsp2_uart3; - serial2 = &blsp1_uart2; - i2c0 = &blsp1_i2c3; - i2c1 = &blsp2_i2c1; - i2c2 = &blsp2_i2c1; - spi0 = &blsp1_spi1; - spi1 = &blsp2_spi6; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - div1_mclk: divclk1 { - compatible = "gpio-gate-clock"; - pinctrl-0 = <&audio_mclk>; - pinctrl-names = "default"; - clocks = <&rpmcc RPM_SMD_DIV_CLK1>; - #clock-cells = <0>; - enable-gpios = <&pm8994_gpios 15 0>; - }; - - divclk4: divclk4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "divclk4"; - - pinctrl-names = "default"; - pinctrl-0 = <&divclk4_pin_a>; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-names = "default"; - pinctrl-0 = <&volume_up_gpio>; - - button { - label = "Volume Up"; - linux,code = ; - gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; - }; - }; - - usb2_id: usb2-id { - compatible = "linux,extcon-usb-gpio"; - id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_vbus_det_gpio>; - }; - - usb3_id: usb3-id { - compatible = "linux,extcon-usb-gpio"; - id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb3_vbus_det_gpio>; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - wlan_en: wlan-en-1-8v { - pinctrl-names = "default"; - pinctrl-0 = <&wlan_en_gpios>; - compatible = "regulator-fixed"; - regulator-name = "wlan-en-regulator"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8994_gpios 8 0>; - - /* WLAN card specific delay */ - startup-delay-us = <70000>; - enable-active-high; - }; -}; - -&blsp1_i2c3 { - /* On Low speed expansion: LS-I2C0 */ - status = "okay"; -}; - -&blsp1_spi1 { - /* On Low speed expansion */ - status = "okay"; -}; - -&blsp1_uart2 { - label = "BT-UART"; - status = "okay"; - - bluetooth { - compatible = "qcom,qca6174-bt"; - - /* bt_disable_n gpio */ - enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; - - clocks = <&divclk4>; - }; -}; - -&adsp_pil { - status = "okay"; - firmware-name = "qcom/apq8096/adsp.mbn"; -}; - -&blsp2_i2c1 { - /* On High speed expansion: HS-I2C2 */ - status = "okay"; -}; - -&blsp2_i2c1 { - /* On Low speed expansion: LS-I2C1 */ - status = "okay"; -}; - -&blsp2_spi6 { - /* On High speed expansion */ - status = "okay"; -}; - -&blsp2_uart2 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart2_2pins_default>; - pinctrl-1 = <&blsp2_uart2_2pins_sleep>; -}; - -&blsp2_uart3 { - label = "LS-UART0"; - status = "disabled"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp2_uart3_4pins_default>; - pinctrl-1 = <&blsp2_uart3_4pins_sleep>; -}; - -&camss { - vdda-supply = <&vreg_l2a_1p25>; -}; - -&gpu { - status = "okay"; -}; - -&gpu_zap_shader { - firmware-name = "qcom/apq8096/a530_zap.mbn"; -}; - -&hsusb_phy1 { - status = "okay"; - - vdd-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&hsusb_phy2 { - status = "okay"; - - vdd-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; - vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; -}; - -&mdp { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_hdmi { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; - pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; - - core-vdda-supply = <&vreg_l12a_1p8>; - core-vcc-supply = <&vreg_s4a_1p8>; -}; - -&mdss_hdmi_phy { - status = "okay"; - - vddio-supply = <&vreg_l12a_1p8>; - vcca-supply = <&vreg_l28a_0p925>; - #phy-cells = <0>; -}; - -&mmcc { - vdd-gfx-supply = <&vdd_gfx>; -}; - -&mss_pil { - status = "okay"; - pll-supply = <&vreg_l12a_1p8>; - firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn"; -}; - -&pm8994_resin { - status = "okay"; - linux,code = ; -}; - -&tlmm { - gpio-line-names = - "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ - "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ - "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */ - "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */ - "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */ - "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */ - "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */ - "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */ - "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */ - "TP93", /* GPIO_9 */ - "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */ - "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */ - "NC", /* GPIO_12 */ - "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ - "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ - "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ - "TP99", /* GPIO_16 */ - "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ - "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ - "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ - "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ - "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ - "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ - "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */ - "GPIO-D", /* GPIO_24, LSEC pin 26 */ - "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */ - "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */ - "BLSP6_I2C_SDA", /* GPIO_27 */ - "BLSP6_I2C_SCL", /* GPIO_28 */ - "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */ - "GPIO30", /* GPIO_30, S HSEC pin 4 */ - "HDMI_CEC", /* GPIO_31 */ - "HDMI_DDC_CLOCK", /* GPIO_32 */ - "HDMI_DDC_DATA", /* GPIO_33 */ - "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ - "PCIE0_RST_N", /* GPIO_35 */ - "PCIE0_CLKREQ_N", /* GPIO_36 */ - "PCIE0_WAKE", /* GPIO_37 */ - "SD_CARD_DET_N", /* GPIO_38 */ - "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ - "W_DISABLE_N", /* GPIO_40 */ - "[BLSP9_UART_TX]", /* GPIO_41 */ - "[BLSP9_UART_RX]", /* GPIO_42 */ - "[BLSP2_UART_CTS_N]", /* GPIO_43 */ - "[BLSP2_UART_RFR_N]", /* GPIO_44 */ - "[BLSP3_UART_TX]", /* GPIO_45 */ - "[BLSP3_UART_RX]", /* GPIO_46 */ - "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */ - "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */ - "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */ - "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */ - "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */ - "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */ - "[CODEC_INT1_N]", /* GPIO_53 */ - "[CODEC_INT2_N]", /* GPIO_54 */ - "[BLSP7_I2C_SDA]", /* GPIO_55 */ - "[BLSP7_I2C_SCL]", /* GPIO_56 */ - "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ - "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */ - "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */ - "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */ - "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */ - "GPIO-E", /* GPIO_62, LSEC pin 27 */ - "TP87", /* GPIO_63 */ - "[CODEC_RST_N]", /* GPIO_64 */ - "[PCM1_CLK]", /* GPIO_65 */ - "[PCM1_SYNC]", /* GPIO_66 */ - "[PCM1_DIN]", /* GPIO_67 */ - "[PCM1_DOUT]", /* GPIO_68 */ - "AUDIO_REF_CLK", /* GPIO_69 */ - "SLIMBUS_CLK", /* GPIO_70 */ - "SLIMBUS_DATA0", /* GPIO_71 */ - "SLIMBUS_DATA1", /* GPIO_72 */ - "NC", /* GPIO_73 */ - "NC", /* GPIO_74 */ - "NC", /* GPIO_75 */ - "NC", /* GPIO_76 */ - "TP94", /* GPIO_77 */ - "NC", /* GPIO_78 */ - "TP95", /* GPIO_79 */ - "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */ - "TP88", /* GPIO_81 */ - "TP89", /* GPIO_82 */ - "TP90", /* GPIO_83 */ - "TP91", /* GPIO_84 */ - "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ - "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ - "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ - "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */ - "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ - "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ - "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ - "NC", /* GPIO_92 */ - "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ - "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ - "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ - "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ - "NC", /* GPIO_97 */ - "CAM1_STANDBY_N", /* GPIO_98 */ - "NC", /* GPIO_99 */ - "NC", /* GPIO_100 */ - "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ - "BOOT_CONFIG1", /* GPIO_102 */ - "USB_HUB_RESET", /* GPIO_103 */ - "CAM1_RST_N", /* GPIO_104 */ - "NC", /* GPIO_105 */ - "NC", /* GPIO_106 */ - "NC", /* GPIO_107 */ - "NC", /* GPIO_108 */ - "NC", /* GPIO_109 */ - "NC", /* GPIO_110 */ - "NC", /* GPIO_111 */ - "NC", /* GPIO_112 */ - "PMI8994_BUA", /* GPIO_113 */ - "PCIE2_RST_N", /* GPIO_114 */ - "PCIE2_CLKREQ_N", /* GPIO_115 */ - "PCIE2_WAKE", /* GPIO_116 */ - "SSC_IRQ_0", /* GPIO_117 */ - "SSC_IRQ_1", /* GPIO_118 */ - "SSC_IRQ_2", /* GPIO_119 */ - "NC", /* GPIO_120 */ - "GPIO121", /* GPIO_121, S HSEC pin 2 */ - "NC", /* GPIO_122 */ - "SSC_IRQ_6", /* GPIO_123 */ - "SSC_IRQ_7", /* GPIO_124 */ - "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */ - "BOOT_CONFIG5", /* GPIO_126 */ - "NC", /* GPIO_127 */ - "NC", /* GPIO_128 */ - "BOOT_CONFIG7", /* GPIO_129 */ - "PCIE1_RST_N", /* GPIO_130 */ - "PCIE1_CLKREQ_N", /* GPIO_131 */ - "PCIE1_WAKE", /* GPIO_132 */ - "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */ - "NC", /* GPIO_134 */ - "NC", /* GPIO_135 */ - "BOOT_CONFIG8", /* GPIO_136 */ - "NC", /* GPIO_137 */ - "NC", /* GPIO_138 */ - "GPS_SSBI2", /* GPIO_139 */ - "GPS_SSBI1", /* GPIO_140 */ - "NC", /* GPIO_141 */ - "NC", /* GPIO_142 */ - "NC", /* GPIO_143 */ - "BOOT_CONFIG6", /* GPIO_144 */ - "NC", /* GPIO_145 */ - "NC", /* GPIO_146 */ - "NC", /* GPIO_147 */ - "NC", /* GPIO_148 */ - "NC"; /* GPIO_149 */ - - sdc2_cd_on: sdc2-cd-on-state { - pins = "gpio38"; - function = "gpio"; - bias-pull-up; - drive-strength = <16>; - }; - - sdc2_cd_off: sdc2-cd-off-state { - pins = "gpio38"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; - - hdmi_hpd_active: hdmi-hpd-active-state { - pins = "gpio34"; - function = "hdmi_hot"; - bias-pull-down; - drive-strength = <16>; - }; - - hdmi_hpd_suspend: hdmi-hpd-suspend-state { - pins = "gpio34"; - function = "hdmi_hot"; - bias-pull-down; - drive-strength = <2>; - }; - - hdmi_ddc_active: hdmi-ddc-active-state { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - drive-strength = <2>; - bias-pull-up; - }; - - hdmi_ddc_suspend: hdmi-ddc-suspend-state { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - drive-strength = <2>; - bias-pull-down; - }; -}; - -&pcie0 { - status = "okay"; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&wlan_en>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie1 { - status = "okay"; - perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie2 { - status = "okay"; - perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; - vdda-supply = <&vreg_l28a_0p925>; -}; - -&pcie_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; -}; - -&pm8994_gpios { - gpio-line-names = - "NC", - "KEY_VOLP_N", - "NC", - "BL1_PWM", - "GPIO-F", /* BL0_PWM, LSEC pin 28 */ - "BL1_EN", - "NC", - "WLAN_EN", - "NC", - "NC", - "NC", - "NC", - "NC", - "NC", - "DIVCLK1", - "DIVCLK2", - "DIVCLK3", - "DIVCLK4", - "BT_EN", - "PMIC_SLB", - "PMIC_BUA", - "USB_VBUS_DET"; - - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; - - ls_exp_gpio_f: pm8994-gpio5-state { - pinconf { - pins = "gpio5"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = ; /* 1.8V */ - }; - }; - - bt_en_gpios: bt-en-pios-state { - pinconf { - pins = "gpio19"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = ; /* 1.8V */ - qcom,drive-strength = ; - bias-pull-down; - }; - }; - - wlan_en_gpios: wlan-en-gpios-state { - pinconf { - pins = "gpio8"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - power-source = ; /* 1.8V */ - qcom,drive-strength = ; - bias-pull-down; - }; - }; - - audio_mclk: clk-div1-state { - pinconf { - pins = "gpio15"; - function = "func1"; - power-source = ; /* 1.8V */ - }; - }; - - volume_up_gpio: pm8996-gpio2-state { - pinconf { - pins = "gpio2"; - function = "normal"; - input-enable; - drive-push-pull; - bias-pull-up; - qcom,drive-strength = ; - power-source = ; /* 1.8V */ - }; - }; - - divclk4_pin_a: divclk4-state { - pinconf { - pins = "gpio18"; - function = PMIC_GPIO_FUNC_FUNC2; - - bias-disable; - power-source = ; - }; - }; - - usb3_vbus_det_gpio: pm8996-gpio22-state { - pinconf { - pins = "gpio22"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - qcom,drive-strength = ; - power-source = ; /* 1.8V */ - }; - }; -}; - -&pm8994_mpps { - gpio-line-names = - "VDDPX_BIAS", - "WIFI_LED", - "NC", - "BT_LED", - "PM_MPP05", - "PM_MPP06", - "PM_MPP07", - "NC"; -}; - -&pm8994_spmi_regulators { - qcom,saw-reg = <&saw3>; - vdd_s11-supply = <&vph_pwr>; - - s9 { - qcom,saw-slave; - }; - s10 { - qcom,saw-slave; - }; - s11 { - qcom,saw-leader; - regulator-name = "VDD_APCC"; - regulator-always-on; - regulator-min-microvolt = <980000>; - regulator-max-microvolt = <980000>; - }; -}; - -&pmi8994_gpios { - gpio-line-names = - "NC", - "SPKR_AMP_EN1", - "SPKR_AMP_EN2", - "TP61", - "NC", - "USB2_VBUS_DET", - "NC", - "NC", - "NC", - "NC"; - - usb2_vbus_det_gpio: pmi8996-gpio6-state { - pinconf { - pins = "gpio6"; - function = PMIC_GPIO_FUNC_NORMAL; - input-enable; - bias-pull-down; - qcom,drive-strength = ; - power-source = ; /* 1.8V */ - }; - }; -}; - -&pmi8994_lpg { - qcom,power-source = <1>; - - pinctrl-names = "default"; - pinctrl-0 = <&pmi8994_mpp2_userled4>; - - qcom,dtest = <0 0>, - <0 0>, - <0 0>, - <4 1>; - - status = "okay"; - - led@1 { - reg = <1>; - color = ; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <1>; - - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - - led@2 { - reg = <2>; - color = ; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <0>; - }; - - led@3 { - reg = <3>; - color = ; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <2>; - }; - - led@4 { - reg = <4>; - color = ; - function = LED_FUNCTION_HEARTBEAT; - function-enumerator = <3>; - }; -}; - -&pmi8994_mpps { - pmi8994_mpp2_userled4: mpp2-userled4-state { - pins = "mpp2"; - function = "sink"; - - output-low; - qcom,dtest = <4>; - }; -}; - -&pmi8994_spmi_regulators { - vdd_s2-supply = <&vph_pwr>; - - vdd_gfx: s2 { - regulator-name = "VDD_GFX"; - regulator-min-microvolt = <980000>; - regulator-max-microvolt = <980000>; - }; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - vdd_s5-supply = <&vph_pwr>; - vdd_s6-supply = <&vph_pwr>; - vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; - vdd_l1-supply = <&vreg_s1b_1p025>; - vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; - vdd_l3_l11-supply = <&vreg_s3a_1p3>; - vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; - vdd_l5_l7-supply = <&vreg_s5a_2p15>; - vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; - vdd_l8_l16_l30-supply = <&vph_pwr>; - vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; - vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; - vdd_l14_l15-supply = <&vreg_s5a_2p15>; - vdd_l17_l29-supply = <&vph_pwr_bbyp>; - vdd_l20_l21-supply = <&vph_pwr_bbyp>; - vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_2-supply = <&vreg_s4a_1p8>; - - vreg_s3a_1p3: s3 { - regulator-name = "vreg_s3a_1p3"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - /** - * 1.8v required on LS expansion - * for mezzanine boards - */ - vreg_s4a_1p8: s4 { - regulator-name = "vreg_s4a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - vreg_s5a_2p15: s5 { - regulator-name = "vreg_s5a_2p15"; - regulator-min-microvolt = <2150000>; - regulator-max-microvolt = <2150000>; - }; - vreg_s7a_1p0: s7 { - regulator-name = "vreg_s7a_1p0"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - }; - - vreg_l1a_1p0: l1 { - regulator-name = "vreg_l1a_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l2a_1p25: l2 { - regulator-name = "vreg_l2a_1p25"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - }; - vreg_l3a_0p875: l3 { - regulator-name = "vreg_l3a_0p875"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - }; - vreg_l4a_1p225: l4 { - regulator-name = "vreg_l4a_1p225"; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - vreg_l6a_1p2: l6 { - regulator-name = "vreg_l6a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - vreg_l8a_1p8: l8 { - regulator-name = "vreg_l8a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l9a_1p8: l9 { - regulator-name = "vreg_l9a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l10a_1p8: l10 { - regulator-name = "vreg_l10a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l11a_1p15: l11 { - regulator-name = "vreg_l11a_1p15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - }; - vreg_l12a_1p8: l12 { - regulator-name = "vreg_l12a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l13a_2p95: l13 { - regulator-name = "vreg_l13a_2p95"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - vreg_l14a_1p8: l14 { - regulator-name = "vreg_l14a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l15a_1p8: l15 { - regulator-name = "vreg_l15a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l16a_2p7: l16 { - regulator-name = "vreg_l16a_2p7"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; - vreg_l17a_2p8: l17 { - regulator-name = "vreg_l17a_2p8"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - vreg_l18a_2p85: l18 { - regulator-name = "vreg_l18a_2p85"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2900000>; - }; - vreg_l19a_2p8: l19 { - regulator-name = "vreg_l19a_2p8"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - vreg_l20a_2p95: l20 { - regulator-name = "vreg_l20a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - vreg_l21a_2p95: l21 { - regulator-name = "vreg_l21a_2p95"; - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - vreg_l22a_3p0: l22 { - regulator-name = "vreg_l22a_3p0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - vreg_l23a_2p8: l23 { - regulator-name = "vreg_l23a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l24a_3p075: l24 { - regulator-name = "vreg_l24a_3p075"; - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - vreg_l25a_1p2: l25 { - regulator-name = "vreg_l25a_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-allow-set-load; - }; - vreg_l26a_0p8: l27 { - regulator-name = "vreg_l26a_0p8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - vreg_l28a_0p925: l28 { - regulator-name = "vreg_l28a_0p925"; - regulator-min-microvolt = <925000>; - regulator-max-microvolt = <925000>; - regulator-allow-set-load; - }; - vreg_l29a_2p8: l29 { - regulator-name = "vreg_l29a_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - vreg_l30a_1p8: l30 { - regulator-name = "vreg_l30a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - vreg_l32a_1p8: l32 { - regulator-name = "vreg_l32a_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vreg_lvs1a_1p8: lvs1 { - regulator-name = "vreg_lvs1a_1p8"; - }; - - vreg_lvs2a_1p8: lvs2 { - regulator-name = "vreg_lvs2a_1p8"; - }; - }; - - regulators-1 { - compatible = "qcom,rpm-pmi8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_bst_byp-supply = <&vph_pwr>; - - vph_pwr_bbyp: boost-bypass { - regulator-name = "vph_pwr_bbyp"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vreg_s1b_1p025: s1 { - regulator-name = "vreg_s1b_1p025"; - regulator-min-microvolt = <1025000>; - regulator-max-microvolt = <1025000>; - }; - }; -}; - -&sdhc2 { - /* External SD card */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>; - cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vreg_l21a_2p95>; - vqmmc-supply = <&vreg_l13a_2p95>; - status = "okay"; -}; - -&q6asmdai { - dai@0 { - reg = ; - }; - - dai@1 { - reg = ; - }; - - dai@2 { - reg = ; - }; -}; - -&slim_msm { - status = "okay"; - - slim@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - - tasha_ifd: tas-ifd@0,0 { - compatible = "slim217,1a0"; - reg = <0 0>; - }; - - wcd9335: codec@1,0 { - compatible = "slim217,1a0"; - reg = <1 0>; - - clock-names = "mclk", "slimbus"; - clocks = <&div1_mclk>, - <&rpmcc RPM_SMD_BB_CLK1>; - interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, - <53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1", "intr2"; - interrupt-controller; - #interrupt-cells = <1>; - - pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; - pinctrl-names = "default"; - - reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; - slim-ifc-dev = <&tasha_ifd>; - - #sound-dai-cells = <1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - }; - }; -}; - -&sound { - compatible = "qcom,apq8096-sndcard"; - model = "DB820c"; - audio-routing = "RX_BIAS", "MCLK"; - - mm1-dai-link { - link-name = "MultiMedia1"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; - }; - }; - - mm2-dai-link { - link-name = "MultiMedia2"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; - }; - }; - - mm3-dai-link { - link-name = "MultiMedia3"; - cpu { - sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; - }; - }; - - hdmi-dai-link { - link-name = "HDMI"; - cpu { - sound-dai = <&q6afedai HDMI_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&mdss_hdmi 0>; - }; - }; - - slim-dai-link { - link-name = "SLIM Playback"; - cpu { - sound-dai = <&q6afedai SLIMBUS_6_RX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9335 AIF4_PB>; - }; - }; - - slimcap-dai-link { - link-name = "SLIM Capture"; - cpu { - sound-dai = <&q6afedai SLIMBUS_0_TX>; - }; - - platform { - sound-dai = <&q6routing>; - }; - - codec { - sound-dai = <&wcd9335 AIF1_CAP>; - }; - }; -}; - -&ufsphy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; -}; - -&ufshc { - status = "okay"; - - vcc-supply = <&vreg_l20a_2p95>; - vccq-supply = <&vreg_l25a_1p2>; - vccq2-supply = <&vreg_s4a_1p8>; - vdd-hba-supply = <&vreg_l25a_1p2>; - - vcc-max-microamp = <600000>; - vccq-max-microamp = <450000>; - vccq2-max-microamp = <450000>; -}; - -&usb2 { - status = "okay"; - extcon = <&usb2_id>; -}; - -&usb2_dwc3 { - extcon = <&usb2_id>; - dr_mode = "otg"; - maximum-speed = "high-speed"; -}; - -&usb3 { - status = "okay"; - extcon = <&usb3_id>; -}; - -&usb3_dwc3 { - extcon = <&usb3_id>; - dr_mode = "otg"; -}; - -&usb3phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l28a_0p925>; - vdda-pll-supply = <&vreg_l12a_1p8>; -}; - -&venus { - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi new file mode 100644 index 000000000000..0c076852b494 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -0,0 +1,1133 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + */ + + +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include +#include +#include +#include +#include +#include +#include + +/* + * GPIO name legend: proper name = the GPIO line is used as GPIO + * NC = not connected (pin out but not routed from the chip to + * anything the board) + * "[PER]" = pin is muxed for [peripheral] (not GPIO) + * LSEC = Low Speed External Connector + * P HSEC = Primary High Speed External Connector + * S HSEC = Secondary High Speed External Connector + * J14 = Camera Connector + * TP = Test Points + * + * Line names are taken from the schematic "DragonBoard 820c", + * drawing no: LM25-P2751-1 + * + * For the lines routed to the external connectors the + * lines are named after the 96Boards CE Specification 1.0, + * Appendix "Expansion Connector Signal Description". + * + * When the 96Board naming of a line and the schematic name of + * the same line are in conflict, the 96Board specification + * takes precedence, which means that the external UART on the + * LSEC is named UART0 while the schematic and SoC names this + * UART3. This is only for the informational lines i.e. "[FOO]", + * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only + * ones actually used for GPIO. + */ + +/ { + aliases { + serial0 = &blsp2_uart2; + serial1 = &blsp2_uart3; + serial2 = &blsp1_uart2; + i2c0 = &blsp1_i2c3; + i2c1 = &blsp2_i2c1; + i2c2 = &blsp2_i2c1; + spi0 = &blsp1_spi1; + spi1 = &blsp2_spi6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + div1_mclk: divclk1 { + compatible = "gpio-gate-clock"; + pinctrl-0 = <&audio_mclk>; + pinctrl-names = "default"; + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; + #clock-cells = <0>; + enable-gpios = <&pm8994_gpios 15 0>; + }; + + divclk4: divclk4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "divclk4"; + + pinctrl-names = "default"; + pinctrl-0 = <&divclk4_pin_a>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_up_gpio>; + + button { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; + }; + }; + + usb2_id: usb2-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_vbus_det_gpio>; + }; + + usb3_id: usb3-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_det_gpio>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + wlan_en: wlan-en-1-8v { + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_gpios>; + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8994_gpios 8 0>; + + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&blsp1_i2c3 { + /* On Low speed expansion: LS-I2C0 */ + status = "okay"; +}; + +&blsp1_spi1 { + /* On Low speed expansion */ + status = "okay"; +}; + +&blsp1_uart2 { + label = "BT-UART"; + status = "okay"; + + bluetooth { + compatible = "qcom,qca6174-bt"; + + /* bt_disable_n gpio */ + enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; + + clocks = <&divclk4>; + }; +}; + +&adsp_pil { + status = "okay"; + firmware-name = "qcom/apq8096/adsp.mbn"; +}; + +&blsp2_i2c1 { + /* On High speed expansion: HS-I2C2 */ + status = "okay"; +}; + +&blsp2_i2c1 { + /* On Low speed expansion: LS-I2C1 */ + status = "okay"; +}; + +&blsp2_spi6 { + /* On High speed expansion */ + status = "okay"; +}; + +&blsp2_uart2 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart2_2pins_default>; + pinctrl-1 = <&blsp2_uart2_2pins_sleep>; +}; + +&blsp2_uart3 { + label = "LS-UART0"; + status = "disabled"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart3_4pins_default>; + pinctrl-1 = <&blsp2_uart3_4pins_sleep>; +}; + +&camss { + vdda-supply = <&vreg_l2a_1p25>; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/apq8096/a530_zap.mbn"; +}; + +&hsusb_phy1 { + status = "okay"; + + vdd-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&hsusb_phy2 { + status = "okay"; + + vdd-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&mdp { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_hdmi { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; + pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; +}; + +&mdss_hdmi_phy { + status = "okay"; + + vddio-supply = <&vreg_l12a_1p8>; + vcca-supply = <&vreg_l28a_0p925>; + #phy-cells = <0>; +}; + +&mmcc { + vdd-gfx-supply = <&vdd_gfx>; +}; + +&mss_pil { + status = "okay"; + pll-supply = <&vreg_l12a_1p8>; + firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn"; +}; + +&pm8994_resin { + status = "okay"; + linux,code = ; +}; + +&tlmm { + gpio-line-names = + "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ + "[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */ + "[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */ + "[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */ + "[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */ + "[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */ + "[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */ + "[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */ + "GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */ + "TP93", /* GPIO_9 */ + "GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */ + "[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */ + "NC", /* GPIO_12 */ + "[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */ + "[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */ + "[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */ + "TP99", /* GPIO_16 */ + "[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */ + "[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */ + "[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */ + "[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */ + "FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */ + "FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */ + "GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */ + "GPIO-D", /* GPIO_24, LSEC pin 26 */ + "GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */ + "GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */ + "BLSP6_I2C_SDA", /* GPIO_27 */ + "BLSP6_I2C_SCL", /* GPIO_28 */ + "GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */ + "GPIO30", /* GPIO_30, S HSEC pin 4 */ + "HDMI_CEC", /* GPIO_31 */ + "HDMI_DDC_CLOCK", /* GPIO_32 */ + "HDMI_DDC_DATA", /* GPIO_33 */ + "HDMI_HOT_PLUG_DETECT", /* GPIO_34 */ + "PCIE0_RST_N", /* GPIO_35 */ + "PCIE0_CLKREQ_N", /* GPIO_36 */ + "PCIE0_WAKE", /* GPIO_37 */ + "SD_CARD_DET_N", /* GPIO_38 */ + "TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */ + "W_DISABLE_N", /* GPIO_40 */ + "[BLSP9_UART_TX]", /* GPIO_41 */ + "[BLSP9_UART_RX]", /* GPIO_42 */ + "[BLSP2_UART_CTS_N]", /* GPIO_43 */ + "[BLSP2_UART_RFR_N]", /* GPIO_44 */ + "[BLSP3_UART_TX]", /* GPIO_45 */ + "[BLSP3_UART_RX]", /* GPIO_46 */ + "[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */ + "[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */ + "[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */ + "[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */ + "[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */ + "[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */ + "[CODEC_INT1_N]", /* GPIO_53 */ + "[CODEC_INT2_N]", /* GPIO_54 */ + "[BLSP7_I2C_SDA]", /* GPIO_55 */ + "[BLSP7_I2C_SCL]", /* GPIO_56 */ + "MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */ + "[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */ + "[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */ + "[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */ + "[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */ + "GPIO-E", /* GPIO_62, LSEC pin 27 */ + "TP87", /* GPIO_63 */ + "[CODEC_RST_N]", /* GPIO_64 */ + "[PCM1_CLK]", /* GPIO_65 */ + "[PCM1_SYNC]", /* GPIO_66 */ + "[PCM1_DIN]", /* GPIO_67 */ + "[PCM1_DOUT]", /* GPIO_68 */ + "AUDIO_REF_CLK", /* GPIO_69 */ + "SLIMBUS_CLK", /* GPIO_70 */ + "SLIMBUS_DATA0", /* GPIO_71 */ + "SLIMBUS_DATA1", /* GPIO_72 */ + "NC", /* GPIO_73 */ + "NC", /* GPIO_74 */ + "NC", /* GPIO_75 */ + "NC", /* GPIO_76 */ + "TP94", /* GPIO_77 */ + "NC", /* GPIO_78 */ + "TP95", /* GPIO_79 */ + "GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */ + "TP88", /* GPIO_81 */ + "TP89", /* GPIO_82 */ + "TP90", /* GPIO_83 */ + "TP91", /* GPIO_84 */ + "[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */ + "[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */ + "[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */ + "[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */ + "TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */ + "TSIF1_EN", /* GPIO_90, S HSEC pin 46 */ + "TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */ + "NC", /* GPIO_92 */ + "TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */ + "TSIF2_EN", /* GPIO_94, S HSEC pin 56 */ + "TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */ + "TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */ + "NC", /* GPIO_97 */ + "CAM1_STANDBY_N", /* GPIO_98 */ + "NC", /* GPIO_99 */ + "NC", /* GPIO_100 */ + "[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */ + "BOOT_CONFIG1", /* GPIO_102 */ + "USB_HUB_RESET", /* GPIO_103 */ + "CAM1_RST_N", /* GPIO_104 */ + "NC", /* GPIO_105 */ + "NC", /* GPIO_106 */ + "NC", /* GPIO_107 */ + "NC", /* GPIO_108 */ + "NC", /* GPIO_109 */ + "NC", /* GPIO_110 */ + "NC", /* GPIO_111 */ + "NC", /* GPIO_112 */ + "PMI8994_BUA", /* GPIO_113 */ + "PCIE2_RST_N", /* GPIO_114 */ + "PCIE2_CLKREQ_N", /* GPIO_115 */ + "PCIE2_WAKE", /* GPIO_116 */ + "SSC_IRQ_0", /* GPIO_117 */ + "SSC_IRQ_1", /* GPIO_118 */ + "SSC_IRQ_2", /* GPIO_119 */ + "NC", /* GPIO_120 */ + "GPIO121", /* GPIO_121, S HSEC pin 2 */ + "NC", /* GPIO_122 */ + "SSC_IRQ_6", /* GPIO_123 */ + "SSC_IRQ_7", /* GPIO_124 */ + "GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */ + "BOOT_CONFIG5", /* GPIO_126 */ + "NC", /* GPIO_127 */ + "NC", /* GPIO_128 */ + "BOOT_CONFIG7", /* GPIO_129 */ + "PCIE1_RST_N", /* GPIO_130 */ + "PCIE1_CLKREQ_N", /* GPIO_131 */ + "PCIE1_WAKE", /* GPIO_132 */ + "GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */ + "NC", /* GPIO_134 */ + "NC", /* GPIO_135 */ + "BOOT_CONFIG8", /* GPIO_136 */ + "NC", /* GPIO_137 */ + "NC", /* GPIO_138 */ + "GPS_SSBI2", /* GPIO_139 */ + "GPS_SSBI1", /* GPIO_140 */ + "NC", /* GPIO_141 */ + "NC", /* GPIO_142 */ + "NC", /* GPIO_143 */ + "BOOT_CONFIG6", /* GPIO_144 */ + "NC", /* GPIO_145 */ + "NC", /* GPIO_146 */ + "NC", /* GPIO_147 */ + "NC", /* GPIO_148 */ + "NC"; /* GPIO_149 */ + + sdc2_cd_on: sdc2-cd-on-state { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + + sdc2_cd_off: sdc2-cd-off-state { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + hdmi_hpd_active: hdmi-hpd-active-state { + pins = "gpio34"; + function = "hdmi_hot"; + bias-pull-down; + drive-strength = <16>; + }; + + hdmi_hpd_suspend: hdmi-hpd-suspend-state { + pins = "gpio34"; + function = "hdmi_hot"; + bias-pull-down; + drive-strength = <2>; + }; + + hdmi_ddc_active: hdmi-ddc-active-state { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + drive-strength = <2>; + bias-pull-up; + }; + + hdmi_ddc_suspend: hdmi-ddc-suspend-state { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&pcie0 { + status = "okay"; + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&wlan_en>; + vdda-supply = <&vreg_l28a_0p925>; +}; + +&pcie1 { + status = "okay"; + perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; + vdda-supply = <&vreg_l28a_0p925>; +}; + +&pcie2 { + status = "okay"; + perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; + vdda-supply = <&vreg_l28a_0p925>; +}; + +&pcie_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&pm8994_gpios { + gpio-line-names = + "NC", + "KEY_VOLP_N", + "NC", + "BL1_PWM", + "GPIO-F", /* BL0_PWM, LSEC pin 28 */ + "BL1_EN", + "NC", + "WLAN_EN", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "DIVCLK1", + "DIVCLK2", + "DIVCLK3", + "DIVCLK4", + "BT_EN", + "PMIC_SLB", + "PMIC_BUA", + "USB_VBUS_DET"; + + pinctrl-names = "default"; + pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>; + + ls_exp_gpio_f: pm8994-gpio5-state { + pinconf { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = ; /* 1.8V */ + }; + }; + + bt_en_gpios: bt-en-pios-state { + pinconf { + pins = "gpio19"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = ; /* 1.8V */ + qcom,drive-strength = ; + bias-pull-down; + }; + }; + + wlan_en_gpios: wlan-en-gpios-state { + pinconf { + pins = "gpio8"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = ; /* 1.8V */ + qcom,drive-strength = ; + bias-pull-down; + }; + }; + + audio_mclk: clk-div1-state { + pinconf { + pins = "gpio15"; + function = "func1"; + power-source = ; /* 1.8V */ + }; + }; + + volume_up_gpio: pm8996-gpio2-state { + pinconf { + pins = "gpio2"; + function = "normal"; + input-enable; + drive-push-pull; + bias-pull-up; + qcom,drive-strength = ; + power-source = ; /* 1.8V */ + }; + }; + + divclk4_pin_a: divclk4-state { + pinconf { + pins = "gpio18"; + function = PMIC_GPIO_FUNC_FUNC2; + + bias-disable; + power-source = ; + }; + }; + + usb3_vbus_det_gpio: pm8996-gpio22-state { + pinconf { + pins = "gpio22"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + qcom,drive-strength = ; + power-source = ; /* 1.8V */ + }; + }; +}; + +&pm8994_mpps { + gpio-line-names = + "VDDPX_BIAS", + "WIFI_LED", + "NC", + "BT_LED", + "PM_MPP05", + "PM_MPP06", + "PM_MPP07", + "NC"; +}; + +&pm8994_spmi_regulators { + qcom,saw-reg = <&saw3>; + vdd_s11-supply = <&vph_pwr>; + + s9 { + qcom,saw-slave; + }; + s10 { + qcom,saw-slave; + }; + s11 { + qcom,saw-leader; + regulator-name = "VDD_APCC"; + regulator-always-on; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + }; +}; + +&pmi8994_gpios { + gpio-line-names = + "NC", + "SPKR_AMP_EN1", + "SPKR_AMP_EN2", + "TP61", + "NC", + "USB2_VBUS_DET", + "NC", + "NC", + "NC", + "NC"; + + usb2_vbus_det_gpio: pmi8996-gpio6-state { + pinconf { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + qcom,drive-strength = ; + power-source = ; /* 1.8V */ + }; + }; +}; + +&pmi8994_lpg { + qcom,power-source = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmi8994_mpp2_userled4>; + + qcom,dtest = <0 0>, + <0 0>, + <0 0>, + <4 1>; + + status = "okay"; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <1>; + + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <0>; + }; + + led@3 { + reg = <3>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <2>; + }; + + led@4 { + reg = <4>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <3>; + }; +}; + +&pmi8994_mpps { + pmi8994_mpp2_userled4: mpp2-userled4-state { + pins = "mpp2"; + function = "sink"; + + output-low; + qcom,dtest = <4>; + }; +}; + +&pmi8994_spmi_regulators { + vdd_s2-supply = <&vph_pwr>; + + vdd_gfx: s2 { + regulator-name = "VDD_GFX"; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + }; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_l1-supply = <&vreg_s1b_1p025>; + vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; + vdd_l3_l11-supply = <&vreg_s3a_1p3>; + vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; + vdd_l5_l7-supply = <&vreg_s5a_2p15>; + vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; + vdd_l8_l16_l30-supply = <&vph_pwr>; + vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; + vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; + vdd_l14_l15-supply = <&vreg_s5a_2p15>; + vdd_l17_l29-supply = <&vph_pwr_bbyp>; + vdd_l20_l21-supply = <&vph_pwr_bbyp>; + vdd_l25-supply = <&vreg_s3a_1p3>; + vdd_lvs1_2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p3: s3 { + regulator-name = "vreg_s3a_1p3"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + /** + * 1.8v required on LS expansion + * for mezzanine boards + */ + vreg_s4a_1p8: s4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + vreg_s5a_2p15: s5 { + regulator-name = "vreg_s5a_2p15"; + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + vreg_s7a_1p0: s7 { + regulator-name = "vreg_s7a_1p0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l1a_1p0: l1 { + regulator-name = "vreg_l1a_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + vreg_l2a_1p25: l2 { + regulator-name = "vreg_l2a_1p25"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + vreg_l3a_0p875: l3 { + regulator-name = "vreg_l3a_0p875"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + }; + vreg_l4a_1p225: l4 { + regulator-name = "vreg_l4a_1p225"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + vreg_l6a_1p2: l6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + vreg_l8a_1p8: l8 { + regulator-name = "vreg_l8a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l9a_1p8: l9 { + regulator-name = "vreg_l9a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l10a_1p8: l10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l11a_1p15: l11 { + regulator-name = "vreg_l11a_1p15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + vreg_l12a_1p8: l12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l13a_2p95: l13 { + regulator-name = "vreg_l13a_2p95"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + vreg_l14a_1p8: l14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l15a_1p8: l15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l16a_2p7: l16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + vreg_l17a_2p8: l17 { + regulator-name = "vreg_l17a_2p8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + vreg_l18a_2p85: l18 { + regulator-name = "vreg_l18a_2p85"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + vreg_l19a_2p8: l19 { + regulator-name = "vreg_l19a_2p8"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + vreg_l20a_2p95: l20 { + regulator-name = "vreg_l20a_2p95"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + vreg_l21a_2p95: l21 { + regulator-name = "vreg_l21a_2p95"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + vreg_l22a_3p0: l22 { + regulator-name = "vreg_l22a_3p0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + vreg_l23a_2p8: l23 { + regulator-name = "vreg_l23a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l24a_3p075: l24 { + regulator-name = "vreg_l24a_3p075"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + vreg_l25a_1p2: l25 { + regulator-name = "vreg_l25a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + vreg_l26a_0p8: l27 { + regulator-name = "vreg_l26a_0p8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + vreg_l28a_0p925: l28 { + regulator-name = "vreg_l28a_0p925"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + vreg_l29a_2p8: l29 { + regulator-name = "vreg_l29a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l30a_1p8: l30 { + regulator-name = "vreg_l30a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l32a_1p8: l32 { + regulator-name = "vreg_l32a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-name = "vreg_lvs1a_1p8"; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-name = "vreg_lvs2a_1p8"; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + vph_pwr_bbyp: boost-bypass { + regulator-name = "vph_pwr_bbyp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_s1b_1p025: s1 { + regulator-name = "vreg_s1b_1p025"; + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + }; +}; + +&sdhc2 { + /* External SD card */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + status = "okay"; +}; + +&q6asmdai { + dai@0 { + reg = ; + }; + + dai@1 { + reg = ; + }; + + dai@2 { + reg = ; + }; +}; + +&slim_msm { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + tasha_ifd: tas-ifd@0,0 { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1,0 { + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_BB_CLK1>; + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + slim-ifc-dev = <&tasha_ifd>; + + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + }; + }; +}; + +&sound { + compatible = "qcom,apq8096-sndcard"; + model = "DB820c"; + audio-routing = "RX_BIAS", "MCLK"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + hdmi-dai-link { + link-name = "HDMI"; + cpu { + sound-dai = <&q6afedai HDMI_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&mdss_hdmi 0>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_6_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 AIF4_PB>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 AIF1_CAP>; + }; + }; +}; + +&ufsphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&ufshc { + status = "okay"; + + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l25a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + vdd-hba-supply = <&vreg_l25a_1p2>; + + vcc-max-microamp = <600000>; + vccq-max-microamp = <450000>; + vccq2-max-microamp = <450000>; +}; + +&usb2 { + status = "okay"; + extcon = <&usb2_id>; +}; + +&usb2_dwc3 { + extcon = <&usb2_id>; + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + +&usb3 { + status = "okay"; + extcon = <&usb3_id>; +}; + +&usb3_dwc3 { + extcon = <&usb3_id>; + dr_mode = "otg"; +}; + +&usb3phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/apq8096sg-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096sg-db820c.dts new file mode 100644 index 000000000000..f3ab5a7c6e53 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8096sg-db820c.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "msm8996pro.dtsi" +#include "apq8096-db820c.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. DB820c"; + compatible = "arrow,apq8096sg-db820c", "arrow,apq8096-db820c", + "qcom,apq8096-sbc", "qcom,apq8096sg", "qcom,apq8096"; +}; diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts new file mode 100644 index 000000000000..90f629800cb0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include "eliza.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Eliza MTP"; + compatible = "qcom,eliza-mtp", "qcom,eliza"; + chassis-type = "handset"; + + aliases { + serial0 = &uart14; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3b>; + vdd-l2-l3-supply = <&vreg_s3b>; + vdd-l4-l5-supply = <&vreg_s2b>; + vdd-l6-supply = <&vreg_s2b>; + vdd-l7-supply = <&vreg_s1b>; + vdd-l8-supply = <&vreg_s1b>; + vdd-l9-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s1b>; + vdd-l12-l14-supply = <&vreg_bob>; + vdd-l13-l16-supply = <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-bob-supply = <&vph_pwr>; + + qcom,pmic-id = "b"; + + vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s2b: smps2 { + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <2744000>; + regulator-initial-mode = ; + }; + + vreg_s3b: smps3 { + regulator-name = "vreg_s3b"; + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <2744000>; + regulator-initial-mode = ; + }; + + vreg_s4b: smps4 { + regulator-name = "vreg_s4b"; + regulator-min-microvolt = <2156000>; + regulator-max-microvolt = <2400000>; + regulator-initial-mode = ; + }; + + vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = ; + }; + + vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10b: ldo10 { + regulator-name = "vreg_l10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; + /* Voltage range for UFS 3.x and above */ + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l20b: ldo20 { + regulator-name = "vreg_l20b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l21b: ldo21 { + regulator-name = "vreg_l21b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l22b: ldo22 { + regulator-name = "vreg_l22b"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l23b: ldo23 { + regulator-name = "vreg_l23b"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s2b>; + + qcom,pmic-id = "d"; + + vreg_l1d: ldo1 { + regulator-name = "vreg_l1d"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s2b>; + vdd-l3-supply = <&vreg_s2b>; + + qcom,pmic-id = "g"; + + vreg_l1g: ldo1 { + regulator-name = "vreg_l1g"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l3g: ldo3 { + regulator-name = "vreg_l3g"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + }; + + regulators-3 { + compatible = "qcom,pmr735d-rpmh-regulators"; + + vdd-l1-l2-l5-supply = <&vreg_s3b>; + vdd-l3-l4-supply = <&vreg_s2b>; + vdd-l6-supply = <&vreg_s1b>; + vdd-l7-supply = <&vreg_s3b>; + + qcom,pmic-id = "k"; + + vreg_l1k: ldo1 { + regulator-name = "vreg_l1k"; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2k: ldo2 { + regulator-name = "vreg_l2k"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <969000>; + regulator-initial-mode = ; + }; + + vreg_l3k: ldo3 { + regulator-name = "vreg_l3k"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + }; + + vreg_l4k: ldo4 { + regulator-name = "vreg_l4k"; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l5k: ldo5 { + regulator-name = "vreg_l5k"; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <931000>; + regulator-initial-mode = ; + }; + + vreg_l6k: ldo6 { + regulator-name = "vreg_l6k"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l7k: ldo7 { + regulator-name = "vreg_l7k"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = ; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <20 4>, /* NFC SPI */ + <111 2>, /* WCN UART1 */ + <118 1>; /* NFC Secure I/O */ +}; + +&uart14 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l12b>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1d>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l4b>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi new file mode 100644 index 000000000000..4a7a0ac40ce6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -0,0 +1,1885 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x0>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + + l3: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x100>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x200>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x300>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_3>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x400>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_4>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + l2_4: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x500>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_5>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + l2_5: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x600>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_6>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + l2_6: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-x3"; + reg = <0x0 0x700>; + + clocks = <&cpufreq_hw 2>; + + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_7>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <588>; + + qcom,freq-domain = <&cpufreq_hw 2>; + + l2_7: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + + core6 { + cpu = <&cpu6>; + }; + + core7 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cluster0_c4: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + }; + + cluster1_c4: cpu-sleep-1 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <550>; + exit-latency-us = <1050>; + min-residency-us = <7951>; + }; + + cluster2_c4: cpu-sleep-2 { + compatible = "arm,idle-state"; + idle-state-name = "gold-plus-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100b344>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-eliza", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + qcom,dload-mode = <&tcsr 0x1a000>; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,eliza-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,eliza-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster1_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster1_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster1_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster1_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster2_c4>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_0>, + <&cluster_sleep_1>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp@80000000 { + reg = <0x0 0x80000000 0x0 0xe00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-mem@80e00000 { + reg = <0x0 0x80e00000 0x0 0x40000>; + no-map; + }; + + cpucp_mem: cpucp@81200000 { + reg = <0x0 0x81200000 0x0 0x200000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog@81a00000 { + reg = <0x0 0x81a00000 0x0 0x40000>; + no-map; + }; + + aop_image_mem: aop-image@81c00000 { + reg = <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ + aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { + reg = <0x0 0x81c80000 0x0 0x74000>; + no-map; + }; + + /* Secdata region can be reused by apps */ + smem_mem: smem@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + cpucp_scandump_mem: cpucp-scandump@82000000 { + reg = <0x0 0x82200000 0x0 0x180000>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi@82380000 { + reg = <0x0 0x82380000 0x0 0x20000>; + no-map; + }; + + soccp_sdi_mem: soccp-sdi@823a0000 { + reg = <0x0 0x823a0000 0x0 0x40000>; + no-map; + }; + + pmic_minii_dump_mem: pmic-minii-dump@823e0000 { + reg = <0x0 0x823e0000 0x0 0x80000>; + no-map; + }; + + pvmfw_mem: pvmfw@824a0000 { + reg = <0x0 0x824a0000 0x0 0x100000>; + no-map; + }; + + hyp_db_mem: hyp-db@825a0000 { + reg = <0x0 0x825a0000 0x0 0x60000>; + no-map; + }; + + global_sync_mem: global-sync@82600000 { + reg = <0x0 0x82600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat@82700000 { + reg = <0x0 0x82700000 0x0 0x100000>; + no-map; + }; + + qdss_mem: qdss@82800000 { + reg = <0x0 0x82800000 0x0 0x2000000>; + no-map; + }; + + dsm_partition_1_mem: dsm-partition-1@84a00000 { + reg = <0x0 0x84a00000 0x0 0x3700000>; + no-map; + }; + + mpss_mem: mpss@88100000 { + reg = <0x0 0x88100000 0x0 0xcd00000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@94e00000 { + reg = <0x0 0x94e00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@94e80000 { + reg = <0x0 0x94e80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@94e90000 { + reg = <0x0 0x94e90000 0x0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code@94e9a000 { + reg = <0x0 0x94e9a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@94f00000 { + reg = <0x0 0x94f00000 0x0 0x800000>; + no-map; + }; + + camera_2_mem: camera-2@95700000 { + reg = <0x0 0x95700000 0x0 0x800000>; + no-map; + }; + + video_mem: video@95f00000 { + reg = <0x0 0x95f00000 0x0 0x800000>; + no-map; + }; + + soccp_mem: soccp@96700000 { + reg = <0x0 0x96700000 0x0 0x180000>; + no-map; + }; + + wpss_mem: wpss@97000000 { + reg = <0x0 0x97000000 0x0 0x1900000>; + no-map; + }; + + cdsp_mem: cdsp@98900000 { + reg = <0x0 0x98900000 0x0 0x1400000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@99d00000 { + reg = <0x0 0x99d00000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@99d80000 { + reg = <0x0 0x99d80000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi@99e00000 { + reg = <0x0 0x99e00000 0x0 0x2a00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@a6400000 { + reg = <0x0 0xa6400000 0x0 0xc00000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump@b8000000 { + reg = <0x0 0xb8000000 0x0 0x1c0000>; + no-map; + }; + + /* Merged tz_reserved, xbl_sc, and qtee regions */ + tz_merged_mem: tz-merged@d8000000 { + reg = <0x0 0xd8000000 0x0 0x600000>; + no-map; + }; + + trust_ui_vm_mem: trust-ui-vm@f3800000 { + reg = <0x0 0xf3800000 0x0 0x4400000>; + no-map; + }; + + oem_vm_mem: oem-vm@f7c00000 { + reg = <0x0 0xf7c00000 0x0 0x4c00000>; + no-map; + }; + + llcc_lpi_mem: llcc-lpi@ff800000 { + reg = <0x0 0xff800000 0x0 0x180000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + gcc: clock-controller@100000 { + compatible = "qcom,eliza-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <0>, + <0>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <0>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x423 0x0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart14: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart14_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,eliza-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x5200>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,eliza-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x16080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,eliza-system-noc"; + reg = <0x0 0x01680000 0x0 0x40000>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,eliza-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x11400>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + #interconnect-cells = <2>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,eliza-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x16400>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + #interconnect-cells = <2>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,eliza-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1f400>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + #interconnect-cells = <2>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,eliza-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x7d800>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,eliza-qmp-ufs-phy", + "qcom,sm8650-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,eliza-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x01da0000 0x0 0x15000>; + reg-names = "std", + "mcq"; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 = <&ufs_opp_table>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x60 0x0>; + dma-coherent; + + msi-parent = <&gic_its 0x60>; + + lanes-per-direction = <2>; + qcom,ice = <&ice>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-201500000 { + opp-hz = /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <201500000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible = "qcom,eliza-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fbf000 { + compatible = "qcom,eliza-tcsr", "syscon"; + reg = <0x0 0x01fbf000 0x0 0x21000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,eliza-lpass-ag-noc"; + reg = <0x0 0x07e40000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,eliza-lpass-lpiaon-noc"; + reg = <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,eliza-lpass-lpicx-noc"; + reg = <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,eliza-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x40000>, + <0x0 0x174000f0 0x0 0x64>; + + qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, + <10 230 1>, <11 724 1>, <12 716 1>, + <13 727 1>, <14 720 1>, <15 726 1>, + <16 721 1>, <17 262 1>, <18 70 1>, + <19 723 1>, <20 234 1>, <22 725 1>, + <23 231 1>, <24 504 5>, <30 510 8>, + <40 520 6>, <51 531 4>, <58 538 2>, + <61 541 5>, <66 92 1>, <67 547 13>, + <80 240 1>, <81 235 1>, <82 310 2>, + <84 248 1>, <85 241 1>, <86 238 2>, + <88 254 1>, <89 509 1>, <90 563 1>, + <91 259 2>, <93 201 1>, <94 246 1>, + <95 93 1>, <96 611 29>, <125 63 1>, + <126 366 2>, <128 374 1>, <129 377 1>, + <130 428 1>, <131 434 2>, <133 437 1>, + <134 452 2>, <136 458 2>, <138 464 11>, + <149 671 1>, <150 688 1>, <151 714 2>, + <153 722 1>, <154 255 1>, <155 269 2>, + <157 276 1>, <158 287 1>, <159 306 4>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c228000 { + compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c228000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <14>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22a000 { + compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22a000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <5>; + + #thermal-sensor-cells = <1>; + }; + + spmi: arbiter@c400000 { + compatible = "qcom,eliza-spmi-pmic-arb", + "qcom,x1e80100-spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>; + reg-names = "core", + "chnls", + "obsrvr"; + + qcom,ee = <0>; + qcom,channel = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg = <0x0 0x0c42d000 0x0 0x4000>, + <0x0 0x0c4c0000 0x0 0x10000>; + reg-names = "cnfg", + "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c432000 { + reg = <0x0 0x0c432000 0x0 0x4000>, + <0x0 0x0c4d0000 0x0 0x10000>; + reg-names = "cnfg", + "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17100000 0x0 0x10000>, + <0x0 0x17180000 0x0 0x200000>; + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17140000 0x0 0x40000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + + interrupts = , + , + ; + + power-domains = <&cluster_pd>; + label = "apps_rsc"; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,eliza-rpmh-clk"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmhpd: power-controller { + compatible = "qcom,eliza-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level = ; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level = ; + }; + }; + }; + }; + + epss_l3: interconnect@17d90000 { + compatible = "qcom,eliza-epss-l3", "qcom,epss-l3"; + reg = <0x0 0x17d90000 0x0 0x1000>; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,eliza-tlmm"; + reg = <0x0 0x0f100000 0x0 0xf00000>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 184>; + wakeup-parent = <&pdc>; + + qup_uart14_default: qup-uart14-default-state { + /* TX, RX */ + pins = "gpio18", "gpio19"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,eliza-gem-noc"; + reg = <0x0 0x24100000 0x0 0x163080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,eliza-nsp-noc"; + reg = <0x0 0x320c0000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + }; + + thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + aoss-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + aoss-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + aoss-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + aoss-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors = <&tsens1 12>; + + trips { + camera-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + camera-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera1-thermal { + thermal-sensors = <&tsens1 13>; + + trips { + camera-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + camera-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-top-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-bottom-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-top-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpuss-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + cpuss-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpuss-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + cpuss-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + thermal-sensors = <&tsens1 11>; + + trips { + ddr-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + ddr-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 8>; + + trips { + gpu-alert { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + gpu-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 9>; + + trips { + gpu-alert { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + gpu-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem0-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + modem-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem1-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + modem-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem2-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + modem-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem3-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + modem-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx0-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + nsphmx-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphmx-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx1-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + nsphmx-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphmx-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx0-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + nsphvx-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphvx-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx1-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + nsphvx-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphvx-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens1 10>; + + trips { + video-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + video-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts new file mode 100644 index 000000000000..35aaf09e4e2b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "glymur.dtsi" +#include "glymur-crd.dtsi" + +#include + +/ { + model = "Qualcomm Technologies, Inc. Glymur CRD"; + compatible = "qcom,glymur-crd", "qcom,glymur"; + + pmic-glink { + compatible = "qcom,glymur-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + ptn3222_0: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; + + ptn3222_1: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna60cl08", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p83>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&tlmm { + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; +}; + +&usb_0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l3f_e0_0p72>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l1h_e0_0p89>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb_hs { + status = "okay"; +}; + +&usb_hs_phy { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_1>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_0>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi new file mode 100644 index 000000000000..2852d257ac8c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -0,0 +1,697 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "pmcx0102.dtsi" /* SPMI0: SID-2/3 SPMI1: SID-2/3 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0110-glymur.dtsi" /* SPMI0: SID-5/7 SPMI1: SID-5 */ +#include "pmh0104-glymur.dtsi" /* SPMI0: SID-8/9 SPMI1: SID-11 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ + +/ { + model = "Qualcomm Technologies, Inc. Glymur CRD"; + compatible = "qcom,glymur-crd", "qcom,glymur"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + i2c0 = &i2c0; + i2c1 = &i2c4; + i2c2 = &i2c5; + spi0 = &spi18; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pmh0101_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvmesec: regulator-nvmesec { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_SEC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e1_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_sec_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WWAN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 246 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_reg_en>; + pinctrl-names = "default"; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_e0_1p8>; + vddaon-supply = <&vreg_l15b_e0_1p8>; + vdddig-supply = <&vreg_l15b_e0_1p8>; + vddrfa1p2-supply = <&vreg_l15b_e0_1p8>; + vddrfa1p8-supply = <&vreg_l15b_e0_1p8>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_bob1_e0: bob1 { + regulator-name = "vreg_bob1_e0"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <4224000>; + regulator-initial-mode = ; + }; + + vreg_bob2_e0: bob2 { + regulator-name = "vreg_bob2_e0"; + regulator-min-microvolt = <2540000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + }; + + vreg_l1b_e0_1p8: ldo1 { + regulator-name = "vreg_l1b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_e0_2p9: ldo2 { + regulator-name = "vreg_l2b_e0_2p9"; + regulator-min-microvolt = <2904000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + + vreg_l7b_e0_2p79: ldo7 { + regulator-name = "vreg_l7b_e0_2p79"; + regulator-min-microvolt = <2790000>; + regulator-max-microvolt = <2792000>; + regulator-initial-mode = ; + }; + + vreg_l8b_e0_1p50: ldo8 { + regulator-name = "vreg_l8b_e0_1p50"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_e0_2p7: ldo9 { + regulator-name = "vreg_l9b_e0_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l10b_e0_1p8: ldo10 { + regulator-name = "vreg_l10b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b_e0_1p2: ldo11 { + regulator-name = "vreg_l11b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l12b_e0_1p14: ldo12 { + regulator-name = "vreg_l12b_e0_1p14"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1144000>; + regulator-initial-mode = ; + }; + + vreg_l15b_e0_1p8: ldo15 { + regulator-name = "vreg_l15b_e0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_e0_2p4: ldo17 { + regulator-name = "vreg_l17b_e0_2p4"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + }; + + vreg_l18b_e0_1p2: ldo18 { + regulator-name = "vreg_l18b_e0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c_e1_0p82: ldo1 { + regulator-name = "vreg_l1c_e1_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2c_e1_1p14: ldo2 { + regulator-name = "vreg_l2c_e1_1p14"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1144000>; + regulator-initial-mode = ; + }; + + vreg_l3c_e1_0p89: ldo3 { + regulator-name = "vreg_l3c_e1_0p89"; + regulator-min-microvolt = <890000>; + regulator-max-microvolt = <980000>; + regulator-initial-mode = ; + }; + + vreg_l4c_e1_0p72: ldo4 { + regulator-name = "vreg_l4c_e1_0p72"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <720000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s7f_e0_1p32: smps7 { + regulator-name = "vreg_s7f_e0_1p32"; + regulator-min-microvolt = <1320000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s8f_e0_0p95: smps8 { + regulator-name = "vreg_s8f_e0_0p95"; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s9f_e0_1p9: smps9 { + regulator-name = "vreg_s9f_e0_1p9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e0_0p82: ldo2 { + regulator-name = "vreg_l2f_e0_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l3f_e0_0p72: ldo3 { + regulator-name = "vreg_l3f_e0_0p72"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <720000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e0_0p3: ldo4 { + regulator-name = "vreg_l4f_e0_0p3"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_s7f_e1_0p3: smps7 { + regulator-name = "vreg_s7f_e1_0p3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l1f_e1_0p82: ldo1 { + regulator-name = "vreg_l1f_e1_0p82"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e1_0p83: ldo2 { + regulator-name = "vreg_l2f_e1_0p83"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e1_1p08: ldo4 { + regulator-name = "vreg_l4f_e1_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "H_E0"; + + vreg_l1h_e0_0p89: ldo1 { + regulator-name = "vreg_l1h_e0_0p89"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l2h_e0_0p72: ldo2 { + regulator-name = "vreg_l2h_e0_0p72"; + regulator-min-microvolt = <832000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l3h_e0_0p32: ldo3 { + regulator-name = "vreg_l3h_e0_0p32"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l4h_e0_1p2: ldo4 { + regulator-name = "vreg_l4h_e0_1p2"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + }; +}; + +&pcie3b { + vddpe-3v3-supply = <&vreg_nvmesec>; + + pinctrl-0 = <&pcie3b_default>; + pinctrl-names = "default"; +}; + +&pcie3b_phy { + vdda-phy-supply = <&vreg_l3c_e1_0p89>; + vdda-pll-supply = <&vreg_l2c_e1_1p14>; +}; + +&pcie3b_port0 { + reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0_0p82>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pcie6 { + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-0 = <&pcie6_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&pcie6_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0110_f_e1_gpios { + nvme_sec_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmh0101_gpios { + key_vol_up_default: key-vol-up-default-state { + pins = "gpio6"; + function = "normal"; + output-disable; + bias-pull-up; + }; +}; + +&pmk8850_rtc { + qcom,no-alarm; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>; /* Security SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6_default: pcie6-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie6_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3b_default: pcie3b-default-state { + clkreq-n-pins { + pins = "gpio156"; + function = "pcie3b_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio155"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio157"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_reg_en: wwan-reg-en-state { + pins = "gpio246"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi new file mode 100644 index 000000000000..f23cf81ddb77 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -0,0 +1,7135 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "glymur-ipcc.h" + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,oryon-2-2"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&cpu_pd0>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,oryon-2-2"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&cpu_pd1>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,oryon-2-2"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&cpu_pd2>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,oryon-2-2"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&cpu_pd3>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,oryon-2-2"; + reg = <0x0 0x400>; + enable-method = "psci"; + power-domains = <&cpu_pd4>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,oryon-2-2"; + reg = <0x0 0x500>; + enable-method = "psci"; + power-domains = <&cpu_pd5>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_0>; + }; + + cpu6: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x10000>; + enable-method = "psci"; + power-domains = <&cpu_pd6>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x10100>; + enable-method = "psci"; + power-domains = <&cpu_pd7>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu8: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x10200>; + enable-method = "psci"; + power-domains = <&cpu_pd8>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu9: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x10300>; + enable-method = "psci"; + power-domains = <&cpu_pd9>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu10: cpu@10400 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x10400>; + enable-method = "psci"; + power-domains = <&cpu_pd10>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu11: cpu@10500 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x10500>; + enable-method = "psci"; + power-domains = <&cpu_pd11>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_1>; + }; + + cpu12: cpu@20000 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x20000>; + enable-method = "psci"; + power-domains = <&cpu_pd12>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu13: cpu@20100 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x20100>; + enable-method = "psci"; + power-domains = <&cpu_pd13>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu14: cpu@20200 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x20200>; + enable-method = "psci"; + power-domains = <&cpu_pd14>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu15: cpu@20300 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x20300>; + enable-method = "psci"; + power-domains = <&cpu_pd15>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu16: cpu@20400 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x20400>; + enable-method = "psci"; + power-domains = <&cpu_pd16>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu17: cpu@20500 { + device_type = "cpu"; + compatible = "qcom,oryon-2-1"; + reg = <0x0 0x20500>; + enable-method = "psci"; + power-domains = <&cpu_pd17>, <&scmi_perf 2>; + power-domain-names = "psci", "perf"; + next-level-cache = <&l2_2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + + core2 { + cpu = <&cpu8>; + }; + + core3 { + cpu = <&cpu9>; + }; + + core4 { + cpu = <&cpu10>; + }; + + core5 { + cpu = <&cpu11>; + }; + }; + + cpu_map_cluster2: cluster2 { + core0 { + cpu = <&cpu12>; + }; + + core1 { + cpu = <&cpu13>; + }; + + core2 { + cpu = <&cpu14>; + }; + + core3 { + cpu = <&cpu15>; + }; + + core4 { + cpu = <&cpu16>; + }; + + core5 { + cpu = <&cpu17>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_c4: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "ret"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <180>; + exit-latency-us = <320>; + min-residency-us = <1000>; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x01000054>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <9000>; + }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x0200c354>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-glymur", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x4000>; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,glymur-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,glymur-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster0_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd8: power-domain-cpu8 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd9: power-domain-cpu9 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd10: power-domain-cpu10 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd11: power-domain-cpu11 { + #power-domain-cells = <0>; + power-domains = <&cluster1_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd12: power-domain-cpu12 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd13: power-domain-cpu13 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd14: power-domain-cpu14 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd15: power-domain-cpu15 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd16: power-domain-cpu16 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cpu_pd17: power-domain-cpu17 { + #power-domain-cells = <0>; + power-domains = <&cluster2_pd>; + domain-idle-states = <&cpu_c4>; + }; + + cluster0_pd: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + cluster1_pd: power-domain-cpu-cluster1 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + cluster2_pd: power-domain-cpu-cluster2 { + #power-domain-cells = <0>; + power-domains = <&system_pd>; + domain-idle-states = <&cluster_cl5>; + }; + + system_pd: power-domain-system { + #power-domain-cells = <0>; + domain-idle-states = <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pdp_mem: pdp@81400000 { + reg = <0x0 0x81400000 0x0 0x100000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared@81e00000 { + reg = <0x0 0x81e00000 0x0 0x200000>; + no-map; + }; + + oobdaretag_mem: oobdaretag@86e10000 { + reg = <0x0 0x86e10000 0x0 0x360000>; + no-map; + }; + + oob_secure_mem: oob-secure@87170000 { + reg = <0x0 0x87170000 0x0 0xbc0000>; + no-map; + }; + + oobdtbqc_mem: oobdtbqc@87d30000 { + reg = <0x0 0x87d30000 0x0 0x20000>; + no-map; + }; + + oobdtboem_mem: oobdtboem@87d50000 { + reg = <0x0 0x87d50000 0x0 0x20000>; + no-map; + }; + + oob_nonsecure_mem: oob-nonsecure@87e00000 { + reg = <0x0 0x87e00000 0x0 0xc00000>; + no-map; + }; + + spss_region_mem: spss@88a00000 { + reg = <0x0 0x88a00000 0x0 0x400000>; + no-map; + }; + + soccpdtb_mem: soccpdtb@892e0000 { + reg = <0x0 0x892e0000 0x0 0x20000>; + no-map; + }; + + soccp_mem: soccp@89300000 { + reg = <0x0 0x89300000 0x0 0x400000>; + no-map; + }; + + cvp_mem: cvp@89700000 { + reg = <0x0 0x89700000 0x0 0x700000>; + no-map; + }; + + adspslpi_mem: adspslpi@89e00000 { + reg = <0x0 0x89e00000 0x0 0x3a00000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { + reg = <0x0 0x8d800000 0x0 0x80000>; + no-map; + }; + + cdsp_mem: cdsp@8d900000 { + reg = <0x0 0x8d900000 0x0 0x4000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { + reg = <0x0 0x91900000 0x0 0x80000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@919fe000 { + reg = <0x0 0x919fe000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@91a00000 { + reg = <0x0 0x91a00000 0x0 0x800000>; + no-map; + }; + + av1_encoder_mem: av1-encoder@92200000 { + reg = <0x0 0x92200000 0x0 0x700000>; + no-map; + }; + + video_mem: video@92900000 { + reg = <0x0 0x92900000 0x0 0xc00000>; + no-map; + }; + + smem_mem: smem@ffe00000 { + compatible = "qcom,smem"; + reg = <0x0 0xffe00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-soccp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <617>, <616>; + qcom,local-pid = <0>; + qcom,remote-pid = <19>; + + soccp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + soccp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + gcc: clock-controller@100000 { + compatible = "qcom,glymur-gcc"; + reg = <0x0 0x00100000 0x0 0x1f9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ + <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ + <&sleep_clk>, /* Sleep */ + <0>, /* USB 0 Phy DP0 GMUX */ + <0>, /* USB 0 Phy DP1 GMUX */ + <0>, /* USB 0 Phy PCIE PIPEGMUX */ + <0>, /* USB 0 Phy PIPEGMUX */ + <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 1 Phy DP0 GMUX 2 */ + <0>, /* USB 1 Phy DP1 GMUX 2 */ + <0>, /* USB 1 Phy PCIE PIPEGMUX */ + <0>, /* USB 1 Phy PIPEGMUX */ + <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ + <0>, /* USB 2 Phy DP0 GMUX 2 */ + <0>, /* USB 2 Phy DP1 GMUX 2 */ + <0>, /* USB 2 Phy PCIE PIPEGMUX */ + <0>, /* USB 2 Phy PIPEGMUX */ + <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ + <0>, /* PCIe 3a */ + <&pcie3b_phy>, /* PCIe 3b */ + <&pcie4_phy>, /* PCIe 4 */ + <&pcie5_phy>, /* PCIe 5 */ + <&pcie6_phy>, /* PCIe 6 */ + <0>, /* QUSB4 0 PHY RX 0 */ + <0>, /* QUSB4 0 PHY RX 1 */ + <0>, /* QUSB4 1 PHY RX 0 */ + <0>, /* QUSB4 1 PHY RX 1 */ + <0>, /* QUSB4 2 PHY RX 0 */ + <0>, /* QUSB4 2 PHY RX 1 */ + <0>, /* UFS PHY RX Symbol 0 */ + <0>, /* UFS PHY RX Symbol 1 */ + <0>, /* UFS PHY TX Symbol 0 */ + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, + <0>, /* USB4 PHY 0 pcie pipe */ + <0>, /* USB4 PHY 0 Max pipe */ + <0>, /* USB4 PHY 1 pcie pipe */ + <0>, /* USB4 PHY 1 Max pipe */ + <0>, /* USB4 PHY 2 pcie */ + <0>; /* USB4 PHY 2 Max */ + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpi_dma2: dma-controller@800000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xd76 0x0>; + }; + + qupv3_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xd63 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c16: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c16_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi16: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c17: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c17_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi17: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c18: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c18_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi18: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c19: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c19_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi19: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart19: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart19_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c20: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c20_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi20: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c21: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c21_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi21: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart21: serial@894000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart21_default>; + pinctrl-names = "default"; + }; + + i2c22: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c22_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi22: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart22: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart22_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c23: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0089c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c23_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi23: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0089c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xcb6 0x0>; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xca3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart14: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart14_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma0: dma-controller@b00000 { + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00b00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <16>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + iommus = <&apps_smmu 0xd36 0x0>; + }; + + qupv3_0: geniqup@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00bc0000 0x0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + iommus = <&apps_smmu 0xd23 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@b80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@b80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@b84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@b84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@b88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@b88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart2: serial@b88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00b88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c3: i2c@b8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@b8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c4: i2c@b90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@b90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c5: i2c@b94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@b94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c6: i2c@b98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@b98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b98000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c7: i2c@b9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00b9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@b9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00b9c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + usb_hs_phy: phy@fa0000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x00fa0000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status = "disabled"; + }; + + usb_mp_hsphy0: phy@fa1000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x00fa1000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + status = "disabled"; + }; + + usb_mp_hsphy1: phy@fa2000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x00fa2000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + status = "disabled"; + }; + + usb_mp_qmpphy0: phy@fa3000 { + compatible = "qcom,glymur-qmp-usb3-uni-phy"; + reg = <0x0 0x00fa3000 0x0 0x2000>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_0_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names = "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; + + resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names = "phy", + "phy_phy"; + + clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_mp_qmpphy1: phy@fa5000 { + compatible = "qcom,glymur-qmp-usb3-uni-phy"; + reg = <0x0 0x00fa5000 0x0 0x2000>; + + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_1_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names = "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names = "phy", + "phy_phy"; + + clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; + + #clock-cells = <0>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp3_phy: phy@faac00 { + compatible = "qcom,glymur-dp-phy"; + reg = <0x0 0x00faac00 0x0 0x1d0>, + <0x0 0x00faa400 0x0 0x128>, + <0x0 0x00faa800 0x0 0x128>, + <0x0 0x00faa000 0x0 0x358>; + + clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb", + "ref"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_0_hsphy: phy@fd3000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x00fd3000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_0_qmpphy: phy@fd5000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0x0 0x00fd5000 0x0 0x8000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB_0_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + }; + + usb_1_hsphy: phy@fdd000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x00fdd000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status = "disabled"; + }; + + usb_1_qmpphy: phy@fde000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0x0 0x00fde000 0x0 0x8000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_1_CLKREF_EN>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains = <&gcc GCC_USB_1_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; + }; + }; + }; + }; + + + /* cluster0 */ + bwmon_cluster0: pmu@100c400 { + compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x0100c400 0x0 0x600>; + + interrupts = ; + + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000>; + }; + + opp-1 { + opp-peak-kBps = <2188800>; + }; + + opp-2 { + opp-peak-kBps = <5414400>; + }; + + opp-3 { + opp-peak-kBps = <6220800>; + }; + + opp-4 { + opp-peak-kBps = <6835200>; + }; + + opp-5 { + opp-peak-kBps = <8371200>; + }; + + opp-6 { + opp-peak-kBps = <10944000>; + }; + + opp-7 { + opp-peak-kBps = <12748800>; + }; + + opp-8 { + opp-peak-kBps = <14745600>; + }; + + opp-9 { + opp-peak-kBps = <16896000>; + }; + + opp-10 { + opp-peak-kBps = <19046400>; + }; + + opp-11 { + opp-peak-kBps = <21332000>; + }; + }; + }; + + /* cluster1 */ + bwmon_cluster1: pmu@100d400 { + compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x0100d400 0x0 0x600>; + + interrupts = ; + + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + /* cluster2 */ + bwmon_cluster2: pmu@100e400 { + compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x0100e400 0x0 0x600>; + + interrupts = ; + + interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + cnoc_main: interconnect@1500000 { + compatible = "qcom,glymur-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x17080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,glymur-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x6600>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,glymur-system-noc"; + reg = <0x0 0x01680000 0x0 0x1c080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_west_anoc: interconnect@16c0000 { + compatible = "qcom,glymur-pcie-west-anoc"; + reg = <0x0 0x016c0000 0x0 0xf580>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; + }; + + pcie_east_anoc: interconnect@16d0000 { + compatible = "qcom,glymur-pcie-east-anoc"; + reg = <0x0 0x016d0000 0x0 0xf300>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,glymur-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + aggre2_noc: interconnect@1720000 { + compatible = "qcom,glymur-aggre2-noc"; + reg = <0x0 0x01720000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + }; + + aggre3_noc: interconnect@1700000 { + compatible = "qcom,glymur-aggre3-noc"; + reg = <0x0 0x01700000 0x0 0x1d400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + aggre4_noc: interconnect@1740000 { + compatible = "qcom,glymur-aggre4-noc"; + reg = <0x0 0x01740000 0x0 0x14400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,glymur-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_east_slv_noc: interconnect@1900000 { + compatible = "qcom,glymur-pcie-east-slv-noc"; + reg = <0x0 0x01900000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_west_slv_noc: interconnect@1920000 { + compatible = "qcom,glymur-pcie-west-slv-noc"; + reg = <0x0 0x01920000 0x0 0xf180>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie4: pci@1bf0000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01bf0000 0x0 0x3000>, + <0x0 0x78000000 0x0 0xf20>, + <0x0 0x78000f40 0x0 0xa8>, + <0x0 0x78001000 0x0 0x4000>, + <0x0 0x78005000 0x0 0x100000>, + <0x0 0x01bf3000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, + <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, + <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <4>; + num-lanes = <2>; + + operating-points-v2 = <&pcie4_opp_table>; + + msi-map = <0x0 &gic_its 0xc0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_AXI_CLK>, + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_4_BCR>, + <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_4_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + status = "disabled"; + + pcie4_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + }; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie4_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie4_phy: phy@1bf6000 { + compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01bf6000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, + <&gcc GCC_PCIE_4_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_2_CLKREF_EN>, + <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_4_PIPE_CLK>, + <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_4_PHY_BCR>, + <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie4_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie5: pci@1b40000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01b40000 0x0 0x3000>, + <0x0 0x7a000000 0x0 0xf20>, + <0x0 0x7a000f40 0x0 0xa8>, + <0x0 0x7a001000 0x0 0x4000>, + <0x0 0x7a100000 0x0 0x100000>, + <0x0 0x01b43000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, + <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, + <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <5>; + num-lanes = <4>; + + operating-points-v2 = <&pcie5_opp_table>; + + msi-map = <0x0 &gic_its 0xd0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_AXI_CLK>, + <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_5_BCR>, + <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_5_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie5_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + opp-level = <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + opp-level = <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <15753000 1>; + opp-level = <5>; + }; + }; + + pcie5_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie5_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie5_phy: phy@1b50000 { + compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg = <0x0 0x01b50000 0x0 0x10000>; + + clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_5_PHY_BCR>, + <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie5_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie6: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x7e000000 0x0 0xf20>, + <0x0 0x7e000f40 0x0 0xa8>, + <0x0 0x7e001000 0x0 0x4000>, + <0x0 0x7e100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, + <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, + <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <6>; + num-lanes = <2>; + + operating-points-v2 = <&pcie6_opp_table>; + + msi-map = <0x0 &gic_its 0xe0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_6_AUX_CLK>, + <&gcc GCC_PCIE_6_CFG_AHB_CLK>, + <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_6_SLV_AXI_CLK>, + <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_6_BCR>, + <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_6_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + status = "disabled"; + + pcie6_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + }; + + pcie6_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie6_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie6_phy: phy@1c06000 { + compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01c06000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, + <&gcc GCC_PCIE_6_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_4_CLKREF_EN>, + <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_6_PIPE_CLK>, + <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_6_PHY_BCR>, + <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie6_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie3b: pci@1b80000 { + device_type = "pci"; + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; + reg = <0x0 0x01b80000 0x0 0x3000>, + <0x0 0x74000000 0x0 0xf20>, + <0x0 0x74000f40 0x0 0xa8>, + <0x0 0x74001000 0x0 0x4000>, + <0x0 0x74100000 0x0 0x100000>, + <0x0 0x01b83000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, + <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, + <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <7>; + num-lanes = <4>; + + operating-points-v2 = <&pcie3b_opp_table>; + + msi-map = <0x0 &gic_its 0xf0000 0x10000>; + iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, + <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr"; + + assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + resets = <&gcc GCC_PCIE_3B_BCR>, + <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_3B_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + status = "disabled"; + + pcie3b_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* GEN 1 x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* GEN 1 x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* GEN 2 x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* GEN 2 x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* GEN 2 x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* GEN 3 x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* GEN 3 x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* GEN 3 x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* GEN 4 x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* GEN 4 x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* GEN 4 x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + + /* GEN 5 x1 */ + opp-32000000-5 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + opp-level = <5>; + }; + + /* GEN 5 x2 */ + opp-64000000-5 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + opp-level = <5>; + }; + + /* GEN 5 x4 */ + opp-128000000-5 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <15753000 1>; + opp-level = <5>; + }; + }; + + pcie3b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie3b_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie3b_phy: phy@f10000 { + compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; + reg = <0x0 0x00f10000 0x0 0x10000>; + + clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie3b_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fd5000 { + compatible = "qcom,glymur-tcsr", + "syscon"; + reg = <0x0 0x1fd5000 0x0 0x21000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + hsc_noc: interconnect@2000000 { + compatible = "qcom,glymur-hscnoc"; + reg = <0x0 0x02000000 0x0 0x93a080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + ipcc: mailbox@3e04000 { + compatible = "qcom,glymur-ipcc", "qcom,ipcc"; + reg = <0x0 0x03e04000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,glymur-lpass-lpiaon-noc"; + reg = <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,glymur-lpass-lpicx-noc"; + reg = <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,glymur-lpass-ag-noc"; + reg = <0x0 0x07e40000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + usb_2_hsphy: phy@88e0000 { + compatible = "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg = <0x0 0x088e0000 0x0 0x29c>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status = "disabled"; + }; + + usb_2_qmpphy: phy@88e1000 { + compatible = "qcom,glymur-qmp-usb3-dp-phy"; + reg = <0x0 0x088e1000 0x0 0x8000>; + + clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_2_CLKREF_EN>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains = <&gcc GCC_USB_2_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB3PHY_PHY_TERT_BCR>; + reset-names = "phy", + "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + mode-switch; + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_2_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_2_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; + }; + }; + }; + }; + + usb_0: usb@a600000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_EDGE_BOTH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + resets = <&gcc GCC_USB30_PRIM_BCR>; + + iommus = <&apps_smmu 0x1420 0x0>; + phys = <&usb_0_hsphy>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_1: usb@a800000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a800000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 88 IRQ_TYPE_EDGE_BOTH>, + <&pdc 87 IRQ_TYPE_EDGE_BOTH>, + <&pdc 76 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets = <&gcc GCC_USB30_SEC_BCR>; + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + + iommus = <&apps_smmu 0x1460 0x0>; + + phys = <&usb_1_hsphy>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_2: usb@a000000 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a000000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 89 IRQ_TYPE_EDGE_BOTH>, + <&pdc 81 IRQ_TYPE_EDGE_BOTH>, + <&pdc 75 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets = <&gcc GCC_USB30_TERT_BCR>; + power-domains = <&gcc GCC_USB30_TERT_GDSC>; + + iommus = <&apps_smmu 0x420 0x0>; + + phys = <&usb_2_hsphy>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_2_dwc3_ss: endpoint { + remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_hs: usb@a2f8800 { + compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a200000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_EDGE_BOTH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "hs_phy_irq"; + + resets = <&gcc GCC_USB20_PRIM_BCR>; + + power-domains = <&gcc GCC_USB20_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x0ce0 0x0>; + + interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + + phys = <&usb_hs_phy>; + phy-names = "usb2-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode = "host"; + + maximum-speed = "high-speed"; + + status = "disabled"; + }; + + usb_mp: usb@a400000 { + compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; + reg = <0x0 0x0a400000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event_1", + "pwr_event_2", + "hs_phy_1", + "hs_phy_2", + "dp_hs_phy_1", + "dm_hs_phy_1", + "dp_hs_phy_2", + "dm_hs_phy_2", + "ss_phy_1", + "ss_phy_2"; + + resets = <&gcc GCC_USB30_MP_BCR>; + power-domains = <&gcc GCC_USB30_MP_GDSC>; + + iommus = <&apps_smmu 0xda0 0x0>; + + phys = <&usb_mp_hsphy0>, + <&usb_mp_qmpphy0>, + <&usb_mp_hsphy1>, + <&usb_mp_qmpphy1>; + phy-names = "usb2-0", + "usb3-0", + "usb2-1", + "usb3-1"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode = "host"; + + status = "disabled"; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,glymur-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1de0 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,glymur-dpu"; + reg = <0x0 0x0ae01000 0x0 0x93000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + + mdss_intf4_out: endpoint { + remote-endpoint = <&mdss_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + + mdss_intf5_out: endpoint { + remote-endpoint = <&mdss_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + + mdss_intf6_out: endpoint { + remote-endpoint = <&mdss_dp2_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-205000000 { + opp-hz = /bits/ 64 <205000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-660000000 { + opp-hz = /bits/ 64 <660000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-717000000 { + opp-hz = /bits/ 64 <717000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf54000 0x0 0x200>, + <0x0 0xaf54200 0x0 0x200>, + <0x0 0xaf55000 0x0 0xc00>, + <0x0 0xaf56000 0x0 0x400>, + <0x0 0xaf57000 0x0 0x400>, + <0x0 0xaf58000 0x0 0x400>, + <0x0 0xaf59000 0x0 0x400>, + <0x0 0xaf5a000 0x0 0x600>, + <0x0 0xaf5b000 0x0 0x600>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + + mdss_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dp1: displayport-controller@af5c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0xaf5c000 0x0 0x200>, + <0x0 0xaf5c200 0x0 0x200>, + <0x0 0xaf5d000 0x0 0xc00>, + <0x0 0xaf5e000 0x0 0x400>, + <0x0 0xaf5f000 0x0 0x400>, + <0x0 0xaf60000 0x0 0x400>, + <0x0 0xaf61000 0x0 0x400>, + <0x0 0xaf62000 0x0 0x600>, + <0x0 0xaf63000 0x0 0x600>; + + interrupts-extended = <&mdss 13>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp1_in: endpoint { + remote-endpoint = <&mdss_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp1_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp2: displayport-controller@af64000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af64000 0x0 0x200>, + <0x0 0x0af64200 0x0 0x200>, + <0x0 0x0af65000 0x0 0xc00>, + <0x0 0x0af66000 0x0 0x400>, + <0x0 0x0af67000 0x0 0x400>, + <0x0 0x0af68000 0x0 0x400>, + <0x0 0x0af69000 0x0 0x400>, + <0x0 0x0af6a000 0x0 0x600>, + <0x0 0x0af6b000 0x0 0x600>; + + interrupts-extended = <&mdss 14>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp2_in: endpoint { + remote-endpoint = <&mdss_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb_2_qmpphy_dp_in>; + }; + }; + }; + }; + + mdss_dp3: displayport-controller@af6c000 { + compatible = "qcom,glymur-dp"; + reg = <0x0 0x0af6c000 0x0 0x200>, + <0x0 0x0af6c200 0x0 0x200>, + <0x0 0x0af6d000 0x0 0xc00>, + <0x0 0x0af6e000 0x0 0x400>, + <0x0 0x0af6f000 0x0 0x400>, + <0x0 0x0af70000 0x0 0x400>, + <0x0 0x0af71000 0x0 0x400>, + <0x0 0x0af72000 0x0 0x600>, + <0x0 0x0af73000 0x0 0x600>; + + interrupts-extended = <&mdss 15>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss_dp3_phy 0>, + <&mdss_dp3_phy 1>; + + operating-points-v2 = <&mdss_dp0_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dp3_phy>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp3_in: endpoint { + remote-endpoint = <&mdss_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + }; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,glymur-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ + <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss_dp3_phy 0>, /* dp3 */ + <&mdss_dp3_phy 1>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,glymur-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x10000>; + qcom,pdc-ranges = <0 745 51>, + <51 527 47>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <171 4104 36>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c22c000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c22d000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <9>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22e000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22f000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <8>; + + #thermal-sensor-cells = <1>; + }; + + tsens4: thermal-sensor@c230000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c230000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens5: thermal-sensor@c231000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c231000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <8>; + + #thermal-sensor-cells = <1>; + }; + + tsens6: thermal-sensor@c232000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c232000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + tsens7: thermal-sensor@c233000 { + compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c233000 0x0 0x1000>, + <0x0 0x0c229000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <15>; + + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c30f000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c30f000 0x0 0x400>; + }; + + arbiter@c400000 { + compatible = "qcom,glymur-spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c900000 0x0 0x400000>, + <0x0 0x0c4c0000 0x0 0x400000>, + <0x0 0x0c403000 0x0 0x8000>; + reg-names = "core", + "chnls", + "obsrvr", + "chnl_map"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + qcom,channel = <0>; + qcom,ee = <0>; + + spmi_bus0: spmi@c426000 { + reg = <0x0 0x0c426000 0x0 0x4000>, + <0x0 0x0c8c0000 0x0 0x10000>, + <0x0 0x0c42a000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c437000 { + reg = <0x0 0x0c437000 0x0 0x4000>, + <0x0 0x0c8d0000 0x0 0x10000>, + <0x0 0x0c43b000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus2: spmi@c48000 { + reg = <0x0 0x0c448000 0x0 0x4000>, + <0x0 0x0c8e0000 0x0 0x10000>, + <0x0 0x0c44c000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,glymur-tlmm"; + reg = <0x0 0x0f100000 0x0 0xf00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 249>; + wakeup-parent = <&pdc>; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio0", "gpio1"; + function = "qup0_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup0_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio16", "gpio17"; + function = "qup0_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio6", "gpio7"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio14", "gpio15"; + function = "qup0_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins = "gpio40", "gpio41"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins = "gpio54", "gpio55"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins = "gpio64", "gpio65"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins = "gpio68", "gpio69"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c18_data_clk: qup-i2c18-data-clk-state { + /* SDA, SCL */ + pins = "gpio72", "gpio73"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins = "gpio76", "gpio77"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins = "gpio84", "gpio85"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins = "gpio88", "gpio89"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio3"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio7"; + function = "qup0_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio4", "gpio5", "gpio6"; + function = "qup0_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio8", "gpio9", "gpio10"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio15"; + function = "qup0_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio12", "gpio13", "gpio14"; + function = "qup0_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio19"; + function = "qup0_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio16", "gpio17", "gpio18"; + function = "qup0_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio23"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio20", "gpio21", "gpio22"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio5"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio6", "gpio7", "gpio4"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio13"; + function = "qup0_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio14", "gpio15", "gpio12"; + function = "qup0_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio35"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio39"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio36", "gpio37", "gpio38"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio43"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio40", "gpio41", "gpio42"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio47"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio51"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio48", "gpio49", "gpio50"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio56", "gpio57", "gpio58"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio53"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio54", "gpio55", "gpio52"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins = "gpio67"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio64", "gpio65", "gpio66"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins = "gpio71"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio68", "gpio69", "gpio70"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi18_cs: qup-spi18-cs-state { + pins = "gpio75"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi18_data_clk: qup-spi18-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio72", "gpio73", "gpio74"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins = "gpio79"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio76", "gpio77", "gpio78"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins = "gpio83"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio81", "gpio82"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio84", "gpio85", "gpio86"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi22_cs: qup-spi22-cs-state { + pins = "gpio91"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi22_data_clk: qup-spi22-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio88", "gpio89", "gpio90"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi23_cs: qup-spi23-cs-state { + pins = "gpio83"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi23_data_clk: qup-spi23-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio81", "gpio82"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + tx-pins { + pins = "gpio10"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio11"; + function = "qup0_se2"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart14_default: qup-uart14-default-state { + cts-pins { + pins = "gpio56"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio58"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart19_default: qup-uart19-default-state { + cts-pins { + pins = "gpio76"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + rts-pins { + pins = "gpio77"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio78"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio79"; + function = "qup2_se3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart21_default: qup-uart21-default-state { + tx-pins { + pins = "gpio86"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + + qup_uart22_default: qup-uart22-default-state { + tx-pins { + pins = "gpio90"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio91"; + function = "qup2_se6"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,glymur-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-coherent; + }; + + pcie_smmu: iommu@15480000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x15480000 0x0 0x20000>; + interrupts = , + , + ; + interrupt-names = "eventq", "cmdq-sync", "gerror"; + dma-coherent; + #iommu-cells = <1>; + }; + + intc: interrupt-controller@17000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17040000 0x0 0x40000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + watchdog@17600000 { + compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; + reg = <0x0 0x17600000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; + interrupts = ; + #mbox-cells = <1>; + }; + + timer@17810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17810000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x0 0x20000000>; + + frame@17811000 { + reg = <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + + interrupts = , + ; + + frame-number = <0>; + }; + + frame@17813000 { + reg = <0x0 0x17813000 0x1000>; + + interrupts = ; + + frame-number = <1>; + + status = "disabled"; + }; + + frame@17815000 { + reg = <0x0 0x17815000 0x1000>; + + interrupts = ; + + frame-number = <2>; + + status = "disabled"; + }; + + frame@17817000 { + reg = <0x0 0x17817000 0x1000>; + + interrupts = ; + + frame-number = <3>; + + status = "disabled"; + }; + + frame@17819000 { + reg = <0x0 0x17819000 0x1000>; + + interrupts = ; + + frame-number = <4>; + + status = "disabled"; + }; + + frame@1781b000 { + reg = <0x0 0x1781b000 0x1000>; + + interrupts = ; + + frame-number = <5>; + + status = "disabled"; + }; + + frame@1781d000 { + reg = <0x0 0x1781d000 0x1000>; + + interrupts = ; + + frame-number = <6>; + + status = "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible = "qcom,rpmh-rsc"; + label = "apps_rsc"; + reg = <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + power-domains = <&system_pd>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,glymur-rpmh-clk"; + + clocks = <&xo_board>; + clock-names = "xo"; + + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,glymur-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + }; + }; + }; + + nsi_noc: interconnect@1d600000 { + compatible = "qcom,glymur-nsinoc"; + reg = <0x0 0x1d600000 0x0 0x14080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + oobm_ss_noc: interconnect@1f300000 { + compatible = "qcom,glymur-oobm-ss-noc"; + reg = <0x0 0x1f300000 0x0 0x49a00>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system-cache-controller@20400000 { + compatible = "qcom,glymur-llcc"; + reg = <0x0 0x21800000 0x0 0x100000>, + <0x0 0x21a00000 0x0 0x100000>, + <0x0 0x21c00000 0x0 0x100000>, + <0x0 0x21e00000 0x0 0x100000>, + <0x0 0x22800000 0x0 0x100000>, + <0x0 0x22a00000 0x0 0x100000>, + <0x0 0x22c00000 0x0 0x100000>, + <0x0 0x22e00000 0x0 0x100000>, + <0x0 0x23800000 0x0 0x100000>, + <0x0 0x23a00000 0x0 0x100000>, + <0x0 0x23c00000 0x0 0x100000>, + <0x0 0x23e00000 0x0 0x100000>, + <0x0 0x20400000 0x0 0x100000>, + <0x0 0x20600000 0x0 0x100000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc6_base", + "llcc7_base", + "llcc8_base", + "llcc9_base", + "llcc10_base", + "llcc11_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = ; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,glymur-nsp-noc"; + reg = <0x0 0x320c0000 0x0 0x21280>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + imem: sram@81e08000 { + compatible = "mmio-sram"; + reg = <0x0 0x81e08600 0x0 0x300>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81e08600 0x300>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x180>; + }; + + cpu_scp_lpri1: scp-sram-section@180 { + compatible = "arm,scmi-shmem"; + reg = <0x180 0x180>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; + + thermal_zones: thermal-zones { + aoss-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpu-0-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpu-0-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpu-0-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpu-0-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + cpu-0-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + cpu-0-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + cpu-0-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + cpu-0-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + cpu-0-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + cpu-0-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + cpu-0-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + cpu-0-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-0-0-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpullc-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpullc-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + qmx-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + qmx-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + qmx-0-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-0-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + ddr-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_video_0: video-0-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + video-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_video_1: video-1-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + video-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + aoss-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + cpu-1-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + cpu-1-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + cpu-1-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + cpu-1-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-0-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + cpu-1-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-1-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + cpu-1-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-0-thermal { + thermal-sensors = <&tsens2 7>; + + trips { + cpu-1-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-1-thermal { + thermal-sensors = <&tsens2 8>; + + trips { + cpu-1-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-4-0-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + cpu-1-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-4-1-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + cpu-1-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-5-0-thermal { + thermal-sensors = <&tsens2 11>; + + trips { + cpu-1-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-5-1-thermal { + thermal-sensors = <&tsens2 12>; + + trips { + cpu-1-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + aoss-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + cpullc-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + cpullc-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + qmx-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + qmx-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors = <&tsens3 5>; + + trips { + qmx-1-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors = <&tsens3 6>; + + trips { + qmx-1-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors = <&tsens3 7>; + + trips { + qmx-1-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-4-thermal { + thermal-sensors = <&tsens4 0>; + + trips { + aoss-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_0_0: cpu-2-0-0-thermal { + thermal-sensors = <&tsens4 1>; + + trips { + cpu-2-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_0_1: cpu-2-0-1-thermal { + thermal-sensors = <&tsens4 2>; + + trips { + cpu-2-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_1_0: cpu-2-1-0-thermal { + thermal-sensors = <&tsens4 3>; + + trips { + cpu-2-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_1_1: cpu-2-1-1-thermal { + thermal-sensors = <&tsens4 4>; + + trips { + cpu-2-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_2_0: cpu-2-2-0-thermal { + thermal-sensors = <&tsens4 5>; + + trips { + cpu-2-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_2_1: cpu-2-2-1-thermal { + thermal-sensors = <&tsens4 6>; + + trips { + cpu-2-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_3_0: cpu-2-3-0-thermal { + thermal-sensors = <&tsens4 7>; + + trips { + cpu-2-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_3_1: cpu-2-3-1-thermal { + thermal-sensors = <&tsens4 8>; + + trips { + cpu-2-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_4_0: cpu-2-4-0-thermal { + thermal-sensors = <&tsens4 9>; + + trips { + cpu-2-4-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_4_1: cpu-2-4-1-thermal { + thermal-sensors = <&tsens4 10>; + + trips { + cpu-2-4-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_5_0: cpu-2-5-0-thermal { + thermal-sensors = <&tsens4 11>; + + trips { + cpu-2-5-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpu_2_5_1: cpu-2-5-1-thermal { + thermal-sensors = <&tsens4 12>; + + trips { + cpu-2-5-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-5-thermal { + thermal-sensors = <&tsens5 0>; + + trips { + aoss-5-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpullc_2_0: cpullc-2-0-thermal { + thermal-sensors = <&tsens5 1>; + + trips { + cpullc-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_cpuillc_2_1: cpuillc-2-1-thermal { + thermal-sensors = <&tsens5 2>; + + trips { + cpullc-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_qmx_2_0: qmx-2-0-thermal { + thermal-sensors = <&tsens5 3>; + + trips { + qmx-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_qmx_2_1: qmx-2-1-thermal { + thermal-sensors = <&tsens5 4>; + + trips { + qmx-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_qmx_2_2: qmx-2-2-thermal { + thermal-sensors = <&tsens5 5>; + + trips { + qmx-2-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_qmx_2_3: qmx-2-3-thermal { + thermal-sensors = <&tsens5 6>; + + trips { + qmx-2-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_qmx_2_4: qmx-2-4-thermal { + thermal-sensors = <&tsens5 7>; + + trips { + qmx-2-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_aoss_6: aoss-6-thermal { + thermal-sensors = <&tsens6 0>; + + trips { + aoss-6-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_nsphvx_0: nsphvx-0-thermal { + thermal-sensors = <&tsens6 1>; + + trips { + nsphvx-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_nsphvx_1: nsphvx-1-thermal { + thermal-sensors = <&tsens6 2>; + + trips { + nsphvx-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_nsphvx_2: nsphvx-2-thermal { + thermal-sensors = <&tsens6 3>; + + trips { + nsphvx-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_nsphvx_3: nsphvx-3-thermal { + thermal-sensors = <&tsens6 4>; + + trips { + nsphvx-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_nsphmx_0: nsphmx-0-thermal { + thermal-sensors = <&tsens6 5>; + + trips { + nsphmx-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_nsphmx_1: nsphmx-1-thermal { + thermal-sensors = <&tsens6 6>; + + trips { + nsphmx-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_nsphmx_2: nsphmx-2-thermal { + thermal-sensors = <&tsens6 7>; + + trips { + nsphmx-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_nsphmx_3: nsphmx-3-thermal { + thermal-sensors = <&tsens6 8>; + + trips { + nsphmx-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_camera_0: camera-0-thermal { + thermal-sensors = <&tsens6 9>; + + trips { + camera-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_camera_1: camera-1-thermal { + thermal-sensors = <&tsens6 10>; + + trips { + camera-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_ddr_1: ddr-1-thermal { + thermal-sensors = <&tsens6 11>; + + trips { + ddr-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_ddr_2: ddr-2-thermal { + thermal-sensors = <&tsens6 12>; + + trips { + ddr-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_aoss_7: aoss-7-thermal { + thermal-sensors = <&tsens7 0>; + + trips { + aoss-7-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_0_0: gpu-0-0-thermal { + thermal-sensors = <&tsens7 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_0_1: gpu-0-1-thermal { + thermal-sensors = <&tsens7 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_0_2: gpu-0-2-thermal { + thermal-sensors = <&tsens7 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-0-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_1_0: gpu-1-0-thermal { + thermal-sensors = <&tsens7 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_1_1: gpu-1-1-thermal { + thermal-sensors = <&tsens7 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_1_2: gpu-1-2-thermal { + thermal-sensors = <&tsens7 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-1-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_2_0: gpu-2-0-thermal { + thermal-sensors = <&tsens7 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_2_1: gpu-2-1-thermal { + thermal-sensors = <&tsens7 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_2_2: gpu-2-2-thermal { + thermal-sensors = <&tsens7 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-2-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_3_0: gpu-3-0-thermal { + thermal-sensors = <&tsens7 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_3_1: gpu-3-1-thermal { + thermal-sensors = <&tsens7 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpu_3_2: gpu-3-2-thermal { + thermal-sensors = <&tsens7 12>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpu-3-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpuss_0: gpuss-0-thermal { + thermal-sensors = <&tsens7 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + thermal_gpuss_1: gpuss-1-thermal { + thermal-sensors = <&tsens7 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 2390648a248f..460f27dcd6f6 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -616,6 +616,38 @@ platform { sound-dai = <&q6apm>; }; }; + + dp0-dai-link { + link-name = "DP0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dp1-dai-link { + link-name = "DP1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; usb-1-ss0-sbu-mux { @@ -1102,9 +1134,7 @@ edp_bl_reg_en: edp-bl-reg-en-state { pins = "gpio10"; function = "normal"; }; -}; -&pmc8380_3_gpios { pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { pins = "gpio8"; function = "normal"; @@ -1144,6 +1174,22 @@ &pmk8550_pwm { status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &smb2360_0 { status = "okay"; }; @@ -1326,6 +1372,13 @@ rtmr2_default: rtmr2-reset-n-active-state { bias-disable; }; + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { pins = "gpio188"; function = "gpio"; @@ -1461,6 +1514,24 @@ &uart21 { status = "okay"; }; +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + &usb_1_ss0_dwc3_hs { remote-endpoint = <&pmic_glink_ss0_hs_in>; }; @@ -1511,3 +1582,69 @@ &usb_mp_hsphy0 { &usb_mp_hsphy1 { phys = <&eusb6_repeater>; }; + +&thermal_zones { + gpuss-0-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-1-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-2-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-3-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-4-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-5-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-6-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; + + gpuss-7-thermal { + trips { + trip-point0 { + temperature = <105000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index b8e3e04a6fbd..9c5e77df0054 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -447,14 +447,20 @@ &pcie6a_phy { }; &qupv3_0 { + firmware-name = "qcom/x1e80100/qupv3fw.elf"; + status = "okay"; }; &qupv3_1 { + firmware-name = "qcom/x1e80100/qupv3fw.elf"; + status = "okay"; }; &qupv3_2 { + firmware-name = "qcom/x1e80100/qupv3fw.elf"; + status = "okay"; }; @@ -570,12 +576,10 @@ wake-n-pins { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_ss0_hsphy { @@ -593,12 +597,10 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_ss1_hsphy { @@ -616,12 +618,10 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss2 { - status = "okay"; -}; - -&usb_1_ss2_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_ss2_hsphy { @@ -639,11 +639,9 @@ &usb_1_ss2_qmpphy { }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts new file mode 100644 index 000000000000..bfb7cea56df9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts @@ -0,0 +1,1200 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include + +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" + +/ { + model = "Lenovo IdeaCentre Mini 01Q8X10"; + compatible = "lenovo,ideacentre-mini-01q8x10", "qcom,x1e80100"; + chassis-type = "desktop"; + + aliases { + serial0 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + mux-controls = <&us_euro_mux_ctrl>; + + vdd-buck-supply = <&vreg_l15b>; + vdd-rxtx-supply = <&vreg_l15b>; + vdd-io-supply = <&vreg_l15b>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + dp-connector { + compatible = "dp-connector"; + type = "full-size"; + + pinctrl-0 = <&usb1_dp_hot_plug_detect>; + pinctrl-names = "default"; + + port { + dp_port_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out_dp>; + }; + }; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&usb2_dp_hot_plug_detect>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_out>; + }; + }; + }; + + us_euro_mux_ctrl: mux-controller { + compatible = "gpio-mux"; + pinctrl-0 = <&us_euro_hs_sel>; + pinctrl-names = "default"; + mux-supply = <&vreg_l16b>; + #mux-control-cells = <0>; + mux-gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_port0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_port0_ss_in: endpoint { + remote-endpoint = <&usb0_retimer_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_port0_sbu_in: endpoint { + remote-endpoint = <&usb0_retimer_sbu_out>; + }; + }; + }; + }; + }; + + vreg_nvme1_3p3: regulator-nvme1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme2_3p3: regulator-nvme2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_v0p9: regulator-v0p9 { + compatible = "regulator-fixed"; + + regulator-name = "V0P9"; + regulator-min-microvolt = <906000>; + regulator-max-microvolt = <906000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_vdd1v8: regulator-vdd1v8 { + compatible = "regulator-fixed"; + + regulator-name = "VDD1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_l15b>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_vdd33_rtmr: regulator-vdd33-rtmr { + compatible = "regulator-fixed"; + + regulator-name = "VDD33_RTMR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wifi_3v3>; + }; + + vreg_wifi_3v3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "WIFI_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + }; + + vreg_wifi_1v8: regulator-wifi-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "WIFI_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_l15b>; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-IdeaCentre-Mini"; + audio-routing = "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wifi_1v8>; + vddrfa1p8-supply = <&vreg_wifi_1v8>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l2b: ldo2 { + regulator-name = "VREG_L2B"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b: ldo4 { + regulator-name = "VREG_L4B"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b: ldo13 { + regulator-name = "VREG_L13B"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b: ldo15 { + regulator-name = "VREG_L15B"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b: ldo16 { + regulator-name = "VREG_L16B"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l3c: ldo3 { + regulator-name = "VREG_L3C"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vreg_l1d: ldo1 { + regulator-name = "VREG_L1D"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d: ldo2 { + regulator-name = "VREG_L2D"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d: ldo3 { + regulator-name = "VREG_L3D"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_l2e: ldo2 { + regulator-name = "VREG_L2E"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e: ldo3 { + regulator-name = "VREG_L3E"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vreg_l3i: ldo3 { + regulator-name = "VREG_L3I"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vreg_l1j: ldo1 { + regulator-name = "VREG_L1J"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j: ldo2 { + regulator-name = "VREG_L2J"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j: ldo3 { + regulator-name = "VREG_L3J"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8833", "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_v0p9>; + vdd33-supply = <&vreg_vdd33_rtmr>; + vdd33-cap-supply = <&vreg_vdd33_rtmr>; + vddar-supply = <&vreg_v0p9>; + vddat-supply = <&vreg_v0p9>; + vddio-supply = <&vreg_vdd1v8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&usb0_reset_n>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb0_retimer_out: endpoint { + remote-endpoint = <&pmic_glink_port0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + usb0_retimer_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + usb0_retimer_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_port0_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b>; + vdd1v8-supply = <&vreg_l4b>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b>; + vdd1v8-supply = <&vreg_l4b>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&iris { + firmware-name = "qcom/x1e80100/LENOVO/91B6/qcvss8380.mbn"; + + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/LENOVO/91B6/qcdxkmsuc8380.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vreg_nvme2_3p3>; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; + + status = "okay"; +}; + +&pcie3_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i>; + vdda-pll-supply = <&vreg_l3e>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i>; + vdda-pll-supply = <&vreg_l3e>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme1_3p3>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d>; + vdda-pll-supply = <&vreg_l2j>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550_gpios { + usb0_reset_n: usb0-reset-n-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/LENOVO/91B6/qcadsp8380.mbn", + "qcom/x1e80100/LENOVO/91B6/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/LENOVO/91B6/qccdsp8380.mbn", + "qcom/x1e80100/LENOVO/91B6/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d>; + vdd3-supply = <&vreg_l2b>; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ + <76 4>, /* SPI19 (TZ Protected) */ + <238 1>; /* UFS Reset */ + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + us_euro_hs_sel: us-euro-hs-sel-state { + pins = "gpio68"; + function = "gpio"; + bias-pull-down; + drive-strength = <2>; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_dp_hot_plug_detect: ub1-dp-hot-plug-detect-state { + pins = "gpio124"; + function = "usb1_dp"; + bias-disable; + }; + + usb2_dp_hot_plug_detect: usb2-dp-hot-plug-detect-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_port0_hs_in>; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j>; + vdda12-supply = <&vreg_l2j>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j>; + vdda-pll-supply = <&vreg_l1j>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&usb0_retimer_in>; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j>; + vdda-pll-supply = <&vreg_l2d>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss1_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&dp_port_in>; + }; + }; + }; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j>; + vdda-pll-supply = <&vreg_l2d>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_in>; + }; + }; + }; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e>; + vdda12-supply = <&vreg_l3e>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e>; + vdda12-supply = <&vreg_l3e>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e>; + vdda-pll-supply = <&vreg_l3c>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e>; + vdda-pll-supply = <&vreg_l3c>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 4b0784af4bd3..051dee076416 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -75,6 +75,7 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -91,6 +92,7 @@ cpu1: cpu@100 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -101,6 +103,7 @@ cpu2: cpu@200 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -111,6 +114,7 @@ cpu3: cpu@300 { next-level-cache = <&l2_0>; power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu4: cpu@10000 { @@ -121,6 +125,7 @@ cpu4: cpu@10000 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd4>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -137,6 +142,7 @@ cpu5: cpu@10100 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd5>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu6: cpu@10200 { @@ -147,6 +153,7 @@ cpu6: cpu@10200 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu7: cpu@10300 { @@ -157,6 +164,7 @@ cpu7: cpu@10300 { next-level-cache = <&l2_1>; power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu8: cpu@20000 { @@ -167,6 +175,7 @@ cpu8: cpu@20000 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd8>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; l2_2: l2-cache { compatible = "cache"; @@ -183,6 +192,7 @@ cpu9: cpu@20100 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd9>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu10: cpu@20200 { @@ -193,6 +203,7 @@ cpu10: cpu@20200 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd10>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu11: cpu@20300 { @@ -203,6 +214,7 @@ cpu11: cpu@20300 { next-level-cache = <&l2_2>; power-domains = <&cpu_pd11>, <&scmi_dvfs 2>; power-domain-names = "psci", "perf"; + #cooling-cells = <2>; }; cpu-map { @@ -835,9 +847,9 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <0>, - <0>, - <0>; + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; @@ -3869,6 +3881,122 @@ pcie4_phy: phy@1c0e000 { status = "disabled"; }; + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,x1e80100-qmp-ufs-phy", + "qcom,sm8550-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_PHY_CLKREF_EN>; + + clock-names = "ref", + "ref_aux", + "qref"; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,x1e80100-ufshc", + "qcom,sm8550-ufshc", + "qcom,ufshc"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 = <&ufs_opp_table>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x1a0 0>; + dma-coherent; + + lanes-per-direction = <2>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; @@ -4714,7 +4842,7 @@ sdhc_2: mmc@8804000 { clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; + <&bi_tcxo_div2>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x520 0>; qcom,dll-config = <0x0007642c>; @@ -4767,7 +4895,7 @@ sdhc_4: mmc@8844000 { clocks = <&gcc GCC_SDCC4_AHB_CLK>, <&gcc GCC_SDCC4_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; + <&bi_tcxo_div2>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x160 0>; qcom,dll-config = <0x0007642c>; @@ -4908,9 +5036,9 @@ usb_mp_qmpphy1: phy@88e5000 { status = "disabled"; }; - usb_1_ss2: usb@a0f8800 { - compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; - reg = <0 0x0a0f8800 0 0x400>; + usb_1_ss2: usb@a000000 { + compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a000000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, <&gcc GCC_USB30_TERT_MASTER_CLK>, @@ -4936,11 +5064,13 @@ usb_1_ss2: usb@a0f8800 { assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, <&pdc 58 IRQ_TYPE_EDGE_BOTH>, <&pdc 57 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -4959,61 +5089,47 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, wakeup-source; - #address-cells = <2>; - #size-cells = <2>; - ranges; + iommus = <&apps_smmu 0x14a0 0x0>; + + phys = <&usb_1_ss2_hsphy>, + <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + dma-coherent; status = "disabled"; - usb_1_ss2_dwc3: usb@a000000 { - compatible = "snps,dwc3"; - reg = <0 0x0a000000 0 0xcd00>; + ports { + #address-cells = <1>; + #size-cells = <0>; - interrupts = ; + port@0 { + reg = <0>; - iommus = <&apps_smmu 0x14a0 0x0>; - - phys = <&usb_1_ss2_hsphy>, - <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - - dma-coherent; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_ss2_dwc3_hs: endpoint { - }; + usb_1_ss2_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_ss2_dwc3_ss: endpoint { - remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; - }; + usb_1_ss2_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; }; }; }; }; - usb_2: usb@a2f8800 { - compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; - reg = <0 0x0a2f8800 0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_2: usb@a200000 { + compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a200000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, <&gcc GCC_USB20_MASTER_CLK>, @@ -5038,10 +5154,12 @@ usb_2: usb@a2f8800 { <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <&pdc 50 IRQ_TYPE_EDGE_BOTH>, <&pdc 49 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -5060,31 +5178,26 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, qcom,select-utmi-as-pipe-clk; wakeup-source; + iommus = <&apps_smmu 0x14e0 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + dma-coherent; + status = "disabled"; - usb_2_dwc3: usb@a200000 { - compatible = "snps,dwc3"; - reg = <0 0x0a200000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x14e0 0x0>; - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - - dma-coherent; - - port { - usb_2_dwc3_hs: endpoint { - }; + port { + usb_2_dwc3_hs: endpoint { }; }; }; - usb_mp: usb@a4f8800 { - compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; - reg = <0 0x0a4f8800 0 0x400>; + usb_mp: usb@a400000 { + compatible = "qcom,x1e80100-dwc3-mp", "qcom,snps-dwc3"; + reg = <0 0x0a400000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, <&gcc GCC_USB30_MP_MASTER_CLK>, @@ -5110,7 +5223,8 @@ usb_mp: usb@a4f8800 { assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, @@ -5120,7 +5234,8 @@ usb_mp: usb@a4f8800 { <&pdc 53 IRQ_TYPE_EDGE_BOTH>, <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event_1", "pwr_event_2", + interrupt-names = "dwc_usb3", + "pwr_event_1", "pwr_event_2", "hs_phy_1", "hs_phy_2", "dp_hs_phy_1", "dm_hs_phy_1", "dp_hs_phy_2", "dm_hs_phy_2", @@ -5140,39 +5255,28 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, wakeup-source; - #address-cells = <2>; - #size-cells = <2>; - ranges; + iommus = <&apps_smmu 0x1400 0x0>; + + phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, + <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; + phy-names = "usb2-0", "usb3-0", + "usb2-1", "usb3-1"; + dr_mode = "host"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + dma-coherent; status = "disabled"; - - usb_mp_dwc3: usb@a400000 { - compatible = "snps,dwc3"; - reg = <0 0x0a400000 0 0xcd00>; - - interrupts = ; - - iommus = <&apps_smmu 0x1400 0x0>; - - phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, - <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; - phy-names = "usb2-0", "usb3-0", - "usb2-1", "usb3-1"; - dr_mode = "host"; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - - dma-coherent; - }; }; - usb_1_ss0: usb@a6f8800 { - compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; + usb_1_ss0: usb@a600000 { + compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -5198,11 +5302,13 @@ usb_1_ss0: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, <&pdc 61 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -5214,58 +5320,47 @@ usb_1_ss0: usb@a6f8800 { wakeup-source; - #address-cells = <2>; - #size-cells = <2>; - ranges; + iommus = <&apps_smmu 0x1420 0x0>; + + phys = <&usb_1_ss0_hsphy>, + <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + dma-coherent; status = "disabled"; - usb_1_ss0_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; + ports { + #address-cells = <1>; + #size-cells = <0>; - interrupts = ; + port@0 { + reg = <0>; - iommus = <&apps_smmu 0x1420 0x0>; - - phys = <&usb_1_ss0_hsphy>, - <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - - dma-coherent; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_ss0_dwc3_hs: endpoint { - }; + usb_1_ss0_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_ss0_dwc3_ss: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; - }; + usb_1_ss0_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; }; }; }; }; - usb_1_ss1: usb@a8f8800 { - compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; + usb_1_ss1: usb@a800000 { + compatible = "qcom,x1e80100-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a800000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, @@ -5291,11 +5386,13 @@ usb_1_ss1: usb@a8f8800 { assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, <&pdc 60 IRQ_TYPE_EDGE_BOTH>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -5314,50 +5411,39 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, wakeup-source; - #address-cells = <2>; - #size-cells = <2>; - ranges; + iommus = <&apps_smmu 0x1460 0x0>; + + phys = <&usb_1_ss1_hsphy>, + <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + dma-coherent; status = "disabled"; - usb_1_ss1_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; + ports { + #address-cells = <1>; + #size-cells = <0>; - interrupts = ; + port@0 { + reg = <0>; - iommus = <&apps_smmu 0x1460 0x0>; - - phys = <&usb_1_ss1_hsphy>, - <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - - dma-coherent; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_ss1_dwc3_hs: endpoint { - }; + usb_1_ss1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_ss1_dwc3_ss: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; - }; + usb_1_ss1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; }; }; }; @@ -5432,19 +5518,19 @@ opp-338000000 { opp-366000000 { opp-hz = /bits/ 64 <366000000>; - required-opps = <&rpmhpd_opp_svs_l1>, + required-opps = <&rpmhpd_opp_svs>, <&rpmhpd_opp_svs_l1>; }; opp-444000000 { opp-hz = /bits/ 64 <444000000>; - required-opps = <&rpmhpd_opp_nom>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_nom>; }; opp-481000000 { opp-hz = /bits/ 64 <481000000>; - required-opps = <&rpmhpd_opp_turbo>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_turbo>; }; }; @@ -5658,8 +5744,8 @@ mdss_dp0_out: endpoint { mdss_dp0_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5747,8 +5833,8 @@ mdss_dp1_out: endpoint { mdss_dp1_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5835,8 +5921,8 @@ mdss_dp2_out: endpoint { mdss_dp2_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5918,8 +6004,8 @@ mdss_dp3_out: endpoint { mdss_dp3_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -9230,7 +9316,7 @@ aoss0-critical { }; }; - cpu2-0-top-thermal { + thermal_cpu2_0_top: cpu2-0-top-thermal { thermal-sensors = <&tsens2 1>; trips { @@ -9242,7 +9328,7 @@ cpu-critical { }; }; - cpu2-0-btm-thermal { + thermal_cpu2_0_btm: cpu2-0-btm-thermal { thermal-sensors = <&tsens2 2>; trips { @@ -9254,7 +9340,7 @@ cpu-critical { }; }; - cpu2-1-top-thermal { + thermal_cpu2_1_top: cpu2-1-top-thermal { thermal-sensors = <&tsens2 3>; trips { @@ -9266,7 +9352,7 @@ cpu-critical { }; }; - cpu2-1-btm-thermal { + thermal_cpu2_1_btm: cpu2-1-btm-thermal { thermal-sensors = <&tsens2 4>; trips { @@ -9278,7 +9364,7 @@ cpu-critical { }; }; - cpu2-2-top-thermal { + thermal_cpu2_2_top: cpu2-2-top-thermal { thermal-sensors = <&tsens2 5>; trips { @@ -9290,7 +9376,7 @@ cpu-critical { }; }; - cpu2-2-btm-thermal { + thermal_cpu2_2_btm: cpu2-2-btm-thermal { thermal-sensors = <&tsens2 6>; trips { @@ -9302,7 +9388,7 @@ cpu-critical { }; }; - cpu2-3-top-thermal { + thermal_cpu2_3_top: cpu2-3-top-thermal { thermal-sensors = <&tsens2 7>; trips { @@ -9314,7 +9400,7 @@ cpu-critical { }; }; - cpu2-3-btm-thermal { + thermal_cpu2_3_btm: cpu2-3-btm-thermal { thermal-sensors = <&tsens2 8>; trips { @@ -9326,7 +9412,7 @@ cpu-critical { }; }; - cpuss2-top-thermal { + thermal_cpuss2_top: cpuss2-top-thermal { thermal-sensors = <&tsens2 9>; trips { @@ -9338,7 +9424,7 @@ cpuss2-critical { }; }; - cpuss2-btm-thermal { + thermal_cpuss2_btm: cpuss2-btm-thermal { thermal-sensors = <&tsens2 10>; trips { @@ -9350,7 +9436,7 @@ cpuss2-critical { }; }; - aoss3-thermal { + thermal_aoss3: aoss3-thermal { thermal-sensors = <&tsens3 0>; trips { @@ -9368,7 +9454,7 @@ aoss0-critical { }; }; - nsp0-thermal { + thermal_nsp0: nsp0-thermal { thermal-sensors = <&tsens3 1>; trips { @@ -9386,7 +9472,7 @@ nsp0-critical { }; }; - nsp1-thermal { + thermal_nsp1: nsp1-thermal { thermal-sensors = <&tsens3 2>; trips { @@ -9404,7 +9490,7 @@ nsp1-critical { }; }; - nsp2-thermal { + thermal_nsp2: nsp2-thermal { thermal-sensors = <&tsens3 3>; trips { @@ -9422,7 +9508,7 @@ nsp2-critical { }; }; - nsp3-thermal { + thermal_nsp3: nsp3-thermal { thermal-sensors = <&tsens3 4>; trips { @@ -9440,7 +9526,7 @@ nsp3-critical { }; }; - gpuss-0-thermal { + thermal_gpuss_0: gpuss-0-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 5>; @@ -9467,7 +9553,7 @@ gpu-critical { }; }; - gpuss-1-thermal { + thermal_gpuss_1: gpuss-1-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 6>; @@ -9494,7 +9580,7 @@ gpu-critical { }; }; - gpuss-2-thermal { + thermal_gpuss_2: gpuss-2-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 7>; @@ -9521,7 +9607,7 @@ gpu-critical { }; }; - gpuss-3-thermal { + thermal_gpuss_3: gpuss-3-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 8>; @@ -9548,7 +9634,7 @@ gpu-critical { }; }; - gpuss-4-thermal { + thermal_gpuss_4: gpuss-4-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 9>; @@ -9575,7 +9661,7 @@ gpu-critical { }; }; - gpuss-5-thermal { + thermal_gpuss_5: gpuss-5-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 10>; @@ -9602,7 +9688,7 @@ gpu-critical { }; }; - gpuss-6-thermal { + thermal_gpuss_6: gpuss-6-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 11>; @@ -9629,7 +9715,7 @@ gpu-critical { }; }; - gpuss-7-thermal { + thermal_gpuss_7: gpuss-7-thermal { polling-delay-passive = <200>; thermal-sensors = <&tsens3 12>; @@ -9656,7 +9742,7 @@ gpu-critical { }; }; - camera0-thermal { + thermal_camera0: camera0-thermal { thermal-sensors = <&tsens3 13>; trips { @@ -9674,7 +9760,7 @@ camera0-critical { }; }; - camera1-thermal { + thermal_camera1: camera1-thermal { thermal-sensors = <&tsens3 14>; trips { diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts new file mode 100644 index 000000000000..941f866ecfe9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq5210.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5210 RDP504"; + compatible = "qcom,ipq5210-rdp504", "qcom,ipq5210"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&sdhc { + max-frequency = <192000000>; + bus-width = <4>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + pinctrl-0 = <&sdhc_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + qup_uart1_default_state: qup-uart1-default-state { + pins = "gpio38", "gpio39"; + function = "qup_se1"; + drive-strength = <6>; + bias-pull-down; + }; + + sdhc_default_state: sdhc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&uart1 { + pinctrl-0 = <&qup_uart1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi new file mode 100644 index 000000000000..3761eb03ab24 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&intc>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + }; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scm { + compatible = "qcom,scm-ipq5210", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + bootloader@87800000 { + reg = <0x0 0x87800000 0x0 0x400000>; + no-map; + }; + + smem@87c00000 { + compatible = "qcom,smem"; + reg = <0x0 0x87c00000 0x0 0x40000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + }; + + tfa@87d00000 { + reg = <0x0 0x87d00000 0x0 0x80000>; + no-map; + }; + + optee@87d80000 { + reg = <0x0 0x87d80000 0x0 0x280000>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x10 0>; + ranges = <0 0 0 0 0x10 0>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5210-tlmm"; + reg = <0x0 0x01000000 0x0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq5210-gcc"; + reg = <0x0 0x01800000 0x0 0x40000>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01905000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + qupv3: geniqup@1ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x01ac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, + <&gcc GCC_QUPV3_AHB_SLV_CLK>; + clock-names = "m-ahb", "s-ahb"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + uart1: serial@1a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x01a84000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>; + clock-names = "se"; + interrupts = ; + + status = "disabled"; + }; + }; + + sdhc: mmc@7804000 { + compatible = "qcom,ipq5210-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", + "core", + "xo"; + non-removable; + + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0 0xb000000 0x0 0x1000>, + <0x0 0xb002000 0x0 0x1000>, + <0x0 0xb001000 0x0 0x1000>, + <0x0 0xb004000 0x0 0x1000>; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0x0b00c000 0 0x3000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x0 0x0 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x00001000 0x0 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x00002000 0x0 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0b120000 0x0 0x1000>; + ranges = <0 0 0 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@b121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0x0b123000 0x1000>; + + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0x0b124000 0x1000>; + + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0x0b125000 0x1000>; + + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0x0b126000 0x1000>; + + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0x0b127000 0x1000>; + + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0x0b128000 0x1000>; + + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi index b37ae7749083..8967861be5fd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -78,4 +78,48 @@ gpio_leds_default: gpio-leds-default-state { drive-strength = <8>; bias-pull-down; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins = "gpio13"; + function = "qspi_clk"; + drive-strength = <8>; + bias-disable; + }; + + cs-pins { + pins = "gpio12"; + function = "qspi_cs"; + drive-strength = <8>; + bias-disable; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qspi_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_snand_default_state>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts index ed8a54eb95c0..6e2abde9ed89 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -35,17 +35,6 @@ flash@0 { }; }; -&sdhc { - bus-width = <4>; - max-frequency = <192000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-0 = <&sdc_default_state>; - pinctrl-names = "default"; - status = "okay"; -}; - &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; @@ -54,29 +43,6 @@ i2c_1_pins: i2c-1-state { bias-pull-up; }; - sdc_default_state: sdc-default-state { - clk-pins { - pins = "gpio13"; - function = "sdc_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio12"; - function = "sdc_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio8", "gpio9", "gpio10", "gpio11"; - function = "sdc_data"; - drive-strength = <8>; - bias-pull-up; - }; - }; - spi_0_data_clk_pins: spi-0-data-clk-state { pins = "gpio14", "gpio15", "gpio16"; function = "blsp0_spi"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 45fc512a3bab..e227730d99a6 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -423,6 +423,39 @@ blsp1_spi2: spi@78b7000 { status = "disabled"; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1c000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq5332-snand", "qcom,ipq9574-snand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", + "aon", + "iom"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", + "rx", + "cmd"; + + status = "disabled"; + }; + usb: usb@8af8800 { compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; reg = <0x08af8800 0x400>; diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index 738618551203..de71b72ae6dc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -124,13 +124,6 @@ &qusb_phy_1 { status = "okay"; }; -&sdhc { - pinctrl-0 = <&sdc_default_state>; - pinctrl-names = "default"; - - status = "okay"; -}; - &sleep_clk { clock-frequency = <32000>; }; @@ -201,26 +194,26 @@ mosi-pins { }; }; - sdc_default_state: sdc-default-state { - clk-pins { + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { pins = "gpio5"; - function = "sdc_clk"; + function = "qspi_clk"; drive-strength = <8>; - bias-disable; + bias-pull-down; }; - cmd-pins { + cs-pins { pins = "gpio4"; - function = "sdc_cmd"; + function = "qspi_cs"; drive-strength = <8>; bias-pull-up; }; data-pins { pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "sdc_data"; + function = "qspi_data"; drive-strength = <8>; - bias-pull-up; + bias-pull-down; }; }; @@ -246,6 +239,27 @@ pcie3_default_state: pcie3-default-state { }; }; +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + pinctrl-0 = <&qpic_snand_default_state>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index eb393f3fd728..f20cda429094 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -572,6 +572,39 @@ sdhc: mmc@7804000 { status = "disabled"; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x07984000 0x0 0x1c000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq5424-snand", "qcom,ipq9574-snand"; + reg = <0x0 0x079b0000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", + "aon", + "iom"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", + "rx", + "cmd"; + + status = "disabled"; + }; + intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0 0xf200000 0 0x10000>, /* GICD */ diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index bdb396afb992..62877b46f9b3 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -22,6 +22,15 @@ chosen { stdout-path = "serial0:115200n8"; }; + regulator_fixed_1p8: s1800 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_1p8"; + }; + regulator_fixed_3p3: s3300 { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; @@ -88,11 +97,27 @@ &blsp1_uart2 { status = "okay"; }; +&cpu0 { + cpu-supply = <&mp5496_s1>; +}; + +&cpu1 { + cpu-supply = <&mp5496_s1>; +}; + +&cpu2 { + cpu-supply = <&mp5496_s1>; +}; + +&cpu3 { + cpu-supply = <&mp5496_s1>; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-mp5496-regulators"; - ipq9574_s1: s1 { + mp5496_s1: s1 { /* * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. * During regulator registration, kernel not knowing the initial voltage, @@ -121,6 +146,11 @@ mp5496_l5: l5 { }; }; +&sdhc_1 { + vmmc-supply = <®ulator_fixed_3p3>; + vqmmc-supply = <®ulator_fixed_1p8>; +}; + &sleep_clk { clock-frequency = <32000>; }; @@ -169,6 +199,38 @@ data-pins { bias-disable; }; }; + + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", + "gpio3", "gpio6", "gpio7", + "gpio8", "gpio9"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio10"; + function = "sdc_rclk"; + drive-strength = <8>; + bias-pull-down; + }; + }; }; &qpic_bam { @@ -179,8 +241,6 @@ &qpic_nand { pinctrl-0 = <&qpic_snand_default_state>; pinctrl-names = "default"; - status = "okay"; - flash@0 { compatible = "spi-nand"; reg = <0>; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418-emmc.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418-emmc.dts new file mode 100644 index 000000000000..2cf35c717411 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * IPQ9574 RDP418 (eMMC variant) board device tree source + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq9574-rdp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2 (eMMC)"; + compatible = "qcom,ipq9574-ap-al02-c2-emmc", "qcom,ipq9574"; + +}; + +&sdhc_1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts index f4f9199d4ab1..23d4cba7c6b6 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts @@ -16,48 +16,6 @@ / { }; -&sdhc_1 { - pinctrl-0 = <&sdc_default_state>; - pinctrl-names = "default"; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - max-frequency = <384000000>; - bus-width = <8>; +&qpic_nand { status = "okay"; }; - -&tlmm { - sdc_default_state: sdc-default-state { - clk-pins { - pins = "gpio5"; - function = "sdc_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio4"; - function = "sdc_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio0", "gpio1", "gpio2", - "gpio3", "gpio6", "gpio7", - "gpio8", "gpio9"; - function = "sdc_data"; - drive-strength = <8>; - bias-pull-up; - }; - - rclk-pins { - pins = "gpio10"; - function = "sdc_rclk"; - drive-strength = <8>; - bias-pull-down; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi new file mode 100644 index 000000000000..3422058ac480 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ9574 RDP433 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie2 { + pinctrl-0 = <&pcie2_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie3_phy { + status = "okay"; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&tlmm { + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio25"; + function = "pcie1_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio27"; + function = "pcie1_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie2_default: pcie2-default-state { + clkreq-n-pins { + pins = "gpio28"; + function = "pcie2_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio29"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + + wake-n-pins { + pins = "gpio30"; + function = "pcie2_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio31"; + function = "pcie3_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio32"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio33"; + function = "pcie3_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433-emmc.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-emmc.dts new file mode 100644 index 000000000000..44884231499f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * IPQ9574 RDP433 (eMMC variant) board device tree source + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "ipq9574-rdp-common.dtsi" +#include "ipq9574-rdp433-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7 (eMMC)"; + compatible = "qcom,ipq9574-ap-al02-c7-emmc", "qcom,ipq9574"; +}; + +&sdhc_1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 5a546a14998b..88439697c074 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -8,124 +8,14 @@ /dts-v1/; -#include #include "ipq9574-rdp-common.dtsi" +#include "ipq9574-rdp433-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; }; -&pcie1_phy { +&qpic_nand { status = "okay"; }; - -&pcie1 { - pinctrl-0 = <&pcie1_default>; - pinctrl-names = "default"; - - perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie2_phy { - status = "okay"; -}; - -&pcie2 { - pinctrl-0 = <&pcie2_default>; - pinctrl-names = "default"; - - perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie3_phy { - status = "okay"; -}; - -&pcie3 { - pinctrl-0 = <&pcie3_default>; - pinctrl-names = "default"; - - perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&tlmm { - - pcie1_default: pcie1-default-state { - clkreq-n-pins { - pins = "gpio25"; - function = "pcie1_clk"; - drive-strength = <6>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio26"; - function = "gpio"; - drive-strength = <8>; - bias-pull-down; - output-low; - }; - - wake-n-pins { - pins = "gpio27"; - function = "pcie1_wake"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - pcie2_default: pcie2-default-state { - clkreq-n-pins { - pins = "gpio28"; - function = "pcie2_clk"; - drive-strength = <6>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio29"; - function = "gpio"; - drive-strength = <8>; - bias-pull-down; - output-low; - }; - - wake-n-pins { - pins = "gpio30"; - function = "pcie2_wake"; - drive-strength = <6>; - bias-pull-up; - }; - }; - - pcie3_default: pcie3-default-state { - clkreq-n-pins { - pins = "gpio31"; - function = "pcie3_clk"; - drive-strength = <6>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio32"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - output-low; - }; - - wake-n-pins { - pins = "gpio33"; - function = "pcie3_wake"; - drive-strength = <6>; - bias-pull-up; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts index d36d1078763e..cbc9047cfe92 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts @@ -15,3 +15,7 @@ / { compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574"; }; + +&qpic_nand { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts index c30c9fbedf26..d233ec530cc3 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts @@ -15,3 +15,7 @@ / { compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574"; }; + +&qpic_nand { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts index 0dc382f5d5ec..f2334b9e0ed4 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts @@ -14,3 +14,7 @@ / { model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9"; compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574"; }; + +&qpic_nand { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index d7278f2137ac..622cfa96ed2b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -56,7 +56,6 @@ cpu0: cpu@0 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; }; @@ -69,7 +68,6 @@ cpu1: cpu@1 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; }; @@ -82,7 +80,6 @@ cpu2: cpu@2 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; }; @@ -95,7 +92,6 @@ cpu3: cpu@3 { clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq9574_s1>; #cooling-cells = <2>; }; @@ -467,6 +463,15 @@ sdhc_1: mmc@7804000 { clock-names = "iface", "core", "xo", "ice"; non-removable; supports-cqe; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <384000000>; + bus-width = <8>; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 32a082598434..07247dc98b70 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -5,9 +5,21 @@ /dts-v1/; +#include +#include +#include #include #include "kaanapali.dtsi" +#include "pm8010-kaanapali.dtsi" /* SPMI1: SID-12/13 */ +#include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0104-kaanapali.dtsi" /* SPMI1: SID-9 */ +#include "pmh0110-kaanapali.dtsi" /* SPMI0: SID-3/5/6/8 */ +#include "pmih0108-kaanapali.dtsi" /* SPMI1: SID-7 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "pmr735d-kaanapali.dtsi" /* SPMI1: SID-10 */ + / { model = "Qualcomm Technologies, Inc. Kaanapali MTP"; compatible = "qcom,kaanapali-mtp", "qcom,kaanapali"; @@ -15,6 +27,7 @@ / { aliases { serial0 = &uart7; + serial1 = &uart18; }; chosen { @@ -52,6 +65,193 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-div = <2>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + sound { + compatible = "qcom,kaanapali-sndcard", "qcom,sm8450-sndcard"; + model = "Kaanapali-MTP"; + + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, + <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcd939x: audio-codec { + compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + vdd-px-supply = <&vreg_l1g_1p2>; + + #sound-dai-cells = <1>; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-0 = <&bt_default>, <&sw_ctrl_default>, <&wlan_en>; + pinctrl-names = "default"; + + bt-enable-gpios = <&pmh0104_j_e1_gpios 5 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_s2j_0p8>; + vddio-supply = <&vreg_l2g_1p8>; + vddio1p2-supply = <&vreg_l3g_1p2>; + vddaon-supply = <&vreg_s7g_0p9>; + vdddig-supply = <&vreg_s1j_0p8>; + vddrfa1p2-supply = <&vreg_s7f_1p2>; + vddrfa1p8-supply = <&vreg_s8f_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -175,7 +375,7 @@ vreg_l11b_1p0: ldo11 { vreg_l12b_1p8: ldo12 { regulator-name = "vreg_l12b_1p8"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; regulator-allow-set-load; @@ -665,6 +865,59 @@ vreg_l7n_3p3: ldo7 { }; }; +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l10b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l1d_1p2>; + status = "okay"; + + panel@0 { + compatible = "novatek,nt37801"; + reg = <0>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend + &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active + &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend + &sde_mdp_vsync_p_1p2_active &sde_mdp_vsync_p_1p8_active + &sde_disp0_rst_1p2_active &sde_disp0_rst_1p8_active>; + pinctrl-names = "default", "sleep"; + + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p0>; + vddio-supply = <&vreg_l12b_1p8>; + + reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l3d_0p8>; + + status = "okay"; +}; + &pcie0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -682,6 +935,140 @@ &pcie0_phy { &pcie_port0 { wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pmh0101_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + function-enumerator = <0>; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + function-enumerator = <1>; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pmh0101_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + +&pmh0104_j_e1_gpios { + bt_default: bt-default-state { + pins = "gpio5"; + function = "normal"; + input-disable; + output-enable; + output-low; + bias-disable; + power-source = <1>; + }; +}; + +&pmh0110_d_e0_gpios { + sde_mdp_vsync_p_1p2_active: sde-mdp-vsync-p-1p2-active-state { + pins = "gpio9"; + function = "paired"; + input-disable; + output-enable; + power-source = <2>; /* 1.2v */ + }; + + sde_mdp_vsync_p_1p8_active: sde-mdp-vsync-p-1p8-active-state { + pins = "gpio10"; + function = "paired"; + input-enable; + output-disable; + power-source = <1>; /* 1.8v */ + }; +}; + +&pmh0110_f_e0_gpios { + sde_disp0_rst_1p2_active: sde-disp0-rst-1p2-active-state { + pins = "gpio9"; + function = "paired"; + input-enable; + output-disable; + power-source = <2>; /* 1.2v */ + }; + + sde_disp0_rst_1p8_active: sde-disp0-rst-1p8-active-state { + pins = "gpio10"; + function = "paired"; + input-disable; + output-enable; + power-source = <1>; /* 1.8v */ + }; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/kaanapali/adsp.mbn", + "qcom/kaanapali/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/kaanapali/cdsp.mbn", + "qcom/kaanapali/cdsp_dtb.mbn"; + + status = "okay"; }; &sdhc_2 { @@ -701,12 +1088,169 @@ &sdhc_2 { status = "okay"; }; +&swr0 { + status = "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_0_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 76 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l2i_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l2i_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + &tlmm { gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ <119 2>, /* SoCCP */ <144 4>; /* CXM UART */ + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + + spkr_0_sd_n_active: spkr-0-sd-n-active-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_esync0_suspend: sde-esync0-suspend-state { + pins = "gpio88"; + function = "mdp_esync0_out"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + key_vol_up_default: key-vol-up-default-state { + pins = "gpio101"; + function = "gpio"; + output-disable; + bias-pull-up; + }; + pcie0_default_state: pcie0-default-state { perst-n-pins { pins = "gpio102"; @@ -729,12 +1273,37 @@ wake-n-pins { bias-pull-up; }; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio161"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; &uart7 { status = "okay"; }; +&uart18 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + + max-speed = <3200000>; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 66b423a497b3..da0e8f9091c3 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -5,9 +5,21 @@ /dts-v1/; +#include +#include +#include #include #include "kaanapali.dtsi" +#include "pm8010-kaanapali.dtsi" /* SPMI1: SID-12/13 */ +#include "pmd8028-kaanapali.dtsi" /* SPMI1: SID-4 */ +#include "pmh0101.dtsi" /* SPMI0: SID-1 */ +#include "pmh0104-kaanapali.dtsi" /* SPMI1: SID-9 */ +#include "pmh0110-kaanapali.dtsi" /* SPMI0: SID-3/5/6/8 */ +#include "pmih0108-kaanapali.dtsi" /* SPMI1: SID-7 */ +#include "pmk8850.dtsi" /* SPMI0: SID-0 */ +#include "pmr735d-kaanapali.dtsi" /* SPMI1: SID-10 */ + / { model = "Qualcomm Technologies, Inc. Kaanapali QRD"; compatible = "qcom,kaanapali-qrd", "qcom,kaanapali"; @@ -52,6 +64,22 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-div = <2>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; }; &apps_rsc { @@ -665,6 +693,63 @@ vreg_l7n_3p3: ldo7 { }; }; +&pmh0101_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + function-enumerator = <0>; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + function-enumerator = <1>; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pmh0101_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; @@ -682,11 +767,32 @@ &sdhc_2 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/kaanapali/adsp.mbn", + "qcom/kaanapali/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/kaanapali/cdsp.mbn", + "qcom/kaanapali/cdsp_dtb.mbn"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ <119 2>, /* SoCCP */ <144 4>; /* CXM UART */ + + key_vol_up_default: key-vol-up-default-state { + pins = "gpio101"; + function = "gpio"; + output-disable; + bias-pull-up; + }; }; &uart7 { diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 9ef57ad0ca71..7cc326aa1a1a 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3,9 +3,17 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include +#include +#include #include +#include +#include +#include #include #include +#include #include #include #include @@ -15,7 +23,9 @@ #include #include #include +#include #include +#include #include "kaanapali-ipcc.h" @@ -442,6 +452,58 @@ rmtfs_mem: rmtfs@d7c00000 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -468,6 +530,508 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x1f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x436 0x0>; + dma-coherent; + }; + + qupv3_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x423 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c8: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c9: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi9: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c10: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi10: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c11: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi11: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0088c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c12: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + i2c_master_hub: geniqup@9c0000 { + compatible = "qcom,geni-se-i2c-master-hub"; + reg = <0x0 0x009c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + clock-names = "s-ahb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c_hub_0: i2c@980000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00980000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00984000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00988000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c2_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x0098c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00990000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x1f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xb6 0x0>; + dma-coherent; + }; + qupv3_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x2000>; @@ -485,6 +1049,447 @@ qupv3_1: geniqup@ac0000 { #size-cells = <2>; ranges; + i2c0: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c4: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c5: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c6: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart7: serial@a9c000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a9c000 0x0 0x4000>; @@ -559,6 +1564,24 @@ aggre_noc: interconnect@16e0000 { <&rpmhcc RPMH_IPA_CLK>; }; + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,kaanapali-cambistmclkcc"; + reg = <0x0 0x01760000 0x0 0x8000>; + + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + mmss_noc: interconnect@1780000 { compatible = "qcom,kaanapali-mmss-noc"; reg = <0x0 0x01780000 0x0 0x5b800>; @@ -566,6 +1589,653 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; + gpi_dma3: dma-controller@1900000 { + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x01900000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x1e>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x4d6 0x0>; + dma-coherent; + }; + + qupv3_3: geniqup@19c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x019c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x4c3 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c13: i2c@1980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01980000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, + <&gpi_dma3 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c14: i2c@1984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01984000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 1 QCOM_GPI_I2C>, + <&gpi_dma3 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi14: spi@1984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01984000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma3 0 1 QCOM_GPI_SPI>, + <&gpi_dma3 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c15: i2c@1988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01988000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 2 QCOM_GPI_I2C>, + <&gpi_dma3 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi15: spi@1988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01988000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma3 0 2 QCOM_GPI_SPI>, + <&gpi_dma3 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c16: i2c@198c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0198c000 0x0 0x4000>; + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 3 QCOM_GPI_I2C>, + <&gpi_dma3 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c16_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi16: spi@198c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x198c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma3 0 3 QCOM_GPI_SPI>, + <&gpi_dma3 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c17: i2c@1990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01990000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma3 0 4 QCOM_GPI_I2C>, + <&gpi_dma3 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c17_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi17: spi@1990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01990000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma3 0 4 QCOM_GPI_SPI>, + <&gpi_dma3 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart18: serial@1994000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x01994000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP3_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart18_default>, <&qup_uart18_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + gpi_dma4: dma-controller@1a00000 { + compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x01a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x1e>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x536 0x0>; + dma-coherent; + }; + + qupv3_4: geniqup@1ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x01ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_4_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_4_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x523 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c19: i2c@1a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 0 QCOM_GPI_I2C>, + <&gpi_dma4 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c19_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi19: spi@1a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma4 0 0 QCOM_GPI_SPI>, + <&gpi_dma4 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c20: i2c@1a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 1 QCOM_GPI_I2C>, + <&gpi_dma4 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c20_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi20: spi@1a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma4 0 1 QCOM_GPI_SPI>, + <&gpi_dma4 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c21: i2c@1a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 2 QCOM_GPI_I2C>, + <&gpi_dma4 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c21_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi21: spi@1a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x01a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma4 0 2 QCOM_GPI_SPI>, + <&gpi_dma4 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c22: i2c@1a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 3 QCOM_GPI_I2C>, + <&gpi_dma4 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c22_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c23: i2c@1a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP4_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma4 0 4 QCOM_GPI_I2C>, + <&gpi_dma4 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c23_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; @@ -887,6 +2557,354 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + videocc: clock-controller@20f0000 { + compatible = "qcom,kaanapali-videocc"; + reg = <0x0 0x020f0000 0x0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,kaanapali-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,kaanapali-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + remoteproc_adsp: remoteproc@6800000 { + compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; + reg = <0x0 0x06800000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <2>; + + label = "lpass"; + + fastrpc { + compatible = "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1041 0x20>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + + lpass_wsa2macro: codec@6aa0000 { + compatible = "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06aa0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + }; + + swr3: soundwire@6ab0000 { + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg = <0 0x06ab0000 0 0x10000>; + interrupts = ; + clocks = <&lpass_wsa2macro>; + clock-names = "iface"; + label = "WSA2"; + + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible = "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; + reg = <0x0 0x06ac0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr1: soundwire@6ad0000 { + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg = <0 0x06ad0000 0 0x10000>; + interrupts = ; + clocks = <&lpass_rxmacro>; + clock-names = "iface"; + label = "RX"; + + pinctrl-0 = <&rx_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <1>; + qcom,dout-ports = <11>; + + qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_txmacro: codec@6ae0000 { + compatible = "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; + reg = <0x0 0x06ae0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,kaanapali-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06b00000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr0: soundwire@6b10000 { + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg = <0 0x06b10000 0 0x10000>; + interrupts = ; + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + label = "WSA"; + + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,kaanapali-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -901,6 +2919,168 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + swr2: soundwire@7630000 { + compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; + reg = <0 0x07630000 0 0x10000>; + interrupts-extended = <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core", "wakeup"; + clocks = <&lpass_txmacro>; + clock-names = "iface"; + label = "TX"; + + pinctrl-0 = <&tx_swr_active>; + pinctrl-names = "default"; + + qcom,din-ports = <4>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_vamacro: codec@7660000 { + compatible = "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; + reg = <0 0x07660000 0 0x2000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible = "qcom,sm8750-lpass-lpi-pinctrl", + "qcom,sm8650-lpass-lpi-pinctrl"; + reg = <0 0x07760000 0 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + lpass_ag_noc: interconnect@7f40000 { compatible = "qcom,kaanapali-lpass-ag-noc"; reg = <0x0 0x07f40000 0x0 0xe080>; @@ -958,6 +3138,290 @@ opp-202000000 { }; }; + camcc: clock-controller@956d000 { + compatible = "qcom,kaanapali-camcc"; + reg = <0x0 0x0956d000 0x0 0x80000>; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + mdss: display-subsystem@9800000 { + compatible = "qcom,kaanapali-mdss"; + reg = <0x0 0x09800000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_AHB_SWI_CLK>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@9801000 { + compatible = "qcom,kaanapali-dpu"; + reg = <0x0 0x09801000 0x0 0x1c8000>, + <0x0 0x09b16000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + }; + }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz = /bits/ 64 <207000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@9ac0000 { + compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x09ac0000 0x0 0x1000>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-312500000 { + opp-hz = /bits/ 64 <312500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@9ac1000 { + compatible = "qcom,kaanapali-dsi-phy-3nm"; + reg = <0x0 0x09ac1000 0x0 0x1cc>, + <0x0 0x09ac1200 0x0 0x280>, + <0x0 0x09ac1500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@9ba2000 { + compatible = "qcom,kaanapali-dispcc"; + reg = <0x0 0x09ba2000 0x0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <0>, + <0>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,kaanapali-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, @@ -992,6 +3456,90 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + tsens0: thermal-sensor@c229000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c22a000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22a000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <12>; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22b000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22b000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <7>; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22c000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22c000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <4>; + #thermal-sensor-cells = <1>; + }; + + tsens4: thermal-sensor@c22d000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22d000 0x0 0x1000>, + <0x0 0x0c226000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <8>; + #thermal-sensor-cells = <1>; + }; + + tsens5: thermal-sensor@c22e000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22e000 0x0 0x1000>, + <0x0 0x0c227000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <12>; + #thermal-sensor-cells = <1>; + }; + + tsens6: thermal-sensor@c22f000 { + compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22f000 0x0 0x1000>, + <0x0 0x0c228000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <7>; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-management@c300000 { compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; @@ -1006,6 +3554,53 @@ IPCC_MPROC_SIGNAL_GLINK_QMP #clock-cells = <0>; }; + arbiter@c400000 { + compatible = "qcom,kaanapali-spmi-pmic-arb", "qcom,glymur-spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c900000 0x0 0x400000>, + <0x0 0x0c4c0000 0x0 0x400000>, + <0x0 0x0c403000 0x0 0x8000>; + reg-names = "core", + "chnls", + "obsrvr", + "chnl_map"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + qcom,channel = <0>; + qcom,ee = <0>; + + spmi_bus0: spmi@c426000 { + reg = <0x0 0x0c426000 0x0 0x4000>, + <0x0 0x0c8c0000 0x0 0x10000>, + <0x0 0x0c42a000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c437000 { + reg = <0x0 0x0c437000 0x0 0x4000>, + <0x0 0x0c8d0000 0x0 0x10000>, + <0x0 0x0c43b000 0x0 0x8000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,kaanapali-tlmm"; reg = <0x0 0x0f100000 0x0 0x300000>; @@ -1017,6 +3612,491 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; wakeup-parent = <&pdc>; + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio66", "gpio67"; + function = "i2chub0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio78", "gpio79"; + function = "i2chub0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio68", "gpio69"; + function = "i2chub0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio70", "gpio71"; + function = "i2chub0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio72", "gpio73"; + function = "i2chub0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio83"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio74", "gpio75"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio40", "gpio41"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio0", "gpio1"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins = "gpio117", "gpio118"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins = "gpio122", "gpio123"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins = "gpio208", "gpio209"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins = "gpio64", "gpio65"; + function = "qup3_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "qup3_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup3_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk-state { + /* SDA, SCL */ + pins = "gpio16", "gpio17"; + function = "qup3_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup3_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk-state { + /* SDA, SCL */ + pins = "gpio48", "gpio49"; + function = "qup4_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk-state { + /* SDA, SCL */ + pins = "gpio28", "gpio29"; + function = "qup4_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup4_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c22_data_clk: qup-i2c22-data-clk-state { + /* SDA, SCL */ + pins = "gpio121", "gpio84"; + function = "qup4_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c23_data_clk: qup-i2c23-data-clk-state { + /* SDA, SCL */ + pins = "gpio161", "gpio162"; + function = "qup4_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio81"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio83", "gpio82"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio77"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio74", "gpio75", "gpio76"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio43"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio40", "gpio41", "gpio42"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio47"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio39"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio36", "gpio37", "gpio38"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio56", "gpio57", "gpio58"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio3"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */pins = "gpio0", "gpio1", "gpio2"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio7"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio4", "gpio5", "gpio6"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio120"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio117", "gpio118", "gpio119"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio125"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio122", "gpio123", "gpio124"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio11"; + function = "qup3_se1"; + drive-strength = <6>; + bias-pull-up; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio8", "gpio9", "gpio10"; + function = "qup3_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio15"; + function = "qup3_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio12", "gpio13", "gpio14"; + function = "qup3_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_cs: qup-spi16-cs-state { + pins = "gpio19"; + function = "qup3_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi16_data_clk: qup-spi16-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio16", "gpio17", "gpio18"; + function = "qup3_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_cs: qup-spi17-cs-state { + pins = "gpio23"; + function = "qup3_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi17_data_clk: qup-spi17-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio20", "gpio21", "gpio22"; + function = "qup3_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs-state { + pins = "gpio51"; + function = "qup4_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio48", "gpio49", "gpio50"; + function = "qup4_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs-state { + pins = "gpio31"; + function = "qup4_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_data_clk: qup-spi20-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio28", "gpio29", "gpio30"; + function = "qup4_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_cs: qup-spi21-cs-state { + pins = "gpio35"; + function = "qup4_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi21_data_clk: qup-spi21-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup4_se2"; + drive-strength = <6>; + bias-disable; + }; + qup_uart7_default: qup-uart7-state { /* TX, RX */ pins = "gpio62", "gpio63"; @@ -1025,6 +4105,22 @@ qup_uart7_default: qup-uart7-state { bias-disable; }; + qup_uart18_default: qup-uart18-default-state { + /* TX, RX */ + pins = "gpio26", "gpio27"; + function = "qup3_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart18_cts_rts: qup-uart18-cts-rts-state { + /* CTS, RTS */ + pins = "gpio24", "gpio25"; + function = "qup3_se5"; + drive-strength = <2>; + bias-pull-down; + }; + sdc2_default: sdc2-default-state { clk-pins { pins = "sdc2_clk"; @@ -1080,6 +4176,1114 @@ card-detect-pins { }; }; + stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in7>; + }; + }; + }; + }; + + tpdm@10003000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10003000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_dcc_out: endpoint { + remote-endpoint = <&tpda_qdss_in0>; + }; + }; + }; + }; + + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_qdss_in0: endpoint { + remote-endpoint = <&tpdm_dcc_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint = <&tpdm_spdm_out>; + }; + }; + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint = <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint = <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_in0_in0: endpoint { + remote-endpoint = <&tn_ag_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_in0_in6: endpoint { + remote-endpoint = <&tpda_qdss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_in0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&funnel_aoss_in6>; + }; + }; + }; + }; + + tpdm@11000000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11000000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_modem0_out: endpoint { + remote-endpoint = <&tpda_modem_in0>; + }; + }; + }; + }; + + tpda@11004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_modem_in0: endpoint { + remote-endpoint = <&tpdm_modem0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_modem_in1: endpoint { + remote-endpoint = <&tpdm_modem1_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_modem_in2: endpoint { + remote-endpoint = <&tpdm_modem2_out>; + }; + }; + }; + + out-ports { + port { + tpda_modem_out: endpoint { + remote-endpoint = <&funnel_modem_dl_in0>; + }; + }; + }; + }; + + funnel@11005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11005000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_modem_dl_in0: endpoint { + remote-endpoint = <&tpda_modem_out>; + }; + }; + }; + + out-ports { + port { + funnel_modem_dl_out: endpoint { + remote-endpoint = <&tn_ag_in13>; + }; + }; + }; + }; + + tpdm@1102c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1102c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_gcc_out: endpoint { + remote-endpoint = <&tn_ag_in17>; + }; + }; + }; + }; + + tpdm@11180000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11180000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint = <&tpda_cdsp_in0>; + }; + }; + }; + }; + + tpdm@11183000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11183000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_cmsr1_out: endpoint { + remote-endpoint = <&tpda_cdsp_in3>; + }; + }; + }; + }; + + tpdm@11184000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11184000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_cmsr2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in4>; + }; + }; + }; + }; + + tpdm@11185000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11185000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_cdsp_dpm1_out: endpoint { + remote-endpoint = <&tpda_cdsp_in5>; + }; + }; + }; + }; + + tpdm@11186000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11186000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_cdsp_dpm2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in6>; + }; + }; + }; + }; + + tpda@11188000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11188000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_cdsp_in0: endpoint { + remote-endpoint = <&tpdm_cdsp_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_cdsp_in1: endpoint { + remote-endpoint = <&tpdm_cdsp_llm_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_cdsp_in2: endpoint { + remote-endpoint = <&tpdm_cdsp_llm2_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_cdsp_in3: endpoint { + remote-endpoint = <&tpdm_cdsp_cmsr1_out>; + }; + }; + + port@4 { + reg = <4>; + + tpda_cdsp_in4: endpoint { + remote-endpoint = <&tpdm_cdsp_cmsr2_out>; + }; + }; + + port@5 { + reg = <5>; + + tpda_cdsp_in5: endpoint { + remote-endpoint = <&tpdm_cdsp_dpm1_out>; + }; + }; + + port@6 { + reg = <6>; + + tpda_cdsp_in6: endpoint { + remote-endpoint = <&tpdm_cdsp_dpm2_out>; + }; + }; + }; + + out-ports { + port { + tpda_cdsp_out: endpoint { + remote-endpoint = <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11189000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint = <&tpda_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out: endpoint { + remote-endpoint = <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@111a3000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_pmu_out: endpoint { + remote-endpoint = <&tn_ag_in29>; + }; + }; + }; + }; + + tpdm@111a4000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qrng_out: endpoint { + remote-endpoint = <&tn_ag_in18>; + }; + }; + }; + }; + + tpdm@111a5000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a5000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_dlmm_out: endpoint { + remote-endpoint = <&tn_ag_in25>; + }; + }; + }; + }; + + tpdm@111a6000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a6000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_north_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in26>; + }; + }; + }; + }; + + tpdm@111a7000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a7000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_south_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in27>; + }; + }; + }; + }; + + tpdm@111a8000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a8000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb0_out: endpoint { + remote-endpoint = <&tn_ag_in30>; + }; + }; + }; + }; + + tpdm@111a9000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111a9000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb1_out: endpoint { + remote-endpoint = <&tn_ag_in31>; + }; + }; + }; + }; + + tpdm@111aa000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111aa000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_rdpm_cmb2_out: endpoint { + remote-endpoint = <&tn_ag_in32>; + }; + }; + }; + }; + + tpdm@111ab000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111ab000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb0_out: endpoint { + remote-endpoint = <&tn_ag_in36>; + }; + }; + }; + }; + + tpdm@111ac000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111ac000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb1_out: endpoint { + remote-endpoint = <&tn_ag_in28>; + }; + }; + }; + }; + + tpdm@111ad000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111ad000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb2_out: endpoint { + remote-endpoint = <&tn_ag_in34>; + }; + }; + }; + }; + + tpdm@111ae000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111ae000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb3_out: endpoint { + remote-endpoint = <&tn_ag_in37>; + }; + }; + }; + }; + + tpdm@111af000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111af000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_ipcc_cmb4_out: endpoint { + remote-endpoint = <&tn_ag_in35>; + }; + }; + }; + }; + + tpdm@111b3000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111b3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_pcie_rscc_out: endpoint { + remote-endpoint = <&tn_ag_in8>; + }; + }; + }; + }; + + tn@111b8000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x0 0x111b8000 0x0 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + + tn_ag_in8: endpoint { + remote-endpoint = <&tpdm_pcie_rscc_out>; + }; + }; + + port@d { + reg = <0xd>; + + tn_ag_in13: endpoint { + remote-endpoint = <&funnel_modem_dl_out>; + }; + }; + + port@10 { + reg = <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint = <&funnel_cdsp_out>; + }; + }; + + port@11 { + reg = <0x11>; + + tn_ag_in17: endpoint { + remote-endpoint = <&tpdm_gcc_out>; + }; + }; + + port@12 { + reg = <0x12>; + + tn_ag_in18: endpoint { + remote-endpoint = <&tpdm_qrng_out>; + }; + }; + + port@13 { + reg = <0x13>; + + tn_ag_in19: endpoint { + remote-endpoint = <&tpdm_qm_out>; + }; + }; + + port@15 { + reg = <0x15>; + + tn_ag_in21: endpoint { + remote-endpoint = <&tpdm_ipa_out>; + }; + }; + + port@19 { + reg = <0x19>; + + tn_ag_in25: endpoint { + remote-endpoint = <&tpdm_dlmm_out>; + }; + }; + + port@1a { + reg = <0x1a>; + + tn_ag_in26: endpoint { + remote-endpoint = <&tpdm_north_dsb_out>; + }; + }; + + port@1b { + reg = <0x1b>; + + tn_ag_in27: endpoint { + remote-endpoint = <&tpdm_south_dsb_out>; + }; + }; + + port@1c { + reg = <0x1c>; + + tn_ag_in28: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb1_out>; + }; + }; + + port@1d { + reg = <0x1d>; + + tn_ag_in29: endpoint { + remote-endpoint = <&tpdm_pmu_out>; + }; + }; + + port@1e { + reg = <0x1e>; + + tn_ag_in30: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb0_out>; + }; + }; + + port@1f { + reg = <0x1f>; + + tn_ag_in31: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb1_out>; + }; + }; + + port@20 { + reg = <0x20>; + + tn_ag_in32: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb2_out>; + }; + }; + + port@22 { + reg = <0x22>; + + tn_ag_in34: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb2_out>; + }; + }; + + port@23 { + reg = <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb4_out>; + }; + }; + + port@24 { + reg = <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb0_out>; + }; + }; + + port@25 { + reg = <37>; + + tn_ag_in37: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb3_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint = <&funnel_in0_in0>; + }; + }; + }; + }; + + tpdm@111d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x111d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint = <&tn_ag_in19>; + }; + }; + }; + }; + + tpdm@11303000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11303000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio4_out: endpoint { + remote-endpoint = <&tpda_aoss_in4>; + }; + }; + }; + }; + + funnel@11304000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x11304000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@5 { + reg = <5>; + + funnel_aoss_in5: endpoint { + remote-endpoint = <&tpda_aoss_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_aoss_in6: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out: endpoint { + remote-endpoint = <&tmc_etf_in>; + }; + }; + }; + }; + + tmc@11305000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x11305000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint = <&funnel_aoss_out>; + }; + }; + }; + }; + + tpda@11308000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x11308000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_aoss_in0: endpoint { + remote-endpoint = <&tpdm_swao_prio0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_aoss_in1: endpoint { + remote-endpoint = <&tpdm_swao_prio1_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_aoss_in2: endpoint { + remote-endpoint = <&tpdm_swao_prio2_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_aoss_in3: endpoint { + remote-endpoint = <&tpdm_swao_prio3_out>; + }; + }; + + port@4 { + reg = <4>; + + tpda_aoss_in4: endpoint { + remote-endpoint = <&tpdm_swao_prio4_out>; + }; + }; + + port@5 { + reg = <5>; + + tpda_aoss_in5: endpoint { + remote-endpoint = <&tpdm_swao_out>; + }; + }; + }; + + out-ports { + port { + tpda_aoss_out: endpoint { + remote-endpoint = <&funnel_aoss_in5>; + }; + }; + }; + }; + + tpdm@11309000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11309000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio0_out: endpoint { + remote-endpoint = <&tpda_aoss_in0>; + }; + }; + }; + }; + + tpdm@1130a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1130a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio1_out: endpoint { + remote-endpoint = <&tpda_aoss_in1>; + }; + }; + }; + }; + + tpdm@1130b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1130b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio2_out: endpoint { + remote-endpoint = <&tpda_aoss_in2>; + }; + }; + }; + }; + + tpdm@1130c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1130c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_swao_prio3_out: endpoint { + remote-endpoint = <&tpda_aoss_in3>; + }; + }; + }; + }; + + tpdm@1130d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1130d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_out: endpoint { + remote-endpoint = <&tpda_aoss_in5>; + }; + }; + }; + }; + + tpdm@11422000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x11422000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_ipa_out: endpoint { + remote-endpoint = <&tn_ag_in21>; + }; + }; + }; + }; + sram@14680000 { compatible = "qcom,kaanapali-imem", "mmio-sram"; reg = <0x0 0x14680000 0x0 0x1000>; @@ -1239,7 +5443,7 @@ intc: interrupt-controller@17000000 { gic_its: msi-controller@17040000 { compatible = "arm,gic-v3-its"; - reg = <0x0 0x17040000 0x0 0x20000>; + reg = <0x0 0x17040000 0x0 0x40000>; msi-controller; #msi-cells = <1>; @@ -1476,8 +5680,165 @@ nsp_noc: interconnect@260c0000 { #interconnect-cells = <2>; }; + remoteproc_cdsp: remoteproc@26300000 { + compatible = "qcom,kaanapali-cdsp-pas", "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x26300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,kaanapali-fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x19c1 0x0>, + <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x0c21 0x0>, + <&apps_smmu 0x0c01 0x40>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x0c42 0x0>, + <&apps_smmu 0x19c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c23 0x0>, + <&apps_smmu 0x0c03 0x40>, + <&apps_smmu 0x19c3 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c44 0x0>, + <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x19c4 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c45 0x0>, + <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x19c5 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x0c46 0x0>, + <&apps_smmu 0x19c6 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c27 0x0>, + <&apps_smmu 0x0c07 0x40>, + <&apps_smmu 0x19c7 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x0c48 0x0>, + <&apps_smmu 0x19c8 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c2c 0x00>, + <&apps_smmu 0x0c0c 0x40>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x40>, + <&apps_smmu 0x0c2e 0x0>, + <&apps_smmu 0x0c2d 0x0>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + }; + }; + }; + /* Cluster 0 */ - pmu@310b3400 { + pmu@310b3400 { compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0x0 0x310b3400 0x0 0x600>; @@ -1538,7 +5899,7 @@ opp-10 { }; /* Cluster 1 */ - pmu@310b7400 { + pmu@310b7400 { compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0x0 0x310b7400 0x0 0x600>; @@ -1595,6 +5956,997 @@ pdp_tx: scp-sram-section@100 { }; }; + thermal-zones { + cpullc-0-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + cpullc-0-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpullc-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpullc-0-1-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpullc-0-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpullc-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-0-0-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + qmx-0-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-0-1-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + qmx-0-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-0-2-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + qmx-0-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-0-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + cpu-0-0-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpu-0-0-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpu-0-1-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + cpu-0-1-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + cpu-0-2-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-2-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + cpu-0-2-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-2-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + cpu-0-3-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-3-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + cpu-0-3-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-3-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + cpu-0-4-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-4-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + cpu-0-4-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-4-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors = <&tsens1 10>; + + trips { + cpu-0-5-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-5-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors = <&tsens1 11>; + + trips { + cpu-0-5-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-5-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpullc-1-0-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + cpullc-1-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpullc-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpullc-1-1-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + cpullc-1-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpullc-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-0-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + qmx-1-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-1-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + qmx-1-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-2-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + qmx-1-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-3-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + qmx-1-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + qmx-1-4-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + qmx-1-4-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + qmx-1-4-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + cpu-1-0-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + cpu-1-0-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + cpu-1-1-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + cpu-1-1-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx-0-thermal { + thermal-sensors = <&tsens4 0>; + + trips { + nsphvx-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx-1-thermal { + thermal-sensors = <&tsens4 1>; + + trips { + nsphvx-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx-2-thermal { + thermal-sensors = <&tsens4 2>; + + trips { + nsphvx-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx-3-thermal { + thermal-sensors = <&tsens4 3>; + + trips { + nsphvx-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx-0-thermal { + thermal-sensors = <&tsens4 4>; + + trips { + nsphmx-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx-1-thermal { + thermal-sensors = <&tsens4 5>; + + trips { + nsphmx-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx-2-thermal { + thermal-sensors = <&tsens4 6>; + + trips { + nsphmx-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx-3-thermal { + thermal-sensors = <&tsens4 7>; + + trips { + nsphmx-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors = <&tsens5 0>; + + trips { + gpuss-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors = <&tsens5 1>; + + trips { + gpuss-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-2-thermal { + thermal-sensors = <&tsens5 2>; + + trips { + gpuss-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors = <&tsens5 3>; + + trips { + gpuss-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors = <&tsens5 4>; + + trips { + gpuss-4-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-4-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-5-thermal { + thermal-sensors = <&tsens5 5>; + + trips { + gpuss-5-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-5-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-6-thermal { + thermal-sensors = <&tsens5 6>; + + trips { + gpuss-6-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-6-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-7-thermal { + thermal-sensors = <&tsens5 7>; + + trips { + gpuss-7-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-7-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-8-thermal { + thermal-sensors = <&tsens5 8>; + + trips { + gpuss-8-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-8-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-9-thermal { + thermal-sensors = <&tsens5 9>; + + trips { + gpuss-9-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-9-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-10-thermal { + thermal-sensors = <&tsens5 10>; + + trips { + gpuss-10-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-10-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + thermal-sensors = <&tsens5 11>; + + trips { + ddr-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + ddr-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss-0-thermal { + thermal-sensors = <&tsens6 0>; + + trips { + mdmss-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss-1-thermal { + thermal-sensors = <&tsens6 1>; + trips { + mdmss-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss-2-thermal { + thermal-sensors = <&tsens6 2>; + + trips { + mdmss-2-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss-2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss-3-thermal { + thermal-sensors = <&tsens6 3>; + + trips { + mdmss-3-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss-3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-0-thermal { + thermal-sensors = <&tsens6 4>; + + trips { + camera-0-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-1-thermal { + thermal-sensors = <&tsens6 5>; + + trips { + camera-1-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens6 6>; + + trips { + video-hot { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + video-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; @@ -1603,4 +6955,56 @@ timer { , ; }; + + tpdm-cdsp-llm { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm_out: endpoint { + remote-endpoint = <&tpda_cdsp_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in2>; + }; + }; + }; + }; + + tpdm-modem1 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_modem1_out: endpoint { + remote-endpoint = <&tpda_modem_in1>; + }; + }; + }; + }; + + tpdm-modem2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <64>; + + out-ports { + port { + tpdm_modem2_out: endpoint { + remote-endpoint = <&tpda_modem_in2>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 6079e67ea829..988ca5f7c8a0 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2445,7 +2445,7 @@ pcie1_phy: phy@1c0e000 { reg = <0 0x01c0e000 0 0x1000>; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "aux", @@ -2642,6 +2642,8 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + sram = <&ipa_modem_tables>; + status = "disabled"; }; @@ -3036,6 +3038,110 @@ lpass_dmic23_data: dmic23-data-state { bias-pull-down; }; + lpass_i2s1_active: i2s1-active-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + + lpass_i2s1_sleep: i2s1-sleep-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + lpass_i2s2_active: i2s2-active-state { + clk-pins { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio11"; + function = "i2s2_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio12", "gpio13"; + function = "i2s2_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + + lpass_i2s2_sleep: i2s2-sleep-state { + clk-pins { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins = "gpio11"; + function = "i2s2_ws"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins = "gpio12", "gpio13"; + function = "i2s2_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + lpass_rx_swr_clk: rx-swr-clk-state { pins = "gpio3"; function = "swr_rx_clk"; @@ -4849,6 +4955,7 @@ usb_1: usb@a600000 { phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; + usb-role-switch; ports { #address-cells = <1>; @@ -5505,8 +5612,8 @@ port@1 { edp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5604,8 +5711,8 @@ mdss_dp_out: endpoint { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5721,6 +5828,13 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + cam_mclk3_default: cam-mclk3-default-state { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + cci0_default: cci0-default-state { pins = "gpio69", "gpio70"; function = "cci_i2c"; @@ -6577,6 +6691,10 @@ sram@146a5000 { ranges = <0 0 0x146a5000 0x6000>; + ipa_modem_tables: modem-tables@3000 { + reg = <0x3000 0x2000>; + }; + pil-reloc@594c { compatible = "qcom,pil-reloc-info"; reg = <0x594c 0xc8>; diff --git a/arch/arm64/boot/dts/qcom/lemans-el2.dtso b/arch/arm64/boot/dts/qcom/lemans-el2.dtso index ed615dce6c78..621ad930cf54 100644 --- a/arch/arm64/boot/dts/qcom/lemans-el2.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-el2.dtso @@ -10,6 +10,10 @@ /dts-v1/; /plugin/; +&gpu_zap_shader { + status = "disabled"; +}; + &iris { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso new file mode 100644 index 000000000000..268fc6b05d4b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + model = "Qualcomm Technologies, Inc. Lemans-evk IFP Mezzanine"; + + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +ðernet1 { + phy-handle = <&hsgmii_phy1>; + phy-mode = "2500base-x"; + + pinctrl-0 = <ðernet1_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + + nvmem-cells = <&mac_addr1>; + nvmem-cell-names = "mac-address"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy1: ethernet-phy@18 { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x18>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&i2c18 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@52 { + compatible = "giantec,gt24c256c", "atmel,24c256"; + reg = <0x52>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_addr1: mac-addr@0 { + reg = <0x0 0x6>; + }; + }; + }; +}; + +&pcie0 { + iommu-map = <0x0 &pcie_smmu 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x1>, + <0x208 &pcie_smmu 0x2 0x1>, + <0x210 &pcie_smmu 0x3 0x1>, + <0x218 &pcie_smmu 0x4 0x1>, + <0x300 &pcie_smmu 0x5 0x1>, + <0x400 &pcie_smmu 0x6 0x1>, + <0x500 &pcie_smmu 0x7 0x1>, + <0x501 &pcie_smmu 0x8 0x1>; +}; + +&pcieport0 { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c18 0x77>; + + resx-gpios = <&tlmm 140 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&serdes1 { + phy-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&tlmm { + ethernet1_default: ethernet1-default-state { + ethernet1-mdc-pins { + pins = "gpio20"; + function = "emac1_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet1-mdio-pins { + pins = "gpio21"; + function = "emac1_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + tc9563_resx_n: tc9563-resx-state { + pins = "gpio140"; + function = "gpio"; + bias-disable; + /* Reset pin of tc9563 is active low hence set default + * state of this pin to output-high. + */ + output-high; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 90fce947ca7e..c665db6a4595 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -21,6 +21,7 @@ aliases { ethernet0 = ðernet0; mmc1 = &sdhc; serial0 = &uart10; + serial2 = &uart0; }; dmic: audio-codec-0 { @@ -44,7 +45,7 @@ connector-0 { data-role = "dual"; power-role = "dual"; - vbus-supply = <&vbus_supply_regulator_0>; + vbus-supply = <&usb0_vbus>; ports { #address-cells = <1>; @@ -68,6 +69,25 @@ usb0_con_ss_ep: endpoint { }; }; + connector-2 { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + + id-gpios = <&pmm8654au_2_gpios 11 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&expander3 3 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb2_vbus>; + + pinctrl-0 = <&usb2_id>; + pinctrl-names = "default"; + + port { + usb2_con_hs_ep: endpoint { + remote-endpoint = <&usb_2_dwc3_hs>; + }; + }; + }; + edp0-connector { compatible = "dp-connector"; label = "EDP0"; @@ -132,15 +152,24 @@ platform { }; }; - vbus_supply_regulator_0: regulator-vbus-supply-0 { + usb0_vbus: regulator-usb0-vbus { compatible = "regulator-fixed"; - regulator-name = "vbus_supply_0"; + regulator-name = "usb0_vbus"; gpio = <&expander1 2 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; enable-active-high; }; + usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&pmm8654au_1_gpios 9 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + vmmc_sdc: regulator-vmmc-sdc { compatible = "regulator-fixed"; @@ -546,6 +575,11 @@ expander0: gpio@38 { reg = <0x38>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 138 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander0_int>; + pinctrl-names = "default"; }; expander1: gpio@39 { @@ -553,6 +587,11 @@ expander1: gpio@39 { reg = <0x39>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 19 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander1_int>; + pinctrl-names = "default"; }; expander2: gpio@3a { @@ -560,6 +599,11 @@ expander2: gpio@3a { reg = <0x3a>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 139 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander2_int>; + pinctrl-names = "default"; }; expander3: gpio@3b { @@ -567,6 +611,11 @@ expander3: gpio@3b { reg = <0x3b>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 39 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander3_int>; + pinctrl-names = "default"; }; eeprom@50 { @@ -699,6 +748,14 @@ usb0_intr_state: usb0-intr-state { bias-pull-up; power-source = <0>; }; + + usb2_id: usb2-id-state { + pins = "gpio11"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; }; &qup_i2c19_default { @@ -804,6 +861,30 @@ ethernet0_mdio: ethernet0-mdio-pins { }; }; + expander0_int: expander0-int-state { + pins = "gpio138"; + function = "gpio"; + bias-pull-up; + }; + + expander1_int: expander1-int-state { + pins = "gpio19"; + function = "gpio"; + bias-pull-up; + }; + + expander2_int: expander2-int-state { + pins = "gpio139"; + function = "gpio"; + bias-pull-up; + }; + + expander3_int: expander3-int-state { + pins = "gpio39"; + function = "gpio"; + bias-pull-up; + }; + pcie0_default_state: pcie0-default-state { clkreq-pins { pins = "gpio1"; @@ -870,6 +951,10 @@ usb_id: usb-id-state { }; }; +&uart0 { + status = "okay"; +}; + &uart10 { compatible = "qcom,geni-debug-uart"; pinctrl-0 = <&qup_uart10_default>; @@ -922,6 +1007,22 @@ &usb_0_qmpphy { status = "okay"; }; +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3_hs { + remote-endpoint = <&usb2_con_hs_ep>; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 8fb7d1fc6d56..31bd00546d55 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -21,28 +21,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - vreg_12p0: vreg-12p0-regulator { - compatible = "regulator-fixed"; - regulator-name = "VREG_12P0"; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vreg_5p0: vreg-5p0-regulator { - compatible = "regulator-fixed"; - regulator-name = "VREG_5P0"; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&vreg_12p0>; - }; - vreg_1p8: vreg-1p8-regulator { compatible = "regulator-fixed"; regulator-name = "VREG_1P8"; @@ -51,8 +29,6 @@ vreg_1p8: vreg-1p8-regulator { regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - - vin-supply = <&vreg_5p0>; }; vreg_1p0: vreg-1p0-regulator { @@ -75,8 +51,6 @@ vreg_3p0: vreg-3p0-regulator { regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - - vin-supply = <&vreg_12p0>; }; vreg_conn_1p8: vreg_conn_1p8 { diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 808827b83553..fe6e76351823 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -1512,7 +1512,7 @@ i2c20: i2c@898000 { reg = <0x0 0x898000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c20_default>; @@ -1539,7 +1539,7 @@ spi20: spi@898000 { reg = <0x0 0x898000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi20_default>; @@ -1564,7 +1564,7 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, uart20: serial@898000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00898000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart20_default>; @@ -2510,7 +2510,7 @@ i2c13: i2c@a98000 { reg = <0x0 0xa98000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c13_default>; @@ -4270,7 +4270,14 @@ usb_2: usb@a400000 { snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; + usb-role-switch; + status = "disabled"; + + port { + usb_2_dwc3_hs: endpoint { + }; + }; }; tcsr_mutex: hwlock@1f40000 { @@ -4625,19 +4632,19 @@ opp-366000000 { opp-444000000 { opp-hz = /bits/ 64 <444000000>; - required-opps = <&rpmhpd_opp_nom>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_nom>; }; opp-533000000 { opp-hz = /bits/ 64 <533000000>; - required-opps = <&rpmhpd_opp_turbo>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_turbo>; }; opp-560000000 { opp-hz = /bits/ 64 <560000000>; - required-opps = <&rpmhpd_opp_turbo_l1>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_turbo_l1>; }; }; @@ -5404,8 +5411,8 @@ port@1 { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5492,8 +5499,8 @@ port@1 { dp1_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -8575,10 +8582,10 @@ trip-point1 { arch_timer: timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; turing-llm-tpdm { diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts new file mode 100644 index 000000000000..9c8244e892dd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "mahua.dtsi" +#include "glymur-crd.dtsi" + +/delete-node/ &pmcx0102_d_e0; +/delete-node/ &pmcx0102_d0_thermal; +/delete-node/ &pmh0104_i_e0; +/delete-node/ &pmh0104_i0_thermal; +/delete-node/ &pmh0104_j_e0; +/delete-node/ &pmh0104_j0_thermal; + +/ { + model = "Qualcomm Technologies, Inc. Mahua CRD"; + compatible = "qcom,mahua-crd", "qcom,mahua"; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi new file mode 100644 index 000000000000..990a02c6afc1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Mahua is heavily based on Glymur, with some meaningful differences */ +#include "glymur.dtsi" + +/delete-node/ &bwmon_cluster2; +/delete-node/ &cluster2_pd; +/delete-node/ &cpu_map_cluster2; +/delete-node/ &cpu12; +/delete-node/ &cpu13; +/delete-node/ &cpu14; +/delete-node/ &cpu15; +/delete-node/ &cpu16; +/delete-node/ &cpu17; +/delete-node/ &cpu_pd12; +/delete-node/ &cpu_pd13; +/delete-node/ &cpu_pd14; +/delete-node/ &cpu_pd15; +/delete-node/ &cpu_pd16; +/delete-node/ &cpu_pd17; +/delete-node/ &thermal_aoss_6; +/delete-node/ &thermal_aoss_7; +/delete-node/ &thermal_cpu_2_0_0; +/delete-node/ &thermal_cpu_2_0_1; +/delete-node/ &thermal_cpu_2_1_0; +/delete-node/ &thermal_cpu_2_1_1; +/delete-node/ &thermal_cpu_2_2_0; +/delete-node/ &thermal_cpu_2_2_1; +/delete-node/ &thermal_cpu_2_3_0; +/delete-node/ &thermal_cpu_2_3_1; +/delete-node/ &thermal_cpu_2_4_0; +/delete-node/ &thermal_cpu_2_4_1; +/delete-node/ &thermal_cpu_2_5_0; +/delete-node/ &thermal_cpu_2_5_1; +/delete-node/ &thermal_cpuillc_2_1; +/delete-node/ &thermal_cpullc_2_0; +/delete-node/ &thermal_ddr_2; +/delete-node/ &thermal_gpu_3_0; +/delete-node/ &thermal_gpu_3_1; +/delete-node/ &thermal_gpu_3_2; +/delete-node/ &thermal_qmx_2_0; +/delete-node/ &thermal_qmx_2_1; +/delete-node/ &thermal_qmx_2_2; +/delete-node/ &thermal_qmx_2_3; +/delete-node/ &thermal_qmx_2_4; +/delete-node/ &thermal_video_1; +/delete-node/ &tsens6; +/delete-node/ &tsens7; + +&aggre1_noc { + compatible = "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc"; +}; + +&aggre2_noc { + compatible = "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc"; +}; + +&aggre3_noc { + compatible = "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc"; +}; + +&aggre4_noc { + compatible = "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc"; +}; + +&clk_virt { + compatible = "qcom,mahua-clk-virt", "qcom,glymur-clk-virt"; +}; + +&cnoc_main { + compatible = "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main"; +}; + +&config_noc { + compatible = "qcom,mahua-cnoc-cfg"; +}; + +&hsc_noc { + compatible = "qcom,mahua-hscnoc"; +}; + +&lpass_ag_noc { + compatible = "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc"; +}; + +&lpass_lpiaon_noc { + compatible = "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-noc"; +}; + +&lpass_lpicx_noc { + compatible = "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc"; +}; + +&mc_virt { + compatible = "qcom,mahua-mc-virt"; +}; + +&mmss_noc { + compatible = "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc"; +}; + +&nsi_noc { + compatible = "qcom,mahua-nsinoc", "qcom,glymur-nsinoc"; +}; + +&nsp_noc { + compatible = "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc"; +}; + +&oobm_ss_noc { + compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; +}; + +&pcie_east_anoc { + compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; +}; + +&pcie_east_slv_noc { + compatible = "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv-noc"; +}; + +&pcie_west_anoc { + compatible = "qcom,mahua-pcie-west-anoc"; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; +}; + +&pcie_west_slv_noc { + compatible = "qcom,mahua-pcie-west-slv-noc"; +}; + +&system_noc { + compatible = "qcom,mahua-system-noc", "qcom,glymur-system-noc"; +}; + +&thermal_camera_0 { + thermal-sensors = <&tsens4 9>; +}; + +&thermal_camera_1 { + thermal-sensors = <&tsens4 10>; +}; + +&thermal_ddr_1 { + thermal-sensors = <&tsens1 7>; +}; + +&thermal_gpu_0_0 { + thermal-sensors = <&tsens5 1>; +}; + +&thermal_gpu_0_1 { + thermal-sensors = <&tsens5 2>; +}; + +&thermal_gpu_0_2 { + thermal-sensors = <&tsens5 3>; +}; + +&thermal_gpu_1_0 { + thermal-sensors = <&tsens5 4>; +}; + +&thermal_gpu_1_1 { + thermal-sensors = <&tsens5 5>; +}; + +&thermal_gpu_1_2 { + thermal-sensors = <&tsens5 6>; +}; + +&thermal_gpu_2_0 { + thermal-sensors = <&tsens5 7>; +}; + +&thermal_gpu_2_1 { + thermal-sensors = <&tsens5 8>; +}; + +&thermal_gpu_2_2 { + thermal-sensors = <&tsens5 9>; +}; + +&thermal_gpuss_0 { + thermal-sensors = <&tsens5 10>; +}; + +&thermal_gpuss_1 { + thermal-sensors = <&tsens5 11>; +}; + +&thermal_nsphmx_0 { + thermal-sensors = <&tsens4 5>; +}; + +&thermal_nsphmx_1 { + thermal-sensors = <&tsens4 6>; +}; + +&thermal_nsphmx_2 { + thermal-sensors = <&tsens4 7>; +}; + +&thermal_nsphmx_3 { + thermal-sensors = <&tsens4 8>; +}; + +&thermal_nsphvx_0 { + thermal-sensors = <&tsens4 1>; +}; + +&thermal_nsphvx_1 { + thermal-sensors = <&tsens4 2>; +}; + +&thermal_nsphvx_2 { + thermal-sensors = <&tsens4 3>; +}; + +&thermal_nsphvx_3 { + thermal-sensors = <&tsens4 4>; +}; + +&thermal_video_0 { + thermal-sensors = <&tsens1 8>; +}; + +&thermal_zones { + gpuss-2-thermal { + thermal-sensors = <&tsens5 12>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-3-thermal { + thermal-sensors = <&tsens5 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-4-thermal { + thermal-sensors = <&tsens5 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-4-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; +}; + +&tlmm { + compatible = "qcom,mahua-tlmm"; +}; + +&tsens4 { + #qcom,sensors = <11>; +}; + +&tsens5 { + #qcom,sensors = <15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index 52895dd9e4fa..c1899db46e71 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -29,9 +29,19 @@ aliases { gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&volume_up_default>; + pinctrl-0 = <&volume_up_default>, <&hall_sensor_default>; pinctrl-names = "default"; + /* Powered by the always-on vreg_l10b */ + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + key-volume-up { label = "Volume Up"; gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>; @@ -316,6 +326,8 @@ vreg_l10b: ldo10 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + /* Hall sensor VDD */ + regulator-always-on; }; vreg_l11b: ldo11 { @@ -529,6 +541,56 @@ vreg_l11f: ldo11 { }; }; +&cci0 { + status = "okay"; +}; + +&cci0_i2c0 { + /* Main cam: Sony IMX896 @ 0x1a */ + + eeprom@50 { + compatible = "puya,p24c128f", "atmel,24c128"; + reg = <0x50>; + vcc-supply = <&vreg_l6p>; + read-only; + }; + + /* Dongwoon DW9784 VCM/OIS @ 0x72 */ +}; + + +&cci0_i2c1 { + /* Awinic AW86017 VCM @ 0x0c */ + /* UW cam: OmniVision OV13B10 @ 0x36 */ + + eeprom@52 { + compatible = "puya,p24c128f", "atmel,24c128"; + reg = <0x52>; + vcc-supply = <&vreg_l6p>; + read-only; + }; +}; + +&cci1 { + /* cci1_i2c0 is not used for CCI */ + pinctrl-0 = <&cci1_1_default>; + pinctrl-1 = <&cci1_1_sleep>; + + status = "okay"; +}; + +&cci1_i2c1 { + /* Awinic AW86016 VCM @ 0x0c */ + /* Front cam: Samsung S5KKD1 @ 0x3d */ + + eeprom@51 { + compatible = "puya,p24c128f", "atmel,24c128"; + reg = <0x51>; + vcc-supply = <&vreg_l6p>; + read-only; + }; +}; + &gcc { protected-clocks = , , , , @@ -755,6 +817,13 @@ sdc2_card_det_n: sdc2-card-det-state { bias-pull-up; }; + hall_sensor_default: hall-sensor-default-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + pm8008_int_default: pm8008-int-default-state { pins = "gpio125"; function = "gpio"; @@ -767,6 +836,24 @@ &uart5 { status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 167 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l12b>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l5f>; + vccq-max-microamp = <750000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l2b>; + vdda-pll-supply = <&vreg_l4b>; + + status = "okay"; +}; + &usb_1 { dr_mode = "otg"; diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index e1a51d43943f..4a64a98a434b 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -18,7 +18,9 @@ #include #include #include +#include #include +#include / { interrupt-parent = <&intc>; @@ -797,11 +799,13 @@ gcc: clock-controller@100000 { <&sleep_clk>, <0>, /* pcie_0_pipe_clk */ <0>, /* pcie_1_pipe_clk */ - <0>, /* ufs_phy_rx_symbol_0_clk */ - <0>, /* ufs_phy_rx_symbol_1_clk */ - <0>, /* ufs_phy_tx_symbol_0_clk */ + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -1151,6 +1155,129 @@ aggre2_noc: interconnect@1700000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,milos-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + operating-points-v2 = <&ufs_opp_table>; + + iommus = <&apps_smmu 0x60 0>; + + dma-coherent; + + lanes-per-direction = <2>; + qcom,ice = <&ice>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible = "qcom,milos-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; @@ -1214,6 +1341,197 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "lpass"; qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0>, + <&apps_smmu 0x1063 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0>, + <&apps_smmu 0x1064 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0>, + <&apps_smmu 0x1065 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0>, + <&apps_smmu 0x1066 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x0>, + <&apps_smmu 0x1067 0x0>; + dma-coherent; + }; + }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x0>, + <&apps_smmu 0x1061 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + + lpass_tlmm: pinctrl@3440000 { + compatible = "qcom,milos-lpass-lpi-pinctrl"; + reg = <0x0 0x03440000 0x0 0x20000>, + <0x0 0x034d0000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <4>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + drive-strength = <4>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + lpi_i2s2_active: lpi-i2s2-active-state { + clk-pins { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio11"; + function = "i2s2_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio12", "gpio13"; + function = "i2s2_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + + lpi_i2s2_sleep: lpi-i2s2-sleep-state { + clk-pins { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins = "gpio11"; + function = "i2s2_ws"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins = "gpio12", "gpio13"; + function = "i2s2_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; }; }; @@ -1531,6 +1849,72 @@ videocc: clock-controller@aaf0000 { #power-domain-cells = <1>; }; + cci0: cci@ac15000 { + compatible = "qcom,milos-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac15000 0x0 0x1000>; + interrupts = ; + power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>; + clocks = <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "soc_ahb", + "cpas_ahb", + "cci"; + pinctrl-0 = <&cci0_0_default &cci0_1_default>; + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac16000 { + compatible = "qcom,milos-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac16000 0x0 0x1000>; + interrupts = ; + power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>; + clocks = <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "soc_ahb", + "cpas_ahb", + "cci"; + pinctrl-0 = <&cci1_0_default &cci1_1_default>; + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camcc: clock-controller@adb0000 { compatible = "qcom,milos-camcc"; reg = <0x0 0x0adb0000 0x0 0x40000>; @@ -1667,6 +2051,21 @@ tlmm: pinctrl@f100000 { wakeup-parent = <&pdc>; + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio3"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { /* SDA, SCL */ pins = "gpio4", "gpio5"; @@ -1683,29 +2082,6 @@ qup_i2c3_data_clk: qup-i2c3-data-clk-state { bias-pull-up = <2200>; }; - qup_i2c7_data_clk: qup-i2c7-data-clk-state { - /* SDA, SCL */ - pins = "gpio32", "gpio33"; - function = "qup1_se0"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_spi0_cs: qup-spi0-cs-state { - pins = "gpio3"; - function = "qup0_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi0_data_clk: qup-spi0-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio0", "gpio1", "gpio2"; - function = "qup0_se0"; - drive-strength = <6>; - bias-disable; - }; - qup_uart5_default: qup-uart5-default-state { /* TX, RX */ pins = "gpio25", "gpio26"; @@ -1714,10 +2090,10 @@ qup_uart5_default: qup-uart5-default-state { bias-disable; }; - qup_uart11_default: qup-uart11-default-state { - /* TX, RX */ - pins = "gpio50", "gpio51"; - function = "qup1_se4"; + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se0"; drive-strength = <2>; bias-pull-up; }; @@ -1730,6 +2106,14 @@ qup_uart11_cts_rts: qup-uart11-cts-rts-state { bias-pull-down; }; + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins = "gpio50", "gpio51"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + sdc2_default: sdc2-default-state { clk-pins { pins = "gpio62"; @@ -1775,6 +2159,134 @@ data-pins { bias-pull-up; }; }; + + cci0_0_default: cci0-0-default-state { + sda-pins { + pins = "gpio88"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio89"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins = "gpio88"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio89"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins = "gpio90"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio91"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins = "gpio90"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio91"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins = "gpio92"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio93"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins = "gpio92"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio93"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins = "gpio94"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio95"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins = "gpio94"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio95"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; apps_smmu: iommu@15000000 { @@ -1911,7 +2423,7 @@ ppi_cluster1: interrupt-partition-1 { gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; - reg = <0x0 0x17140000 0x0 0x20000>; + reg = <0x0 0x17140000 0x0 0x40000>; msi-controller; #msi-cells = <1>; @@ -2164,6 +2676,101 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0c01 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0c02 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0c06 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x0c07 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x0c08 0x0>; + dma-coherent; + }; + + /* note: secure cb9 in downstream */ + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x0c0c 0x0>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x0c0d 0x0>; + dma-coherent; + }; + + compute-cb@14 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + iommus = <&apps_smmu 0x0c0e 0x0>; + dma-coherent; + }; + + compute-cb@15 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <15>; + iommus = <&apps_smmu 0x0c0f 0x0>; + dma-coherent; + }; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts new file mode 100644 index 000000000000..ca14f0ea4dae --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" +#include "monaco-monza-som.dtsi" + +/ { + model = "Arduino VENTUNO Q"; + compatible = "arduino,monza", "qcom,qcs8300"; + + aliases { + ethernet0 = ðernet0; + i2c1 = &i2c1; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-home { + label = "Home Key"; + linux,code = ; + gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + sound { + compatible = "qcom,qcs8275-sndcard"; + model = "arduino-monza"; + audio-routing = "IN12", "Headset Mic12", + "Headset Mic12", "MICBIAS", + "IN56", "Headset Mic56", + "Headset Mic56", "MICBIAS", + "MIC1", "MICBIAS", + "Headphone", "HPL", + "Headphone", "HPR", + "Receiver", "RCVL", + "Receiver", "RCVR", + "Speaker", "SPKL", + "Speaker", "SPKR"; + + pinctrl-0 = <&quad_mi2s_active>, <&quad_mclk_active>, <&lpi_i2s4_active>; + pinctrl-names = "default"; + + pri-i2s-playback-dai-link { + link-name = "Analog Playback"; + + codec { + sound-dai = <&max98091>; + }; + + cpu { + sound-dai = <&q6apmbedai 137>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + pri-i2s-capture-dai-link { + link-name = "Analog Capture"; + + codec { + sound-dai = <&max98091>; + }; + + cpu { + sound-dai = <&q6apmbedai 138>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + hdmi-mi2s-playback-dai-link { + link-name = "HDMI Playback"; + + codec { + sound-dai = <&adv7535>; + }; + + cpu { + sound-dai = <&q6apmbedai 145>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vdc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdc_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdc_5v: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <20000>; + }; + + vreg_nvme: regulator-3p3-m2 { + compatible = "regulator-fixed"; + regulator-name = "vreg_m2_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; +}; + +ðernet0 { + phy-mode = "2500base-x"; + phy-handle = <&hsgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&i2c12 { + clock-frequency = <400000>; + + status = "okay"; + + max98091: audio-codec@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + pinctrl-0 = <&max98091_default>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_16 */ + clocks = <&q6prmcc LPASS_CLK_ID_MCLK_3 LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; + + adv7535: bridge@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + pinctrl-0 = <&adv7535_default>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 93 IRQ_TYPE_EDGE_FALLING>; + avdd-supply = <&vdc_1v8>; + dvdd-supply = <&vdc_1v8>; + pvdd-supply = <&vdc_1v8>; + a2vdd-supply = <&vdc_1v8>; + v3p3-supply = <&vdc_3v3>; + v1p2-supply = <&vdc_1v8>; + adi,dsi-lanes = <4>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp0_phy { + status = "okay"; +}; + +&mdss_dsi0 { + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&adv7535_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vdc_3v3>; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vreg_nvme>; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + + pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x01 0xff>; + ranges; + reg = <0x010000 0x00 0x00 0x00 0x00>; + + pci@2,0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges; + reg = <0x021000 0x00 0x00 0x00 0x00>; + + usb@0 { + compatible = "pci104c,8241"; + reg = <0 0 0 0 0>; + ti,pwron-active-high; + }; + }; + }; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; +}; + +&tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio5"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio6"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + max98091_default: max98091-default-state { + pins = "gpio16"; + function = "gpio"; + bias-pull-up; + }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio79"; + function = "gpio"; + bias-disable; + }; + + adv7535_default: adv7535-default-state { + pins = "gpio93"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +/* Internally connected to the MCU (e.g. for DFU). */ +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-el2.dtso b/arch/arm64/boot/dts/qcom/monaco-el2.dtso new file mode 100644 index 000000000000..a7e3270f8609 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-el2.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Monaco specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +&gpu_zap_shader { + status = "disabled"; +}; + +&iris { + status = "disabled"; +}; + +&remoteproc_adsp { + iommus = <&apps_smmu 0x2000 0x0>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x19c0 0x0400>; +}; + +&remoteproc_gpdsp { + iommus = <&apps_smmu 0x28a0 0x0>; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso new file mode 100644 index 000000000000..0d5ccd020e6e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 = <&cci1_0_default>; + pinctrl-1 = <&cci1_0_sleep>; + + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&expander2 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam1_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vreg_cam1_2p8>; + + port { + imx577_ep1: endpoint { + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso new file mode 100644 index 000000000000..e6beb4393430 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + model = "Qualcomm Technologies, Inc. Monaco-EVK IFP Mezzanine"; + + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c15 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom1: eeprom@52 { + compatible = "giantec,gt24c256c", "atmel,24c256"; + reg = <0x52>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&pcie0 { + iommu-map = <0x0 &pcie_smmu 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x1>, + <0x208 &pcie_smmu 0x2 0x1>, + <0x210 &pcie_smmu 0x3 0x1>, + <0x218 &pcie_smmu 0x4 0x1>, + <0x300 &pcie_smmu 0x5 0x1>, + <0x400 &pcie_smmu 0x6 0x1>, + <0x500 &pcie_smmu 0x7 0x1>, + <0x501 &pcie_smmu 0x8 0x1>; +}; + +&pcieport0 { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c15 0x77>; + + resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&tlmm { + tc9563_resx_n: tc9563-resx-state { + pins = "gpio124"; + function = "gpio"; + bias-disable; + /* Reset pin of tc9563 is active low hence set default + * state of this pin to output-high. + */ + output-high; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 565418b86b2a..9d17ef7d2caf 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -21,12 +21,32 @@ aliases { ethernet0 = ðernet0; i2c1 = &i2c1; serial0 = &uart7; + serial2 = &uart6; }; chosen { stdout-path = "serial0:115200n8"; }; + connector-2 { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + + id-gpios = <&pmm8620au_0_gpios 9 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&expander6 7 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb2_vbus>; + + pinctrl-0 = <&usb2_id>; + pinctrl-names = "default"; + + port { + usb2_con_hs_ep: endpoint { + remote-endpoint = <&usb_2_dwc3_hs>; + }; + }; + }; + dmic: audio-codec-0 { compatible = "dmic-codec"; #sound-dai-cells = <0>; @@ -38,6 +58,39 @@ max98357a: audio-codec-1 { #sound-dai-cells = <0>; }; + dp-connector-0 { + compatible = "dp-connector"; + label = "DP0"; + type = "mini"; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <<8713sx_dp0_out>; + }; + }; + }; + + dp-connector-1 { + compatible = "dp-connector"; + label = "DP1"; + type = "mini"; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <<8713sx_dp1_out>; + }; + }; + }; + + usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&pmm8650au_1_gpios 7 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + sound { compatible = "qcom,qcs8275-sndcard"; model = "MONACO-EVK"; @@ -77,6 +130,57 @@ platform { }; }; }; + + vreg_cam0_2p8: vreg-cam0-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam0_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + vreg_cam1_2p8: vreg-cam1-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam1_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + vreg_cam2_2p8: vreg-cam2-2p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam2_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <10000>; + + gpio = <&tlmm 75 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam2_avdd_2v8_en_default>; + pinctrl-names = "default"; + }; + + /* This comes from a PMIC handled within the SAIL domain */ + vreg_s2s: vreg-s2s { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2s"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &apps_rsc { @@ -318,6 +422,45 @@ &gpu_zap_shader { firmware-name = "qcom/qcs8300/a623_zap.mbn"; }; +&i2c0 { + status = "okay"; + + bridge@4f { + compatible = "lontium,lt8713sx"; + reg = <0x4f>; + reset-gpios = <&expander5 6 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt8713sx_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8713sx_dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + + port@2 { + reg = <2>; + + lt8713sx_dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; + }; + }; +}; + &i2c1 { pinctrl-0 = <&qup_i2c1_default>; pinctrl-names = "default"; @@ -362,6 +505,11 @@ expander0: gpio@38 { reg = <0x38>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 56 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander0_int>; + pinctrl-names = "default"; }; expander1: gpio@39 { @@ -369,6 +517,11 @@ expander1: gpio@39 { reg = <0x39>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 16 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander1_int>; + pinctrl-names = "default"; }; expander2: gpio@3a { @@ -376,6 +529,11 @@ expander2: gpio@3a { reg = <0x3a>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 95 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander2_int>; + pinctrl-names = "default"; }; expander3: gpio@3b { @@ -383,6 +541,11 @@ expander3: gpio@3b { reg = <0x3b>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander3_int>; + pinctrl-names = "default"; }; expander4: gpio@3c { @@ -390,6 +553,11 @@ expander4: gpio@3c { reg = <0x3c>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 96 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander4_int>; + pinctrl-names = "default"; }; expander5: gpio@3d { @@ -397,6 +565,11 @@ expander5: gpio@3d { reg = <0x3d>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander5_int>; + pinctrl-names = "default"; }; expander6: gpio@3e { @@ -404,6 +577,11 @@ expander6: gpio@3e { reg = <0x3e>; #gpio-cells = <2>; gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&tlmm 52 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&expander6_int>; + pinctrl-names = "default"; }; }; @@ -411,6 +589,30 @@ &iris { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <<8713sx_dp_in>; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + &pcie0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -449,6 +651,21 @@ &pcieport1 { wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; }; +&pmm8620au_0_gpios { + usb2_id: usb2-id-state { + pins = "gpio9"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + +&qup_i2c0_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + &qupv3_id_0 { firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; @@ -477,6 +694,17 @@ &remoteproc_gpdsp { status = "okay"; }; +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; + + no-sd; + no-sdio; + non-removable; + + status = "okay"; +}; + &serdes0 { phy-supply = <&vreg_l4a>; @@ -494,7 +722,6 @@ tpm@0 { }; &tlmm { - pcie0_default_state: pcie0-default-state { wake-pins { pins = "gpio0"; @@ -534,6 +761,18 @@ ethernet0_mdio: ethernet0-mdio-pins { }; }; + expander5_int: expander5-int-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + expander1_int: expander1-int-state { + pins = "gpio16"; + function = "gpio"; + bias-pull-up; + }; + qup_i2c1_default: qup-i2c1-state { pins = "gpio19", "gpio20"; function = "qup0_se1"; @@ -564,12 +803,67 @@ perst-pins { }; }; + expander3_int: expander3-int-state { + pins = "gpio24"; + function = "gpio"; + bias-pull-up; + }; + + expander6_int: expander6-int-state { + pins = "gpio52"; + function = "gpio"; + bias-pull-up; + }; + + expander0_int: expander0-int-state { + pins = "gpio56"; + function = "gpio"; + bias-pull-up; + }; + + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state { + pins = "gpio75"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c15_default: qup-i2c15-state { pins = "gpio91", "gpio92"; function = "qup1_se7"; drive-strength = <2>; bias-pull-up; }; + + expander2_int: expander2-int-state { + pins = "gpio95"; + function = "gpio"; + bias-pull-up; + }; + + expander4_int: expander4-int-state { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart6 { + status = "okay"; }; &uart7 { @@ -613,3 +907,19 @@ &usb_qmpphy { status = "okay"; }; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3_hs { + remote-endpoint = <&usb2_con_hs_ep>; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi new file mode 100644 index 000000000000..9b5ed55939b8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" + +/ { + /* This comes from a PMIC handled within the SAIL domain */ + vreg_s2s: vreg-s2s { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2s"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s5c: smps5 { /* LPDDR VDD2H */ + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { /* LPDDR VDDQ */ + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <512000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { /* LPDDR VDD2L */ + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { /* LPDDR VDD1 */ + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { /* QFPROM */ + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hpd>; + pinctrl-names = "default"; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l5a>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l4a>; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + +&iris { + status = "okay"; +}; + +/* PCIe0 Gen4 x2 */ +&pcie0 { + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>, + <0x200 &pcie_smmu 0x0007 0x1>, + <0x208 &pcie_smmu 0x0002 0x1>, + <0x210 &pcie_smmu 0x0003 0x1>, + <0x218 &pcie_smmu 0x0004 0x1>, + <0x300 &pcie_smmu 0x0005 0x1>, + <0x400 &pcie_smmu 0x0006 0x1>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +/* PCIe1 Gen4 x4 */ +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs8300/qupv3fw.elf"; + status = "okay"; +}; + +/* There is a HW/FW issue preventing proper REFGEN hardware voting + * for the USB2 HS PHY. As a workaround, we force REFGEN to stay + * always‑on in software, matching initial bootloader config. + */ +&refgen { + regulator-always-on; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8300/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8300/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp { + firmware-name = "qcom/qcs8300/gpdsp0.mbn"; + + status = "okay"; +}; + +/* OnSom eMMC */ +&sdhc_1 { + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s2s>; + + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + no-sd; + no-sdio; + non-removable; + + status = "okay"; +}; + +/* Ethernet/SGMII */ +&serdes0 { + phy-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&tlmm { + dp_hpd: dp-hpd-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; +}; + +/* USB0 HS + SS */ +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +/* USB1 HS */ +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 0cb9fd154b68..7b1d57460f1e 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include / { @@ -2239,6 +2241,10 @@ aggre1_noc: interconnect@16c0000 { reg = <0x0 0x016c0000 0x0 0x17080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -2246,6 +2252,7 @@ aggre2_noc: interconnect@1700000 { reg = <0x0 0x01700000 0x0 0x1a080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; pcie_anoc: interconnect@1760000 { @@ -2871,6 +2878,75 @@ q6prmcc: clock-controller { }; }; + lpass_tlmm: pinctrl@3440000 { + compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl"; + reg = <0x0 0x03440000 0x0 0x20000>, + <0x0 0x034d0000 0x0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + quad_mclk_active: quad-mclk-state { + clk-pins { + pins = "gpio5"; + function = "ext_mclk1_c"; + drive-strength = <8>; + bias-disable; + }; + }; + + quad_mi2s_active: quad-active-state { + data-pins { + pins = "gpio2", "gpio3"; + function = "qua_mi2s_data"; + drive-strength = <8>; + bias-disable; + }; + + sclk-pins { + pins = "gpio0"; + function = "qua_mi2s_sclk"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio1"; + function = "qua_mi2s_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + + lpi_i2s4_active: lpi_i2s4-active-state { + data0-pins { + pins = "gpio17"; + function = "i2s4_data"; + drive-strength = <8>; + bias-disable; + }; + + clk-pins { + pins = "gpio12"; + function = "i2s4_clk"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio13"; + function = "i2s4_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,qcs8300-lpass-ag-noc"; reg = <0x0 0x03c40000 0x0 0x17200>; @@ -4745,11 +4821,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "sdhc-ddr", "cpu-sdhc"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + qcom,dll-config = <0x000f64ee>; qcom,ddr-config = <0x80040868>; + bus-width = <8>; supports-cqe; dma-coherent; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "disabled"; sdhc1_opp_table: opp-table { @@ -5108,6 +5194,7 @@ gem_noc: interconnect@9100000 { reg = <0x0 0x9100000 0x0 0xf7080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; }; llcc: system-cache-controller@9200000 { @@ -5176,9 +5263,29 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; + usb-role-switch; wakeup-source; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; usb_2: usb@a400000 { @@ -5237,7 +5344,14 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, qcom,select-utmi-as-pipe-clk; wakeup-source; + usb-role-switch; + status = "disabled"; + + port { + usb_2_dwc3_hs: endpoint { + }; + }; }; iris: video-codec@aa00000 { @@ -5293,19 +5407,19 @@ opp-366000000 { opp-444000000 { opp-hz = /bits/ 64 <444000000>; - required-opps = <&rpmhpd_opp_nom>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_nom>; }; opp-533000000 { opp-hz = /bits/ 64 <533000000>; - required-opps = <&rpmhpd_opp_turbo>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_turbo>; }; opp-560000000 { opp-hz = /bits/ 64 <560000000>; - required-opps = <&rpmhpd_opp_turbo_l1>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_turbo_l1>; }; }; @@ -5324,6 +5438,117 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + cci0: cci@ac13000 { + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac13000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci0_0_default &cci0_1_default>; + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac14000 { + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac14000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci1_0_default &cci1_1_default>; + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci2: cci@ac15000 { + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac15000 0x0 0x1000>; + + interrupts = ; + + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names = "ahb", + "cci"; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 = <&cci2_0_default &cci2_1_default>; + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: isp@ac78000 { compatible = "qcom,qcs8300-camss"; @@ -5578,9 +5803,19 @@ port@0 { reg = <0>; dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; }; }; + + port@1 { + reg = <1>; + + dpu_intf1_out: endpoint { + + remote-endpoint = <&mdss_dsi0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -5608,6 +5843,98 @@ opp-650000000 { }; }; + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,qcs8300-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + refgen-supply = <&refgen>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,qcs8300-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg = <0x0 0x0ae94400 0x0 0x200>, + <0x0 0x0ae94600 0x0 0x280>, + <0x0 0x0ae94900 0x0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + status = "disabled"; + }; + mdss_dp0_phy: phy@aec2a00 { compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; @@ -5702,8 +6029,8 @@ port@1 { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5735,7 +6062,9 @@ dispcc: clock-controller@af00000 { <&mdss_dp0_phy 0>, <&mdss_dp0_phy 1>, <0>, <0>, - <0>, <0>, <0>, <0>; + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; #clock-cells = <1>; #reset-cells = <1>; @@ -5881,6 +6210,225 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; wakeup-parent = <&pdc>; + cam0_default: cam0-default-state { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam1_default: cam1-default-state { + pins = "gpio68"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam2_default: cam2-default-state { + pins = "gpio69"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cci0_0_default: cci0-0-default-state { + sda-pins { + pins = "gpio57"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio58"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins = "gpio57"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio58"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins = "gpio29"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio30"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins = "gpio29"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio30"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins = "gpio59"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio60"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins = "gpio59"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio60"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins = "gpio31"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio32"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins = "gpio31"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio32"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_0_default: cci2-0-default-state { + sda-pins { + pins = "gpio61"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio62"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci2_0_sleep: cci2-0-sleep-state { + sda-pins { + pins = "gpio61"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio62"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cci2_1_default: cci2-1-default-state { + sda-pins { + pins = "gpio54"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + scl-pins { + pins = "gpio55"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + }; + + cci2_1_sleep: cci2-1-sleep-state { + sda-pins { + pins = "gpio54"; + function = "cci_i2c_sda"; + drive-strength = <2>; + bias-pull-down; + }; + + scl-pins { + pins = "gpio55"; + function = "cci_i2c_scl"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + dp_hot_plug_det: dp-hot-plug-det-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins = "gpio106", "gpio107", "gpio108", "gpio109"; function = "hs0_mi2s"; @@ -7197,6 +7745,55 @@ compute-cb@4 { <&apps_smmu 0x1964 0x0400>; dma-coherent; }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x19c5 0x0400>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x19c6 0x0400>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x19c7 0x0400>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x19c8 0x0400>; + dma-coherent; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x19c9 0x0400>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <0xb>; + iommus = <&apps_smmu 0x19cb 0x0400>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <0xc>; + iommus = <&apps_smmu 0x19cc 0x000>; + dma-coherent; + }; }; }; }; @@ -7712,9 +8309,9 @@ cpuss1-critical { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts index fba68bf8bf79..aed90c8089aa 100644 --- a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts +++ b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts @@ -16,6 +16,15 @@ &battery { constant-charge-voltage-max-microvolt = <4350000>; }; +&charger { + richtek,usb-connector = <&usb_con_sm5502>; + status = "okay"; +}; + +&muic_sm5502 { + status = "okay"; +}; + &st_accel { status = "okay"; }; @@ -23,3 +32,12 @@ &st_accel { &st_magn { status = "okay"; }; + +&usb { + extcon = <&muic_sm5502>, <&muic_sm5502>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic_sm5502>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-coreprimeltevzw.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-coreprimeltevzw.dts new file mode 100644 index 000000000000..40415b5635ef --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-coreprimeltevzw.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-rossa-common.dtsi" + +/ { + model = "Samsung Galaxy Core Prime LTE Verizon Wireless"; + compatible = "samsung,coreprimeltevzw", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&battery { + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <700000>; + constant-charge-voltage-max-microvolt = <4400000>; +}; + +&charger { + richtek,usb-connector = <&usb_con_sm5502>; + status = "okay"; +}; + +&mpss_mem { + /* Firmware for coreprimeltevzw needs more space */ + reg = <0x0 0x86800000 0x0 0x5400000>; +}; + +&muic_sm5502 { + status = "okay"; +}; + +&s3fwrn5_nfc { + status = "disabled"; +}; + +&usb { + extcon = <&muic_sm5502>, <&muic_sm5502>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic_sm5502>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index fb790b02736a..fd62e82075c4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -144,14 +144,31 @@ reg_vdd_tsp_a: regulator-vdd-tsp-a { &blsp_i2c1 { status = "okay"; - muic: extcon@25 { + /* MUIC/extcon varies depending on model variant */ + muic_sm5504: extcon@14 { + compatible = "siliconmitus,sm5504-muic"; + reg = <0x14>; + interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&muic_int_default>; + pinctrl-names = "default"; + status = "disabled"; + + usb_con_sm5504: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; + }; + + muic_sm5502: extcon@25 { compatible = "siliconmitus,sm5502-muic"; reg = <0x25>; interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&muic_int_default>; pinctrl-names = "default"; + status = "disabled"; - usb_con: connector { + usb_con_sm5502: connector { compatible = "usb-b-connector"; label = "micro-USB"; type = "micro"; @@ -298,7 +315,7 @@ rt5033_reg_safe_ldo: SAFE_LDO { charger: charger { compatible = "richtek,rt5033-charger"; monitored-battery = <&battery>; - richtek,usb-connector = <&usb_con>; + status = "disabled"; }; }; }; @@ -348,15 +365,6 @@ &sound { "AMIC3", "MIC BIAS External1"; }; -&usb { - extcon = <&muic>, <&muic>; - status = "okay"; -}; - -&usb_hs_phy { - extcon = <&muic>; -}; - &venus { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts index 677e4e286ac0..15dcfe8234d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts @@ -86,7 +86,7 @@ rt5033_reg_safe_ldo: SAFE_LDO { charger: charger { compatible = "richtek,rt5033-charger"; monitored-battery = <&battery>; - richtek,usb-connector = <&usb_con>; + richtek,usb-connector = <&usb_con_sm5502>; }; }; }; @@ -95,3 +95,16 @@ &mpss_mem { /* Firmware for gprimeltecan needs more space */ reg = <0x0 0x86800000 0x0 0x5400000>; }; + +&muic_sm5502 { + status = "okay"; +}; + +&usb { + extcon = <&muic_sm5502>, <&muic_sm5502>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic_sm5502>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts index 582bfcb09684..268277c1caf4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts @@ -24,7 +24,25 @@ &bosch_magn { status = "okay"; }; +&charger { + richtek,usb-connector = <&usb_con_sm5502>; + status = "okay"; +}; + &mpss_mem { /* Firmware for grandprimelte needs more space */ reg = <0x0 0x86800000 0x0 0x5400000>; }; + +&muic_sm5502 { + status = "okay"; +}; + +&usb { + extcon = <&muic_sm5502>, <&muic_sm5502>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic_sm5502>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index e33453c3e51e..5b08f0e11105 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -2,28 +2,9 @@ #include "msm8916-samsung-fortuna-common.dtsi" -/* SM5504 MUIC instead of SM5502 */ -/delete-node/ &muic; - /* IST3038 instead of Zinitix BT541 */ /delete-node/ &touchscreen; -&blsp_i2c1 { - muic: extcon@14 { - compatible = "siliconmitus,sm5504-muic"; - reg = <0x14>; - interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; - pinctrl-0 = <&muic_int_default>; - pinctrl-names = "default"; - - usb_con: connector { - compatible = "usb-b-connector"; - label = "micro-USB"; - type = "micro"; - }; - }; -}; - &blsp_i2c5 { touchscreen: touchscreen@50 { compatible = "imagis,ist3038"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts index 1981bb71f6a9..a5106afc3c59 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts @@ -16,7 +16,25 @@ &battery { constant-charge-voltage-max-microvolt = <4400000>; }; +&charger { + richtek,usb-connector = <&usb_con_sm5504>; + status = "okay"; +}; + &mpss_mem { /* Firmware for rossa needs more space */ reg = <0x0 0x86800000 0x0 0x5800000>; }; + +&muic_sm5504 { + status = "okay"; +}; + +&usb { + extcon = <&muic_sm5504>, <&muic_sm5504>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic_sm5504>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wiko-chuppito.dts b/arch/arm64/boot/dts/qcom/msm8916-wiko-chuppito.dts new file mode 100644 index 000000000000..262d9a959e6a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-wiko-chuppito.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" + +#include +#include +#include + +/ { + model = "Wiko Pulp 4G"; + compatible = "wiko,chuppito", "qcom,msm8916"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8916_pwm 0 100000>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <255>; + enable-gpios = <&tlmm 119 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&button_backlight_default>; + pinctrl-names = "default"; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + label = "Hall Effect Sensor"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + label = "Buttons"; + + button-volume-up { + label = "Volume up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + vdd-supply = <&pm8916_l17>; + vid-supply = <&pm8916_l6>; + reset-gpios = <&tlmm 120 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&mag_reset_default>; + pinctrl-names = "default"; + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "1"; + }; + + proximity@48 { + compatible = "sensortek,stk3310"; + reg = <0x48>; + interrupts-extended = <&tlmm 113 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&proximity_int_default>; + pinctrl-names = "default"; + }; + + imu@68 { + compatible = "invensense,mpu6880"; + reg = <0x68>; + interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + pinctrl-0 = <&imu_int_default>; + pinctrl-names = "default"; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@39 { + compatible = "syna,rmi4-i2c"; + reg = <0x39>; + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8916_l17>; + vio-supply = <&pm8916_l6>; + pinctrl-0 = <&touchscreen_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + syna,startup-delay-ms = <100>; + syna,reset-delay-ms = <160>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp_uart2 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5600000>; +}; + +&pm8916_codec { + qcom,hphl-jack-type-normally-open; +}; + +&pm8916_mpps { + pwm_out: mpp4-state { + pins = "mpp4"; + function = "digital"; + power-source = ; + output-low; + qcom,dtest = <1>; + }; +}; + +&pm8916_pwm { + pinctrl-0 = <&pwm_out>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pm8916_resin { + linux,code = ; + + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + +&pm8916_vib { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default>, <&sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&sound { + audio-routing = "AMIC1", "MIC BIAS Internal1", + "AMIC2", "MIC BIAS Internal2"; +}; + +&tlmm { + button_backlight_default: button-backlight-default-state { + pins = "gpio119"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + imu_int_default: imu-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + mag_reset_default: mag-reset-default-state { + pins = "gpio120"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + proximity_int_default: proximity-int-default-state { + pins = "gpio113"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen_default: touchscreen-default-state { + touchscreen-pins { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + reset-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&venus { + status = "okay"; +}; + +&venus_mem { + status = "okay"; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts index 9db503e21888..4ea4fbdb5ce7 100644 --- a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-riva.dts @@ -5,28 +5,13 @@ /dts-v1/; -#include -#include -#include "msm8917.dtsi" -#include "pm8937.dtsi" - -/delete-node/ &qseecom_mem; +#include "msm8917-xiaomi-wingtech.dtsi" / { model = "Xiaomi Redmi 5A (riva)"; compatible = "xiaomi,riva", "qcom,msm8917"; - chassis-type = "handset"; - qcom,msm-id = ; - qcom,board-id = <0x1000b 2>, <0x2000b 2>; - - pwm_backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pm8937_pwm 0 100000>; - brightness-levels = <0 255>; - num-interpolated-steps = <255>; - default-brightness-level = <128>; - }; + qcom,board-id = <0x1000b 1>, <0x1000b 2>; battery: battery { compatible = "simple-battery"; @@ -38,96 +23,18 @@ battery: battery { charge-term-current-microamp = <60000>; voltage-min-design-microvolt = <3400000>; }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - stdout-path = "framebuffer0"; - - framebuffer0: framebuffer@90001000 { - compatible = "simple-framebuffer"; - reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>; - width = <720>; - height = <1280>; - stride = <(720 * 3)>; - format = "r8g8b8"; - - clocks = <&gcc GCC_MDSS_AHB_CLK>, - <&gcc GCC_MDSS_AXI_CLK>, - <&gcc GCC_MDSS_VSYNC_CLK>, - <&gcc GCC_MDSS_MDP_CLK>, - <&gcc GCC_MDSS_BYTE0_CLK>, - <&gcc GCC_MDSS_PCLK0_CLK>, - <&gcc GCC_MDSS_ESC0_CLK>; - power-domains = <&gcc MDSS_GDSC>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&gpio_keys_default>; - pinctrl-names = "default"; - - key-volup { - label = "Volume Up"; - linux,code = ; - gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; - debounce-interval = <15>; - }; - }; - - vph_pwr: regulator-vph-pwr { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - regulator-boot-on; - }; - - reserved-memory { - qseecom_mem: qseecom@84a00000 { - reg = <0x0 0x84a00000 0x0 0x1900000>; - no-map; - }; - - framebuffer_mem: memory@90001000 { - reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>; - no-map; - }; - }; -}; - -&blsp1_i2c3 { - status = "okay"; - - touchscreen@38 { - compatible = "edt,edt-ft5306"; - reg = <0x38>; - interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&tsp_int_rst_default>; - pinctrl-names = "default"; - vcc-supply = <&pm8937_l10>; - iovcc-supply = <&pm8937_l5>; - touchscreen-size-x = <720>; - touchscreen-size-y = <1280>; - }; }; &blsp2_i2c1 { status = "okay"; - bq27426@55 { + power-monitor@55 { compatible = "ti,bq27426"; reg = <0x55>; monitored-battery = <&battery>; }; - bq25601@6b { + charger@6b { compatible = "ti,bq25601"; reg = <0x6b>; interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; @@ -139,172 +46,6 @@ bq25601@6b { }; }; -&pm8937_gpios { - pwm_enable_default: pwm-enable-default-state { - pins = "gpio8"; - function = "dtest2"; - output-low; - bias-disable; - qcom,drive-strength = <2>; - }; -}; - -&pm8937_pwm { - pinctrl-0 = <&pwm_enable_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pm8937_resin { - linux,code = ; - - status = "okay"; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm8937-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; - vdd_s3-supply = <&vph_pwr>; - vdd_s4-supply = <&vph_pwr>; - - vdd_l1_l19-supply = <&pm8937_s3>; - vdd_l2_l23-supply = <&pm8937_s3>; - vdd_l3-supply = <&pm8937_s3>; - vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>; - vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>; - vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>; - - pm8937_s1: s1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1225000>; - }; - - pm8937_s3: s3 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - }; - - pm8937_s4: s4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - pm8937_l2: l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pm8937_l5: l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8937_l6: l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8937_l7: l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8937_l8: l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - pm8937_l9: l9 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; - }; - - pm8937_l10: l10 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - }; - - pm8937_l11: l11 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - pm8937_l12: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - pm8937_l13: l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - pm8937_l14: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8937_l15: l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - pm8937_l16: l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - pm8937_l17: l17 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2900000>; - }; - - pm8937_l19: l19 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1350000>; - }; - - pm8937_l22: l22 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - pm8937_l23: l23 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - }; - -}; - -&sdhc_1 { - vmmc-supply = <&pm8937_l8>; - vqmmc-supply = <&pm8937_l5>; - - status = "okay"; -}; - -&sdhc_2 { - cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>; - vmmc-supply = <&pm8937_l11>; - vqmmc-supply = <&pm8937_l12>; - pinctrl-0 = <&sdc2_default &sdc2_cd_default>; - pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; - pinctrl-names = "default", "sleep"; - - status = "okay"; -}; - -&sleep_clk { - clock-frequency = <32768>; -}; - &tlmm { bq25601_int_default: bq25601-int-default-state { pins = "gpio61"; @@ -312,47 +53,4 @@ bq25601_int_default: bq25601-int-default-state { drive-strength = <2>; bias-pull-up; }; - - gpio_keys_default: gpio-keys-default-state { - pins = "gpio91"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - sdc2_cd_default: sdc2-cd-default-state { - pins = "gpio67"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - tsp_int_rst_default: tsp-int-rst-default-state { - pins = "gpio64", "gpio65"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - }; -}; - -&wcnss { - vddpx-supply = <&pm8937_l5>; - - status = "okay"; -}; - -&wcnss_iris { - compatible = "qcom,wcn3620"; - vddxo-supply = <&pm8937_l7>; - vddrfa-supply = <&pm8937_l19>; - vddpa-supply = <&pm8937_l9>; - vdddig-supply = <&pm8937_l5>; -}; - -&wcnss_mem { - status = "okay"; -}; - -&xo_board { - clock-frequency = <19200000>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-rolex.dts b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-rolex.dts new file mode 100644 index 000000000000..f0b72d9878c4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-rolex.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026, Barnabas Czeman + */ + +/dts-v1/; + +#include "msm8917-xiaomi-wingtech.dtsi" + +/ { + model = "Xiaomi Redmi 4A (rolex)"; + compatible = "xiaomi,rolex", "qcom,msm8917"; + + qcom,board-id = <0x1000b 1>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-tiare.dts b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-tiare.dts new file mode 100644 index 000000000000..fe844230030f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-tiare.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026, Barnabas Czeman + */ + +/dts-v1/; + +#include "msm8917-xiaomi-wingtech.dtsi" + +/ { + model = "Xiaomi Redmi Go (tiare)"; + compatible = "xiaomi,tiare", "qcom,msm8917"; + + qcom,board-id = <0x1000b 1>; +}; + +&pm8937_l22 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8917-xiaomi-wingtech.dtsi b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-wingtech.dtsi new file mode 100644 index 000000000000..69eda5f42c06 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8917-xiaomi-wingtech.dtsi @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Barnabas Czeman + */ + +/dts-v1/; + +#include +#include +#include "msm8917.dtsi" +#include "pm8937.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + chassis-type = "handset"; + + qcom,msm-id = ; + + pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8937_pwm 0 100000>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <128>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_mem>; + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + power-domains = <&gcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + key-volup { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + framebuffer_mem: memory@90001000 { + reg = <0x0 0x90001000 0x0 (720 * 1280 * 3)>; + no-map; + }; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + + edt_ft5306: touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&tsp_int_rst_default>; + pinctrl-names = "default"; + vcc-supply = <&pm8937_l10>; + iovcc-supply = <&pm8937_l5>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + status = "disabled"; + }; + + goodix_gt911: touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&tsp_int_rst_default>; + pinctrl-names = "default"; + AVDD28-supply = <&pm8937_l10>; + VDDIO-supply = <&pm8937_l5>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + status = "disabled"; + }; +}; + +&pm8937_gpios { + pwm_enable_default: pwm-enable-default-state { + pins = "gpio8"; + function = "dtest2"; + output-low; + bias-disable; + qcom,drive-strength = <2>; + }; +}; + +&pm8937_pwm { + pinctrl-0 = <&pwm_enable_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pm8937_resin { + linux,code = ; + + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8937-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + + vdd_l1_l19-supply = <&pm8937_s3>; + vdd_l2_l23-supply = <&pm8937_s3>; + vdd_l3-supply = <&pm8937_s3>; + vdd_l4_l5_l6_l7_l16-supply = <&pm8937_s4>; + vdd_l8_l11_l12_l17_l22-supply = <&vph_pwr>; + vdd_l9_l10_l13_l14_l15_l18-supply = <&vph_pwr>; + + pm8937_s1: s1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pm8937_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pm8937_s4: s4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8937_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8937_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l8: l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + pm8937_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l10: l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8937_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pm8937_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8937_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8937_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8937_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8937_l17: l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + }; + + pm8937_l19: l19 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8937_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8937_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8937_l8>; + vqmmc-supply = <&pm8937_l5>; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 67 GPIO_ACTIVE_LOW>; + vmmc-supply = <&pm8937_l11>; + vqmmc-supply = <&pm8937_l12>; + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32768>; +}; + +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default: tsp-int-rst-default-state { + pins = "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&wcnss { + vddpx-supply = <&pm8937_l5>; + + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; + vddxo-supply = <&pm8937_l7>; + vddrfa-supply = <&pm8937_l19>; + vddpa-supply = <&pm8937_l9>; + vdddig-supply = <&pm8937_l5>; +}; + +&wcnss_mem { + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts b/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts index 91837ff940f1..4f301e7c6517 100644 --- a/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts +++ b/arch/arm64/boot/dts/qcom/msm8937-xiaomi-land.dts @@ -178,7 +178,7 @@ &pmi8950_wled { qcom,num-strings = <2>; qcom,external-pfet; qcom,current-limit-microamp = <20000>; - qcom,ovp-millivolt = <29600>; + qcom,ovp-millivolt = <29500>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts index ea90b00a2c8a..90e966242720 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts @@ -147,6 +147,20 @@ magnetometer@c { pinctrl-names = "default"; }; + light-sensor@60 { + compatible = "capella,cm36686", "vishay,vcnl4040"; + reg = <0x60>; + + interrupts-extended = <&tlmm 113 IRQ_TYPE_EDGE_FALLING>; + proximity-near-level = <30>; + + vdd-supply = <&pm8916_l8>; + vio-supply = <&pm8916_l6>; + + pinctrl-0 = <&light_int_default>; + pinctrl-names = "default"; + }; + imu@68 { compatible = "invensense,mpu6515"; reg = <0x68>; @@ -330,4 +344,11 @@ mag_reset_default: mag-reset-default-state { drive-strength = <2>; bias-disable; }; + + light_int_default: light-int-default-state { + pins = "gpio113"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts index ddd7af616794..59f873a06e4d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -157,7 +157,7 @@ &pm8953_resin { &pmi8950_wled { qcom,current-limit-microamp = <20000>; - qcom,num-strings = <2>; + qcom,num-strings = <3>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts index d46325e79917..c2a290bf493c 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts @@ -169,7 +169,7 @@ &pm8953_resin { &pmi8950_wled { qcom,current-limit-microamp = <20000>; - qcom,ovp-millivolt = <29600>; + qcom,ovp-millivolt = <29500>; qcom,num-strings = <2>; qcom,external-pfet; qcom,cabc; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 63ab564655bc..a4dcc88bb01f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -745,14 +745,7 @@ mdss_dsi_suspend: mdss-dsi-suspend-state { bias-pull-down; }; - mdss_te_active: mdss-te-active-state { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - mdss_te_suspend: mdss-te-suspend-state { + mdss_te: mdss-te-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi b/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi deleted file mode 100644 index 929bdcd45d02..000000000000 --- a/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Konrad Dybcio - */ - -#include "msm8996.dtsi" - -/ { - qcom,msm-id = <246 0x30000>; -}; - - /* - * This revision seems to have differ GPU CPR - * parameters, GPU frequencies and some differences - * when it comes to voltage delivery to.. once again - * the GPU. Funnily enough, it's simpler to make it an - * overlay on top of 3.1 (the final one) than vice versa. - * The differences will show here as more and more - * features get enabled upstream. - */ - -gpu_opp_table_3_0: opp-table-gpu30 { - compatible = "operating-points-v2"; - - opp-624000000 { - opp-hz = /bits/ 64 <624000000>; - opp-level = <7>; - }; - - opp-560000000 { - opp-hz = /bits/ 64 <560000000>; - opp-level = <6>; - }; - - opp-510000000 { - opp-hz = /bits/ 64 <510000000>; - opp-level = <5>; - }; - - opp-401800000 { - opp-hz = /bits/ 64 <401800000>; - opp-level = <4>; - }; - - opp-315000000 { - opp-hz = /bits/ 64 <315000000>; - opp-level = <3>; - }; - - opp-214000000 { - opp-hz = /bits/ 64 <214000000>; - opp-level = <3>; - }; - - opp-133000000 { - opp-hz = /bits/ 64 <133000000>; - opp-level = <3>; - }; -}; - -&gpu { - operating-points-v2 = <&gpu_opp_table_3_0>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 0386636a29f0..77ad613590a3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -247,7 +247,7 @@ &mdss_dsi0 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&mdss_dsi_default &mdss_te_default>; - pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_default>; }; &mdss_dsi0_out { @@ -730,14 +730,7 @@ mdss_dsi_sleep: mdss-dsi-sleep-state { bias-pull-down; }; - mdss_te_default: mdss-te-default-state { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - mdss_te_sleep: mdss-te-sleep-state { + mdss_te_default: mdss-te-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 3c6a40212a8d..fd3a2121465b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -104,7 +104,7 @@ &mdss_dsi0 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&mdss_dsi_default &mdss_te_default>; - pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_default>; panel: panel@0 { compatible = "jdi,fhd-r63452"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 9d4ce47578fb..2f67e665996f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3255,7 +3255,7 @@ sdhc2: mmc@74a4900 { bus-width = <4>; status = "disabled"; - }; + }; blsp1_dma: dma-controller@7544000 { compatible = "qcom,bam-v1.7.0"; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index f8ab03f106a1..7e2ee9a4e9f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -51,7 +51,7 @@ &mdss_dsi0 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&mdss_dsi_default &mdss_te_default>; - pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_default>; panel: panel@0 { compatible = "jdi,fhd-r63452"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts index 0cac06f25a77..30222f6608da 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts @@ -543,14 +543,7 @@ mdss_dsi_suspend_state: mdss-dsi-suspend-state { bias-pull-down; }; - mdss_te_active_state: mdss-te-active-state { - pins = "gpio10"; - function = "mdp_vsync_a"; - drive-strength = <2>; - bias-pull-down; - }; - - mdss_te_suspend_state: mdss-te-suspend-state { + mdss_te_state: mdss-te-state { pins = "gpio10"; function = "mdp_vsync_a"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index d0db28336fa9..cb067adb7d17 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -138,7 +138,6 @@ pm6125_rtc: rtc@6000 { reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - status = "disabled"; }; pm6125_gpios: gpio@c000 { diff --git a/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi new file mode 100644 index 000000000000..bfc58a6589d3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pm8010-m-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8010_m_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pm8010-n-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8010_n_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pm8010_m_e1: pmic@c { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_m_e1_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; + + pm8010_n_e1: pmic@d { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_n_e1_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi new file mode 100644 index 000000000000..db2da9ef4f01 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmcx0102-c0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_c_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102-c1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_c_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102_d0_thermal: pmcx0102-d0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_d_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmcx0102-d1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmcx0102_d_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmcx0102_c_e0: pmic@2 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_c_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_c_e0_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_c_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmcx0102_d_e0: pmic@3 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_d_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_d_e0_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_d_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmcx0102_c_e1: pmic@2 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_c_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_c_e1_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_c_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmcx0102_d_e1: pmic@3 { + compatible = "qcom,pmcx0102", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmcx0102_d_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmcx0102_d_e1_gpios: gpio@8800 { + compatible = "qcom,pmcx0102-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmcx0102_d_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi new file mode 100644 index 000000000000..db4dc16a66e7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmd8028-kaanapali.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmd8028-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmd8028_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmd8028_e1: pmic@4 { + compatible = "qcom,pmd8028", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmd8028_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmd8028_e1_gpios: gpio@8800 { + compatible = "qcom,pmd8028-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmd8028_e1_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0101.dtsi b/arch/arm64/boot/dts/qcom/pmh0101.dtsi new file mode 100644 index 000000000000..b1ec41325958 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0101.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0101-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0101_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmic@1 { + compatible = "qcom,pmh0101", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0101_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0101_gpios: gpio@8800 { + compatible = "qcom,pmh0101-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0101_gpios 0 0 18>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmh0101_flash: led-controller@ee00 { + compatible = "qcom,pmh0101-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; + + pmh0101_pwm: pwm { + compatible = "qcom,pmh0101-pwm", "qcom,pm8350c-pwm"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi new file mode 100644 index 000000000000..7a1e5f355c17 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/{ + thermal_zones { + pmh0104_i0_thermal: pmh0104-i0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_i_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0104_j0_thermal: pmh0104-j0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_j_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0104-l1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0104_l_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmh0104_i_e0: pmic@8 { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_i_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_i_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_i_e0_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0104_j_e0: pmic@9 { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_j_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_j_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_j_e0_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmh0104_l_e1: pmic@b { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_l_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_l_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_l_e1_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi new file mode 100644 index 000000000000..d009c9a9f59e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0104-kaanapali.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0104-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0104_j_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmh0104_j_e1: pmic@9 { + compatible = "qcom,pmh0104", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0104_j_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0104_j_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0104_j_e1_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi new file mode 100644 index 000000000000..7655bc030348 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0110-f0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_f_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-f1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_f_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-h0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmh0110_h_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmh0110_f_e0: pmic@5 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_f_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_h_e0: pmic@7 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_h_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_h_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&spmi_bus1 { + pmh0110_f_e1: pmic@5 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_f_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e1_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi new file mode 100644 index 000000000000..15d9cff246b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmh0110-kaanapali.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmh0110-d-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0110_d_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-f-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0110_f_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-g-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0110_g_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmh0110-i-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmh0110_i_e0_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmh0110_d_e0: pmic@3 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_d_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_d_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_d_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_f_e0: pmic@5 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_f_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_f_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_f_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_g_e0: pmic@6 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_g_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_g_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_g_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmh0110_i_e0: pmic@8 { + compatible = "qcom,pmh0110", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmh0110_i_e0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmh0110_i_e0_gpios: gpio@8800 { + compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmh0110_i_e0_gpios 0 0 14>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi new file mode 100644 index 000000000000..b73b0e82c3d3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmih0108-kaanapali.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmih0108-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pmih0108_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmih0108_e1: pmic@7 { + compatible = "qcom,pmih0108", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmih0108_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmih0108_e1_gpios: gpio@8800 { + compatible = "qcom,pmih0108-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmih0108_e1_gpios 0 0 18>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmih0108_e1_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index 583f61fc16ad..3049eb6b46d7 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -73,5 +73,15 @@ pmk8550_gpios: gpio@b800 { interrupt-controller; #interrupt-cells = <2>; }; + + pmk8550_pwm: pwm { + compatible = "qcom,pmk8550-pwm"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pmk8850.dtsi b/arch/arm64/boot/dts/qcom/pmk8850.dtsi new file mode 100644 index 000000000000..c7ba72fd48bc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8850.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +&spmi_bus0 { + pmic@0 { + compatible = "qcom,pmk8850", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8850_pon: pon@1300 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, + <0x800>; + reg-names = "hlos", + "pbs"; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8850_gpios: gpio@b800 { + compatible = "qcom,pmk8850-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8850_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmk8850_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, + <0x6200>; + reg-names = "rtc", + "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pmk8850_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi new file mode 100644 index 000000000000..d0dd5e078cdc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmr735d-kaanapali.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +/ { + thermal-zones { + pmr735d-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmr735d_e1_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus1 { + pmr735d_e1: pmic@a { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_e1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_e1_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_e1_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts new file mode 100644 index 000000000000..ad503beec1d3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-iot-evk.dts @@ -0,0 +1,1590 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include "purwa-iot-som.dtsi" +#include + +/ { + model = "Qualcomm Technologies, Inc. Purwa IoT EVK"; + compatible = "qcom,purwa-iot-evk", "qcom,purwa-iot-som", "qcom,x1p42100"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector3 { + compatible = "usb-a-connector"; + label = "USB-3-Type-A"; + power-role = "source"; + + vbus-supply = <®ulator_usb3_vbus>; + + port { + connector_3_in: endpoint { + }; + }; + }; + + connector6 { + compatible = "usb-a-connector"; + label = "USB-6-Type-A"; + power-role = "source"; + + vbus-supply = <®ulator_usb6_vbus>; + + port { + connector_4_in: endpoint { + }; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss2_con_sbu_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_bl_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_pcie_12v: regulator-pcie-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pcie_x8_12v>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_main_3p3_en>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_aux_3p3_en>; + pinctrl-names = "default"; + }; + + /* Left unused as the retimer is not used on this board. */ + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + regulator_usb3_vbus: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB3_VBUS"; + gpio = <&pm8550ve_9_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb3_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + + regulator_usb6_vbus: regulator-usb6-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB6_VBUS"; + gpio = <&pm8550ve_9_gpios 5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb6_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the EVK mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "SDX_VPH_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-EVK"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, + <&left_tweeter>, + <&swr0 0>, + <&lpass_wsamacro 0>, + <&right_woofer>, + <&right_tweeter>, + <&swr3 0>, + <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK5>; + + vdd-supply = <&vreg_rtmr2_1p15>; + vdd33-supply = <&vreg_rtmr2_3p3>; + vdd33-cap-supply = <&vreg_rtmr2_3p3>; + vddar-supply = <&vreg_rtmr2_1p15>; + vddat-supply = <&vreg_rtmr2_1p15>; + vddio-supply = <&vreg_rtmr2_1p8>; + + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr2_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&lpass_tlmm { + spkr_0_sd_n_active: spkr-0-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_3_sd_n_active: spkr-3-sd-n-active-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie3_port0 { + vpcie12v-supply = <&vreg_pcie_12v>; + vpcie3v3-supply = <&vreg_pcie_3v3>; + vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; + + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_wwan>; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb3_en: usb3-en-state { + pins = "gpio4"; + function = "normal"; + qcom,drive-strength = ; + output-enable; + power-source = <0>; + }; + + usb6_en: usb6-en-state { + pins = "gpio5"; + function = "normal"; + qcom,drive-strength = ; + output-enable; + power-source = <0>; + }; +}; + +&pm8550_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; + + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + bias-pull-down; + power-source = <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins = "gpio6"; + function = "normal"; + output-enable; + bias-pull-down; + power-source = <0>; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&spi11 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_0_sd_n_active>; + pinctrl-names = "default"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 17 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + pinctrl-0 = <&spkr_3_sd_n_active>; + pinctrl-names = "default"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 18 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins = "gpio185"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { + pins = "gpio189"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { + pins = "gpio126"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { + pins = "gpio187"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + mode-pins { + pins = "gpio166"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_bt_en: wcn-bt-en-state { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_en: wcn-wlan-en-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_sw_en: wwan-sw-en-state { + pins = "gpio221"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* Switches USB signal routing between the USB connector and the Wi-Fi card. */ + wcn_usb_sw_n: wcn-usb-sw-n-state { + pins = "gpio225"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&uart21 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_hsphy { + phys = <&smb2360_0_eusb2_repeater>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_hsphy { + phys = <&smb2360_1_eusb2_repeater>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_hsphy { + phys = <&smb2360_2_eusb2_repeater>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&retimer_ss2_ss_in>; +}; + +&usb_2_hsphy { + phys = <&eusb5_repeater>; + + pinctrl-0 = <&wcn_usb_sw_n>; + pinctrl-names = "default"; +}; + +&usb_mp_hsphy0 { + phys = <&eusb3_repeater>; +}; + +&usb_mp_hsphy1 { + phys = <&eusb6_repeater>; +}; diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi new file mode 100644 index 000000000000..394e65518ac5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -0,0 +1,677 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" +#include +#include + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; +}; + +&apps_rsc { + /* PMC8380C_B */ + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_C */ + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_D */ + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_E */ + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_F */ + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_I */ + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_J */ + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/gen71500_zap.mbn"; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie5 { + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ + + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + + }; + }; +}; + +&usb_1_ss0 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss1 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss2 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 2cecd2dd0de8..9ab4f26b35f2 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -20,7 +20,21 @@ /delete-node/ &gpu_opp_table; /delete-node/ &gpu_speed_bin; /delete-node/ &pcie3_phy; -/delete-node/ &thermal_zones; +/delete-node/ &thermal_aoss3; +/delete-node/ &thermal_cpu2_0_btm; +/delete-node/ &thermal_cpu2_0_top; +/delete-node/ &thermal_cpu2_1_btm; +/delete-node/ &thermal_cpu2_1_top; +/delete-node/ &thermal_cpu2_2_btm; +/delete-node/ &thermal_cpu2_2_top; +/delete-node/ &thermal_cpu2_3_btm; +/delete-node/ &thermal_cpu2_3_top; +/delete-node/ &thermal_cpuss2_btm; +/delete-node/ &thermal_cpuss2_top; +/delete-node/ &thermal_gpuss_4; +/delete-node/ &thermal_gpuss_5; +/delete-node/ &thermal_gpuss_6; +/delete-node/ &thermal_gpuss_7; &gcc { compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; @@ -198,557 +212,47 @@ pcie3_phy: phy@1bd4000 { }; }; +&thermal_camera0 { + thermal-sensors = <&tsens2 9>; +}; + +&thermal_camera1 { + thermal-sensors = <&tsens2 10>; +}; + +&thermal_gpuss_0 { + thermal-sensors = <&tsens2 5>; +}; + +&thermal_gpuss_1 { + thermal-sensors = <&tsens2 6>; +}; + +&thermal_gpuss_2 { + thermal-sensors = <&tsens2 7>; +}; + +&thermal_gpuss_3 { + thermal-sensors = <&tsens2 8>; +}; + +&thermal_nsp0 { + thermal-sensors = <&tsens2 1>; +}; + +&thermal_nsp1 { + thermal-sensors = <&tsens2 2>; +}; + +&thermal_nsp2 { + thermal-sensors = <&tsens2 3>; +}; + +&thermal_nsp3 { + thermal-sensors = <&tsens2 4>; +}; + /* While physically present, this controller is left unconfigured and unused */ &tsens3 { status = "disabled"; }; - -/ { - thermal-zones { - aoss0-thermal { - thermal-sensors = <&tsens0 0>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-0-top-thermal { - thermal-sensors = <&tsens0 1>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-0-btm-thermal { - thermal-sensors = <&tsens0 2>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-1-top-thermal { - thermal-sensors = <&tsens0 3>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-1-btm-thermal { - thermal-sensors = <&tsens0 4>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-2-top-thermal { - thermal-sensors = <&tsens0 5>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-2-btm-thermal { - thermal-sensors = <&tsens0 6>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-3-top-thermal { - thermal-sensors = <&tsens0 7>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu0-3-btm-thermal { - thermal-sensors = <&tsens0 8>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuss0-top-thermal { - thermal-sensors = <&tsens0 9>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuss0-btm-thermal { - thermal-sensors = <&tsens0 10>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - mem-thermal { - thermal-sensors = <&tsens0 11>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - video-thermal { - thermal-sensors = <&tsens0 12>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss1-thermal { - thermal-sensors = <&tsens1 0>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-0-top-thermal { - thermal-sensors = <&tsens1 1>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-0-btm-thermal { - thermal-sensors = <&tsens1 2>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-1-top-thermal { - thermal-sensors = <&tsens1 3>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-1-btm-thermal { - thermal-sensors = <&tsens1 4>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-2-top-thermal { - thermal-sensors = <&tsens1 5>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-2-btm-thermal { - thermal-sensors = <&tsens1 6>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-3-top-thermal { - thermal-sensors = <&tsens1 7>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpu1-3-btm-thermal { - thermal-sensors = <&tsens1 8>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuss1-top-thermal { - thermal-sensors = <&tsens1 9>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - cpuss1-btm-thermal { - thermal-sensors = <&tsens1 10>; - - trips { - trip-point0 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - aoss2-thermal { - thermal-sensors = <&tsens2 0>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsp0-thermal { - thermal-sensors = <&tsens2 1>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsp1-thermal { - thermal-sensors = <&tsens2 2>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsp2-thermal { - thermal-sensors = <&tsens2 3>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - nsp3-thermal { - thermal-sensors = <&tsens2 4>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-0-thermal { - polling-delay-passive = <200>; - - thermal-sensors = <&tsens2 5>; - - cooling-maps { - map0 { - trip = <&gpuss0_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - gpuss0_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-1-thermal { - polling-delay-passive = <200>; - - thermal-sensors = <&tsens2 6>; - - cooling-maps { - map0 { - trip = <&gpuss1_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - gpuss1_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-2-thermal { - polling-delay-passive = <200>; - - thermal-sensors = <&tsens2 7>; - - cooling-maps { - map0 { - trip = <&gpuss2_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - gpuss2_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - gpuss-3-thermal { - polling-delay-passive = <200>; - - thermal-sensors = <&tsens2 8>; - - cooling-maps { - map0 { - trip = <&gpuss3_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - - trips { - gpuss3_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - camera0-thermal { - thermal-sensors = <&tsens2 9>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - - camera1-thermal { - thermal-sensors = <&tsens2 10>; - - trips { - trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "hot"; - }; - - trip-point1 { - temperature = <115000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 455e5c9bb072..04cb9230d29f 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -626,6 +627,23 @@ vreg_bob: bob { }; }; +&camss { + vdda-phy-supply = <&vreg_l10c>; + vdda-pll-supply = <&vreg_l6b>; + + status = "okay"; + + ports { + port@3 { + csiphy3_ep: endpoint { + data-lanes = <0 1 2 3>; + bus-type = ; + remote-endpoint = <&camera_s5kjn1_ep>; + }; + }; + }; +}; + &cci0 { status = "okay"; }; @@ -666,7 +684,34 @@ &cci1 { }; &cci1_i2c1 { - /* S5KJN1SQ03 @ 10 */ + camera@10 { + compatible = "samsung,s5kjn1"; + reg = <0x10>; + + vdda-supply = <&vreg_l3p>; + vddd-supply = <&vreg_l2p>; + vddio-supply = <&vreg_l6p>; + + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&cam_mclk3_default>; + pinctrl-names = "default"; + + orientation = <0>; /* Front facing */ + rotation = <270>; + + port { + camera_s5kjn1_ep: endpoint { + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <700000000>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; eeprom@51 { compatible = "giantec,gt24p128f", "atmel,24c128"; @@ -1257,41 +1302,6 @@ &tlmm { */ gpio-reserved-ranges = <32 2>, <56 4>; - bluetooth_enable_default: bluetooth-enable-default-state { - pins = "gpio85"; - function = "gpio"; - output-low; - bias-disable; - }; - - disp_reset_n_active: disp-reset-n-active-state { - pins = "gpio44"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - disp_reset_n_suspend: disp-reset-n-suspend-state { - pins = "gpio44"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - hall_sensor_default: hall-sensor-default-state { - pins = "gpio155"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - mdp_vsync: mdp-vsync-state { - pins = "gpio80"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - pm8008_int_default: pm8008-int-default-state { pins = "gpio25"; function = "gpio"; @@ -1345,9 +1355,17 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { bias-pull-up; }; - sw_ctrl_default: sw-ctrl-default-state { - pins = "gpio86"; + disp_reset_n_active: disp-reset-n-active-state { + pins = "gpio44"; function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp_reset_n_suspend: disp-reset-n-suspend-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <2>; bias-pull-down; }; @@ -1359,12 +1377,39 @@ usb_redrive_1v8_en_default: usb-redrive-1v8-en-default-state { output-high; }; + mdp_vsync: mdp-vsync-state { + pins = "gpio80"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + bluetooth_enable_default: bluetooth-enable-default-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio86"; + function = "gpio"; + bias-pull-down; + }; + aw86927_int_default: aw86927-int-default-state { pins = "gpio101"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; + + hall_sensor_default: hall-sensor-default-state { + pins = "gpio155"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart5 { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index b2f00e107643..bdc02260f902 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -36,6 +36,7 @@ / { aliases { serial0 = &uart5; + serial1 = &uart7; }; pm8350c_pwm_backlight: backlight { @@ -194,6 +195,63 @@ wcd9370: audio-codec-0 { #sound-dai-cells = <1>; }; + + wcn6750-pmu { + compatible = "qcom,wcn6750-pmu"; + pinctrl-0 = <&bt_en>; + pinctrl-names = "default"; + vddaon-supply = <&vreg_s7b_0p972>; + vddasd-supply = <&vreg_l11c_2p8>; + vddpmu-supply = <&vreg_s7b_0p972>; + vddrfa0p8-supply = <&vreg_s7b_0p972>; + vddrfa1p2-supply = <&vreg_s8b_1p272>; + vddrfa1p7-supply = <&vreg_s1b_1p872>; + vddrfa2p2-supply = <&vreg_s1c_2p19>; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -695,6 +753,39 @@ &pon_resin { status = "okay"; }; +&qup_uart7_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + &qupv3_id_0 { status = "okay"; }; @@ -920,6 +1011,59 @@ &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ + bt_en: bt-en-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + sd_cd: sd-cd-state { pins = "gpio91"; function = "gpio"; @@ -938,6 +1082,31 @@ &uart5 { status = "okay"; }; +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + max-speed = <3200000>; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l7b_2p952>; diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 5a24c19c415e..7e05f873194a 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -91,16 +91,6 @@ regulator-usb2-vbus { regulator-always-on; }; - vreg_12p0: regulator-vreg-12p0 { - compatible = "regulator-fixed"; - regulator-name = "VREG_12P0"; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - vreg_1p0: regulator-vreg-1p0 { compatible = "regulator-fixed"; regulator-name = "VREG_1P0"; @@ -121,8 +111,6 @@ vreg_1p8: regulator-vreg-1p8 { regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - - vin-supply = <&vreg_5p0>; }; vreg_3p0: regulator-vreg-3p0 { @@ -133,20 +121,6 @@ vreg_3p0: regulator-vreg-3p0 { regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - - vin-supply = <&vreg_12p0>; - }; - - vreg_5p0: regulator-vreg-5p0 { - compatible = "regulator-fixed"; - regulator-name = "VREG_5P0"; - - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&vreg_12p0>; }; wcn6855-pmu { @@ -372,6 +346,14 @@ vreg_l17a: ldo17 { }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs615/a612_zap.mbn"; +}; + &i2c2 { clock-frequency = <400000>; status = "okay"; @@ -655,14 +637,12 @@ &usb_qmpphy_2 { }; &usb_1 { + dr_mode = "peripheral"; + status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_hsphy_2 { +&usb_2_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; vdda-phy-dpdm-supply = <&vreg_l13a>; @@ -671,11 +651,9 @@ &usb_hsphy_2 { }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 619a42b5ef48..83908db335af 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -5,9 +5,37 @@ /dts-v1/; /plugin/; +#include #include #include +&{/} { + + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&remoteproc_wpss { + status = "disabled"; +}; + &spi11 { #address-cells = <1>; #size-cells = <0>; @@ -19,3 +47,244 @@ st33htpm0: tpm@0 { spi-max-frequency = <20000000>; }; }; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; + pinctrl-names = "default"; + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>, + <0x208 &apps_smmu 0x1c04 0x1>, + <0x210 &apps_smmu 0x1c05 0x1>, + <0x218 &apps_smmu 0x1c06 0x1>, + <0x300 &apps_smmu 0x1c07 0x1>, + <0x400 &apps_smmu 0x1c08 0x1>, + <0x500 &apps_smmu 0x1c09 0x1>, + <0x501 &apps_smmu 0x1c10 0x1>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie0_port { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c1 0x33>; + + resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + + }; +}; + +&pcie1 { + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x408 &apps_smmu 0x1c90 0x1>, + <0x410 &apps_smmu 0x1c91 0x1>, + <0x418 &apps_smmu 0x1c92 0x1>, + <0x500 &apps_smmu 0x1c93 0x1>, + <0x600 &apps_smmu 0x1c94 0x1>, + <0x700 &apps_smmu 0x1c95 0x1>, + <0x701 &apps_smmu 0x1c96 0x1>, + <0x800 &apps_smmu 0x1c97 0x1>, + <0x900 &apps_smmu 0x1c98 0x1>, + <0x901 &apps_smmu 0x1c99 0x1>; +}; + +&pcie1_switch0_dsp1 { + #address-cells = <3>; + #size-cells = <2>; + + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x30000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + i2c-parent = <&i2c1 0x77>; + + resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x40800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x41000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x41800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&tlmm { + pcie0_tc9563_resx_n: pcie0-tc9563-resx-state { + pins = "gpio78"; + function = "gpio"; + bias-disable; + input-disable; + output-enable; + }; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie0_clkreq_n: pcie0-clkreq-n-state { + pins = "gpio88"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_tc9563_resx_n: pcie1-tc9563-resx-state { + pins = "gpio124"; + function = "gpio"; + bias-disable; + input-disable; + output-enable; + }; + +}; + +&wifi { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e3d2f01881ae..e393ccf1884a 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -262,6 +262,28 @@ active-config0 { }; }; + vreg_pcie0_1p05: regulator-pcie0-1p05v { + compatible = "regulator-fixed"; + regulator-name = "PCIE0_1.05V"; + gpio = <&pm7250b_gpios 4 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + enable-active-high; + pinctrl-0 = <&upd_pwr_en2_state>; + pinctrl-names = "default"; + }; + + vreg_pcie0_3p3: regulator-pcie0-3p3v-dual { + compatible = "regulator-fixed"; + regulator-name = "PCIE0_3.3V_Dual"; + gpio = <&pm7250b_gpios 1 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + pinctrl-0 = <&upd_pwr_en1_state>; + pinctrl-names = "default"; + }; + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { compatible = "regulator-fixed"; regulator-name = "VDD_NTN_0P9"; @@ -852,7 +874,7 @@ pcie@0,0 { pinctrl-0 = <&tc9563_resx_n>; pinctrl-names = "default"; - pcie@1,0 { + pcie1_switch0_dsp1: pcie@1,0 { reg = <0x20800 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -870,6 +892,41 @@ pcie@2,0 { device_type = "pci"; ranges; bus-range = <0x4 0xff>; + + /* Renesas μPD720201 PCIe USB3.0 Host Controller */ + usb-controller@0,0 { + compatible = "pci1912,0014"; + reg = <0x40000 0x0 0x0 0x0 0x0>; + + avdd33-supply = <&vreg_pcie0_3p3>; + vdd10-supply = <&vreg_pcie0_1p05>; + vdd33-supply = <&vreg_pcie0_3p3>; + + pinctrl-0 = <&upd_hub_rst_state>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + /* Genesys Logic GL3590 USB Hub Controller */ + gl3590_2_0: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + reset-gpios = <&tlmm 162 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_hub_reset_state>; + pinctrl-names = "default"; + + peer-hub = <&gl3590_3_0>; + }; + + gl3590_3_0: hub@2 { + compatible = "usb5e3,625"; + reg = <2>; + + peer-hub = <&gl3590_2_0>; + }; + }; }; pcie@3,0 { @@ -1198,6 +1255,17 @@ ntn_1p8_en: ntn-1p8-en-state { power-source = <0>; }; + upd_hub_rst_state: upd-hub-rst-state { + pins = "gpio4"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + output-high; + power-source = <0>; + }; + tc9563_resx_n: tc9563-resx-state { pins = "gpio1"; function = "normal"; @@ -1378,6 +1446,15 @@ &edp_hot_plug_det { }; &pm7250b_gpios { + upd_pwr_en1_state: upd-pwr-en1-state { + pins = "gpio1"; + function = "normal"; + + output-enable; + input-disable; + power-source = <0>; + }; + lt9611_rst_pin: lt9611-rst-state { pins = "gpio2"; function = "normal"; @@ -1386,6 +1463,15 @@ lt9611_rst_pin: lt9611-rst-state { input-disable; power-source = <0>; }; + + upd_pwr_en2_state: upd-pwr-en2-state { + pins = "gpio4"; + function = "normal"; + + output-enable; + input-disable; + power-source = <0>; + }; }; &sdc2_clk { @@ -1431,6 +1517,13 @@ sd_cd: sd-cd-state { function = "gpio"; bias-pull-up; }; + + usb_hub_reset_state: usb-hub-reset-state { + pins = "gpio162"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; &lpass_audiocc { diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts new file mode 100644 index 000000000000..a5ad796cb65d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -0,0 +1,1093 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Roger Shimizu + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include "kodiak.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model = "Thundercomm AI Mini PC G1 IoT"; + compatible = "thundercomm,minipc-g1iot", "qcom,qcm6490"; + chassis-type = "desktop"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_usb_con_ss>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&redriver_usb_con_sbu>; + }; + }; + }; + }; + }; + + lt9611_1v2: regulator-lt9611-vdd12 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@86100000 { + reg = <0x0 0x86100000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@88900000 { + reg = <0x0 0x88900000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@8a700000 { + reg = <0x0 0x8a700000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@8ae00000 { + reg = <0x0 0x8ae00000 0x0 0x500000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@8b31a000 { + reg = <0x0 0x8b31a000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_0P9"; + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + enable-active-high; + pinctrl-0 = <&ntn_0p9_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_1P8"; + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn_1p8_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + thermal-zones { + sdm-skin-thermal { + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; + vdd-l8-supply = <&vreg_s7b_0p972>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; + vdd-l13-supply = <&vreg_s7b_0p972>; + vdd-l14-l16-supply = <&vreg_s8b_1p272>; + + vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p872>; + vdd-l2-l8-supply = <&vreg_s1b_1p872>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p972>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2208000>; + }; + + vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs6490/a660_zap.mbn"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <&vreg_l11c_2p8>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l18b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_usb_con_ss: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_phy_con_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@2 { + reg = <2>; + + redriver_usb_con_sbu: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_clkreq_n>, + <&pcie0_reset_n>, + <&pcie0_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_clkreq_n>, + <&pcie1_reset_n>, + <&pcie1_wake_n>; + pinctrl-names = "default"; + + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x400 &apps_smmu 0x1c88 0x1>, + <0x500 &apps_smmu 0x1c89 0x1>, + <0x501 &apps_smmu 0x1c90 0x1>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1_port0 { + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + i2c-parent = <&i2c0 0x77>; + + resx-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&pm7250b_gpios { + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio2"; + function = "normal"; + + output-high; + input-disable; + power-source = <0>; + }; +}; + +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8350c_gpios { + ntn_0p9_en: ntn-0p9-en-state { + pins = "gpio2"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + ntn_1p8_en: ntn-1p8-en-state { + pins = "gpio3"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + tc9563_resx_n: tc9563-resx-state { + pins = "gpio1"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; +}; + +&pm8350c_pwm { + nvmem = <&pmk8350_sdam_21>, + <&pmk8350_sdam_22>; + nvmem-names = "lpg_chan_sdam", + "lut_sdam"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + channel@3 { + reg = ; + label = "pmk7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = ; + label = "xo_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg = ; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + + status = "okay"; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; + + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <32 2>, /* ADSP */ + <48 4>; /* NFC */ + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sd_cd: sd-cd-state { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; +}; + +&uart5 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p912>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_phy_con_ss>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index 0b64a0b91202..f47efca42d48 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -755,10 +755,10 @@ ports { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; + port@1 { + reg = <1>; - lt9611_a: endpoint { + lt9611_b: endpoint { remote-endpoint = <&mdss_dsi0_out>; }; }; @@ -801,7 +801,7 @@ &mdss_dsi { }; &mdss_dsi0_out { - remote-endpoint = <<9611_a>; + remote-endpoint = <<9611_b>; data-lanes = <0 1 2 3>; }; diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index c04e0ad53eec..e9a8553a8d82 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -18,12 +18,76 @@ / { aliases { serial0 = &uart7; mmc0 = &sdhc_1; + serial1 = &uart2; }; chosen { stdout-path = "serial0:115200n8"; }; + vreg_1p0: regulator-vreg-1p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P0"; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + vin-supply = <&vreg_1p8>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-vreg-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&vreg_5p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_3p0: regulator-vreg-3p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_3P0"; + + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&vreg_12p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_5p0: regulator-vreg-5p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_5P0"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vreg_12p0>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_12p0: regulator-vreg-12p0 { + compatible = "regulator-fixed"; + regulator-name = "VREG_12P0"; + + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + regulator-always-on; + regulator-boot-on; + }; + dp0-connector { compatible = "dp-connector"; label = "DP0"; @@ -36,6 +100,62 @@ dp0_connector_in: endpoint { }; }; + dp-dsi0-connector { + compatible = "dp-connector"; + label = "DSI0"; + type = "full-size"; + + port { + dp_dsi0_connector_in: endpoint { + remote-endpoint = <&dsi2dp_bridge_out>; + }; + }; + }; + + vreg_conn_1p05: regulator-conn-1p05 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + vin-supply = <&vreg_conn_1p8>; + }; + + vreg_conn_1p35: regulator-conn-1p35 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + vin-supply = <&vreg_conn_1p8>; + }; + + vreg_conn_1p8: regulator-conn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pmm8650au_1_gpios 4 GPIO_ACTIVE_HIGH>; + }; + + vreg_conn_1p95: regulator-conn-1p95 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p95"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + vin-supply = <&vreg_conn_1p8>; + }; + + vreg_conn_pa: regulator-conn-pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pmm8650au_1_gpios 6 GPIO_ACTIVE_HIGH>; + }; + regulator-usb2-vbus { compatible = "regulator-fixed"; regulator-name = "USB2_VBUS"; @@ -45,6 +165,70 @@ regulator-usb2-vbus { enable-active-high; regulator-always-on; }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + pinctrl-0 = <&wlan_en_state>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_conn_pa>; + vddaon-supply = <&vreg_conn_1p8>; + vddpmu-supply = <&vreg_conn_pa>; + vddpmumx-supply = <&vreg_conn_1p8>; + vddpmucx-supply = <&vreg_conn_pa>; + /* WLAN rails: 1.05/1.35/1.95V (nominal 0.95/1.30/1.90V) */ + vddrfa0p95-supply = <&vreg_conn_1p05>; + vddrfa1p3-supply = <&vreg_conn_1p35>; + vddrfa1p9-supply = <&vreg_conn_1p95>; + vddpcie1p3-supply = <&vreg_conn_1p35>; + vddpcie1p9-supply = <&vreg_conn_1p95>; + + bt-enable-gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -316,6 +500,75 @@ &gpu_zap_shader { firmware-name = "qcom/qcs8300/a623_zap.mbn"; }; +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + io_expander: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + interrupts-extended = <&tlmm 93 IRQ_TYPE_EDGE_BOTH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&io_expander_intr_active>, + <&io_expander_reset_active>; + pinctrl-names = "default"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + bridge@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupts-extended = <&io_expander 2 IRQ_TYPE_EDGE_FALLING>; + enable-gpios = <&io_expander 1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&vreg_1p0>; + vdd18-supply = <&vreg_1p8>; + vdd33-supply = <&vreg_3p0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_bridge_in: endpoint { + + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_bridge_out: endpoint { + + remote-endpoint = <&dp_dsi0_connector_in>; + }; + }; + }; + }; + }; + }; +}; + &pmm8650au_1_gpios { usb2_en: usb2-en-state { pins = "gpio7"; @@ -363,6 +616,23 @@ &pcie0 { &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + + qcom,calibration-variant = "QC_QCS8300_Ride"; + }; }; &pcie0_phy { @@ -391,10 +661,31 @@ &pcie1_phy { status = "okay"; }; +&mdss_dsi0 { + vdda-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&dsi2dp_bridge_in>; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/qcs8300/adsp.mbn"; status = "okay"; @@ -436,6 +727,12 @@ &sdhc_1 { }; &tlmm { + bt_en_state: bt-en-state { + pins = "gpio55"; + function = "gpio"; + bias-pull-down; + }; + pcie0_default_state: pcie0-default-state { wake-pins { pins = "gpio0"; @@ -498,11 +795,50 @@ perst-pins { }; }; + io_expander_reset_active: io-expander-reset-active-state { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + io_expander_intr_active: io-expander-intr-active-state { + pins = "gpio93"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + dp_hot_plug_det: dp-hot-plug-det-state { pins = "gpio94"; function = "edp0_hot"; bias-disable; }; + + wlan_en_state: wlan-en-state { + pins = "gpio54"; + function = "gpio"; + bias-pull-down; + }; +}; + +&uart2 { + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6855-bt"; + firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv"; + max-speed = <3200000>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; }; &uart7 { diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index cdfe40da5d33..952d4270d118 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1638,10 +1638,10 @@ multi_chan_ddr: multi-chan-ddr@12b { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - , - ; + interrupts = , + , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts index 197ab6eb1666..bf088fa9807f 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "agatti.dtsi" #include "pm4125.dtsi" @@ -109,6 +110,15 @@ multi-led { leds = <&ledr>, <&ledg>, <&ledb>; }; + vreg_anx_30: regulator-anx-30 { + compatible = "regulator-fixed"; + regulator-name = "anx30"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + /* PM4125 charger out, supplied by VBAT */ vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -142,6 +152,86 @@ &i2c1 { clock-frequency = <100000>; status = "okay"; + + anx7625: encoder@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + interrupts-extended = <&tlmm 81 IRQ_TYPE_EDGE_FALLING>; + vdd10-supply = <&pm4125_l11>; + vdd18-supply = <&pm4125_l15>; + vdd33-supply = <&vreg_anx_30>; + analogix,audio-enable; + analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; + analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>; + + pinctrl-0 = <&anx7625_int_pin>, <&anx7625_cable_det_pin>; + + connector { + compatible = "usb-c-connector"; + power-role = "sink"; + data-role = "dual"; + try-power-role = "sink"; + + pd-revision = /bits/ 8 <0x03 0x00 0x00 0x00>; + op-sink-microwatt = <15000000>; + sink-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + anx_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx_dsi0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + data-lanes = <0 1 2 3>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm4125_l5>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&anx_dsi0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; }; &pm4125_vbus { @@ -325,21 +415,13 @@ &sdhc_1 { &spi5 { status = "okay"; - spidev@0 { - reg = <0>; + mcu@0 { compatible = "arduino,unoq-mcu"; - pinctrl-0 = <&spidev_cs>; - pinctrl-names = "default"; + reg = <0>; }; }; &tlmm { - spidev_cs: spidev-cs-state { - pins = "gpio17"; - function = "gpio"; - drive-strength = <16>; - }; - jmisc_gpio18: jmisc-gpio18-state { pins = "gpio18"; function = "gpio"; @@ -361,6 +443,22 @@ key_vold_n: key-vold-n-state { output-disable; }; + anx7625_cable_det_pin: anx7625-cable-det-pins-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <16>; + output-disable; + bias-pull-up; + }; + + anx7625_int_pin: anx7625-int-pins-state { + pins = "gpio81"; + function = "gpio"; + drive-strength = <16>; + output-disable; + bias-pull-up; + }; + key_volp_n: key-volp-n-state { pins = "gpio96"; function = "gpio"; @@ -428,6 +526,10 @@ &usb { status = "okay"; }; +&usb_dwc3_hs { + remote-endpoint = <&anx_hs_in>; +}; + &usb_hsphy { vdd-supply = <&pm4125_l12>; vdda-pll-supply = <&pm4125_l13>; @@ -443,6 +545,10 @@ &usb_qmpphy { status = "okay"; }; +&usb_qmpphy_out { + remote-endpoint = <&anx_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 9814ac4896c5..da46e9d65528 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -109,7 +109,6 @@ vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { regulator-name = "VREG_HDMI_OUT_1P2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - vin-supply = <&vdc_1v2>; regulator-always-on; regulator-boot-on; }; @@ -119,39 +118,6 @@ lt9611_3v3: regulator-lt9611-3v3 { regulator-name = "LT9611_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vdc_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - /* Main barrel jack input */ - vdc_12v: regulator-vdc-12v { - compatible = "regulator-fixed"; - regulator-name = "DC_12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* 1.2V supply stepped down from the barrel jack input */ - vdc_1v2: regulator-vdc-1v2 { - compatible = "regulator-fixed"; - regulator-name = "VDC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vdc_12v>; - regulator-always-on; - regulator-boot-on; - }; - - /* 3.3V supply stepped down from the barrel jack input */ - vdc_3v3: regulator-vdc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdc_12v>; regulator-always-on; regulator-boot-on; }; @@ -167,23 +133,12 @@ vdc_5v: regulator-vdc-5v { regulator-boot-on; }; - /* "Battery" voltage for the SoM, stepped down from the barrel jack input */ - vdc_vbat_som: regulator-vdc-vbat { - compatible = "regulator-fixed"; - regulator-name = "VBAT_SOM"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - regulator-boot-on; - }; - /* PM2250 charger out, supplied by VBAT */ vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; - vin-supply = <&vdc_vbat_som>; regulator-always-on; regulator-boot-on; @@ -235,6 +190,42 @@ platform { }; }; }; + + wcn3950-pmu { + compatible = "qcom,wcn3950-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + vddio-supply = <&pm4125_l15>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + + swctrl-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &cpu_pd0 { @@ -754,6 +745,12 @@ lt9611_irq_pin: lt9611-irq-state { bias-disable; }; + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio87"; + function = "gpio"; + bias-pull-down; + }; + sd_det_in_on: sd-det-in-on-state { pins = "gpio88"; function = "gpio"; @@ -789,11 +786,10 @@ &uart3 { bluetooth { compatible = "qcom,wcn3950-bt"; - vddio-supply = <&pm4125_l15>; - vddxo-supply = <&pm4125_l13>; - vddrf-supply = <&pm4125_l10>; - vddch0-supply = <&pm4125_l22>; - enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; max-speed = <3200000>; }; }; @@ -834,10 +830,13 @@ &venus { }; &wifi { + /* SoC */ vdd-0.8-cx-mx-supply = <&pm4125_l7>; - vdd-1.8-xo-supply = <&pm4125_l13>; - vdd-1.3-rfa-supply = <&pm4125_l10>; - vdd-3.3-ch0-supply = <&pm4125_l22>; + + /* WiFi / BT PMU */ + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; qcom,calibration-variant = "Thundercomm_RB1"; firmware-name = "qcm2290"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 5f8613150bdd..1203172729fa 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -158,7 +158,6 @@ vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { regulator-name = "VREG_HDMI_OUT_1P2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - vin-supply = <&vdc_1v2>; regulator-always-on; regulator-boot-on; }; @@ -168,39 +167,6 @@ lt9611_3v3: regulator-lt9611-3v3 { regulator-name = "LT9611_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vdc_3v3>; - regulator-always-on; - regulator-boot-on; - }; - - /* Main barrel jack input */ - vdc_12v: regulator-vdc-12v { - compatible = "regulator-fixed"; - regulator-name = "DC_12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - regulator-boot-on; - }; - - /* 1.2V supply stepped down from the barrel jack input */ - vdc_1v2: regulator-vdc-1v2 { - compatible = "regulator-fixed"; - regulator-name = "VDC_1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vdc_12v>; - regulator-always-on; - regulator-boot-on; - }; - - /* 3.3V supply stepped down from the barrel jack input */ - vdc_3v3: regulator-vdc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdc_12v>; regulator-always-on; regulator-boot-on; }; @@ -216,27 +182,52 @@ vdc_5v: regulator-vdc-5v { regulator-boot-on; }; - /* "Battery" voltage for the SoM, stepped down from the barrel jack input */ - vdc_vbat_som: regulator-vdc-vbat { - compatible = "regulator-fixed"; - regulator-name = "VBAT_SOM"; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - regulator-boot-on; - }; - /* PMI632 charger out, supplied by VBAT */ vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; - vin-supply = <&vdc_vbat_som>; regulator-always-on; regulator-boot-on; }; + + wcn3988-pmu { + compatible = "qcom,wcn3988-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_l9a_1p8>; + vddxo-supply = <&vreg_l16a_1p3>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l23a_3p3>; + + swctrl-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &gpi_dma0 { @@ -684,6 +675,12 @@ lt9611_irq_pin: lt9611-irq-state { bias-disable; }; + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio87"; + function = "gpio"; + bias-pull-down; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio88"; function = "gpio"; @@ -703,11 +700,10 @@ &uart3 { bluetooth { compatible = "qcom,wcn3988-bt"; - vddio-supply = <&vreg_l9a_1p8>; - vddxo-supply = <&vreg_l16a_1p3>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l23a_3p3>; - enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; max-speed = <3200000>; }; }; @@ -744,10 +740,13 @@ &usb_qmpphy_out { }; &wifi { + /* SoC */ vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>; - vdd-1.8-xo-supply = <&vreg_l16a_1p3>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l23a_3p3>; + + /* WiFi / BT PMU */ + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; qcom,calibration-variant = "Thundercomm_RB2"; firmware-name = "qrb4210"; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 71b42e76f03d..54da0d759a67 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -38,14 +38,6 @@ clk40m: can-clock { clock-frequency = <40000000>; }; - dc12v: dc12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "DC12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - hdmi-out { compatible = "hdmi-connector"; type = "a"; @@ -92,7 +84,7 @@ lt9611_1v2: lt9611-vdd12-regulator { compatible = "regulator-fixed"; regulator-name = "LT9611_1V2"; - vin-supply = <&vdc_3v3>; + vin-supply = <&vreg_l11c_3p3>; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; @@ -101,7 +93,7 @@ lt9611_3v3: lt9611-3v3 { compatible = "regulator-fixed"; regulator-name = "LT9611_3V3"; - vin-supply = <&vdc_3v3>; + vin-supply = <&vreg_l11c_3p3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -231,33 +223,6 @@ active-config0 { }; }; - vbat: vbat-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT"; - vin-supply = <&vreg_l11c_3p3>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vbat_som: vbat-som-regulator { - compatible = "regulator-fixed"; - regulator-name = "VBAT_SOM"; - vin-supply = <&dc12v>; - regulator-min-microvolt = <4200000>; - regulator-max-microvolt = <4200000>; - regulator-always-on; - }; - - vdc_3v3: vdc-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "VDC_3V3"; - vin-supply = <&vreg_l11c_3p3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - vdc_5v: vdc-5v-regulator { compatible = "regulator-fixed"; regulator-name = "VDC_5V"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts b/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts new file mode 100644 index 000000000000..b84da371581b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include +#include +#include + +#include "sc7180.dtsi" + +#include "pm6150.dtsi" +#include "pm6150l.dtsi" + +/delete-node/ &tz_mem; +/delete-node/ &ipa_fw_mem; + +/ { + model = "ECS LIVA QC710"; + compatible = "ecs,liva-qc710", "qcom,sc7180"; + chassis-type = "desktop"; + + aliases { + bluetooth0 = &bluetooth; + hsuart0 = &uart3; + wifi0 = &wifi; + }; + + hdmi-bridge { + compatible = "algoltek,ag6311"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_out>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + reserved-memory { + gpu_mem: zap-shader@80840000 { + reg = <0x0 0x80840000 0 0x2000>; + no-map; + }; + + venus_mem: venus@85b00000 { + reg = <0x0 0x85b00000 0 0x500000>; + no-map; + }; + + mpss_mem: mpss@86000000 { + reg = <0x0 0x86000000 0x0 0x2000000>; + no-map; + }; + + adsp_mem: adsp@8e400000 { + reg = <0x0 0x8e400000 0x0 0x2800000>; + no-map; + }; + + wlan_mem: wlan@93900000 { + reg = <0x0 0x93900000 0x0 0x200000>; + no-map; + }; + }; + + usb_a_connector: usb-a-connector { + compatible = "usb-a-connector"; + + port { + usb_a_connector_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_out>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm6150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s1a_1p1: smps1 { + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_l4a_0p8: ldo4 { + regulator-min-microvolt = <824000>; + regulator-max-microvolt = <928000>; + regulator-initial-mode = ; + }; + + vreg_l9a_0p6: ldo9 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l11a_1p8: ldo11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_1p8: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p8: ldo18 { + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l19a_2p9: ldo19 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm6150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1616000>; + regulator-max-microvolt = <1984000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1168000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sc7180/ecs/liva-qc710/qcdxkmsuc7180.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_1_qmpphy_dp_in>; +}; + +&pm6150_rtc { + qcom,uefi-rtc-info; + + status = "okay"; +}; + +&qfprom { + vcc-supply = <&vreg_l11a_1p8>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + memory-region = <&adsp_mem>; + firmware-name = "qcom/sc7180/ecs/liva-qc710/qcadsp7180.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sc7180/ecs/liva-qc710/qcmpss7180_nm.mbn"; + + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l19a_2p9>; + vqmmc-supply = <&vreg_l12a_1p8>; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9c_2p9>; + vqmmc-supply = <&vreg_l6c_2p9>; + + cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + /* + * The TZ seem to protect those because some boards can have + * fingerprint sensor connected to this range. Not connected + * on this board + */ + gpio-reserved-ranges = <58 5>; + + qup_uart3_sleep: qup-uart3-sleep-state { + cts-pins { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + function = "gpio"; + bias-pull-down; + }; + + rts-pins { + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + pins = "gpio39"; + function = "gpio"; + bias-pull-down; + }; + + tx-pins { + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + pins = "gpio40"; + function = "gpio"; + bias-pull-up; + }; + + rx-pins { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + pins = "gpio41"; + function = "gpio"; + bias-pull-up; + }; + }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <16>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio69"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd-pins { + pins = "gpio69"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; +}; +&uart3 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 41 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart3_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3991-bt"; + vddio-supply = <&vreg_l10a_1p8>; + vddxo-supply = <&vreg_l1c_1p8>; + vddrf-supply = <&vreg_l2c_1p3>; + vddch0-supply = <&vreg_l10c_3p3>; + max-speed = <3200000>; + }; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb5e3,608"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* @1: 3.0 Type-A port on the back + * @2: 2.0 Type-A port the side + * @3: 2.0 Type-C port on the back + */ + + ethernet@4 { + compatible = "usbbda,8152"; + reg = <4>; + }; + }; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l11a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; + qcom,imp-res-offset-value = <8>; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + qcom,bias-ctrl-value = <0x22>; + qcom,charge-ctrl-value = <3>; + qcom,hsdisc-trim-value = <0>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vreg_l4a_0p8>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_qmpphy_dp_out: endpoint@0 { + reg = <0>; + + data-lanes = <3 2>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + usb_1_qmpphy_usb_ss_out: endpoint@1 { + reg = <1>; + + data-lanes = <1 0>; + remote-endpoint = <&usb_a_connector_ss_in>; + }; + }; + }; +}; + +&usb_1_qmpphy_dp_in { + remote-endpoint = <&mdss_dp_out>; +}; + +&venus { + firmware-name = "qcom/sc7180/ecs/liva-qc710/qcvss7180.mbn"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l9a_0p6>; + vdd-1.8-xo-supply = <&vreg_l1c_1p8>; + vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; + vdd-3.3-ch0-supply = <&vreg_l10c_3p3>; + vdd-3.3-ch1-supply = <&vreg_l11c_3p3>; + + qcom,calibration-variant = "ECS_QC710"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 45b9864e3304..a4b17564469e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1646,6 +1646,8 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + sram = <&ipa_modem_tables>; + status = "disabled"; }; @@ -3460,8 +3462,8 @@ port@1 { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -3587,6 +3589,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x2e000>; + ipa_modem_tables: modem-tables@28000 { + reg = <0x28000 0x2000>; + }; + pil-reloc@2a94c { compatible = "qcom,pil-reloc-info"; reg = <0x2a94c 0xc8>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 617a39d32488..debf62baec9b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -140,17 +140,6 @@ &scm { dma-coherent; }; -&venus { - iommus = <&apps_smmu 0x2180 0x20>, - <&apps_smmu 0x2184 0x20>; - - status = "okay"; - - video-firmware { - iommus = <&apps_smmu 0x21a2 0x0>; - }; -}; - &watchdog { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 8319d892c6e4..f45deb188c6c 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3322,8 +3322,8 @@ mdss_dp0_out: endpoint { dp0_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -3404,8 +3404,8 @@ mdss_dp1_out: endpoint { dp1_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -3480,8 +3480,8 @@ mdss_edp_out: endpoint { edp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 706eb1309d3f..761f229e8f47 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -4652,13 +4653,31 @@ ports { port@0 { reg = <0>; + mdss0_intf0_out: endpoint { remote-endpoint = <&mdss0_dp0_in>; }; }; + port@1 { + reg = <1>; + + mdss0_intf1_out: endpoint { + remote-endpoint = <&mdss0_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + + mdss0_intf2_out: endpoint { + remote-endpoint = <&mdss0_dsi1_in>; + }; + }; + port@4 { reg = <4>; + mdss0_intf4_out: endpoint { remote-endpoint = <&mdss0_dp1_in>; }; @@ -4666,6 +4685,7 @@ mdss0_intf4_out: endpoint { port@5 { reg = <5>; + mdss0_intf5_out: endpoint { remote-endpoint = <&mdss0_dp3_in>; }; @@ -4673,6 +4693,7 @@ mdss0_intf5_out: endpoint { port@6 { reg = <6>; + mdss0_intf6_out: endpoint { remote-endpoint = <&mdss0_dp2_in>; }; @@ -4769,8 +4790,8 @@ mdss0_dp0_out: endpoint { mdss0_dp0_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -4791,6 +4812,189 @@ opp-810000000 { }; }; + mdss0_dsi0: dsi@ae94000 { + compatible = "qcom,sc8280xp-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss0>; + interrupts = <4>; + + clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc0 DISP_CC_MDSS_ESC0_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + refgen-supply = <&refgen>; + + phys = <&mdss0_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss0_dsi0_in: endpoint { + remote-endpoint = <&mdss0_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss0_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi0_phy: phy@ae94400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss0_dsi1: dsi@ae96000 { + compatible = "qcom,sc8280xp-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss0>; + interrupts = <5>; + + clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc0 DISP_CC_MDSS_ESC1_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + refgen-supply = <&refgen>; + + phys = <&mdss0_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss0_dsi1_in: endpoint { + remote-endpoint = <&mdss0_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss0_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss0_dsi1_phy: phy@ae96400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + mdss0_dp1: displayport-controller@ae98000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0xae98000 0 0x200>, @@ -4851,8 +5055,8 @@ mdss0_dp1_out: endpoint { mdss0_dp1_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -4931,8 +5135,8 @@ mdss0_dp2_out: endpoint { mdss0_dp2_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5006,8 +5210,8 @@ mdss0_dp3_out: endpoint { mdss0_dp3_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5080,10 +5284,10 @@ dispcc0: clock-controller@af00000 { <&mdss0_dp2_phy 1>, <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>, - <0>, - <0>, - <0>, - <0>; + <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; power-domains = <&rpmhpd SC8280XP_MMCX>; #clock-cells = <1>; @@ -6011,13 +6215,31 @@ ports { port@0 { reg = <0>; + mdss1_intf0_out: endpoint { remote-endpoint = <&mdss1_dp0_in>; }; }; + port@1 { + reg = <1>; + + mdss1_intf1_out: endpoint { + remote-endpoint = <&mdss1_dsi0_in>; + }; + }; + + port@2 { + reg = <2>; + + mdss1_intf2_out: endpoint { + remote-endpoint = <&mdss1_dsi1_in>; + }; + }; + port@4 { reg = <4>; + mdss1_intf4_out: endpoint { remote-endpoint = <&mdss1_dp1_in>; }; @@ -6025,6 +6247,7 @@ mdss1_intf4_out: endpoint { port@5 { reg = <5>; + mdss1_intf5_out: endpoint { remote-endpoint = <&mdss1_dp3_in>; }; @@ -6032,6 +6255,7 @@ mdss1_intf5_out: endpoint { port@6 { reg = <6>; + mdss1_intf6_out: endpoint { remote-endpoint = <&mdss1_dp2_in>; }; @@ -6125,8 +6349,8 @@ mdss1_dp0_out: endpoint { mdss1_dp0_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -6147,6 +6371,170 @@ opp-810000000 { }; }; + mdss1_dsi0: dsi@22094000 { + compatible = "qcom,sc8280xp-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x22094000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss1>; + interrupts = <4>; + + clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc1 DISP_CC_MDSS_ESC0_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + refgen-supply = <&refgen>; + + phys = <&mdss1_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss1_dsi0_in: endpoint { + remote-endpoint = <&mdss1_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss1_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss1_dsi0_phy: phy@22094400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg = <0 0x22094400 0 0x200>, + <0 0x22094600 0 0x280>, + <0 0x22094900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss1_dsi1: dsi@22096000 { + compatible = "qcom,sc8280xp-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0 0x22096000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss1>; + interrupts = <5>; + + clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc1 DISP_CC_MDSS_ESC1_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + refgen-supply = <&refgen>; + + phys = <&mdss1_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss1_dsi1_in: endpoint { + remote-endpoint = <&mdss1_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss1_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss1_dsi1_phy: phy@22096400 { + compatible = "qcom,sc8280xp-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg = <0 0x22096400 0 0x200>, + <0 0x22096600 0 0x280>, + <0 0x22096900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + mdss1_dp1: displayport-controller@22098000 { compatible = "qcom,sc8280xp-dp"; reg = <0 0x22098000 0 0x200>, @@ -6205,8 +6593,8 @@ mdss1_dp1_out: endpoint { mdss1_dp1_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -6285,8 +6673,8 @@ mdss1_dp2_out: endpoint { mdss1_dp2_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -6360,8 +6748,8 @@ mdss1_dp3_out: endpoint { mdss1_dp3_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -6434,10 +6822,10 @@ dispcc1: clock-controller@22100000 { <&mdss1_dp2_phy 1>, <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>, - <0>, - <0>, - <0>, - <0>; + <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; power-domains = <&rpmhpd SC8280XP_MMCX>; #clock-cells = <1>; @@ -6652,9 +7040,9 @@ trip-point0 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 74cb29cb7f1a..9e14f53b552e 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -108,6 +108,43 @@ vreg_l10a_1p8: vreg-l10a-regulator { regulator-always-on; regulator-boot-on; }; + + wcn3990-pmu { + compatible = "qcom,wcn3990-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_l13a_1p8>; + vddxo-supply = <&vreg_l9a_1p8>; + vddrf-supply = <&vreg_l6a_1p3>; + vddch0-supply = <&vreg_l19a_3p3>; + vddch1-supply = <&vreg_l8b_3p3>; + + swctrl-gpios = <&pm660_gpios 5 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &adreno_gpu { @@ -197,10 +234,10 @@ &blsp2_uart1 { bluetooth { compatible = "qcom,wcn3990-bt"; - vddio-supply = <&vreg_l13a_1p8>; - vddxo-supply = <&vreg_l9a_1p8>; - vddrf-supply = <&vreg_l6a_1p3>; - vddch0-supply = <&vreg_l19a_3p3>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; max-speed = <3200000>; }; }; @@ -238,6 +275,16 @@ &pon_resin { linux,code = ; }; +&pm660_gpios { + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio5"; + function = "normal"; + + input-enable; + bias-pull-down; + }; +}; + &qusb2phy0 { status = "okay"; @@ -503,11 +550,14 @@ &usb3_qmpphy { }; &wifi { + /* SoC */ vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l9a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l6a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l19a_3p3>; - vdd-3.3-ch1-supply = <&vreg_l8b_3p3>; + + /* WiFi / BT PMU */ + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + vdd-3.3-ch1-supply = <&vreg_pmu_ch1>; qcom,calibration-variant = "Inforce_IFC6560"; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index f4b8e8f468f2..bef3213165d6 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1013,6 +1013,20 @@ data-pins { drive-strength = <2>; }; }; + + spi7_default: spi7-default-state { + pins = "gpio24", "gpio25", "gpio26", "gpio27"; + function = "blsp_spi7"; + drive-strength = <6>; + bias-disable; + }; + + spi7_sleep: spi7-sleep-state { + pins = "gpio24", "gpio25", "gpio26", "gpio27"; + function = "blsp_spi7"; + drive-strength = <6>; + bias-disable; + }; }; remoteproc_mss: remoteproc@4080000 { @@ -1950,6 +1964,26 @@ blsp_i2c7: i2c@c1b7000 { status = "disabled"; }; + blsp_spi7: spi@c1b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x0c1b7000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi7_default>; + pinctrl-1 = <&spi7_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c8: i2c@c1b8000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x0c1b8000 0x600>; @@ -2755,10 +2789,10 @@ trip-point2 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 746e9deba526..c195c79c1c85 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1130,6 +1130,17 @@ refgen: regulator@ff1000 { reg = <0x0 0x00ff1000 0x0 0x60>; }; + llcc: system-cache-controller@1100000 { + compatible = "qcom,sdm670-llcc"; + reg = <0 0x01100000 0 0x50000>, + <0 0x01180000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc_broadcast_base"; + interrupts = ; + }; + mem_noc: interconnect@1380000 { compatible = "qcom,sdm670-mem-noc"; reg = <0 0x01380000 0 0x27200>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 5118b776a9bb..02416812b6a7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -276,6 +276,43 @@ vph_pwr: vph-pwr-regulator { vin-supply = <&vbat_som>; }; + + wcn3990-pmu { + compatible = "qcom,wcn3990-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; + + swctrl-gpios = <&pm8998_gpios 3 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &adsp_pas { @@ -659,6 +696,14 @@ cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { qcom,drive-strength = ; }; + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio3"; + function = "normal"; + + input-enable; + bias-pull-down; + }; + vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; @@ -1038,10 +1083,11 @@ &uart6 { bluetooth { compatible = "qcom,wcn3990-bt"; - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + max-speed = <3200000>; }; }; @@ -1155,16 +1201,19 @@ right_spkr: speaker@0,2 { }; &wifi { - status = "okay"; - + /* SoC */ vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + /* WiFi / BT PMU */ + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + vdd-3.3-ch1-supply = <&vreg_pmu_ch1>; qcom,snoc-host-cap-8bit-quirk; qcom,calibration-variant = "Thundercomm_DB845C"; + + status = "okay"; }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi index fd9788d5c3f5..693006685776 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -131,6 +131,33 @@ vreg_s4a_1p8: regulator-vreg-s4a-1p8 { vin-supply = <&vph_pwr>; }; + + wcn3990-pmu { + compatible = "qcom,wcn3990-pmu"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + }; + }; }; &adsp_pas { @@ -462,10 +489,11 @@ &uart6 { bluetooth { compatible = "qcom,wcn3990-bt"; - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + max-speed = <3200000>; }; }; @@ -526,9 +554,9 @@ &venus { &wifi { vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; qcom,snoc-host-cap-8bit-quirk; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 0ee2f4b99fbd..71d070619ad7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include @@ -27,10 +28,19 @@ /delete-node/ &wlan_msa_mem; / { + chassis-type = "handset"; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + chosen { #address-cells = <2>; #size-cells = <2>; ranges; + + stdout-path = "serial0:115200n8"; }; reserved-memory { @@ -38,11 +48,6 @@ reserved-memory { #size-cells = <2>; ranges; - qseecom_mem: memory@b2000000 { - reg = <0 0xb2000000 0 0x1800000>; - no-map; - }; - gpu_mem: memory@8c415000 { reg = <0 0x8c415000 0 0x2000>; no-map; @@ -99,6 +104,11 @@ memory@9d400000 { no-map; }; + qseecom_mem: memory@b2000000 { + reg = <0 0xb2000000 0 0x1800000>; + no-map; + }; + rmtfs_mem: rmtfs-region@f0800000 { compatible = "qcom,rmtfs-mem"; reg = <0 0xf0800000 0 0x202000>; @@ -442,10 +452,6 @@ &cdsp_pas { status = "okay"; }; -&dispcc { - status = "disabled"; -}; - &gcc { protected-clocks = , , @@ -454,6 +460,14 @@ &gcc { ; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; }; @@ -467,14 +481,76 @@ &mss_pil { status = "okay"; }; +&pm8998_gpios { + vol_up_pin_a: vol-up-active-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + }; +}; + &pm8998_resin { linux,code = ; status = "okay"; }; -&sdhc_2 { +&pmi8998_lpg { status = "okay"; + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@3 { + reg = <3>; + color = ; + }; + + led@4 { + reg = <4>; + color = ; + }; + + led@5 { + reg = <5>; + color = ; + }; + }; +}; + +&pmi8998_wled { + qcom,current-limit-microamp = <20000>; + qcom,ovp-millivolt = <29600>; + qcom,switching-freq = <800>; + qcom,num-strings = <3>; + qcom,cabc; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; +}; + +&sdhc_2 { cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -482,55 +558,8 @@ &sdhc_2 { vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vddpx_2>; -}; -/* - * UFS works partially and only with clk_ignore_unused. - * Sometimes it crashes with I/O errors. - */ -&ufs_mem_hc { status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l20a_2p95>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - /* TODO: these devices have usb id pin */ - dr_mode = "peripheral"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ @@ -571,12 +600,85 @@ sd_card_det_n: sd-card-det-n-state { }; }; -&pm8998_gpios { - vol_up_pin_a: vol-up-active-state { - pins = "gpio6"; - function = "normal"; - input-enable; - bias-pull-up; - qcom,drive-strength = ; +&uart6 { + pinctrl-0 = <&qup_uart6_4pin>; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; }; }; + +&uart9 { + status = "okay"; +}; + +/* + * UFS works partially and only with clk_ignore_unused. + * Sometimes it crashes with I/O errors. + */ +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + /* TODO: these devices have usb id pin */ + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts index 09bfcef42402..adf41aa0146a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -21,8 +21,6 @@ framebuffer@9d400000 { height = <3120>; stride = <(1440 * 4)>; format = "a8r8g8b8"; - lab-supply = <&lab>; - ibb-supply = <&ibb>; }; }; @@ -37,22 +35,110 @@ key-thinq { interrupts = <89 IRQ_TYPE_LEVEL_LOW>; }; }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3000000>; + voltage-min-design-microvolt = <3200000>; + voltage-max-design-microvolt = <4400000>; + }; }; &adsp_pas { - firmware-name = "qcom/sdm845/judyln/adsp.mbn"; + firmware-name = "qcom/sdm845/LG/judyln/adsp.mbn"; +}; + +&bluetooth { + /* + * This path is relative to the qca/ + * subdir under lib/firmware. + */ + firmware-name = "judyln/crnv21.bin"; }; &cdsp_pas { - firmware-name = "qcom/sdm845/judyln/cdsp.mbn"; + firmware-name = "qcom/sdm845/LG/judyln/cdsp.mbn"; }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/judyln/a630_zap.mbn"; + firmware-name = "qcom/sdm845/LG/judyln/a630_zap.mbn"; +}; + +&ipa { + firmware-name = "qcom/sdm845/LG/judyln/ipa_fws.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + status = "okay"; + + display_panel: panel@0 { + reg = <0>; + compatible = "lg,sw49410-lh609qh1", "lg,sw49410"; + + backlight = <&pmi8998_wled>; + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + width-mm = <65>; + height-mm = <140>; + + vsp-supply = <&lab>; + vsn-supply = <&ibb>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; + pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; + qcom,te-source = "mdp_vsync_e"; +}; + +&ibb { + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-over-current-protection; + regulator-pull-down; + regulator-soft-start; + qcom,discharge-resistor-kohms = <300>; +}; + +&lab { + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-over-current-protection; + regulator-pull-down; + regulator-soft-start; }; &mss_pil { - firmware-name = "qcom/sdm845/judyln/mba.mbn", "qcom/sdm845/judyln/modem.mbn"; + firmware-name = "qcom/sdm845/LG/judyln/mba.mbn", "qcom/sdm845/LG/judyln/modem.mbn"; +}; + +&pmi8998_charger { + monitored-battery = <&battery>; + + status = "okay"; }; &tlmm { @@ -63,4 +149,33 @@ thinq_key_default: thinq-key-default-state { drive-strength = <2>; bias-pull-up; }; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_sleep: sde-dsi-sleep-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active_sleep: sde-te-active-sleep-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&venus { + firmware-name = "qcom/sdm845/LG/judyln/venus.mbn"; +}; + +&wifi { + qcom,calibration-variant = "lg_judyln"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts index ffe1da2227f0..d244ebdd17be 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyp.dts @@ -26,17 +26,37 @@ framebuffer@9d400000 { }; &adsp_pas { - firmware-name = "qcom/sdm845/judyp/adsp.mbn"; + firmware-name = "qcom/sdm845/LG/judyp/adsp.mbn"; +}; + +&bluetooth { + /* + * This path is relative to the qca/ + * subdir under lib/firmware. + */ + firmware-name = "judyp/crnv21.bin"; }; &cdsp_pas { - firmware-name = "qcom/sdm845/judyp/cdsp.mbn"; + firmware-name = "qcom/sdm845/LG/judyp/cdsp.mbn"; }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/judyp/a630_zap.mbn"; + firmware-name = "qcom/sdm845/LG/judyp/a630_zap.mbn"; +}; + +&ipa { + firmware-name = "qcom/sdm845/LG/judyp/ipa_fws.mbn"; }; &mss_pil { - firmware-name = "qcom/sdm845/judyp/mba.mbn", "qcom/sdm845/judyp/modem.mbn"; + firmware-name = "qcom/sdm845/LG/judyp/mba.mbn", "qcom/sdm845/LG/judyp/modem.mbn"; +}; + +&venus { + firmware-name = "qcom/sdm845/LG/judyp/venus.mbn"; +}; + +&wifi { + qcom,calibration-variant = "lg_judyp"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 5b121ea5520f..6b7378cf4d49 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -25,6 +25,41 @@ / { chassis-type = "handset"; qcom,msm-id = ; + alert-slider { + compatible = "gpio-keys"; + label = "Alert slider"; + + pinctrl-0 = <&alert_slider_default>; + pinctrl-names = "default"; + + switch-top { + label = "Silent"; + linux,input-type = ; + linux,code = ; + linux,input-value = ; + gpios = <&tlmm 126 GPIO_ACTIVE_LOW>; + linux,can-disable; + }; + + switch-middle { + label = "Vibrate"; + linux,input-type = ; + linux,code = ; + linux,input-value = ; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; + linux,can-disable; + }; + + switch-bottom { + label = "Ring"; + linux,input-type = ; + linux,code = ; + linux,input-value = ; + gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; + linux,can-disable; + }; + }; + aliases { serial0 = &uart9; serial1 = &uart6; @@ -195,6 +230,43 @@ panel_vddi_poc_1p8: panel-vddi-poc-regulator { pinctrl-names = "default"; regulator-boot-on; }; + + wcn3990-pmu { + compatible = "qcom,wcn3990-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; + + swctrl-gpios = <&pm8998_gpios 3 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &adsp_pas { @@ -501,6 +573,14 @@ &mss_pil { }; &pm8998_gpios { + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio3"; + function = "normal"; + + input-enable; + bias-pull-down; + }; + volume_down_gpio: pm8998-gpio5-state { pinconf { pins = "gpio5"; @@ -769,10 +849,11 @@ bluetooth { */ firmware-name = "OnePlus/enchilada/crnv21.bin"; - vddio-supply = <&vreg_s4a_1p8>; - vddxo-supply = <&vreg_l7a_1p8>; - vddrf-supply = <&vreg_l17a_1p3>; - vddch0-supply = <&vreg_l25a_3p3>; + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + max-speed = <3200000>; }; }; @@ -946,13 +1027,14 @@ &wcd9340 { }; &wifi { - status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; - vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; - vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + vdd-3.3-ch1-supply = <&vreg_pmu_ch1>; qcom,calibration-variant = "oneplus_sdm845"; qcom,snoc-host-cap-8bit-quirk; + + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 51b041f91d3e..7d81198bc499 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -432,6 +432,8 @@ &gpu_zap_shader { }; &i2c5 { + clock-frequency = <400000>; + status = "okay"; touchscreen@38 { @@ -457,6 +459,19 @@ &i2c10 { /* SMB1355@0x0C */ }; +&i2c11 { + clock-frequency = <400000>; + + status = "okay"; + + audio-codec@34 { + compatible = "nxp,tfa9890"; + reg = <0x34>; + vddd-supply = <&vreg_s4a_1p8>; + #sound-dai-cells = <0>; + }; +}; + &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; @@ -483,8 +498,8 @@ panel@0 { reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + pinctrl-0 = <&sde_dsi_active &sde_te>; + pinctrl-1 = <&sde_dsi_suspend &sde_te>; port { panel_in_0: endpoint { @@ -600,6 +615,24 @@ &qupv3_id_1 { status = "okay"; }; +&sdhc_2 { + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-names = "default"; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + bus-width = <4>; + /* + * Card detection is broken, but because the battery must be removed + * to insert the card, we use this rather than the broken-cd property + * which would just waste CPU cycles polling. + */ + non-removable; + + status = "okay"; +}; + &slpi_pas { firmware-name = "qcom/sdm845/SHIFT/axolotl/slpi.mbn"; @@ -609,6 +642,32 @@ &slpi_pas { &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-disable; + }; + sde_dsi_active: sde-dsi-active-state { pins = "gpio6", "gpio11"; function = "gpio"; @@ -623,14 +682,7 @@ sde_dsi_suspend: sde-dsi-suspend-state { bias-pull-down; }; - sde_te_active: sde-te-active-state { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - sde_te_suspend: sde-te-suspend-state { + sde_te: sde-te-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 7dc9349eedfd..4c63286d8b04 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -17,8 +17,8 @@ / { qcom,board-id = <8 0>; aliases { - serial0 = &uart6; - serial1 = &uart9; + serial0 = &uart9; + serial1 = &uart6; }; chosen { @@ -755,6 +755,19 @@ int-pins { &uart6 { status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + firmware-name = "Sony/tama/crnv21.bin"; + + vddio-supply = <&vreg_s3a_1p3>; + vddxo-supply = <&vreg_s5a_1p9>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p0>; + + max-speed = <3200000>; + }; }; &uart9 { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 01b570d0880d..1298485c4214 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -148,6 +148,7 @@ vreg_l1a_0p875: ldo1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; regulator-initial-mode = ; + regulator-boot-on; }; vreg_l5a_0p8: ldo5 { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bf2f9c04adba..4ae8627d6dbc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2780,6 +2780,8 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + sram = <&ipa_modem_tables>; + status = "disabled"; }; @@ -2805,6 +2807,62 @@ tlmm: pinctrl@3400000 { gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc_intc>; + cam_mclk0_default: cam-mclk0-default-state { + pins = "gpio13"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk0_sleep: cam-mclk0-sleep-state { + pins = "gpio13"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam_mclk1_default: cam-mclk1-default-state { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk1_sleep: cam-mclk1-sleep-state { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam_mclk2_default: cam-mclk2-default-state { + pins = "gpio15"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk2_sleep: cam-mclk2-sleep-state { + pins = "gpio15"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam_mclk3_default: cam-mclk3-default-state { + pins = "gpio16"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk3_sleep: cam-mclk3-sleep-state { + pins = "gpio16"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + cci0_default: cci0-default-state { /* SDA, SCL */ pins = "gpio17", "gpio18"; @@ -5134,6 +5192,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x40000>; + ipa_modem_tables: modem-tables@3d000 { + reg = <0x3d000 0x2000>; + }; + pil-reloc@3f94c { compatible = "qcom,pil-reloc-info"; reg = <0x3f94c 0xc8>; diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index eff4c9055d66..d1b61530b562 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1580,9 +1580,9 @@ gem_noc: interconnect@19100000 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index d217d922811e..696e2e0841ad 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -678,9 +678,9 @@ cpufreq_hw: cpufreq@17d91000 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index e9336adbc391..bd94eb87d6f9 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1864,6 +1864,8 @@ mdss: display-subsystem@5e00000 { <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -3460,9 +3462,9 @@ trip-point1 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi new file mode 100644 index 000000000000..7eecd9dc3028 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Gabriel Gonzales + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "sm6125.dtsi" +#include "pm6125.dtsi" + +/delete-node/ &adsp_pil_mem; +/delete-node/ &cont_splash_mem; +/delete-node/ &gpu_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; + +/ { + model = "Xiaomi Redmi Note 8"; + compatible = "xiaomi,ginkgo", "qcom,sm6125"; + chassis-type = "handset"; + + qcom,msm-id = ; + + aliases { + serial0 = &uart4; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_mem>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + reserved-memory { + adsp_pil_mem: adsp_pil_mem@55300000 { + reg = <0x0 0x55300000 0x0 0x2200000>; + no-map; + }; + + ipa_fw_mem: ipa_fw_mem@57500000 { + reg = <0x0 0x57500000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa_gsi_mem@57510000 { + reg = <0x0 0x57510000 0x0 0x5000>; + no-map; + }; + + gpu_mem: gpu_mem@57515000 { + reg = <0x0 0x57515000 0x0 0x2000>; + no-map; + }; + + framebuffer_mem: framebuffer@5c000000 { + reg = <0x0 0x5c000000 0x0 (2340 * 1080 * 4)>; + no-map; + }; + + /* Matching with recovery values to be able to get the results. */ + ramoops@61600000 { + compatible = "ramoops"; + reg = <0x0 0x61600000 0x0 0x400000>; + record-size = <0x80000>; + pmsg-size = <0x200000>; + console-size = <0x100000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; +}; + +&pm6125_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&hsusb_phy1 { + vdd-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l10a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <1422000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + }; + + vreg_l2a: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1056000>; + }; + + vreg_l3a: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1064000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + regulator-allow-set-load; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + regulator-allow-set-load; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + regulator-allow-set-load; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1996000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1264000>; + regulator-allow-set-load; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2856000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + }; +}; + +&sdc2_off_state { + sd-cd-pins { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&sdc2_on_state { + sd-cd-pins { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&sdhc_1 { + vmmc-supply = <&vreg_l24a>; + vqmmc-supply = <&vreg_l11a>; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <30 4>; +}; + +&uart4 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts index 6b68e391cf3e..496f33e9d73c 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts @@ -2,294 +2,11 @@ /* * Copyright (c) 2025, Gabriel Gonzales */ - /dts-v1/; -#include -#include -#include -#include -#include -#include "sm6125.dtsi" -#include "pm6125.dtsi" +#include "sm6125-xiaomi-ginkgo-common.dtsi" / { model = "Xiaomi Redmi Note 8"; compatible = "xiaomi,ginkgo", "qcom,sm6125"; - chassis-type = "handset"; - - /* required for bootloader to select correct board */ - qcom,msm-id = ; - qcom,board-id = <22 0>; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - framebuffer0: framebuffer@5c000000 { - compatible = "simple-framebuffer"; - reg = <0 0x5c000000 0 (2340 * 1080 * 4)>; - width = <1080>; - height = <2340>; - stride = <(1080 * 4)>; - format = "a8r8g8b8"; - }; - }; - - reserved-memory { - debug_mem: debug@ffb00000 { - reg = <0x0 0xffb00000 0x0 0xc0000>; - no-map; - }; - - last_log_mem: lastlog@ffbc0000 { - reg = <0x0 0xffbc0000 0x0 0x80000>; - no-map; - }; - - pstore_mem: ramoops@ffc00000 { - compatible = "ramoops"; - reg = <0x0 0xffc40000 0x0 0xc0000>; - record-size = <0x1000>; - console-size = <0x40000>; - pmsg-size = <0x20000>; - }; - - cmdline_mem: memory@ffd00000 { - reg = <0x0 0xffd40000 0x0 0x1000>; - no-map; - }; - }; - - extcon_usb: extcon-usb { - compatible = "linux,extcon-usb-gpio"; - id-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&vol_up_n>; - pinctrl-names = "default"; - - key-volume-up { - label = "Volume Up"; - gpios = <&pm6125_gpios 6 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <15>; - linux,can-disable; - wakeup-source; - }; - }; -}; - -&pm6125_gpios { - vol_up_n: vol-up-n-state { - pins = "gpio6"; - function = "normal"; - power-source = <1>; - bias-pull-up; - input-enable; - }; -}; - -&hsusb_phy1 { - vdd-supply = <&vreg_l7a>; - vdda-pll-supply = <&vreg_l10a>; - vdda-phy-dpdm-supply = <&vreg_l15a>; - status = "okay"; -}; - -&pon_pwrkey { - status = "okay"; -}; - -&pon_resin { - linux,code = ; - status = "okay"; -}; - -&rpm_requests { - regulators-0 { - compatible = "qcom,rpm-pm6125-regulators"; - - vreg_s6a: s6 { - regulator-min-microvolt = <936000>; - regulator-max-microvolt = <1422000>; - }; - - vreg_l1a: l1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1256000>; - }; - - vreg_l2a: l2 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1056000>; - }; - - vreg_l3a: l3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1064000>; - }; - - vreg_l4a: l4 { - regulator-min-microvolt = <872000>; - regulator-max-microvolt = <976000>; - regulator-allow-set-load; - }; - - vreg_l5a: l5 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - - vreg_l6a: l6 { - regulator-min-microvolt = <576000>; - regulator-max-microvolt = <656000>; - }; - - vreg_l7a: l7 { - regulator-min-microvolt = <872000>; - regulator-max-microvolt = <976000>; - }; - - vreg_l8a: l8 { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <728000>; - }; - - vreg_l9a: l9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1896000>; - }; - - vreg_l10a: l10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1896000>; - regulator-allow-set-load; - }; - - vreg_l11a: l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1952000>; - regulator-allow-set-load; - }; - - vreg_l12a: l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1996000>; - }; - - vreg_l13a: l13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1832000>; - }; - - vreg_l14a: l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1904000>; - }; - - vreg_l15a: l15 { - regulator-min-microvolt = <3104000>; - regulator-max-microvolt = <3232000>; - }; - - vreg_l16a: l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1904000>; - }; - - vreg_l17a: l17 { - regulator-min-microvolt = <1248000>; - regulator-max-microvolt = <1304000>; - }; - - vreg_l18a: l18 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1264000>; - regulator-allow-set-load; - }; - - vreg_l19a: l19 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <2952000>; - }; - - vreg_l20a: l20 { - regulator-min-microvolt = <1648000>; - regulator-max-microvolt = <2952000>; - }; - - vreg_l21a: l21 { - regulator-min-microvolt = <2600000>; - regulator-max-microvolt = <2856000>; - }; - - vreg_l22a: l22 { - regulator-min-microvolt = <2944000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - - vreg_l23a: l23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3400000>; - }; - - vreg_l24a: l24 { - regulator-min-microvolt = <2944000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - }; - - }; -}; - -&sdc2_off_state { - sd-cd-pins { - pins = "gpio98"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; - -&sdc2_on_state { - sd-cd-pins { - pins = "gpio98"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; -}; - -&sdhc_1 { - vmmc-supply = <&vreg_l24a>; - vqmmc-supply = <&vreg_l11a>; - status = "okay"; -}; - -&sdhc_2 { - cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vreg_l22a>; - vqmmc-supply = <&vreg_l5a>; - no-sdio; - no-mmc; - status = "okay"; -}; - -&tlmm { - gpio-reserved-ranges = <22 2>, <28 6>; -}; - -&usb3 { - status = "okay"; -}; - -&usb3_dwc3 { - extcon = <&extcon_usb>; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index 994fb0412fcb..97f64cb5d570 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -82,6 +82,19 @@ key-volume-up { }; }; + ts_vdd_supply: regulator-ts-vdd { + compatible = "regulator-fixed"; + regulator-name = "ts_vdd_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + + enable-active-high; + gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&ts_vdd_en>; + pinctrl-names = "default"; + }; + thermal-zones { rf-pa0-thermal { thermal-sensors = <&pm6125_adc_tm 0>; @@ -128,6 +141,27 @@ &hsusb_phy1 { status = "okay"; }; +&i2c2 { + status = "okay"; + + touchscreen@38 { + compatible = "focaltech,ft3518"; + reg = <0x38>; + interrupts-extended = <&tlmm 88 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&ts_vdd_supply>; + + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-names = "default","sleep"; + + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1560>; + }; +}; + &pm6125_adc { pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm>; @@ -220,6 +254,10 @@ &pon_resin { status = "okay"; }; +&qupv3_id_0 { + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm6125-regulators"; @@ -387,6 +425,41 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <22 2>, <28 6>; + + ts_vdd_en: ts-vdd-default-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_reset_active: pmx-ts-reset-active-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset_suspend: pmx-ts-reset-suspend-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_int_active: pmx-ts-int-active-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_int_suspend: pmx-ts-int-suspend-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts new file mode 100644 index 000000000000..1231e440ba2c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-willow.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Barnabas Czeman + */ +/dts-v1/; + +#include "sm6125-xiaomi-ginkgo-common.dtsi" + +/ { + model = "Xiaomi Redmi Note 8T"; + compatible = "xiaomi,willow", "qcom,sm6125"; + +}; + +/* Difference from Redmi Note 8 it have NFC */ diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 80c42dff5399..6e84c226948c 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -661,6 +661,13 @@ qup_spi9_sleep: qup-spi9-sleep-state { drive-strength = <6>; bias-disable; }; + + qup_uart4_default: qup-uart4-default-state { + pins = "gpio16", "gpio17"; + function = "qup04"; + drive-strength = <2>; + bias-disable; + }; }; gcc: clock-controller@1400000 { @@ -686,6 +693,13 @@ hsusb_phy1: phy@1613000 { status = "disabled"; }; + rng: rng@1b53000 { + compatible = "qcom,prng-ee"; + reg = <0x01b53000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x01c40000 0x1100>, @@ -978,6 +992,17 @@ i2c4: i2c@4a90000 { #size-cells = <0>; status = "disabled"; }; + + uart4: serial@4a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x04a90000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = ; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; + status = "disabled"; + }; }; gpi_dma1: dma-controller@4c00000 { @@ -1238,6 +1263,8 @@ mdss: display-subsystem@5e00000 { "ahb", "core"; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + power-domains = <&dispcc MDSS_GDSC>; iommus = <&apps_smmu 0x400 0x0>; @@ -1437,6 +1464,7 @@ dispcc: clock-controller@5f00000 { power-domains = <&rpmpd RPMPD_VDDCX>; #clock-cells = <1>; + #reset-cells = <1>; #power-domain-cells = <1>; }; @@ -1592,10 +1620,10 @@ intc: interrupt-controller@f200000 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <19200000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 9f9b9f9af0da..034545d2af2d 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1307,6 +1307,8 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + sram = <&ipa_modem_tables>; + status = "disabled"; }; @@ -2346,8 +2348,8 @@ mdss_dp_out: endpoint { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -2731,6 +2733,20 @@ qup_uart1_tx: qup-uart1-tx-default-state { }; }; + sram@14680000 { + compatible = "qcom,sm6350-imem", "syscon", "simple-mfd"; + reg = <0 0x14680000 0 0x2e000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0 0x14680000 0x2e000>; + + ipa_modem_tables: modem-tables@28000 { + reg = <0x28000 0x2000>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; @@ -3509,9 +3525,9 @@ video-crit { timer { compatible = "arm,armv8-timer"; clock-frequency = <19200000>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 87d6600ccbd9..ccf572bb1549 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -2469,9 +2469,9 @@ video_crit: video-crit { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index a3c2b26736f4..3964aae47fd4 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -1019,12 +1019,14 @@ &qup_uart1_cts { * the Bluetooth module drives the pin in either * direction or leaves the pin fully unpowered. */ + /delete-property/ bias-disable; bias-bus-hold; }; &qup_uart1_rts { /* We'll drive RTS, so no pull */ drive-strength = <2>; + /delete-property/ bias-pull-down; bias-disable; }; @@ -1035,12 +1037,14 @@ &qup_uart1_rx { * in tri-state (module powered off or not driving the * signal yet). */ + /delete-property/ bias-disable; bias-pull-up; }; &qup_uart1_tx { /* We'll drive TX, so no pull */ drive-strength = <2>; + /delete-property/ bias-pull-up; bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 1eea9c5c6684..6ae6e07c37df 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -20,6 +20,7 @@ / { aliases { serial0 = &uart2; + serial1 = &uart13; }; chosen { @@ -66,6 +67,43 @@ hdmi_con: endpoint { }; }; }; + + wcn3998-pmu { + compatible = "qcom,wcn3998-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l2c_1p3>; + vddch0-supply = <&vreg_l11c_3p3>; + vddch1-supply = <&vreg_l10c_3p3>; + + swctrl-gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &apps_rsc { @@ -598,6 +636,10 @@ &qupv3_id_1 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; @@ -630,12 +672,97 @@ lt9611_irq_pin: lt9611-irq-state { bias-disable; }; + qup_uart13_default: qup-uart13-default-state { + cts-pins { + pins = "gpio43"; + function = "qup13"; + drive-strength = <2>; + bias-bus-hold; + }; + + rts-pins { + pins = "gpio44"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio45"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio46"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_uart13_sleep: qup-uart13-sleep-state { + cts-pins { + pins = "gpio43"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + + rts-pins { + pins = "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + tx-pins { + pins = "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + rx-pins { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio50"; + function = "gpio"; + bias-pull-down; + }; }; &uart2 { status = "okay"; }; +&uart13 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 46 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&qup_uart13_default>; + pinctrl-1 = <&qup_uart13_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3998-bt"; + + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + }; +}; + &ufs_mem_hc { status = "okay"; @@ -709,12 +836,16 @@ &usb_2_dwc3 { }; &wifi { - status = "okay"; - + /* SoC */ vdd-0.8-cx-mx-supply = <&vreg_l1a_0p75>; - vdd-1.8-xo-supply = <&vreg_l7a_1p8>; - vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; - vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + + /* WiFi / BT PMU */ + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + vdd-3.3-ch1-supply = <&vreg_pmu_ch1>; qcom,calibration-variant = "Qualcomm_sm8150hdk"; + + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 97ca5275d740..0e101096209a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3954,8 +3954,8 @@ mdss_dp_out: endpoint { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c7dffa440074..7076720413ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -665,6 +665,11 @@ cpu7_opp20: opp-2841600000 { opp-hz = /bits/ 64 <2841600000>; opp-peak-kBps = <8368000 51609600>; }; + + cpu7_opp21: opp-3091200000 { + opp-hz = /bits/ 64 <3091200000>; + opp-peak-kBps = <8368000 51609600>; + }; }; firmware { @@ -4826,8 +4831,8 @@ mdss_dp_out: endpoint { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -6285,14 +6290,10 @@ sound: sound { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 5c8fe213f5e4..c830953156ec 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1866,6 +1866,8 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + sram = <&ipa_modem_tables>; + status = "disabled"; }; @@ -2925,8 +2927,8 @@ mdss_dp_out: endpoint { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -3440,6 +3442,20 @@ qup_i2c19_default: qup-i2c19-default-state { }; }; + sram@14680000 { + compatible = "qcom,sm8350-imem", "syscon", "simple-mfd"; + reg = <0 0x14680000 0 0x40000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0 0x14680000 0x40000>; + + ipa_modem_tables: modem-tables@3d000 { + reg = <0x3d000 0x2000>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; @@ -4523,9 +4539,9 @@ camera2_alert0: trip-point0 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 920a2d1c04d0..03bf30b53f28 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3508,8 +3508,8 @@ mdss_dp0_out: endpoint { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -5104,7 +5104,7 @@ intc: interrupt-controller@17100000 { gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; - reg = <0x0 0x17140000 0x0 0x20000>; + reg = <0x0 0x17140000 0x0 0x40000>; msi-controller; #msi-cells = <1>; }; @@ -5429,9 +5429,6 @@ sdhc_2: mmc@8804000 { bus-width = <4>; dma-coherent; - /* Forbid SDR104/SDR50 - broken hw! */ - sdhci-caps-mask = <0x3 0x0>; - status = "disabled"; sdhc2_opp_table: opp-table { @@ -6327,10 +6324,10 @@ reset-mon-cfg { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <19200000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk-display-card.dtso b/arch/arm64/boot/dts/qcom/sm8550-hdk-display-card.dtso new file mode 100644 index 000000000000..7b54b084b8bd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk-display-card.dtso @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2026, Linaro Limited + */ + +/* + * Display Card kit overlay + * This requires S5702 Switch 7 to be turned to OFF to route DSI0 to the display panel + */ + +#include +#include + +/dts-v1/; +/plugin/; + +/* Disable HDMI bridge related nodes (mutually exclusive with the display card) */ + +&i2c0 { + status = "disabled"; +}; + +<9611_1v2 { + status = "disabled"; +}; + +<9611_3v3 { + status = "disabled"; +}; + +&vreg_bob_3v3 { + status = "disabled"; +}; + +<9611_codec { + status = "disabled"; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; +}; + +&spi4 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l14b_3p2>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_irq>, <&ts_reset>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync: mdp-vsync-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_irq: ts-irq-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-disable; + }; + + ts_reset: ts-reset-state { + pins = "gpio24"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 94ed1c221856..5769be83cfbd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -707,8 +707,8 @@ panel@0 { reg = <0>; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + pinctrl-0 = <&sde_dsi_active>, <&sde_te>; + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te>; vddio-supply = <&vreg_l12b_1p8>; vci-supply = <&vreg_l13b_3p0>; @@ -915,14 +915,7 @@ sde_dsi_suspend: sde-dsi-suspend-state { bias-pull-down; }; - sde_te_active: sde-te-active-state { - pins = "gpio86"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - sde_te_suspend: sde-te-suspend-state { + sde_te: sde-te-state { pins = "gpio86"; function = "mdp_vsync"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index c35d4737a412..2fb2e0be5e4c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -870,8 +870,8 @@ panel@0 { compatible = "visionox,vtdr6130"; reg = <0>; - pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + pinctrl-0 = <&sde_dsi_active>, <&sde_te>; + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te>; pinctrl-names = "default", "sleep"; vci-supply = <&vreg_l13b_3p0>; @@ -1179,14 +1179,7 @@ sde_dsi_suspend: sde-dsi-suspend-state { bias-pull-down; }; - sde_te_active: sde-te-active-state { - pins = "gpio86"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - sde_te_suspend: sde-te-suspend-state { + sde_te: sde-te-state { pins = "gpio86"; function = "mdp_vsync"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index e3f93f4f412d..912525e9bca6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -76,8 +76,8 @@ cpu0: cpu@0 { power-domains = <&cpu_pd0>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <326>; + dynamic-power-coefficient = <251>; #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -102,8 +102,8 @@ cpu1: cpu@100 { power-domains = <&cpu_pd1>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <326>; + dynamic-power-coefficient = <251>; #cooling-cells = <2>; l2_100: l2-cache { compatible = "cache"; @@ -123,8 +123,8 @@ cpu2: cpu@200 { power-domains = <&cpu_pd2>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <326>; + dynamic-power-coefficient = <251>; #cooling-cells = <2>; l2_200: l2-cache { compatible = "cache"; @@ -144,8 +144,8 @@ cpu3: cpu@300 { power-domains = <&cpu_pd3>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; - capacity-dmips-mhz = <1792>; - dynamic-power-coefficient = <270>; + capacity-dmips-mhz = <693>; + dynamic-power-coefficient = <447>; #cooling-cells = <2>; l2_300: l2-cache { compatible = "cache"; @@ -165,8 +165,8 @@ cpu4: cpu@400 { power-domains = <&cpu_pd4>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; - capacity-dmips-mhz = <1792>; - dynamic-power-coefficient = <270>; + capacity-dmips-mhz = <693>; + dynamic-power-coefficient = <447>; #cooling-cells = <2>; l2_400: l2-cache { compatible = "cache"; @@ -186,8 +186,8 @@ cpu5: cpu@500 { power-domains = <&cpu_pd5>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; - capacity-dmips-mhz = <1792>; - dynamic-power-coefficient = <270>; + capacity-dmips-mhz = <693>; + dynamic-power-coefficient = <447>; #cooling-cells = <2>; l2_500: l2-cache { compatible = "cache"; @@ -207,8 +207,8 @@ cpu6: cpu@600 { power-domains = <&cpu_pd6>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; - capacity-dmips-mhz = <1792>; - dynamic-power-coefficient = <270>; + capacity-dmips-mhz = <693>; + dynamic-power-coefficient = <447>; #cooling-cells = <2>; l2_600: l2-cache { compatible = "cache"; @@ -228,8 +228,8 @@ cpu7: cpu@700 { power-domains = <&cpu_pd7>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; - capacity-dmips-mhz = <1894>; - dynamic-power-coefficient = <588>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <1057>; #cooling-cells = <2>; l2_700: l2-cache { compatible = "cache"; @@ -1251,6 +1251,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, #size-cells = <0>; status = "disabled"; }; + + uart15: serial@89c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart15_default>; + interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; }; i2c_master_hub_0: geniqup@9c0000 { @@ -2503,48 +2519,56 @@ opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0x882e5ffd>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0xa82f5ffd>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; opp-peak-kBps = <10687500>; + qcom,opp-acd-level = <0xe0285ffd>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xe0285ffd>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xc02a5ffd>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xe02b5ffd>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xe02d5ffd>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc02f5ffd>; }; }; }; @@ -2694,6 +2718,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + sram = <&ipa_modem_tables>; + status = "disabled"; }; @@ -3210,7 +3236,7 @@ sdhc_2: mmc@8804000 { clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; + <&bi_tcxo_div2>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x540 0>; qcom,dll-config = <0x0007642c>; @@ -3227,9 +3253,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, max-sd-hs-hz = <37500000>; dma-coherent; - /* Forbid SDR104/SDR50 - broken hw! */ - sdhci-caps-mask = <0x3 0>; - status = "disabled"; sdhc2_opp_table: opp-table { @@ -3320,19 +3343,19 @@ opp-338000000 { opp-366000000 { opp-hz = /bits/ 64 <366000000>; - required-opps = <&rpmhpd_opp_svs_l1>, + required-opps = <&rpmhpd_opp_svs>, <&rpmhpd_opp_svs_l1>; }; opp-444000000 { opp-hz = /bits/ 64 <444000000>; - required-opps = <&rpmhpd_opp_nom>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_nom>; }; opp-533333334 { opp-hz = /bits/ 64 <533333334>; - required-opps = <&rpmhpd_opp_turbo>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_turbo>; }; }; @@ -5095,6 +5118,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state { bias-pull-down; }; + qup_uart15_default: qup-uart15-default-state { + /* TX, RX */ + pins = "gpio74", "gpio75"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + }; + sdc2_sleep: sdc2-sleep-state { clk-pins { pins = "sdc2_clk"; @@ -5136,6 +5167,20 @@ data-pins { }; }; + sram@14680000 { + compatible = "qcom,sm8550-imem", "syscon", "simple-mfd"; + reg = <0 0x14680000 0 0x2c000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0 0x14680000 0x2c000>; + + ipa_modem_tables: modem-tables@8000 { + reg = <0x8000 0x2000>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; @@ -5274,7 +5319,7 @@ ppi_cluster3: interrupt-partition-3 { gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; - reg = <0 0x17140000 0 0x20000>; + reg = <0 0x17140000 0 0x40000>; msi-controller; #msi-cells = <1>; }; @@ -6758,9 +6803,9 @@ trip-point2 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts new file mode 100644 index 000000000000..0dc994f4e48d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -0,0 +1,1551 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + * Copyright (c) 2025, Kancy Joe + */ + +/dts-v1/; + +#include +#include +#include +#include "sm8650.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/delete-node/ &rmtfs_mem; +/delete-node/ &hwfence_shbuf; + +/ { + model = "AYANEO Pocket S2 (Pro)"; + compatible = "ayaneo,pocket-s2", "qcom,sm8650"; + chassis-type = "handset"; + + aliases { + serial0 = &uart15; + serial1 = &uart14; + }; + + wcd939x: audio-codec { + compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + fan: fan { + compatible = "pwm-fan"; + + interrupts-extended = <&tlmm 14 IRQ_TYPE_EDGE_FALLING>; + + pwms = <&pm8550_pwm 3 50000>; + + fan-supply = <&fan_pwr>; + + #cooling-cells = <2>; + cooling-levels = <0 16 32 45 60 80 105 130 155 180 205 230 255>; + + pinctrl-0 = <&fan_int>, <&pwm_fan_ctrl_active>; + pinctrl-1 = <&pwm_fan_ctrl_sleep>; + pinctrl-names = "default", "sleep"; + }; + + fan_pwr: fan-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "fan_pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpios = <&tlmm 125 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&fan_vdd>; + + pinctrl-0 = <&fan_pwr_pins>; + pinctrl-names = "default"; + }; + + fan_vdd: fan-vdd-regulator { + compatible = "regulator-fixed"; + + regulator-name = "fan_vdd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&fan_vdd_pins>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8650-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&wcd_usbss_sbu_mux>; + }; + }; + }; + }; + }; + + upd720201_avdd33_reg: upd720201-avdd33-regulator { + compatible = "regulator-fixed"; + + regulator-name = "upd720201_avdd33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&tlmm 123 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&upd720201_avdd33>; + pinctrl-names = "default"; + }; + + upd720201_vdd10_reg: upd720201-vdd10-regulator { + compatible = "regulator-fixed"; + + regulator-name = "upd720201_vdd10"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&upd720201_vdd10>; + pinctrl-names = "default"; + }; + + upd720201_vdd33_reg: upd720201-vdd33-regulator { + compatible = "regulator-fixed"; + + regulator-name = "upd720201_vdd33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&upd720201_vdd33>; + pinctrl-names = "default"; + }; + + sound { + compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model = "SM8650-APS2"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT7", "DMIC1_OUTPUT", + "TX SWR_INPUT8", "DMIC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd939x 0>, + <&swr1 0>, + <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + codec { + sound-dai = <&wcd939x 1>, + <&swr2 0>, + <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&right_spkr>, + <&left_spkr>, + <&swr3 0>, + <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + dp-dai-link { + link-name = "DisplayPort Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>, <&bt_default>; + + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_s4i_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddio1p2-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_s2c_0p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p8-supply = <&vreg_s6c_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s1c_1p2>; + vdd-l12-supply = <&vreg_s6c_1p8>; + vdd-l15-supply = <&vreg_s6c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1c_1p2>; + vdd-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "c"; + + vreg_s1c_1p2: smps1 { + regulator-name = "vreg_s1c_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1348000>; + regulator-initial-mode = ; + }; + + vreg_s2c_0p8: smps2 { + regulator-name = "vreg_s2c_0p8"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = ; + }; + + vreg_s3c_0p9: smps3 { + regulator-name = "vreg_s3c_0p9"; + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = ; + }; + + vreg_s4c_1p2: smps4 { + regulator-name = "vreg_s4c_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1280000>; + regulator-initial-mode = ; + }; + + vreg_s5c_0p7: smps5 { + regulator-name = "vreg_s5c_0p7"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = ; + }; + + vreg_s6c_1p8: smps6 { + regulator-name = "vreg_s6c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name = "vreg_l3c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + regulator-always-on; + regulator-boot-on; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name = "vreg_l3e_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "g"; + + vreg_l1g_0p91: ldo1 { + regulator-name = "vreg_l1g_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name = "vreg_l3g_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l2-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s4-supply = <&vph_pwr>; + + qcom,pmic-id = "i"; + + vreg_s4i_0p85: smps4 { + regulator-name = "vreg_s4i_0p85"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name = "vreg_l1i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name = "vreg_l2i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name = "vreg_l3i_0p91"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&cpu2_top_thermal { + trips { + cpu2_active: cpu2-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu2_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu3_top_thermal { + trips { + cpu3_active: cpu3-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu3_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu4_top_thermal { + trips { + cpu4_active: cpu4-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu4_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu5_top_thermal { + trips { + cpu5_active: cpu5-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu5_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu6_top_thermal { + trips { + cpu6_active: cpu6-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu6_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&cpu7_top_thermal { + trips { + cpu7_active: cpu7-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu7_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&gpu0_cooling_maps { + map1 { + trip = <&gpu0_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu1_cooling_maps { + map1 { + trip = <&gpu1_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu2_cooling_maps { + map1 { + trip = <&gpu2_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu3_cooling_maps { + map1 { + trip = <&gpu3_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu4_cooling_maps { + map1 { + trip = <&gpu4_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu5_cooling_maps { + map1 { + trip = <&gpu5_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu6_cooling_maps { + map1 { + trip = <&gpu6_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu7_cooling_maps { + map1 { + trip = <&gpu7_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&gpu0_trips { + gpu0_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu1_trips { + gpu1_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu2_trips { + gpu2_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu3_trips { + gpu3_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu4_trips { + gpu4_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu5_trips { + gpu5_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&gpu6_trips { + gpu6_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; + +}; + +&gpu7_trips { + gpu7_active: trip-active { + temperature = <38000>; + hysteresis = <2000>; + type = "active"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + + status = "okay"; + + wcd_usbss: typec-mux@e { + compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg = <0xe>; + + vdd-supply = <&vreg_l15b_1p8>; + reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + +&i2c6 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; +}; + +&iris { + status = "okay"; +}; + +&lpass_wsa2macro { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + status = "okay"; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1i_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_port0 { + /* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */ + usb-controller@0 { + compatible = "pci1912,0014"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + avdd33-supply = <&upd720201_avdd33_reg>; + vdd10-supply = <&upd720201_vdd10_reg>; + vdd33-supply = <&upd720201_vdd33_reg>; + + pinctrl-0 = <&gamepad_pwr_en>; + pinctrl-names = "default"; + }; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3e_0p9>; + vdda-pll-supply = <&vreg_l3i_1p2>; + vdda-qref-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + power-source = <1>; + }; + + pwm_fan_ctrl_active: pwm-fan-ctrl-active-state { + pins = "gpio9"; + function = "func1"; + bias-disable; + power-source = <0>; + qcom,drive-strength = ; + }; + + pwm_fan_ctrl_sleep: pwm-fan-ctrl-sleep-state { + pins = "gpio9"; + function = "normal"; + output-high; + bias-disable; + power-source = <0>; + qcom,drive-strength = ; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + bias-pull-up; + input-enable; + output-disable; + power-source = <1>; /* 1.8 V */ + }; +}; + +&pm8550_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + label = "Power Status"; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up = <2200>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8650/ayaneo/ps2/adsp.mbn", + "qcom/sm8650/ayaneo/ps2/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8650/ayaneo/ps2/cdsp.mbn", + "qcom/sm8650/ayaneo/ps2/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&reserved_memory { + lost_reg_mem: lost-reg-mem { + reg = <0 0x9b09c000 0 0x4000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf@d4e23000 { + reg = <0 0xd4e23000 0 0x2dd000>; + no-map; + }; + + splash_region: splash-region { + label = "cont_splash_region"; + reg = <0 0xd5100000 0 0x2b00000>; + no-map; + }; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&swr1 { + status = "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Speaker Left */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + #sound-dai-cells = <0>; + reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR3 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR3 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR3 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR3 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR3 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR3 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker Right */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + #sound-dai-cells = <0>; + reset-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR3 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR3 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR3 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR3 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR3 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR3 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges = <32 4>, <36 1>, <38 6>, <74 1>; + + bt_default: bt-default-state { + bt-en-pins { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + }; + + fan_pwr_pins: fan-pwr-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fan_vdd_pins: fan-vdd-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fan_int: fan-int-state { + pins = "gpio14"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + upd720201_avdd33: upd720201-avdd33-state { + pins = "gpio123"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + upd720201_vdd10: pd720201-vdd10-state { + pins = "gpio122"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + upd720201_vdd33: upd720201-vdd33-state { + pins = "gpio121"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gamepad_pwr_en: gamepad-pwr-en-active-state { + pins = "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + + max-speed = <3200000>; + }; +}; + +&uart15 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1c_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +/* + * DPAUX -> WCD9395 -> USB_SBU -> USB-C + * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C + * USB SS -> NB7VPQ904MMUTWG -> USB-C + */ + +&usb_1 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1i_0p88>; + vdda12-supply = <&vreg_l3i_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3i_1p2>; + vdda-pll-supply = <&vreg_l3g_0p91>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index bb688a5d21c2..dd6e33d2dc5d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -618,8 +618,8 @@ panel@0 { vci-supply = <&vreg_l13b_3p0>; vdd-supply = <&vreg_l11b_1p2>; - pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync_active>; - pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync_suspend>; + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; pinctrl-names = "default", "sleep"; port { @@ -821,14 +821,7 @@ disp0_reset_n_suspend: disp0-reset-n-suspend-state { bias-pull-down; }; - mdp_vsync_active: mdp-vsync-active-state { - pins = "gpio86"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - mdp_vsync_suspend: mdp-vsync-suspend-state { + mdp_vsync: mdp-vsync-state { pins = "gpio86"; function = "mdp_vsync"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 087828c60692..a3982ae22929 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -908,8 +908,8 @@ panel@0 { vci-supply = <&vreg_l13b_3p0>; vdd-supply = <&vreg_l11b_1p2>; - pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync_active>; - pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync_suspend>; + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; pinctrl-names = "default", "sleep"; port { @@ -1244,14 +1244,7 @@ disp0_reset_n_suspend: disp0-reset-n-suspend-state { bias-pull-down; }; - mdp_vsync_active: mdp-vsync-active-state { - pins = "gpio86"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-pull-down; - }; - - mdp_vsync_suspend: mdp-vsync-suspend-state { + mdp_vsync: mdp-vsync-state { pins = "gpio86"; function = "mdp_vsync"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 357e43b90740..1604bc8cff37 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3917,7 +3917,7 @@ opp-32000000-4 { }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -4393,6 +4393,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + sram = <&ipa_modem_tables>; + status = "disabled"; }; @@ -4957,7 +4959,7 @@ sdhc_2: mmc@8804000 { clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; + <&bi_tcxo_div2>; clock-names = "iface", "core", "xo"; @@ -4976,9 +4978,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, bus-width = <4>; - /* Forbid SDR104/SDR50 - broken hw! */ - sdhci-caps-mask = <0x3 0>; - qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; @@ -5236,13 +5235,13 @@ opp-196000000 { opp-300000000 { opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_low_svs>, + required-opps = <&rpmhpd_opp_svs>, <&rpmhpd_opp_low_svs>; }; opp-380000000 { opp-hz = /bits/ 64 <380000000>; - required-opps = <&rpmhpd_opp_svs>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_svs>; }; @@ -5254,13 +5253,13 @@ opp-435000000 { opp-480000000 { opp-hz = /bits/ 64 <480000000>; - required-opps = <&rpmhpd_opp_nom>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_nom>; }; opp-533333334 { opp-hz = /bits/ 64 <533333334>; - required-opps = <&rpmhpd_opp_turbo>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_turbo>; }; }; @@ -5905,6 +5904,7 @@ mdss_dp0: displayport-controller@af54000 { phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort0"; status = "disabled"; @@ -7078,6 +7078,20 @@ funnel_apss_out_funnel_in1: endpoint { }; }; + sram@14680000 { + compatible = "qcom,sm8650-imem", "syscon", "simple-mfd"; + reg = <0 0x14680000 0 0x2c000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0 0x14680000 0x2c000>; + + ipa_modem_tables: modem-tables@8000 { + reg = <0x8000 0x2000>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; @@ -7219,7 +7233,7 @@ ppi_cluster2: interrupt-partition-2 { gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; - reg = <0 0x17140000 0 0x20000>; + reg = <0 0x17140000 0 0x40000>; msi-controller; #msi-cells = <1>; @@ -7846,7 +7860,7 @@ cpuss3-critical { }; }; - cpu2-top-thermal { + cpu2_top_thermal: cpu2-top-thermal { thermal-sensors = <&tsens0 5>; trips { @@ -7870,7 +7884,7 @@ cpu2-critical { }; }; - cpu3-top-thermal { + cpu3_top_thermal: cpu3-top-thermal { thermal-sensors = <&tsens0 7>; trips { @@ -7894,7 +7908,7 @@ cpu3-critical { }; }; - cpu4-top-thermal { + cpu4_top_thermal: cpu4-top-thermal { thermal-sensors = <&tsens0 9>; trips { @@ -7918,7 +7932,7 @@ cpu4-critical { }; }; - cpu5-top-thermal { + cpu5_top_thermal: cpu5-top-thermal { thermal-sensors = <&tsens0 11>; trips { @@ -7942,7 +7956,7 @@ cpu5-critical { }; }; - cpu6-top-thermal { + cpu6_top_thermal: cpu6-top-thermal { thermal-sensors = <&tsens0 13>; trips { @@ -7984,7 +7998,7 @@ aoss1-critical { }; }; - cpu7-top-thermal { + cpu7_top_thermal: cpu7-top-thermal { thermal-sensors = <&tsens1 1>; trips { @@ -8247,14 +8261,14 @@ gpuss0-thermal { thermal-sensors = <&tsens2 1>; - cooling-maps { + gpu0_cooling_maps: cooling-maps { map0 { trip = <&gpu0_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu0_trips: trips { gpu0_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8280,14 +8294,14 @@ gpuss1-thermal { thermal-sensors = <&tsens2 2>; - cooling-maps { + gpu1_cooling_maps: cooling-maps { map0 { trip = <&gpu1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu1_trips: trips { gpu1_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8313,14 +8327,14 @@ gpuss2-thermal { thermal-sensors = <&tsens2 3>; - cooling-maps { + gpu2_cooling_maps: cooling-maps { map0 { trip = <&gpu2_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu2_trips: trips { gpu2_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8346,14 +8360,14 @@ gpuss3-thermal { thermal-sensors = <&tsens2 4>; - cooling-maps { + gpu3_cooling_maps: cooling-maps { map0 { trip = <&gpu3_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu3_trips: trips { gpu3_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8379,14 +8393,14 @@ gpuss4-thermal { thermal-sensors = <&tsens2 5>; - cooling-maps { + gpu4_cooling_maps: cooling-maps { map0 { trip = <&gpu4_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu4_trips: trips { gpu4_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8412,14 +8426,14 @@ gpuss5-thermal { thermal-sensors = <&tsens2 6>; - cooling-maps { + gpu5_cooling_maps: cooling-maps { map0 { trip = <&gpu5_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu5_trips: trips { gpu5_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8445,14 +8459,14 @@ gpuss6-thermal { thermal-sensors = <&tsens2 7>; - cooling-maps { + gpu6_cooling_maps: cooling-maps { map0 { trip = <&gpu6_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu6_trips: trips { gpu6_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; @@ -8478,14 +8492,14 @@ gpuss7-thermal { thermal-sensors = <&tsens2 8>; - cooling-maps { + gpu7_cooling_maps: cooling-maps { map0 { trip = <&gpu7_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; - trips { + gpu7_trips: trips { gpu7_alert0: trip-point0 { temperature = <95000>; hysteresis = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index cb718331496e..3837f6785320 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -54,6 +54,15 @@ wcd939x: audio-codec { vdd-px-supply = <&vreg_l2i_1p2>; #sound-dai-cells = <1>; + + mode-switch; + orientation-switch; + + port { + wcd_codec_headset_in: endpoint { + remote-endpoint = <&wcd_usbss_headset_out>; + }; + }; }; chosen { @@ -230,6 +239,7 @@ port@2 { reg = <2>; pmic_glink_sbu: endpoint { + remote-endpoint = <&wcd_usbss_sbu_mux>; }; }; }; @@ -925,6 +935,42 @@ vreg_l7n_3p3: ldo7 { }; }; +&i2c3 { + status = "okay"; + + wcd_usbss: typec-mux@e { + compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg = <0xe>; + + vdd-supply = <&vreg_l15b_1p8>; + reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + + port@1 { + reg = <1>; + + wcd_usbss_headset_out: endpoint { + remote-endpoint = <&wcd_codec_headset_in>; + }; + }; + }; + }; +}; + &iris { status = "okay"; }; @@ -937,6 +983,56 @@ &lpass_vamacro { qcom,dmic-sample-rate = <4800000>; }; +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3g_1p2>; + + status = "okay"; + + panel@0 { + compatible = "novatek,nt37801"; + reg = <0>; + + reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p0>; + + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l3i_0p88>; + + status = "okay"; +}; + &pm8550_flash { status = "okay"; @@ -1053,6 +1149,11 @@ &pmih0108_eusb2_repeater { status = "okay"; }; +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up = <2200>; +}; + &qupv3_1 { status = "okay"; }; @@ -1225,6 +1326,27 @@ sdc2_card_det_n: sd-card-det-n-state { bias-pull-up; }; + mdp_vsync: mdp-vsync-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio101"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index f56b1f889b85..18fb52c14acd 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3,7 +3,9 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include +#include #include #include #include @@ -20,6 +22,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -2787,6 +2790,7 @@ port@2 { reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -2945,19 +2949,19 @@ iris_opp_table: opp-table { opp-240000000 { opp-hz = /bits/ 64 <240000000>; - required-opps = <&rpmhpd_opp_low_svs_d1>, + required-opps = <&rpmhpd_opp_svs>, <&rpmhpd_opp_low_svs_d1>; }; opp-338000000 { opp-hz = /bits/ 64 <338000000>; - required-opps = <&rpmhpd_opp_low_svs>, + required-opps = <&rpmhpd_opp_svs>, <&rpmhpd_opp_low_svs>; }; opp-420000000 { opp-hz = /bits/ 64 <420000000>; - required-opps = <&rpmhpd_opp_svs>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_svs>; }; @@ -2969,19 +2973,19 @@ opp-444000000 { opp-533333334 { opp-hz = /bits/ 64 <533333334>; - required-opps = <&rpmhpd_opp_nom>, + required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_nom>; }; opp-570000000 { opp-hz = /bits/ 64 <570000000>; - required-opps = <&rpmhpd_opp_nom_l1>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_nom_l1>; }; opp-630000000 { opp-hz = /bits/ 64 <630000000>; - required-opps = <&rpmhpd_opp_turbo>, + required-opps = <&rpmhpd_opp_nom>, <&rpmhpd_opp_turbo>; }; }; @@ -3001,6 +3005,437 @@ videocc: clock-controller@aaf0000 { #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8750-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8750-dpu"; + reg = <0x0 0x0ae01000 0x0 0x93000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz = /bits/ 64 <207000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-140630000 { + opp-hz = /bits/ 64 <140630000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,sm8750-dsi-phy-3nm"; + reg = <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x280>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&bi_tcxo_div2>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae96000 0x0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,sm8750-dsi-phy-3nm"; + reg = <0x0 0x0ae97000 0x0 0x200>, + <0x0 0x0ae97200 0x0 0x280>, + <0x0 0x0ae97500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,sm8750-dp", "qcom,sm8650-dp"; + reg = <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0xc0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x9c>, + <0x0 0xaf57000 0x0 0x9c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 = <&dp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + status = "disabled"; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; + }; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8750-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; @@ -3013,6 +3448,54 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + tsens0: thermal-sensor@c228000 { + compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c228000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <15>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <7>; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22a000 { + compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22a000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c22b000 { + compatible = "qcom,sm8750-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c22b000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <9>; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; @@ -4658,7 +5141,7 @@ intc: interrupt-controller@16000000 { gic_its: msi-controller@16040000 { compatible = "arm,gic-v3-its"; - reg = <0x0 0x16040000 0x0 0x20000>; + reg = <0x0 0x16040000 0x0 0x40000>; msi-controller; #msi-cells = <1>; @@ -5459,6 +5942,854 @@ compute-cb@14 { }; }; + thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-2-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-2-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-3-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-3-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-4-0-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-4-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-4-1-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-4-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-5-0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-5-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-5-1-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-0-5-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss-0-0-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss-0-1-thermal { + thermal-sensors = <&tsens0 14>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-0-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-0-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu-1-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss-1-0-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss-1-0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss-1-1-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss-1-1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss2-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss3-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss4-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss4-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss5-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss5-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss6-thermal { + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss6-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss7-thermal { + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss7-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem0-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + modem0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem1-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + modem1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem2-thermal { + thermal-sensors = <&tsens2 11>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + modem2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem3-thermal { + thermal-sensors = <&tsens2 12>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + modem3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors = <&tsens2 13>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera1-thermal { + thermal-sensors = <&tsens2 14>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens2 15>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + video-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx0-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx2-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphvx2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx0-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx1-thermal { + thermal-sensors = <&tsens3 5>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx2-thermal { + thermal-sensors = <&tsens3 6>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx3-thermal { + thermal-sensors = <&tsens3 7>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsphmx3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + thermal-sensors = <&tsens3 8>; + + trips { + trip-point0 { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + ddr-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qcom/smb2370.dtsi new file mode 100644 index 000000000000..80f3fdae5705 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +&spmi_bus2 { + smb2370_j_e2: pmic@9 { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_j_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2370_k_e2: pmic@a { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_k_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2370_l_e2: pmic@b { + compatible = "qcom,smb2370", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2370_l_e2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2370-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-el2.dtso b/arch/arm64/boot/dts/qcom/talos-el2.dtso new file mode 100644 index 000000000000..f6818c058d72 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-el2.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + + * Talos specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +&gpu_zap_shader { + status = "disabled"; +}; + +&remoteproc_adsp { + iommus = <&apps_smmu 0x1720 0x0>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x1080 0x0>; +}; + +&venus { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-camera-imx577.dtso b/arch/arm64/boot/dts/qcom/talos-evk-camera-imx577.dtso new file mode 100644 index 000000000000..e0c385ec53b1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-camera-imx577.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&camss { + vdd-csiphy-1p2-supply = <&vreg_l11a>; + vdd-csiphy-1p8-supply = <&vreg_l12a>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam_mclk2_default &cam1_reset_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK2_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK2_CLK>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vreg_s4a>; + + port { + imx577_ep: endpoint { + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso b/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso new file mode 100644 index 000000000000..8d16ce4a61d2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-lvds-auo,g133han01.dtso @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +#include + +&{/} { + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&tlmm 115 GPIO_ACTIVE_HIGH>; + default-on; + }; + + panel-lvds { + compatible = "auo,g133han01"; + power-supply = <&vreg_v3p3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* LVDS A (Odd pixels) */ + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + lvds_panel_out_a: endpoint { + remote-endpoint = <&sn65dsi84_out_a>; + }; + }; + + /* LVDS B (Even pixels) */ + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + lvds_panel_out_b: endpoint { + remote-endpoint = <&sn65dsi84_out_b>; + }; + }; + }; + }; + + vreg_v3p3: regulator-v3p3 { + compatible = "regulator-fixed"; + regulator-name = "vdd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&hdmi_connector { + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + hdmi_bridge: bridge@3d { + reg = <0x3d>; + status = "disabled"; + }; + + lvds_bridge: bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + enable-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi84_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + sn65dsi84_out_a: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&lvds_panel_out_a>; + }; + }; + + port@3 { + reg = <3>; + + sn65dsi84_out_b: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&lvds_panel_out_b>; + }; + }; + }; + }; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l11a>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi84_in>; + data-lanes = <0 1 2 3>; +}; + +&tlmm { + lcd_bklt_en: lcd-bklt-en-state { + pins = "gpio115"; + function = "gpio"; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi new file mode 100644 index 000000000000..294354c034c3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -0,0 +1,617 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include +#include +#include "talos.dtsi" +#include "pm8150.dtsi" +/ { + aliases { + i2c1 = &i2c1; + i2c5 = &i2c5; + mmc0 = &sdhc_1; + serial0 = &uart0; + serial1 = &uart7; + spi6 = &spi6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + can_osc: can-oscillator { + compatible = "fixed-clock"; + clock-frequency = <20000000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + }; + + vreg_conn_1p8: regulator-conn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + }; + + vreg_conn_pa: regulator-conn-pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8150_gpios 6 GPIO_ACTIVE_HIGH>; + }; + + regulator-usb2-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB2_VBUS"; + gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb2_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + + vreg_v3p3_can: regulator-v3p3-can { + compatible = "regulator-fixed"; + regulator-name = "vreg-v3p3-can"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v5p0_can: regulator-v5p0-can { + compatible = "regulator-fixed"; + regulator-name = "vreg-v5p0-can"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + pinctrl-0 = <&bt_en_state>, <&wlan_en_state>; + pinctrl-names = "default"; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_conn_pa>; + vddaon-supply = <&vreg_s5a>; + vddpmu-supply = <&vreg_conn_1p8>; + vddpmumx-supply = <&vreg_conn_1p8>; + vddpmucx-supply = <&vreg_conn_pa>; + vddrfa0p95-supply = <&vreg_s5a>; + vddrfa1p3-supply = <&vreg_s6a>; + vddrfa1p9-supply = <&vreg_l15a>; + vddpcie1p3-supply = <&vreg_s6a>; + vddpcie1p9-supply = <&vreg_l15a>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s3a: smps3 { + regulator-name = "vreg_s3a"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + regulator-initial-mode = ; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s6a: smps6 { + regulator-name = "vreg_s6a"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1404000>; + regulator-initial-mode = ; + }; + + vreg_l1a: ldo1 { + regulator-name = "vreg_l1a"; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <852000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2a: ldo2 { + regulator-name = "vreg_l2a"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10a: ldo10 { + regulator-name = "vreg_l10a"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11a: ldo11 { + regulator-name = "vreg_l11a"; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12a: ldo12 { + regulator-name = "vreg_l12a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = ; + }; + + vreg_l13a: ldo13 { + regulator-name = "vreg_l13a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15a: ldo15 { + regulator-name = "vreg_l15a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l16a: ldo16 { + regulator-name = "vreg_l16a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17a: ldo17 { + regulator-name = "vreg_l17a"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; + + eeprom@5f { + compatible = "atmel,24mac602"; + reg = <0x5f>; + pagesize = <16>; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint = <&dp0_connector_in>; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l11a>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vcca-supply = <&vreg_l5a>; + status = "okay"; +}; + +&pcie { + perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&pcie_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + qcom,calibration-variant = "QC_QCS615_Ride"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pm8150_gpios { + usb2_en: usb2-en-state { + pins = "gpio10"; + function = "normal"; + output-enable; + power-source = <0>; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs615/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs615/cdsp.mbn"; + + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + vmmc-supply = <&vreg_l17a>; + vqmmc-supply = <&vreg_s4a>; + + non-removable; + no-sd; + no-sdio; + + status = "okay"; +}; + +&spi6 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&can_osc>; + interrupts-extended = <&tlmm 87 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + vdd-supply = <&vreg_v3p3_can>; + xceiver-supply = <&vreg_v5p0_can>; + }; +}; + +&tlmm { + bt_en_state: bt-en-state { + pins = "gpio85"; + function = "gpio"; + bias-pull-down; + }; + + cam1_reset_default: cam1-reset-default-state { + pins = "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie_default_state: pcie-default-state { + clkreq-pins { + pins = "gpio90"; + function = "pcie_clk_req"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wifi_reg_en_pins_state: wifi-reg-en-pins-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <8>; + output-high; + bias-pull-up; + }; + + wlan_en_state: wlan-en-state { + pins = "gpio84"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + +/* + * USB0 routing and EDL mode: + * + * The USB0 controller’s HS differential pair is switched (manually) + * between the Micro-USB port for EDL/ADB and the on-board USB 3.0 hub. + * + * During EDL (Emergency Download) mode, the HS lines are explicitly + * routed to the Micro-USB port to allow the SoC to enter device mode + * for flashing. + * + * After EDL the switch is normally toggled so the HS lines stay + * connected to the hub’s Type-A downstream ports, leaving no electrical + * path to the Micro-USB connector — therefore USB0 runs host-only in + * normal runtime and device mode must not be advertised. + * + * USB0 is configured host-only in the base device tree; a separate + * device-tree overlay enables the Micro-USB peripheral configuration for + * ADB. For ADB to work during normal runtime the DIP switch SW1 must be + * manually toggled to the off position (reconnecting the HS pair to the + * Micro-USB port). + */ + +&usb_1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&usb_qmpphy_2 { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_s4a>; + vccq2-max-microamp = <600000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso b/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso new file mode 100644 index 000000000000..7552ecf9d7ee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk-usb1-peripheral.dtso @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; +/plugin/; + +/* + * USB0 Peripheral Mode Overlay + * + * This overlay switches USB0 from host mode to peripheral mode + * by configuring the USB controller node. + * + * Hardware requirement: + * The DIP switch SW1 must be toggled to reconnect the USB0 HS + * differential pair to the Micro-USB connector instead of the + * on-board USB 3.0 hub. + * + * Without toggling SW1, there is no electrical path to the + * Micro-USB connector and device mode will not function. + */ + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos-evk.dts b/arch/arm64/boot/dts/qcom/talos-evk.dts new file mode 100644 index 000000000000..af100e22beee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-evk.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "talos-evk-som.dtsi" + +/ { + model = "Qualcomm QCS615 IQ 615 EVK"; + compatible = "qcom,talos-evk", "qcom,qcs615", "qcom,sm6150"; + chassis-type = "embedded"; + + aliases { + mmc1 = &sdhc_2; + }; + + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + + hpd-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + + hdmi_connector: hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + vreg_v1p8_out: regulator-v1p8-out { + compatible = "regulator-fixed"; + regulator-name = "vreg-v1p8-out"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vreg_v5p0_out>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v3p3_out: regulator-v3p3-out { + compatible = "regulator-fixed"; + regulator-name = "vreg-v3p3-out"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vreg_v5p0_out>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_v5p0_out: regulator-v5p0-out { + compatible = "regulator-fixed"; + regulator-name = "vreg-v5p0-out"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + /* Powered by system 20V rail (USBC_VBUS_IN) */ + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + hdmi_bridge: bridge@3d { + compatible = "adi,adv7535"; + reg = <0x3d>; + avdd-supply = <&vreg_v1p8_out>; + dvdd-supply = <&vreg_v1p8_out>; + pvdd-supply = <&vreg_v1p8_out>; + a2vdd-supply = <&vreg_v1p8_out>; + v3p3-supply = <&vreg_v3p3_out>; + interrupts-extended = <&tlmm 26 IRQ_TYPE_LEVEL_LOW>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&adv7535_in>; + data-lanes = <0 1 2 3>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <4>; + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l10a>; + vqmmc-supply = <&vreg_s4a>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 75716b4a58d6..ff5afbfce2a4 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -651,6 +652,11 @@ rproc_adsp_mem: rproc-adsp@95900000 { reg = <0x0 0x95900000 0x0 0x1e00000>; no-map; }; + + pil_gpu_mem: pil-gpu@97715000 { + reg = <0x0 0x97715000 0x0 0x2000>; + no-map; + }; }; soc: soc@0 { @@ -666,6 +672,9 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; @@ -1234,6 +1243,10 @@ aggre1_noc: interconnect@1700000 { compatible = "qcom,qcs615-aggre1-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 { @@ -1553,6 +1566,50 @@ tlmm: pinctrl@3100000 { #interrupt-cells = <2>; wakeup-parent = <&pdc>; + cam_mclk0_default: cam-mclk0-default-state { + pins = "gpio28"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk1_default: cam-mclk1-default-state { + pins = "gpio29"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk2_default: cam-mclk2-default-state { + pins = "gpio30"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam_mclk3_default: cam-mclk3-default-state { + pins = "gpio31"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cci_i2c0_default: cci-i2c0-default-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci_i2c1_default: cci-i2c1-default-state { + /* SDA, SCL */ + pins = "gpio34", "gpio35"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { pins = "gpio4", "gpio5"; function = "qup0"; @@ -1830,6 +1887,111 @@ data-pins { }; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-612.0", "qcom,adreno"; + reg = <0x0 0x05000000 0x0 0x40000>, + <0x0 0x0509e000 0x0 0x1000>, + <0x0 0x05061000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>; + clock-names = "core"; + + interrupts = ; + + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0x0 0x401>; + + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + qcom,gmu = <&gmu>; + + #cooling-cells = <2>; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + required-opps = <&rpmhpd_opp_turbo>; + opp-peak-kBps = <7050000>; + }; + + opp-745000000 { + opp-hz = /bits/ 64 <745000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + opp-peak-kBps = <6075000>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5287500>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <3975000>; + }; + + opp-435000000 { + opp-hz = /bits/ 64 <435000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3000000>; + }; + }; + }; + + gmu: gmu@506a000 { + compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; + reg = <0x0 0x0506d000 0x0 0x2c000>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "smmu_vote"; + + power-domains = <&gpucc CX_GDSC>, + <&gpucc GX_GDSC>; + power-domain-names = "cx", + "gx"; + + interrupts = , + ; + interrupt-names = "oob", + "gmu"; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,qcs615-gpucc"; reg = <0 0x05090000 0 0x9000>; @@ -1843,6 +2005,31 @@ gpucc: clock-controller@5090000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@50a0000 { + compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x050a0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + power-domains = <&gpucc CX_GDSC>; + dma-coherent; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>, @@ -2253,6 +2440,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + replicator0_out0: endpoint { + remote-endpoint = <&tmc_etr_in>; + }; + }; + port@1 { reg = <1>; @@ -2287,6 +2482,25 @@ tmc_etf_out: endpoint { }; }; + tmc@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x06048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x01e0 0x0>; + arm,scatter-gather; + + in-ports { + port { + tmc_etr_in: endpoint { + remote-endpoint = <&replicator0_out0>; + }; + }; + }; + }; + replicator@604a000 { compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0x0 0x0604a000 0x0 0x1000>; @@ -3789,6 +4003,241 @@ videocc: clock-controller@ab00000 { #power-domain-cells = <1>; }; + cci: cci@ac4a000 { + compatible = "qcom,sm6150-cci", "qcom,msm8996-cci"; + + reg = <0x0 0x0ac4a000 0x0 0x4000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + clocks = <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + camss: isp@acb3000 { + compatible = "qcom,sm6150-camss"; + + reg = <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0ac65000 0x0 0x1000>, + <0x0 0x0ac66000 0x0 0x1000>, + <0x0 0x0ac67000 0x0 0x1000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0ac6f000 0x0 0x3000>, + <0x0 0x0ac42000 0x0 0x5000>, + <0x0 0x0ac48000 0x0 0x1000>, + <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac18000 0x0 0x3000>, + <0x0 0x0ac00000 0x0 0x6000>, + <0x0 0x0ac10000 0x0 0x8000>, + <0x0 0x0ac87000 0x0 0x3000>, + <0x0 0x0ac52000 0x0 0x4000>, + <0x0 0x0ac4e000 0x0 0x4000>, + <0x0 0x0ac6b000 0x0 0x0a00>; + reg-names = "csid0", + "csid1", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite", + "bps", + "camnoc", + "cpas_cdm", + "cpas_top", + "icp_csr", + "icp_qgic", + "icp_sierra", + "ipe0", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_IPE_0_CLK>, + <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_JPEG_CLK>, + <&camcc CAM_CC_LRME_CLK>; + clock-names = "gcc_ahb", + "gcc_axi_hf", + "camnoc_axi", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "soc_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "bps", + "bps_ahb", + "bps_axi", + "bps_areg", + "icp", + "ipe0", + "ipe0_ahb", + "ipe0_areg", + "ipe0_axi", + "jpeg", + "lrme"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_HF1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0", + "hf_1", + "sf_mnoc"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite", + "camnoc", + "cdm", + "icp", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + iommus = <&apps_smmu 0x0820 0x40>, + <&apps_smmu 0x0840 0x00>, + <&apps_smmu 0x0860 0x40>, + <&apps_smmu 0x0c00 0x00>, + <&apps_smmu 0x0cc0 0x00>, + <&apps_smmu 0x0c80 0x00>, + <&apps_smmu 0x0ca0 0x00>, + <&apps_smmu 0x0d00 0x00>, + <&apps_smmu 0x0d20 0x00>, + <&apps_smmu 0x0d40 0x00>, + <&apps_smmu 0x0d80 0x20>, + <&apps_smmu 0x0da0 0x20>, + <&apps_smmu 0x0de2 0x00>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>, + <&camcc BPS_GDSC>, + <&camcc IPE_0_GDSC>; + power-domain-names = "ife0", + "ife1", + "top", + "bps", + "ipe"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,qcs615-camcc"; reg = <0 0x0ad00000 0 0x10000>; @@ -3958,8 +4407,8 @@ mdss_dp0_out: endpoint { dp_opp_table: opp-table { compatible = "operating-points-v2"; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; required-opps = <&rpmhpd_opp_low_svs>; }; @@ -4417,7 +4866,7 @@ usb_1_hsphy: phy@88e2000 { status = "disabled"; }; - usb_hsphy_2: phy@88e3000 { + usb_2_hsphy: phy@88e3000 { compatible = "qcom,qcs615-qusb2-phy"; reg = <0x0 0x088e3000 0x0 0x180>; @@ -4486,9 +4935,9 @@ usb_qmpphy_2: phy@88e8000 { status = "disabled"; }; - usb_1: usb@a6f8800 { - compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4507,52 +4956,46 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; + iommus = <&apps_smmu 0x140 0x0>; + + phys = <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + + wakeup-source; status = "disabled"; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xcd00>; - - iommus = <&apps_smmu 0x140 0x0>; - interrupts = ; - - phys = <&usb_1_hsphy>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - }; }; - usb_2: usb@a8f8800 { - compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a8f8800 0x0 0x400>; + usb_2: usb@a800000 { + compatible = "qcom,qcs615-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a800000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, <&gcc GCC_USB20_SEC_MASTER_CLK>, @@ -4571,15 +5014,22 @@ usb_2: usb@a8f8800 { <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; + iommus = <&apps_smmu 0xe0 0x0>; + + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + power-domains = <&gcc USB20_SEC_GDSC>; required-opps = <&rpmhpd_opp_nom>; @@ -4587,30 +5037,16 @@ usb_2: usb@a8f8800 { qcom,select-utmi-as-pipe-clk; - #address-cells = <2>; - #size-cells = <2>; - ranges; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + + maximum-speed = "high-speed"; + wakeup-source; status = "disabled"; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a800000 0x0 0xcd00>; - - iommus = <&apps_smmu 0xe0 0x0>; - interrupts = ; - - phys = <&usb_hsphy_2>; - phy-names = "usb2-phy"; - - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - - maximum-speed = "high-speed"; - }; }; tsens0: thermal-sensor@c263000 { @@ -4714,10 +5150,10 @@ cpufreq_hw: cpufreq@18323000 { arch_timer: timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; thermal-zones { @@ -4833,12 +5269,25 @@ gpu-thermal { thermal-sensors = <&tsens0 9>; trips { + gpu_alert0: trip-point0 { + temperature = <105000>; + hysteresis = <5000>; + type = "passive"; + }; + gpu-critical { temperature = <115000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; q6-hvx-thermal { diff --git a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi new file mode 100644 index 000000000000..48c4ad648354 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi @@ -0,0 +1,1356 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Xilin Wu + */ + +#include +#include +#include +#include + +#include "hamoa-pmics.dtsi" + +/ { + chassis-type = "laptop"; + + aliases { + serial1 = &uart14; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Left-side port, closer to the screen */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Left-side port, farther from the screen */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_en>, <&wcn_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; + + /* EC @ 0x76 */ +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna56ac03", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + bias-pull-down; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + wcn_bt_en: wcn-bt-en-state { + pins = "gpio116"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wcn_wlan_en: wcn-wlan-en-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index 0a382cc9e643..66d566808f58 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -63,6 +63,45 @@ switch-lid { }; }; + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -995,6 +1034,14 @@ &mdss_dp1_out { link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -1257,6 +1304,12 @@ hall_int_n_default: hall-int-n-state { bias-disable; }; + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + hdtl_default: hdtl-default-state { pins = "gpio95"; function = "gpio"; @@ -1408,11 +1461,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1440,11 +1491,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1455,6 +1504,32 @@ &usb_1_ss1_qmpphy_out { remote-endpoint = <&retimer_ss1_ss_in>; }; +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + }; + }; +}; + &usb_mp { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 2fbf9ec66fb8..a9c5c523575e 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -226,6 +226,38 @@ sound { "VA DMIC3", "MIC BIAS1", "TX SWR_INPUT1", "ADC2_OUTPUT"; + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + wcd-playback-dai-link { link-name = "WCD Playback"; @@ -1709,11 +1741,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1741,11 +1771,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1773,11 +1801,9 @@ &usb_1_ss2_qmpphy { }; &usb_1_ss2 { - status = "okay"; -}; - -&usb_1_ss2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss2_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index 217ca8c7d81d..0d9a324cc6cc 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -1554,11 +1554,9 @@ bluetooth { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1586,11 +1584,9 @@ &usb_1_ss0_qmpphy_out { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1618,11 +1614,9 @@ &usb_1_ss1_qmpphy_out { }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index 175679be01eb..ee006742d6f3 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -52,6 +52,14 @@ &pcie_smmu { status = "okay"; }; +&remoteproc_adsp { + iommus = <&apps_smmu 0x1000 0x80>; +}; + +&remoteproc_cdsp { + iommus = <&apps_smmu 0x0c00 0x0>; +}; + /* * The "SBSA watchdog" is implemented in software in Gunyah * and can't be used when running in EL2. diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi index 41063948c583..b773a4976d1b 100644 --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -1473,11 +1473,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1505,11 +1503,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1521,12 +1517,10 @@ &usb_1_ss1_qmpphy_out { }; &usb_mp { - status = "okay"; -}; - -&usb_mp_dwc3 { phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>; phy-names = "usb2-0", "usb3-0"; + + status = "okay"; }; &usb_mp_hsphy0 { diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi index ba6b7b5a9191..7559557610ed 100644 --- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -718,11 +718,10 @@ vreg_l3j_0p8: ldo3 { &gpu { status = "okay"; +}; - zap-shader { - memory-region = <&gpu_microcode_mem>; - firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; }; &i2c0 { @@ -1276,11 +1275,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1308,11 +1305,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index d5a60671a383..2e38402e2c14 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1389,12 +1389,10 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1422,11 +1420,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1454,11 +1450,9 @@ &usb_1_ss2_qmpphy { }; &usb_1_ss2 { - status = "okay"; -}; - -&usb_1_ss2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss2_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 4d7fd51f370b..5d49df41be02 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1608,11 +1608,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1640,11 +1638,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1684,11 +1680,9 @@ usb_1_ss2_qmpphy_out_dp: endpoint@0 { }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index 17269eb0638a..519bcbc98985 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -6,1024 +6,22 @@ /dts-v1/; -#include -#include -#include -#include - #include "hamoa.dtsi" -#include "hamoa-pmics.dtsi" +#include "x1-asus-vivobook-s15.dtsi" / { model = "ASUS Vivobook S 15"; compatible = "asus,vivobook-s15", "qcom,x1e80100"; chassis-type = "laptop"; - - aliases { - serial1 = &uart14; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&hall_int_n_default>; - pinctrl-names = "default"; - - switch-lid { - gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - wakeup-event-action = ; - }; - }; - - hdmi-bridge { - compatible = "parade,ps185hdm"; - - pinctrl-0 = <&hdmi_hpd_default>; - pinctrl-names = "default"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - hdmi_bridge_dp_in: endpoint { - remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; - }; - }; - - port@1 { - reg = <1>; - - hdmi_bridge_tmds_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&hdmi_bridge_tmds_out>; - }; - }; - }; - - pmic-glink { - compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", - "qcom,pmic-glink"; - orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, - <&tlmm 123 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - /* Left-side port, closer to the screen */ - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss0_hs_in: endpoint { - remote-endpoint = <&usb_1_ss0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&retimer_ss0_ss_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss0_con_sbu_in: endpoint { - remote-endpoint = <&retimer_ss0_con_sbu_out>; - }; - }; - }; - }; - - /* Left-side port, farther from the screen */ - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss1_hs_in: endpoint { - remote-endpoint = <&usb_1_ss1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&retimer_ss1_ss_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss1_con_sbu_in: endpoint { - remote-endpoint = <&retimer_ss1_con_sbu_out>; - }; - }; - }; - }; - }; - - reserved-memory { - linux,cma { - compatible = "shared-dma-pool"; - size = <0x0 0x8000000>; - reusable; - linux,cma-default; - }; - }; - - vreg_edp_3p3: regulator-edp-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&edp_reg_en>; - pinctrl-names = "default"; - - regulator-always-on; - regulator-boot-on; - }; - - vreg_nvme: regulator-nvme { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p15: regulator-rtmr0-1p15 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - - gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_pwr_1p15_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p8: regulator-rtmr0-1p8 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_1p8_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_3p3: regulator-rtmr0-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_1p15: regulator-rtmr1-1p15 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_1P15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - - gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_1p15_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_1p8: regulator-rtmr1-1p8 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_1P8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_1p8_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr1_3p3: regulator-rtmr1-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR1_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb1_pwr_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vph_pwr: regulator-vph-pwr { - compatible = "regulator-fixed"; - - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - - regulator-always-on; - regulator-boot-on; - }; - - /* - * TODO: These two regulators are actually part of the removable M.2 - * card and not the CRD mainboard. Need to describe this differently. - * Functionally it works correctly, because all we need to do is to - * turn on the actual 3.3V supply above. - */ - vreg_wcn_0p95: regulator-wcn-0p95 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_0P95"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - vreg_wcn_1p9: regulator-wcn-1p9 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_1P9"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - vreg_wcn_3p3: regulator-wcn-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wcn_sw_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - wcn7850-pmu { - compatible = "qcom,wcn7850-pmu"; - - vdd-supply = <&vreg_wcn_0p95>; - vddio-supply = <&vreg_l15b_1p8>; - vddaon-supply = <&vreg_wcn_0p95>; - vdddig-supply = <&vreg_wcn_0p95>; - vddrfa1p2-supply = <&vreg_wcn_1p9>; - vddrfa1p8-supply = <&vreg_wcn_1p9>; - - wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&wcn_wlan_en>, <&wcn_bt_en>; - pinctrl-names = "default"; - - regulators { - vreg_pmu_rfa_cmn: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn"; - }; - - vreg_pmu_aon_0p59: ldo1 { - regulator-name = "vreg_pmu_aon_0p59"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p85: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p85"; - }; - - vreg_pmu_btcmx_0p85: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p85"; - }; - - vreg_pmu_rfa_0p8: ldo5 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; - - vreg_pmu_rfa_1p2: ldo6 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; - - vreg_pmu_rfa_1p8: ldo7 { - regulator-name = "vreg_pmu_rfa_1p8"; - }; - - vreg_pmu_pcie_0p9: ldo8 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; - - vreg_pmu_pcie_1p8: ldo9 { - regulator-name = "vreg_pmu_pcie_1p8"; - }; - }; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8550-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob1-supply = <&vph_pwr>; - vdd-bob2-supply = <&vph_pwr>; - vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; - vdd-l2-l13-l14-supply = <&vreg_bob1>; - vdd-l5-l16-supply = <&vreg_bob1>; - vdd-l6-l7-supply = <&vreg_bob2>; - vdd-l8-l9-supply = <&vreg_bob1>; - vdd-l12-supply = <&vreg_s5j_1p2>; - vdd-l15-supply = <&vreg_s4c_1p8>; - vdd-l17-supply = <&vreg_bob2>; - - vreg_bob1: bob1 { - regulator-name = "vreg_bob1"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - - vreg_bob2: bob2 { - regulator-name = "vreg_bob2"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l2b_3p0: ldo2 { - regulator-name = "vreg_l2b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3100000>; - regulator-initial-mode = ; - }; - - vreg_l4b_1p8: ldo4 { - regulator-name = "vreg_l4b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l13b_3p0: ldo13 { - regulator-name = "vreg_l13b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l14b_3p0: ldo14 { - regulator-name = "vreg_l14b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l15b_1p8: ldo15 { - regulator-name = "vreg_l15b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - regulators-1 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s4-supply = <&vph_pwr>; - - vreg_l3c_0p8: ldo3 { - regulator-name = "vreg_l3c_0p8"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <912000>; - regulator-initial-mode = ; - }; - - vreg_s4c_1p8: smps4 { - regulator-name = "vreg_s4c_1p8"; - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - }; - - regulators-2 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "d"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s4c_1p8>; - vdd-s1-supply = <&vph_pwr>; - - vreg_l1d_0p8: ldo1 { - regulator-name = "vreg_l1d_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2d_0p9: ldo2 { - regulator-name = "vreg_l2d_0p9"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3d_1p8: ldo3 { - regulator-name = "vreg_l3d_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - regulators-3 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s5j_1p2>; - - vreg_l2e_0p8: ldo2 { - regulator-name = "vreg_l2e_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3e_1p2: ldo3 { - regulator-name = "vreg_l3e_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-4 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s5j_1p2>; - vdd-s1-supply = <&vph_pwr>; - - vreg_s1f_0p7: smps1 { - regulator-name = "vreg_s1f_0p7"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - }; - }; - - regulators-6 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "i"; - - vdd-l1-supply = <&vreg_s4c_1p8>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - - vreg_l3i_0p8: ldo3 { - regulator-name = "vreg_l3i_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; - - regulators-7 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "j"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s5-supply = <&vph_pwr>; - - vreg_s5j_1p2: smps5 { - regulator-name = "vreg_s5j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l1j_0p8: ldo1 { - regulator-name = "vreg_l1j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2j_1p2: ldo2 { - regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1256000>; - regulator-initial-mode = ; - }; - - vreg_l3j_0p8: ldo3 { - regulator-name = "vreg_l3j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; -}; - -&gpu { - status = "okay"; }; &gpu_zap_shader { firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn"; }; -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - touchpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-0 = <&tpad_default>; - pinctrl-names = "default"; - - wakeup-source; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - clock-frequency = <400000>; - status = "okay"; - - typec-mux@8 { - compatible = "parade,ps8830"; - reg = <0x08>; - - clocks = <&rpmhcc RPMH_RF_CLK3>; - - vdd-supply = <&vreg_rtmr0_1p15>; - vdd33-supply = <&vreg_rtmr0_3p3>; - vdd33-cap-supply = <&vreg_rtmr0_3p3>; - vddar-supply = <&vreg_rtmr0_1p15>; - vddat-supply = <&vreg_rtmr0_1p15>; - vddio-supply = <&vreg_rtmr0_1p8>; - - reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&rtmr0_default>; - pinctrl-names = "default"; - - orientation-switch; - retimer-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - retimer_ss0_ss_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_ss_in>; - }; - }; - - port@1 { - reg = <1>; - - retimer_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - retimer_ss0_con_sbu_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; - }; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - keyboard@3a { - compatible = "hid-over-i2c"; - reg = <0x3a>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; - - pinctrl-0 = <&kybd_default>; - pinctrl-names = "default"; - - wakeup-source; - }; - - eusb5_repeater: redriver@43 { - compatible = "nxp,ptn3222"; - reg = <0x43>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb5_reset_n>; - pinctrl-names = "default"; - }; - - eusb3_repeater: redriver@47 { - compatible = "nxp,ptn3222"; - reg = <0x47>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb3_reset_n>; - pinctrl-names = "default"; - }; - - eusb6_repeater: redriver@4f { - compatible = "nxp,ptn3222"; - reg = <0x4f>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb6_reset_n>; - pinctrl-names = "default"; - }; - - /* EC @ 0x76 */ -}; - -&i2c7 { - clock-frequency = <400000>; - status = "okay"; - - typec-mux@8 { - compatible = "parade,ps8830"; - reg = <0x8>; - - clocks = <&rpmhcc RPMH_RF_CLK4>; - - vdd-supply = <&vreg_rtmr1_1p15>; - vdd33-supply = <&vreg_rtmr1_3p3>; - vdd33-cap-supply = <&vreg_rtmr1_3p3>; - vddar-supply = <&vreg_rtmr1_1p15>; - vddat-supply = <&vreg_rtmr1_1p15>; - vddio-supply = <&vreg_rtmr1_1p8>; - - reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&rtmr1_default>; - pinctrl-names = "default"; - - retimer-switch; - orientation-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - retimer_ss1_ss_out: endpoint { - remote-endpoint = <&pmic_glink_ss1_ss_in>; - }; - }; - - port@1 { - reg = <1>; - - retimer_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - retimer_ss1_con_sbu_out: endpoint { - remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; - }; - }; - }; - }; -}; - &iris { firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcvss8380.mbn"; - status = "okay"; -}; -&mdss { - status = "okay"; -}; - -&mdss_dp0 { - status = "okay"; -}; - -&mdss_dp0_out { - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp1 { - status = "okay"; -}; - -&mdss_dp1_out { - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp2 { - status = "okay"; -}; - -&mdss_dp2_out { - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp3 { - /delete-property/ #sound-dai-cells; - - pinctrl-0 = <&edp0_hpd_default>; - pinctrl-names = "default"; - - status = "okay"; - - aux-bus { - panel { - compatible = "samsung,atna56ac03", "samsung,atna33xc20"; - enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_3p3>; - - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; -}; - -&mdss_dp3_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pcie4 { - pinctrl-0 = <&pcie4_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l3i_0p8>; - vdda-pll-supply = <&vreg_l3e_1p2>; - - status = "okay"; -}; - -&pcie4_port0 { - reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - - wifi@0 { - compatible = "pci17cb,1107"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; - vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; - vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - }; -}; - -&pcie6a { - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-0 = <&pcie6a_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie6a_phy { - vdda-phy-supply = <&vreg_l1d_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pcie6a_port0 { - reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; -}; - -&pm8550_gpios { - rtmr0_default: rtmr0-reset-n-active-state { - pins = "gpio10"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; - - usb0_3p3_reg_en: usb0-3p3-reg-en-state { - pins = "gpio11"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pm8550ve_9_gpios { - usb0_1p8_reg_en: usb0-1p8-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pmc8380_3_gpios { - edp_bl_en: edp-bl-en-state { - pins = "gpio4"; - function = "normal"; - power-source = <1>; /* 1.8 V */ - qcom,drive-strength = ; - bias-pull-down; - input-disable; - output-enable; - }; -}; - -&pmc8380_5_gpios { - usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&qupv3_0 { - status = "okay"; -}; - -&qupv3_1 { - status = "okay"; -}; - -&qupv3_2 { status = "okay"; }; @@ -1041,345 +39,3 @@ &remoteproc_cdsp { status = "okay"; }; -&smb2360_0 { - status = "okay"; -}; - -&smb2360_0_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l2b_3p0>; -}; - -&smb2360_1 { - status = "okay"; -}; - -&smb2360_1_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l14b_3p0>; -}; - -&tlmm { - gpio-reserved-ranges = <34 2>, /* Unused */ - <44 4>, /* SPI (TPM) */ - <238 1>; /* UFS Reset */ - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - eusb3_reset_n: eusb3-reset-n-state { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-low; - }; - - eusb5_reset_n: eusb5-reset-n-state { - pins = "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-low; - }; - - eusb6_reset_n: eusb6-reset-n-state { - pins = "gpio184"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - output-low; - }; - - hall_int_n_default: hall-int-n-state { - pins = "gpio92"; - function = "gpio"; - bias-disable; - }; - - hdmi_hpd_default: hdmi-hpd-default-state { - pins = "gpio126"; - function = "usb2_dp"; - bias-disable; - }; - - kybd_default: kybd-default-state { - pins = "gpio67"; - function = "gpio"; - bias-disable; - }; - - nvme_reg_en: nvme-reg-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio147"; - function = "pcie4_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio146"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio148"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie6a_default: pcie6a-default-state { - clkreq-n-pins { - pins = "gpio153"; - function = "pcie6a_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio152"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - rtmr1_default: rtmr1-reset-n-active-state { - pins = "gpio176"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - tpad_default: tpad-default-state { - pins = "gpio3"; - function = "gpio"; - bias-disable; - }; - - usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { - pins = "gpio188"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { - pins = "gpio175"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { - pins = "gpio186"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - wcn_bt_en: wcn-bt-en-state { - pins = "gpio116"; - function = "gpio"; - drive-strength = <16>; - bias-pull-down; - }; - - wcn_sw_en: wcn-sw-en-state { - pins = "gpio214"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - wcn_wlan_en: wcn-wlan-en-state { - pins = "gpio117"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; -}; - -&uart14 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn7850-bt"; - max-speed = <3200000>; - - vddaon-supply = <&vreg_pmu_aon_0p59>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; - }; -}; - -&usb_1_ss0_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_0_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; - - status = "okay"; -}; - -&usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss0_dwc3_hs { - remote-endpoint = <&pmic_glink_ss0_hs_in>; -}; - -&usb_1_ss0_qmpphy_out { - remote-endpoint = <&retimer_ss0_ss_in>; -}; - -&usb_1_ss1_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_1_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - status = "okay"; -}; - -&usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss1_dwc3_hs { - remote-endpoint = <&pmic_glink_ss1_hs_in>; -}; - -&usb_1_ss1_qmpphy_out { - remote-endpoint = <&retimer_ss1_ss_in>; -}; - -&usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - /delete-property/ mode-switch; - /delete-property/ orientation-switch; - - status = "okay"; - - ports { - port@0 { - #address-cells = <1>; - #size-cells = <0>; - - /delete-node/ endpoint; - - usb_1_ss2_qmpphy_out_dp: endpoint@0 { - reg = <0>; - - data-lanes = <3 2 1 0>; - remote-endpoint = <&hdmi_bridge_dp_in>; - }; - - /* No USB3 lanes connected */ - }; - }; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb5_repeater>; - - status = "okay"; -}; - -&usb_mp { - status = "okay"; -}; - -&usb_mp_hsphy0 { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb3_repeater>; - - status = "okay"; -}; - -&usb_mp_hsphy1 { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb6_repeater>; - - status = "okay"; -}; - -&usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; - - status = "okay"; -}; - -&usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 4c95b1af2c64..ce7b10ea89b6 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -1293,11 +1293,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1325,11 +1323,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index d7938d349205..beb1475d7fa0 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1571,11 +1571,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1603,11 +1601,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1635,11 +1631,9 @@ &usb_1_ss2_qmpphy { }; &usb_1_ss2 { - status = "okay"; -}; - -&usb_1_ss2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss2_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts index eec5f2f1f75d..f95b1f9f439d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -791,10 +791,10 @@ vreg_s5j_1p2: smps5 { &gpu { status = "okay"; +}; - zap-shader { - firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcdxkmsuc8380.mbn"; - }; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcdxkmsuc8380.mbn"; }; &i2c0 { @@ -1414,11 +1414,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1459,11 +1457,9 @@ usb_1_ss2_qmpphy_out_dp: endpoint@0 { /* Camera */ &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 37539a09b76e..28342cb84ded 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -864,7 +864,6 @@ &gpu { }; &gpu_zap_shader { - memory-region = <&gpu_microcode_mem>; firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; }; @@ -1499,11 +1498,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1531,11 +1528,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 1d402ef86512..8afbac349cc9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -1423,11 +1423,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1455,11 +1453,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1487,11 +1483,9 @@ &usb_1_ss2_qmpphy { }; &usb_1_ss2 { - status = "okay"; -}; - -&usb_1_ss2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss2_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts new file mode 100644 index 000000000000..63e29d2cc4ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Xilin Wu + */ + +/dts-v1/; + +#include "purwa.dtsi" +#include "x1-asus-vivobook-s15.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "ASUS Vivobook S 15 X1P-42-100"; + compatible = "asus,vivobook-s15-x1p4", "qcom,x1p42100"; + chassis-type = "laptop"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcdxkmsucpurwa.mbn"; +}; + +&iris { + firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcvss8380.mbn"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qcadsp8380.mbn", + "qcom/x1p42100/ASUSTeK/vivobook-s15/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/ASUSTeK/vivobook-s15/qccdsp8380.mbn", + "qcom/x1p42100/ASUSTeK/vivobook-s15/cdsp_dtbs.elf"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 06747b54a38e..500809772097 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -1568,11 +1568,9 @@ &usb_1_ss0_qmpphy { }; &usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss0_dwc3_hs { @@ -1600,11 +1598,9 @@ &usb_1_ss1_qmpphy { }; &usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_ss1_dwc3_hs { @@ -1616,15 +1612,12 @@ &usb_1_ss1_qmpphy_out { }; &usb_1_ss2 { - status = "okay"; -}; - -&usb_1_ss2_dwc3 { dr_mode = "host"; maximum-speed = "high-speed"; phys = <&usb_1_ss2_hsphy>; phy-names = "usb2-phy"; + status = "okay"; /delete-property/ port@1; }; @@ -1664,11 +1657,9 @@ usb_1_ss2_qmpphy_out_dp: endpoint@0 { }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 1fab1b50f20e..ca45d2857ea7 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -114,12 +114,18 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-argon40.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtbo +r8a779g3-sparrow-hawk-olimex-dsi-hdmi-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtbo r8a779g3-sparrow-hawk-rpi-display-2-5in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-5in.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo r8a779g3-sparrow-hawk-rpi-display-2-7in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-display-13in.dtbo +r8a779g3-sparrow-hawk-ws-display-13in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-ws-display-13in.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-display-13in.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo @@ -179,6 +185,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb +dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc.dtb + dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb @@ -202,6 +210,9 @@ dtb-$(CONFIG_ARCH_R9A09G057) += rzv2-evk-cn15-sd.dtbo r9a09g057h44-rzv2h-evk-cn15-sd-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15-sd.dtbo dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-sd.dtb dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb +dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip-pixpaper.dtbo +r9a09g057h48-kakip-pixpaper-dtbs := r9a09g057h48-kakip.dtb r9a09g057h48-kakip-pixpaper.dtbo +dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip-pixpaper.dtb dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index d55f2d7066ad..62ab0a3776e7 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -8,15 +8,6 @@ #include / { - backlight_lvds: backlight-lvds { - compatible = "pwm-backlight"; - power-supply = <®_lcd>; - enable-gpios = <&gpio_exp1 3 GPIO_ACTIVE_HIGH>; - pwms = <&pwm2 0 25000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - }; - backlight_dpi: backlight-dpi { compatible = "pwm-backlight"; power-supply = <®_lcd>; @@ -101,38 +92,6 @@ led3 { }; }; - lvds { - compatible = "panel-lvds"; - power-supply = <®_lcd_reset>; - width-mm = <223>; - height-mm = <125>; - backlight = <&backlight_lvds>; - data-mapping = "vesa-24"; - - panel-timing { - /* 800x480@60Hz */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hsync-len = <48>; - hfront-porch = <40>; - hback-porch = <40>; - vfront-porch = <13>; - vback-porch = <29>; - vsync-len = <1>; - hsync-active = <1>; - vsync-active = <3>; - de-active = <1>; - pixelclk-active = <0>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - rgb { /* Different LCD with compatible timings */ compatible = "rocktech,rk070er9427"; @@ -164,16 +123,6 @@ reg_lcd: regulator-lcd { enable-active-high; }; - reg_lcd_reset: regulator-lcd-reset { - compatible = "regulator-fixed"; - regulator-name = "nLCD_RESET"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 3 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_lcd>; - }; - reg_cam0: regulator-cam0 { compatible = "regulator-fixed"; regulator-name = "reg_cam0"; @@ -480,18 +429,6 @@ gpio_exp1: gpio@70 { }; }; -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - &msiof1 { pinctrl-0 = <&msiof1_pins>; pinctrl-names = "default"; @@ -562,11 +499,6 @@ pwm0_pins: pwm0 { function = "pwm0"; }; - pwm2_pins: pwm2 { - groups = "pwm2_a"; - function = "pwm2"; - }; - sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -617,12 +549,6 @@ &pwm0 { status = "okay"; }; -&pwm2 { - pinctrl-0 = <&pwm2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - &rcar_sound { pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index af6d15f90c65..f8442b6a85a7 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -59,8 +59,7 @@ &avb { status = "okay"; phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <0>; interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi index 191b051ecfd4..5815e9d2d8a9 100644 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -22,8 +22,7 @@ &avb { status = "okay"; phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c915", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c915"; reg = <0>; interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 692a2b12aa03..aaedb1fb51ae 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -53,6 +53,12 @@ backlight: backlight { power-supply = <®_12p0v>; }; + pcie_usb_refclk: clk-x7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + cvbs-in { compatible = "composite-video-connector"; label = "CVBS IN"; @@ -439,6 +445,13 @@ adv7511_out: endpoint { }; }; + pcie_usb_clk: clk@68 { + compatible = "renesas,9fgv0841"; + reg = <0x68>; + clocks = <&pcie_usb_refclk>; + #clock-cells = <1>; + }; + video-receiver@70 { compatible = "adi,adv7482"; reg = <0x70>; @@ -577,13 +590,30 @@ &ohci0 { }; &pcie_bus_clk { - clock-frequency = <100000000>; + status = "disabled"; }; &pciec0 { + clocks = <&cpg CPG_MOD 319>, <&pcie_usb_clk 1>; status = "okay"; }; +&pciec0_rp { + /* + * This configuration is valid for SW49 in OFF position, + * which means the PCIe signals are routed to the PCIe slot + * and U11 9FGV0841 PCIe clock generator output 3 supplies + * clock to the PCIe slot. + * + * In case the SW49 is set to ON position, which means the + * PCIe signals are routed to the EX BT/WLAN expansion port, + * and U11 9FGV0841 PCIe clock generator output 4 supplies + * clock to the port, change clocks below to: + * clocks = <&pcie_usb_clk 4>; + */ + clocks = <&pcie_usb_clk 3>; +}; + &pfc { avb_pins: avb { groups = "avb_link", "avb_mii"; @@ -871,7 +901,18 @@ &usb2_phy0 { status = "okay"; }; +&usb3_phy0 { + clocks = <&pcie_usb_clk 6>; + status = "okay"; +}; + +&usb3s0_clk { + status = "disabled"; +}; + &usb3_peri0 { + phys = <&usb3_phy0>; + phy-names = "usb"; companion = <&xhci0>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index 4113710d5522..83b6c04274ac 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -24,8 +24,7 @@ &avb { status = "okay"; phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c915", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c915"; reg = <0>; interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 607f62a448d8..59a0f2e1479d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2814,6 +2814,16 @@ pciec0: pcie@fe000000 { iommu-map = <0 &ipmmu_hc 0 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec0_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; pciec1: pcie@ee800000 { @@ -2843,6 +2853,16 @@ pciec1: pcie@ee800000 { iommu-map = <0 &ipmmu_hc 1 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec1_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; pciec0_ep: pcie-ep@fe000000 { diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index e64c7b1aebc4..ad36aa8e7543 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2619,6 +2619,16 @@ pciec0: pcie@fe000000 { iommu-map = <0 &ipmmu_hc 0 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec0_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; pciec1: pcie@ee800000 { @@ -2648,6 +2658,16 @@ pciec1: pcie@ee800000 { iommu-map = <0 &ipmmu_hc 1 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec1_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; imr-lx4@fe860000 { diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 89f6c052c5e0..9d76e39eab72 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2499,6 +2499,16 @@ pciec0: pcie@fe000000 { iommu-map = <0 &ipmmu_hc 0 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec0_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; pciec1: pcie@ee800000 { @@ -2528,6 +2538,16 @@ pciec1: pcie@ee800000 { iommu-map = <0 &ipmmu_hc 1 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec1_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; fcpf0: fcp@fe950000 { diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 425561e658ca..611a9335c63a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2494,6 +2494,16 @@ pciec0: pcie@fe000000 { iommu-map = <0 &ipmmu_hc 0 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec0_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; pciec1: pcie@ee800000 { @@ -2523,6 +2533,16 @@ pciec1: pcie@ee800000 { iommu-map = <0 &ipmmu_hc 1 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec1_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; fdp1@fe940000 { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index d3698f7e494d..fadb5f4effcf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1912,6 +1912,16 @@ pciec0: pcie@fe000000 { iommu-map = <0 &ipmmu_hc 0 1>; iommu-map-mask = <0>; status = "disabled"; + + /* PCIe bridge, Root Port */ + pciec0_rp: pci@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x0 0x0 0x0 0x0>; + compatible = "pciclass,0604"; + device_type = "pci"; + ranges; + }; }; vspb0: vsp@fe960000 { @@ -2180,4 +2190,21 @@ timer { ; interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; + + /* External USB clock - to be overridden by boards that provide it */ + usb3s0_clk: usb3s0-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb3_phy0: usb-phy { + compatible = "usb-nop-xceiv"; + clocks = <&usb3s0_clk>; + clock-names = "main_clk"; + clock-frequency = <100000000>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + #phy-cells = <0>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtso new file mode 100644 index 000000000000..40cc5ee3b56d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-olimex-dsi-hdmi.dtso @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for Olimex MIPI-HDMI adapter connected to J4:DSI + * on R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2026 Scott Murray + */ + +/dts-v1/; +/plugin/; + +&{/} { + hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI1"; + type = "a"; + ddc-i2c-bus = <&i2c0_mux3>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <<8912b_out>; + }; + }; + }; + + reg_vr1: regulator-vr1 { + compatible = "regulator-fixed"; + regulator-name = "VR1-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_3p3v>; + }; +}; + +&i2c0_mux3 { + #address-cells = <1>; + #size-cells = <0>; + + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48>; + vcchdmipll-supply = <®_vr1>; + vcchdmitx-supply = <®_vr1>; + vcclvdspll-supply = <®_vr1>; + vcclvdstx-supply = <®_vr1>; + vccmipirx-supply = <®_vr1>; + vccsysclk-supply = <®_vr1>; + vdd-supply = <®_vr1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_out_in: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8912b_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&hdmi_out_in>; + data-lanes = <1 2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-display-13in.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-display-13in.dtso new file mode 100644 index 000000000000..26434d4540ef --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-display-13in.dtso @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for the Waveshare 13.3 MIPI DSI panel connected + * to J4:DSI on R-Car V4H ES3.0 Sparrow Hawk board + * + * Copyright (C) 2025-2026 Marek Vasut + */ + +/dts-v1/; +/plugin/; + +&{/} { + panel { + compatible = "waveshare,13.3inch-panel"; + power-supply = <®_5p0v>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c0_mux3 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + }; + + bridge@45 { + compatible = "waveshare,dsi2dpi"; + reg = <0x45>; + power-supply = <®_5p0v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&bridge_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts index 812b133cf29e..af680290ce81 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -547,6 +547,10 @@ msiof1_snd_endpoint: endpoint { }; }; +&otp { + bootph-all; +}; + /* Page 26 / 2230 Key M M.2 */ &pcie0_clkref { status = "disabled"; @@ -631,6 +635,7 @@ canfd4_pins: canfd4 { hscif0_pins: hscif0 { groups = "hscif0_data", "hscif0_ctrl"; function = "hscif0"; + bootph-all; }; /* Page 23 / DEBUG */ diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi new file mode 100644 index 000000000000..28b0c7558748 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3L SoC + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a08g046"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; + cache-level = <3>; + }; + }; + + eth0_txc_tx_clk: eth0-txc-tx-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + eth0_rxc_rx_clk: eth0-rxc-rx-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + eth1_txc_tx_clk: eth1-txc-tx-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + eth1_rxc_rx_clk: eth1-rxc-rx-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@100ac000 { + compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044"; + reg = <0 0x100ac000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + i2c0: i2c@100ae000 { + reg = <0 0x100ae000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + /* placeholder */ + }; + + canfd: can@100c0000 { + reg = <0 0x100c0000 0 0x20000>; + /* placeholder */ + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a08g046-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>, + <ð0_txc_tx_clk>, <ð0_rxc_rx_clk>, + <ð1_txc_tx_clk>, <ð1_rxc_rx_clk>; + clock-names = "extal", + "eth0_txc_tx_clk", "eth0_rxc_rx_clk", + "eth1_txc_tx_clk", "eth1_rxc_rx_clk"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a08g046-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + }; + + pinctrl: pinctrl@11030000 { + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + /* placeholder */ + }; + + sdhi1: mmc@11c10000 { + reg = <0x0 0x11c10000 0 0x10000>; + /* placeholder */ + }; + + pcie: pcie@11e40000 { + reg = <0 0x11e40000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + /* placeholder */ + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + /* placeholder */ + }; + }; + + gic: interrupt-controller@12400000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x12400000 0 0x20000>, + <0x0 0x12440000 0 0x80000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts new file mode 100644 index 000000000000..86db86335d5e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3L SMARC EVK board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/dts-v1/; + +/* Add place holder to avoid compilation error with renesas-smarc2.dtsi */ +#define KEY_1_GPIO 1 +#define KEY_2_GPIO 2 +#define KEY_3_GPIO 3 + +#include +#include +#include "r9a08g046l48.dtsi" +#include "rzg3l-smarc-som.dtsi" +#include "renesas-smarc2.dtsi" + +/ { + model = "Renesas SMARC EVK version 2 based on r9a08g046l48"; + compatible = "renesas,smarc2-evk", "renesas,rzg3l-smarcm", + "renesas,r9a08g046l48", "renesas,r9a08g046"; + + aliases { + serial3 = &scif0; + }; +}; + +&keys { + status = "disabled"; + + /delete-node/ key-1; + /delete-node/ key-2; + /delete-node/ key-3; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi new file mode 100644 index 000000000000..39b114172af5 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3L R9A08G046L48 SoC specific parts + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a08g046.dtsi" + +/ { + compatible = "renesas,r9a08g046l48", "renesas,r9a08g046"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index 39fe3f94991e..07147743de93 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -100,8 +100,7 @@ &avb { status = "okay"; phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <0>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index cbb48ff5028f..95a4e30a064d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -591,6 +591,90 @@ channel5 { }; }; + rspi0: spi@12800000 { + compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x54>, + <&cpg CPG_MOD 0x55>, + <&cpg CPG_MOD 0x56>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7b>, <&cpg 0x7c>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x448c>, <&dmac0 0x448d>, + <&dmac1 0x448c>, <&dmac1 0x448d>, + <&dmac2 0x448c>, <&dmac2 0x448d>, + <&dmac3 0x448c>, <&dmac3 0x448d>, + <&dmac4 0x448c>, <&dmac4 0x448d>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@12800400 { + compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800400 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x57>, + <&cpg CPG_MOD 0x58>, + <&cpg CPG_MOD 0x59>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7d>, <&cpg 0x7e>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x448e>, <&dmac0 0x448f>, + <&dmac1 0x448e>, <&dmac1 0x448f>, + <&dmac2 0x448e>, <&dmac2 0x448f>, + <&dmac3 0x448e>, <&dmac3 0x448f>, + <&dmac4 0x448e>, <&dmac4 0x448f>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@12800800 { + compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800800 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x5a>, + <&cpg CPG_MOD 0x5b>, + <&cpg CPG_MOD 0x5c>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7f>, <&cpg 0x80>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x4490>, <&dmac0 0x4491>, + <&dmac1 0x4490>, <&dmac1 0x4491>, + <&dmac2 0x4490>, <&dmac2 0x4491>, + <&dmac3 0x4490>, <&dmac3 0x4491>, + <&dmac4 0x4490>, <&dmac4 0x4491>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rsci0: serial@12800c00 { compatible = "renesas,r9a09g047-rsci"; reg = <0 0x12800c00 0 0x400>; @@ -841,6 +925,75 @@ wdt3: watchdog@13000400 { status = "disabled"; }; + pcie: pcie@13400000 { + compatible = "renesas,r9a09g047-pcie"; + reg = <0 0x13400000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + renesas,sysc = <&sys>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x0039>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + tsu: thermal@14002000 { compatible = "renesas,r9a09g047-tsu"; reg = <0 0x14002000 0 0x1000>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 696903dc7a63..6372f582a7c4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -122,6 +122,11 @@ key-sleep { #endif }; +&pcie { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; +}; + &pinctrl { canfd_pins: canfd { can1_pins: can1 { @@ -145,6 +150,17 @@ nmi_pins: nmi { input-schmitt-enable; }; + pcie-clkreq-n-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "PCIE_M2B_CKREQ"; + }; + + pcie_pins: pcie { + pinmux = ; /* PCIE_RST_OUT# */ + }; + rsci2_pins: rsci2 { pinmux = , /* RXD2 */ , /* TXD2 */ @@ -167,6 +183,13 @@ rsci9_pins: rsci9 { bias-pull-up; }; + rspi0_pins: rspi0 { + pinmux = , /* MISOA */ + , /* MOSIA */ + , /* RSPCKA */ + ; /* SSLA0 */ + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; @@ -234,6 +257,15 @@ &rsci9 { }; #endif +&rspi0 { + pinctrl-0 = <&rspi0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif_pins>; pinctrl-names = "default"; @@ -248,7 +280,13 @@ &sdhi1 { vqmmc-supply = <&vqmmc_sd1_pvdd>; }; +&usb3_phy { + status = "okay"; +}; + &xhci { pinctrl-0 = <&usb3_pins>; pinctrl-names = "default"; + + status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 9fb15ca24984..40525470194e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -599,16 +599,6 @@ ostm7: timer@12c03000 { status = "disabled"; }; - wdt0: watchdog@11c00400 { - compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; - reg = <0 0x11c00400 0 0x400>; - clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; - clock-names = "pclk", "oscclk"; - resets = <&cpg 0x75>; - power-domains = <&cpg>; - status = "disabled"; - }; - wdt1: watchdog@14400000 { compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; reg = <0 0x14400000 0 0x400>; @@ -619,23 +609,18 @@ wdt1: watchdog@14400000 { status = "disabled"; }; - wdt2: watchdog@13000000 { - compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; - reg = <0 0x13000000 0 0x400>; - clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; - clock-names = "pclk", "oscclk"; - resets = <&cpg 0x77>; - power-domains = <&cpg>; - status = "disabled"; - }; - - wdt3: watchdog@13000400 { - compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; - reg = <0 0x13000400 0 0x400>; - clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; - clock-names = "pclk", "oscclk"; - resets = <&cpg 0x78>; + rtc: rtc@11c00800 { + compatible = "renesas,r9a09g056-rtca3", "renesas,rz-rtca3"; + reg = <0 0x11c00800 0 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>; + clock-names = "bus", "counter"; power-domains = <&cpg>; + resets = <&cpg 0x79>, <&cpg 0x7a>; + reset-names = "rtc", "rtest"; status = "disabled"; }; @@ -769,6 +754,13 @@ rspi0: spi@12800000 { clock-names = "pclk", "pclk_sfr", "tclk"; resets = <&cpg 0x7b>, <&cpg 0x7c>; reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x448c>, <&dmac0 0x448d>, + <&dmac1 0x448c>, <&dmac1 0x448d>, + <&dmac2 0x448c>, <&dmac2 0x448d>, + <&dmac3 0x448c>, <&dmac3 0x448d>, + <&dmac4 0x448c>, <&dmac4 0x448d>; + dma-names = "rx", "tx", "rx", "tx", "rx", + "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -790,6 +782,13 @@ rspi1: spi@12800400 { clock-names = "pclk", "pclk_sfr", "tclk"; resets = <&cpg 0x7d>, <&cpg 0x7e>; reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x448e>, <&dmac0 0x448f>, + <&dmac1 0x448e>, <&dmac1 0x448f>, + <&dmac2 0x448e>, <&dmac2 0x448f>, + <&dmac3 0x448e>, <&dmac3 0x448f>, + <&dmac4 0x448e>, <&dmac4 0x448f>; + dma-names = "rx", "tx", "rx", "tx", "rx", + "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -811,6 +810,13 @@ rspi2: spi@12800800 { clock-names = "pclk", "pclk_sfr", "tclk"; resets = <&cpg 0x7f>, <&cpg 0x80>; reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x4490>, <&dmac0 0x4491>, + <&dmac1 0x4490>, <&dmac1 0x4491>, + <&dmac2 0x4490>, <&dmac2 0x4491>, + <&dmac3 0x4490>, <&dmac3 0x4491>, + <&dmac4 0x4490>, <&dmac4 0x4491>; + dma-names = "rx", "tx", "rx", "tx", "rx", + "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 9af50198d2f1..00e5455ea5ab 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -260,12 +260,12 @@ raa215300: pmic@12 { &mdio0 { phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <0>; rxc-skew-psec = <0>; txc-skew-psec = <0>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -279,12 +279,12 @@ phy0: ethernet-phy@0 { &mdio1 { phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <0>; rxc-skew-psec = <0>; txc-skew-psec = <0>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -446,6 +446,10 @@ &qextal_clk { clock-frequency = <24000000>; }; +&rtc { + status = "okay"; +}; + &rtxin_clk { clock-frequency = <32768>; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 504c28386622..9581af58024e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -735,6 +735,13 @@ rspi0: spi@12800000 { clock-names = "pclk", "pclk_sfr", "tclk"; resets = <&cpg 0x7b>, <&cpg 0x7c>; reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x448c>, <&dmac0 0x448d>, + <&dmac1 0x448c>, <&dmac1 0x448d>, + <&dmac2 0x448c>, <&dmac2 0x448d>, + <&dmac3 0x448c>, <&dmac3 0x448d>, + <&dmac4 0x448c>, <&dmac4 0x448d>; + dma-names = "rx", "tx", "rx", "tx", "rx", + "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -756,6 +763,13 @@ rspi1: spi@12800400 { clock-names = "pclk", "pclk_sfr", "tclk"; resets = <&cpg 0x7d>, <&cpg 0x7e>; reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x448e>, <&dmac0 0x448f>, + <&dmac1 0x448e>, <&dmac1 0x448f>, + <&dmac2 0x448e>, <&dmac2 0x448f>, + <&dmac3 0x448e>, <&dmac3 0x448f>, + <&dmac4 0x448e>, <&dmac4 0x448f>; + dma-names = "rx", "tx", "rx", "tx", "rx", + "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -777,6 +791,13 @@ rspi2: spi@12800800 { clock-names = "pclk", "pclk_sfr", "tclk"; resets = <&cpg 0x7f>, <&cpg 0x80>; reset-names = "presetn", "tresetn"; + dmas = <&dmac0 0x4490>, <&dmac0 0x4491>, + <&dmac1 0x4490>, <&dmac1 0x4491>, + <&dmac2 0x4490>, <&dmac2 0x4491>, + <&dmac3 0x4490>, <&dmac3 0x4491>, + <&dmac4 0x4490>, <&dmac4 0x4491>; + dma-names = "rx", "tx", "rx", "tx", "rx", + "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index dc4577ebf2e9..bd69109a5086 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -108,6 +108,12 @@ vqmmc_sdhi1: regulator-vccq-sdhi1 { states = <3300000 0>, <1800000 1>; }; + x1: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + /* 32.768kHz crystal */ x6: x6-clock { compatible = "fixed-clock"; @@ -277,16 +283,35 @@ raa215300: pmic@12 { clocks = <&x6>; clock-names = "xin"; }; + + versa3: clock-generator@69 { + compatible = "renesas,5l35023"; + reg = <0x69>; + clocks = <&x1>; + #clock-cells = <1>; + assigned-clocks = <&versa3 0>, /* qextal_clk */ + <&versa3 1>, + <&versa3 2>, /* rtxin_clk */ + <&versa3 3>, + <&versa3 4>, + <&versa3 5>; + assigned-clock-rates = <24000000>, + <24576000>, + <32768>, + <22579200>, + <100000000>, + <100000000>; + }; }; &mdio0 { phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <0>; rxc-skew-psec = <0>; txc-skew-psec = <0>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -300,12 +325,12 @@ phy0: ethernet-phy@0 { &mdio1 { phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <0>; rxc-skew-psec = <0>; txc-skew-psec = <0>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip-pixpaper.dtso b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip-pixpaper.dtso new file mode 100644 index 000000000000..7b8209494b73 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip-pixpaper.dtso @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Overlay for Mayqueen (Open-EP Community) pixpaper display + * support on Renesas RZ/V2H platform (KAKIP board). + * + * Copyright (C) 2026 Wig Cheng + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&pinctrl { + rspi0_pins: rspi0 { + pinmux = , /* SPI0 MOSI */ + , /* SPI0 MISO */ + , /* SPI0 CLK */ + ; /* SPI0 CE0 */ + }; +}; + +&rspi0 { + pinctrl-0 = <&rspi0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + display@0 { + compatible = "mayqueen,pixpaper"; + reg = <0>; + spi-max-frequency = <1000000>; + reset-gpios = <&pinctrl RZV2H_GPIO(A, 7) GPIO_ACTIVE_HIGH>; + busy-gpios = <&pinctrl RZV2H_GPIO(B, 3) GPIO_ACTIVE_HIGH>; + dc-gpios = <&pinctrl RZV2H_GPIO(7, 4) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 9d0b4d8d3d5b..3761551c9647 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -8,6 +8,24 @@ #include #include +/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */ +#define RZT2H_IRQ0 16 +#define RZT2H_IRQ1 17 +#define RZT2H_IRQ2 18 +#define RZT2H_IRQ3 19 +#define RZT2H_IRQ4 20 +#define RZT2H_IRQ5 21 +#define RZT2H_IRQ6 22 +#define RZT2H_IRQ7 23 +#define RZT2H_IRQ8 24 +#define RZT2H_IRQ9 25 +#define RZT2H_IRQ10 26 +#define RZT2H_IRQ11 27 +#define RZT2H_IRQ12 28 +#define RZT2H_IRQ13 29 +#define RZT2H_IRQ14 30 +#define RZT2H_IRQ15 31 + / { compatible = "renesas,r9a09g077"; #address-cells = <2>; @@ -200,6 +218,10 @@ rspi0: spi@80007000 { clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, <&cpg CPG_MOD 104>; clock-names = "pclk", "pclkspi"; + dmas = <&dmac0 0x267a>, <&dmac0 0x267b>, + <&dmac1 0x267a>, <&dmac1 0x267b>, + <&dmac2 0x267a>, <&dmac2 0x267b>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -218,6 +240,10 @@ rspi1: spi@80007400 { clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, <&cpg CPG_MOD 105>; clock-names = "pclk", "pclkspi"; + dmas = <&dmac0 0x267f>, <&dmac0 0x2680>, + <&dmac1 0x267f>, <&dmac1 0x2680>, + <&dmac2 0x267f>, <&dmac2 0x2680>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -236,6 +262,10 @@ rspi2: spi@80007800 { clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, <&cpg CPG_MOD 106>; clock-names = "pclk", "pclkspi"; + dmas = <&dmac0 0x2684>, <&dmac0 0x2685>, + <&dmac1 0x2684>, <&dmac1 0x2685>, + <&dmac2 0x2684>, <&dmac2 0x2685>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -254,6 +284,10 @@ rspi3: spi@81007000 { clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, <&cpg CPG_MOD 602>; clock-names = "pclk", "pclkspi"; + dmas = <&dmac0 0x2689>, <&dmac0 0x268a>, + <&dmac1 0x2689>, <&dmac1 0x268a>, + <&dmac2 0x2689>, <&dmac2 0x268a>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index e9639bbb2d70..4c0e52850ca9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -14,12 +14,15 @@ /* * SD0 can be connected to either eMMC (IC49) or SD card slot CN31 * Lets by default enable the eMMC, note we need the below SW settings - * for eMMC. + * for eMMC. Also ensure that CN78 pins 5 and 6 are connected with a jumper + * to provide the SD0 power supply when using eMMC. * SW2[1] = ON; SW2[2] = ON * * To enable SD card and disable eMMC on SDHI0 disable the below macro - * and set the below switch setting: - * SW2[1] = OFF; SW2[2] = ON + * and set the switch as follows. Also ensure that CN78 pins 3 and 4 are connected + * with a jumper to provide the SD0 power supply when using an SD card. + * + * SW2[1] = OFF; SW2[2] = ON. */ #define SD0_EMMC 1 #define SD0_SD (!SD0_EMMC) @@ -224,10 +227,12 @@ &i2c1 { }; &mdio1_phy { + interrupts-extended = <&icu RZT2H_IRQ3 IRQ_TYPE_EDGE_FALLING>; reset-gpios = <&pinctrl RZT2H_GPIO(32, 3) GPIO_ACTIVE_LOW>; }; &mdio2_phy { + interrupts-extended = <&icu RZT2H_IRQ13 IRQ_TYPE_EDGE_FALLING>; /* * PHY2 Reset Configuration: * @@ -248,6 +253,35 @@ can0_pins: can0-pins { ; /* CANTX0 */ }; + /* + * GMAC1 Pin Configuration: + * + * SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and + * P35_0-P35_2 for Ethernet port 3 + */ + gmac1_pins: gmac1-pins { + pinmux = , /* ETH3_TXCLK */ + , /* ETH3_TXD0 */ + , /* ETH3_TXD1 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + , /* ETH3_TXEN */ + , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + , /* ETH3_RXDV */ + , /* ETH3_TXER */ + , /* ETH3_RXER */ + , /* ETH3_CRS */ + , /* ETH3_COL */ + , /* GMAC1_MDC */ + , /* GMAC1_MDIO */ + , /* ETH3_REFCLK */ + ; /* IRQ3 */ + }; + /* * GMAC2 Pin Configuration: * @@ -274,35 +308,8 @@ gmac2_pins: gmac2-pins { , /* ETH2_COL */ , /* GMAC2_MDC */ , /* GMAC2_MDIO */ - ; /* ETH2_REFCLK */ - }; - - /* - * GMAC1 Pin Configuration: - * - * SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and - * P35_0-P35_2 for Ethernet port 3 - */ - gmac1_pins: gmac1-pins { - pinmux = , /* ETH3_TXCLK */ - , /* ETH3_TXD0 */ - , /* ETH3_TXD1 */ - , /* ETH3_TXD2 */ - , /* ETH3_TXD3 */ - , /* ETH3_TXEN */ - , /* ETH3_RXCLK */ - , /* ETH3_RXD0 */ - , /* ETH3_RXD1 */ - , /* ETH3_RXD2 */ - , /* ETH3_RXD3 */ - , /* ETH3_RXDV */ - , /* ETH3_TXER */ - , /* ETH3_RXER */ - , /* ETH3_CRS */ - , /* ETH3_COL */ - , /* GMAC1_MDC */ - , /* GMAC1_MDIO */ - ; /* ETH3_REFCLK */ + , /* ETH2_REFCLK */ + ; /* IRQ13 */ }; /* diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index d407c48f9966..f697e9698ed3 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -8,6 +8,24 @@ #include #include +/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */ +#define RZN2H_IRQ0 16 +#define RZN2H_IRQ1 17 +#define RZN2H_IRQ2 18 +#define RZN2H_IRQ3 19 +#define RZN2H_IRQ4 20 +#define RZN2H_IRQ5 21 +#define RZN2H_IRQ6 22 +#define RZN2H_IRQ7 23 +#define RZN2H_IRQ8 24 +#define RZN2H_IRQ9 25 +#define RZN2H_IRQ10 26 +#define RZN2H_IRQ11 27 +#define RZN2H_IRQ12 28 +#define RZN2H_IRQ13 29 +#define RZN2H_IRQ14 30 +#define RZN2H_IRQ15 31 + / { compatible = "renesas,r9a09g087"; #address-cells = <2>; @@ -200,6 +218,10 @@ rspi0: spi@80007000 { clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, <&cpg CPG_MOD 104>; clock-names = "pclk", "pclkspi"; + dmas = <&dmac0 0x267a>, <&dmac0 0x267b>, + <&dmac1 0x267a>, <&dmac1 0x267b>, + <&dmac2 0x267a>, <&dmac2 0x267b>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -218,6 +240,10 @@ rspi1: spi@80007400 { clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, <&cpg CPG_MOD 105>; clock-names = "pclk", "pclkspi"; + dmas = <&dmac0 0x267f>, <&dmac0 0x2680>, + <&dmac1 0x267f>, <&dmac1 0x2680>, + <&dmac2 0x267f>, <&dmac2 0x2680>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -236,6 +262,10 @@ rspi2: spi@80007800 { clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, <&cpg CPG_MOD 106>; clock-names = "pclk", "pclkspi"; + dmas = <&dmac0 0x2684>, <&dmac0 0x2685>, + <&dmac1 0x2684>, <&dmac1 0x2685>, + <&dmac2 0x2684>, <&dmac2 0x2685>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; @@ -254,6 +284,10 @@ rspi3: spi@81007000 { clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, <&cpg CPG_MOD 602>; clock-names = "pclk", "pclkspi"; + dmas = <&dmac0 0x2689>, <&dmac0 0x268a>, + <&dmac1 0x2689>, <&dmac1 0x268a>, + <&dmac2 0x2689>, <&dmac2 0x268a>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 19f0a2c06753..ef6cc7497c2c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -14,12 +14,14 @@ /* * SD0 can be connected to either eMMC (U33) or SD card slot CN21 * Lets by default enable the eMMC, note we need the below SW settings - * for eMMC. + * for eMMC. Also ensure that JP23 pins 5 and 6 are connected with a jumper + * to provide the SD0 power supply when using eMMC. * DSW5[1] = ON; DSW5[2] = ON * DSW17[5] = OFF; DSW17[6] = ON * * To enable SD card and disable eMMC on SDHI0 disable the below macro - * and set the below switch setting: + * and set the below switch settings. Also ensure that JP23 pins 3 and 4 are + * connected with a jumper to provide the SD0 power supply when using an SD card. * DSW5[1] = OFF; DSW5[2] = ON * P22_6 = SD0_WP; DSW15[1] = OFF; DSW15[2] = ON * P22_5 = SD0_CD; DSW15[3] = OFF; DSW15[4] = ON @@ -303,6 +305,7 @@ &i2c1 { }; &mdio1_phy { + interrupts-extended = <&icu RZN2H_IRQ15 IRQ_TYPE_EDGE_FALLING>; /* * PHY3 Reset Configuration: * @@ -312,6 +315,7 @@ &mdio1_phy { }; &mdio2_phy { + interrupts-extended = <&icu RZN2H_IRQ14 IRQ_TYPE_EDGE_FALLING>; /* * PHY2 Reset Configuration: * @@ -333,37 +337,7 @@ can1_pins: can1-pins { }; /* - * GMAC2 Pin Configuration: - * - * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 - * DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7, - * P31_2, P31_4 and P31_5 are used for Ethernet port 2 - */ - gmac2_pins: gmac2-pins { - pinmux = , /* ETH2_TXCLK */ - , /* ETH2_TXD0 */ - , /* ETH2_TXD1 */ - , /* ETH2_TXD2 */ - , /* ETH2_TXD3 */ - , /* ETH2_TXEN */ - , /* ETH2_RXCLK */ - , /* ETH2_RXD0 */ - , /* ETH2_RXD1 */ - , /* ETH2_RXD2 */ - , /* ETH2_RXD3 */ - , /* ETH2_RXDV */ - , /* ETH2_TXER */ - , /* ETH2_RXER */ - , /* ETH2_CRS */ - , /* ETH2_COL */ - , /* GMAC2_MDC */ - , /* GMAC2_MDIO */ - ; /* ETH2_REFCLK */ - - }; - - /* - * GMAC2 Pin Configuration: + * GMAC1 Pin Configuration: * * DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6 * for Ethernet port 3 @@ -388,7 +362,40 @@ gmac1_pins: gmac1-pins { , /* ETH3_COL */ , /* GMAC1_MDC */ , /* GMAC1_MDIO */ - ; /* ETH3_REFCLK */ + , /* ETH3_REFCLK */ + ; /* IRQ15 */ + }; + + /* + * GMAC2 Pin Configuration: + * + * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 + * DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7, + * P31_2, P31_4 and P31_5 are used for Ethernet port 2 + * DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14 + */ + gmac2_pins: gmac2-pins { + pinmux = , /* ETH2_TXCLK */ + , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + , /* ETH2_TXEN */ + , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + , /* ETH2_RXDV */ + , /* ETH2_TXER */ + , /* ETH2_RXER */ + , /* ETH2_CRS */ + , /* ETH2_COL */ + , /* GMAC2_MDC */ + , /* GMAC2_MDIO */ + , /* ETH2_REFCLK */ + ; /* IRQ14 */ + }; /* diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index b607b5d6c259..696a933af808 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -96,6 +96,10 @@ &i2c0 { clock-frequency = <400000>; }; +&pcie { + status = "okay"; +}; + &scif0 { status = "okay"; }; @@ -107,11 +111,3 @@ &sdhi1 { status = "okay"; }; - -&usb3_phy { - status = "okay"; -}; - -&xhci { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index d511e152d7c6..7eccdaffb221 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -99,8 +99,7 @@ ð0 { status = "okay"; phy0: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <7>; interrupts-extended = <&irqc RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; @@ -126,8 +125,7 @@ ð1 { status = "okay"; phy1: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <7>; interrupts-extended = <&irqc RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 3e8909a872e3..15f2e9eaaf0b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -79,8 +79,7 @@ ð0 { status = "okay"; phy0: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <7>; interrupts-extended = <&irqc RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index cd4275d86935..0f917d7c9939 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -75,8 +75,7 @@ ð0 { status = "okay"; phy0: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <7>; interrupts-extended = <&irqc RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; @@ -103,8 +102,7 @@ ð1 { status = "okay"; phy1: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <7>; interrupts-extended = <&irqc RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 3b571c096752..d978619155d2 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -43,6 +43,12 @@ memory@48000000 { reg = <0x0 0x48000000 0x0 0xf8000000>; }; + pcie_refclk: pcie-ref-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -136,14 +142,13 @@ &i3c { &mdio0 { phy0: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <7>; interrupts-extended = <&icu 3 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <1400>; txc-skew-psec = <1400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -157,14 +162,13 @@ phy0: ethernet-phy@7 { &mdio1 { phy1: ethernet-phy@7 { - compatible = "ethernet-phy-id0022.1640", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1640"; reg = <7>; interrupts-extended = <&icu 16 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <1400>; txc-skew-psec = <1400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -176,6 +180,11 @@ phy1: ethernet-phy@7 { }; }; +&pcie_port0 { + clocks = <&pcie_refclk>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { clk { diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi new file mode 100644 index 000000000000..ab4950671c7c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for R9A08G046L48 SMARC SoM board. + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +/ { + compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046"; + + memory@48000000 { + device_type = "memory"; + /* First 128MiB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index d4a921bed4c3..e505161caa67 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -75,6 +75,12 @@ backlight: backlight { enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; }; + pcie_usb_refclk: clk-x7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + cvbs-in { compatible = "composite-video-connector"; label = "CVBS IN"; @@ -523,6 +529,13 @@ pca9654: gpio@20 { #gpio-cells = <2>; }; + pcie_usb_clk: clk@68 { + compatible = "renesas,9fgv0841"; + reg = <0x68>; + clocks = <&pcie_usb_refclk>; + #clock-cells = <1>; + }; + video-receiver@70 { compatible = "adi,adv7482"; reg = <0x70 0x71 0x72 0x73 0x74 0x75 @@ -640,17 +653,27 @@ &ohci1 { }; &pcie_bus_clk { - clock-frequency = <100000000>; + status = "disabled"; }; &pciec0 { + clocks = <&cpg CPG_MOD 319>, <&pcie_usb_clk 1>; status = "okay"; }; +&pciec0_rp { + clocks = <&pcie_usb_clk 3>; +}; + &pciec1 { + clocks = <&cpg CPG_MOD 318>, <&pcie_usb_clk 2>; status = "okay"; }; +&pciec1_rp { + clocks = <&pcie_usb_clk 4>; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; @@ -1038,11 +1061,12 @@ &usb3_peri0 { }; &usb3_phy0 { + clocks = <&cpg CPG_MOD 328>, <&pcie_usb_clk 6>, <&usb_extal_clk>; status = "okay"; }; &usb3s0_clk { - clock-frequency = <100000000>; + status = "disabled"; }; &vin0 { diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 2a157d1efb3d..97014bcfbb1d 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -351,20 +351,30 @@ &ohci0 { }; &pcie_bus_clk { - clock-frequency = <100000000>; + status = "disabled"; }; &pciec0 { + clocks = <&cpg CPG_MOD 319>, <&pcie_usb_clk 1>; status = "okay"; }; +&pciec0_rp { + clocks = <&pcie_usb_clk 3>; +}; + &pciec1 { + clocks = <&cpg CPG_MOD 318>, <&pcie_usb_clk 2>; status = "okay"; vpcie1v5-supply = <&pcie_1v5>; vpcie3v3-supply = <&pcie_3v3>; }; +&pciec1_rp { + clocks = <&pcie_usb_clk 4>; +}; + &pfc { can0_pins: can0 { groups = "can0_data_a"; @@ -475,6 +485,15 @@ &usb2_phy0 { status = "okay"; }; +&usb3_phy0 { + clocks = <&cpg CPG_MOD 328>, <&pcie_usb_clk 6>, <&usb_extal_clk>; + status = "okay"; +}; + +&usb3s0_clk { + status = "disabled"; +}; + &xhci0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 241caf737abb..67fd6a65db89 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -47,6 +47,12 @@ audio_clkout: audio-clkout { clock-frequency = <12288000>; }; + pcie_usb_refclk: clk-x24 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + hdmi0-out { compatible = "hdmi-connector"; type = "a"; @@ -232,6 +238,13 @@ &i2c4 { clock-frequency = <400000>; + pcie_usb_clk: clk@68 { + compatible = "renesas,9fgv0841"; + reg = <0x68>; + clocks = <&pcie_usb_refclk>; + #clock-cells = <1>; + }; + versaclock5: clock-generator@6a { compatible = "idt,5p49v5925"; reg = <0x6a>; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 4d384f153c13..cb55c6b70d0e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4-hd702e.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb @@ -104,6 +105,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-onething-edge-cube.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb @@ -116,6 +118,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb30.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rk2023.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133-pcb-13.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb @@ -150,7 +153,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233-pcb-12-11.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433-pcb-12-10.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-cm3j-rpi-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb @@ -164,6 +169,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb2-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-khadas-edge-2l.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb @@ -245,6 +252,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-video-demo.dtb px30-ringneck-haikou-haikou-video-demo-dtbs := px30-ringneck-haikou.dtb \ px30-ringneck-haikou-video-demo.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4-hd702e.dtb +rk3399-nanopc-t4-hd702e-dtbs := rk3399-nanopc-t4.dtb \ + rk3399-nanopc-t4-hd702e.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou-haikou-video-demo.dtb rk3368-lion-haikou-haikou-video-demo-dtbs := rk3368-lion-haikou.dtb \ rk3368-lion-haikou-video-demo.dtbo @@ -261,6 +272,18 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2-screen.dtb rk3399-rockpro64-v2-screen-dtbs := rk3399-rockpro64-v2.dtb \ rk3399-rockpro64-screen.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133-pcb-13.dtb +rk3566-qnap-ts133-pcb-13-dtbs := rk3566-qnap-ts133.dtb \ + rk3566-qnap-ts133-pcb-13.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233-pcb-12-11.dtb +rk3568-qnap-ts233-pcb-12-11-dtbs := rk3568-qnap-ts233.dtb \ + rk3568-qnap-ts233-pcb-12-11.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433-pcb-12-10.dtb +rk3568-qnap-ts433-pcb-12-10-dtbs := rk3568-qnap-ts433.dtb \ + rk3568-qnap-ts433-pcb-12-10.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-vz-2-uhd.dtb rk3568-wolfvision-pf5-vz-2-uhd-dtbs := rk3568-wolfvision-pf5.dtb \ rk3568-wolfvision-pf5-display-vz.dtbo \ diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts index 30bdb38f0727..e810ed146451 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts @@ -58,24 +58,6 @@ ir-receiver { gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; linux,rc-map-name = "rc-beelink-gs1"; }; - - spdif_dit: spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; - }; - - spdif_sound: spdif-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "SPDIF"; - - simple-audio-card,cpu { - sound-dai = <&spdif>; - }; - - simple-audio-card,codec { - sound-dai = <&spdif_dit>; - }; - }; }; &analog_sound { @@ -343,11 +325,6 @@ &sdmmc { status = "okay"; }; -&spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; -}; - &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts index f72b1518c14f..4eff0503928a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s-plus.dts @@ -29,20 +29,3 @@ &emmc { pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; status = "okay"; }; - -&gmac2io { - phy-handle = <&rtl8211e>; - tx_delay = <0x24>; - rx_delay = <0x18>; - - mdio { - rtl8211e: ethernet-phy@1 { - reg = <1>; - pinctrl-0 = <ð_phy_reset_pin>; - pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi index 4dcceb9136b7..49c68fe65de6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-base.dtsi @@ -2145,8 +2145,6 @@ edp: dp@ff970000 { interrupts = ; clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; clock-names = "dp", "pclk", "grf"; - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; power-domains = <&power RK3399_PD_EDP>; resets = <&cru SRST_P_EDP_CTRL>; reset-names = "dp"; @@ -2384,6 +2382,7 @@ cif_clkouta: cif-clkouta { }; edp { + /omit-if-no-ref/ edp_hpd: edp-hpd { rockchip,pins = <4 RK_PC7 2 &pcfg_pull_none>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 9d07353df52c..3f3cb0eb5809 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -241,6 +241,8 @@ &dmc { }; &edp { + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; status = "okay"; /* diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4-hd702e.dtso b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4-hd702e.dtso new file mode 100644 index 000000000000..766925b63571 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4-hd702e.dtso @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec HD702E LCD on NanoPC-T4 board + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + vdd_3_3v: regulator-vdd_3_3v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vdd_3.3v"; + vin-supply = <&vcc12v0_sys>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + enable-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 255>; + default-brightness-level = <200>; + num-interpolated-steps = <255>; + pinctrl-0 = <&bl_en>; + pinctrl-names = "default"; + }; +}; + +&edp { + force-hpd; + status = "okay"; + + aux-bus { + panel { + compatible = "friendlyarm,hd702e"; + backlight = <&backlight>; + no-hpd; + power-supply = <&vdd_3_3v>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; +}; + +&edp_out { + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&gpio1>; + interrupts = ; + irq-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int &touch_rst>; + pinctrl-names = "default"; + AVDD28-supply = <&vdd_3_3v>; + VDDIO-supply = <&vdd_3_3v>; + }; +}; + +&pinctrl { + backlight { + bl_en: bl-en { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + touch_int: touch-int { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index c8eb5481f43d..9e4fea84c4fb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -206,6 +206,8 @@ &gpu { }; &hdmi { + avdd-0v9-supply = <&vcca0v9_s3>; + avdd-1v8-supply = <&vcca1v8_s3>; ddc-i2c-bus = <&i2c7>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index ae937a3afa11..b5c05928142c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -401,8 +401,6 @@ &cpu_l3 { &edp { force-hpd; - pinctrl-names = "default"; - pinctrl-0 = <&edp_hpd>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts index a4ceafe6dd7a..80d6ea0eda84 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts @@ -141,6 +141,8 @@ sdio_pwrseq: sdio-pwrseq { }; &edp { + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index d402f2828814..806b8109f67d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -1190,6 +1190,53 @@ sdmmc: mmc@ffc30000 { status = "disabled"; }; + otp: efuse@ffce0000 { + compatible = "rockchip,rk3528-otp"; + reg = <0x0 0xffce0000 0x0 0x4000>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_SBPI_OTPC_NS>; + clock-names = "otp", "apb_pclk", "sbpi"; + resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_SBPI_OTPC_NS>; + reset-names = "otp", "apb", "sbpi"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + + otp_id: id@a { + reg = <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + + logic_leakage: logic-leakage@1b { + reg = <0x1b 0x1>; + }; + + gpu_leakage: gpu-leakage@1c { + reg = <0x1c 0x1>; + }; + + tsadc_trim: tsadc-trim@44 { + reg = <0x44 0x2>; + bits = <0 10>; + }; + }; + }; + dmac: dma-controller@ffd60000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xffd60000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts index 6a84db154a7d..387062eea520 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb2-v10.dts @@ -13,7 +13,7 @@ #include "rk3562.dtsi" / { - model = "Rockchip RK3562 EVB V20 Board"; + model = "Rockchip RK3562 EVB2 V10 Board"; compatible = "rockchip,rk3562-evb2-v10", "rockchip,rk3562"; chosen: chosen { diff --git a/arch/arm64/boot/dts/rockchip/rk3562.dtsi b/arch/arm64/boot/dts/rockchip/rk3562.dtsi index f84676b47b27..e4816aa3dae0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi @@ -1093,6 +1093,52 @@ sdmmc1: mmc@ff890000 { status = "disabled"; }; + otp: efuse@ff930000 { + compatible = "rockchip,rk3562-otp"; + reg = <0x0 0xff930000 0x0 0x4000>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>, <&cru CLK_SBPI_OTPC_NS>; + clock-names = "otp", "apb_pclk", "phy", "sbpi"; + resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_P_OTPPHY>, <&cru SRST_SBPI_OTPC_NS>; + reset-names = "otp", "apb", "phy", "sbpi"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + + otp_id: id@a { + reg = <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + + log_leakage: log-leakage@1b { + reg = <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x1>; + }; + + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x1>; + }; + }; + }; + dmac: dma-controller@ff990000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff990000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts b/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts index ed65d3120444..18a560a6e2a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-lckfb-tspi.dts @@ -635,10 +635,10 @@ &uart1 { status = "okay"; bluetooth: bluetooth { - compatible = "brcm,bcm43438-bt"; + compatible = "brcm,bcm43430a1-bt"; clocks = <&rk809 1>; clock-names = "lpo"; - max-speed = <3000000>; + max-speed = <1500000>; pinctrl-names = "default"; pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-onething-edge-cube.dts b/arch/arm64/boot/dts/rockchip/rk3566-onething-edge-cube.dts new file mode 100644 index 000000000000..b57bf7bf10f5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-onething-edge-cube.dts @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3566.dtsi" + +/ { + model = "OneThing Edge Cube (OEC)/OEC Turbo"; + compatible = "onething,edge-cube", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + rgb_led_b: led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rgb_led_b_enable_l>; + }; + + rgb_led_g: led-1 { + color = ; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rgb_led_g_enable_l>; + }; + + rgb_led_r: led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rgb_led_r_enable_l>; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v0_dcin: regulator-vcc12v0-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v0_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v0_dcin>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v0_dcin>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_cpu: regulator-vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 PWM_POLARITY_INVERTED>; + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + }; + + vdd_fixed: regulator-vdd-fixed { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_fixed"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + }; +}; + + +/* No hardware video output port */ +&display_subsystem { + status = "disabled"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + rgb_led_b_enable_l: rgb-led-b-enable-l { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + rgb_led_g_enable_l: rgb-led-g-enable-l { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + rgb_led_r_enable_l: rgb-led-r-enable-l { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_1v8>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index 791719acb9dd..071cbdc3f6d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -40,6 +40,25 @@ spk_amp: audio-amplifier { sound-name-prefix = "Speaker Amp"; }; + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <4000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <96000>; + voltage-max-design-microvolt = <4200000>; + voltage-min-design-microvolt = <3500000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4168000 100>, <4109000 95>, <4066000 90>, <4023000 85>, + <3985000 80>, <3954000 75>, <3924000 70>, <3897000 65>, + <3866000 60>, <3826000 55>, <3804000 50>, <3789000 45>, + <3777000 40>, <3770000 35>, <3763000 30>, <3750000 25>, + <3732000 20>, <3710000 15>, <3680000 10>, <3670000 5>, + <3500000 0>; + }; + dmic_codec: dmic-codec { compatible = "dmic-codec"; num-channels = <6>; @@ -215,6 +234,11 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -260,6 +284,13 @@ rk817: pmic@20 { vcc8-supply = <&vcc_sys>; vcc9-supply = <&dcdc_boost>; + charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <150000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + regulators { vdd_logic: DCDC_REG1 { regulator-name = "vdd_logic"; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133-pcb-13.dtso b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133-pcb-13.dtso new file mode 100644 index 000000000000..f9a8194f5753 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133-pcb-13.dtso @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree overlay for TS133 board PCB-13 revision. + * + * Copyright (C) 2025 Heiko Stuebner + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + /* + * The default hardware-state of this gpio causes the drive + * to be already running when entering the kernel. + * regulator-boot-on is needed to prevent one additional + * power-cycle on the drive. + * + * With regulator-boot-on we get the expected 1 cycle + * per boot, without it we end up with 2 cycles as seen + * via smartctl. + */ + hdd1_pwr: regulator-hdd1-power { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdd1_power_pin>; + regulator-name = "hdd1-power"; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; +}; + +&gpio2 { + hdd1-present-hog { + gpios = ; + gpio-hog; + input; + line-name = "hdd1-present"; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hdd1_present_pin>; + + hdd-power { + hdd1_power_pin: hdd1-power-pin { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdd-present { + hdd1_present_pin: hdd1-present-pin { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata2_port0 { + target-supply = <&hdd1_pwr>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts b/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts index 6ac1fe0d3c98..8d906ab02c5f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts @@ -354,6 +354,7 @@ sound { compatible = "simple-audio-card"; pinctrl-0 = <&hp_det>; pinctrl-names = "default"; + simple-audio-card,aux-devs = <&aw87391_pa_l>, <&aw87391_pa_r>; simple-audio-card,format = "i2s"; simple-audio-card,hp-det-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; simple-audio-card,mclk-fs = <256>; @@ -363,8 +364,10 @@ sound { "MICL", "Mic Jack", "Headphones", "HPOL", "Headphones", "HPOR", - "Internal Speakers", "HPOL", - "Internal Speakers", "HPOR"; + "Internal Speakers", "Left Amp OUT", + "Internal Speakers", "Right Amp OUT", + "Left Amp IN", "HPOL", + "Right Amp IN", "HPOR"; simple-audio-card,widgets = "Microphone", "Mic Jack", "Headphone", "Headphones", @@ -468,6 +471,18 @@ vcc_wifi: regulator-vcc-wifi { regulator-max-microvolt = <3300000>; regulator-name = "vcc_wifi"; }; + + vdd_amp: regulator-vcc-amp { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vdd_amp_h>; + pinctrl-names = "default"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vccio_acodec>; + regulator-name = "vdd_amp"; + }; }; &cpu0 { @@ -840,8 +855,22 @@ &i2c2 { pinctrl-names = "default"; status = "okay"; - /* awinic,aw87391 at 0x58 */ - /* awinic,aw87391 at 0x5b */ + aw87391_pa_l: audio-codec@58 { + compatible = "anbernic,rgds-amp", "awinic,aw87391"; + reg = <0x58>; + vdd-supply = <&vdd_amp>; + #sound-dai-cells = <0>; + sound-name-prefix = "Left Amp"; + }; + + aw87391_pa_r: audio-codec@5b { + compatible = "anbernic,rgds-amp", "awinic,aw87391"; + reg = <0x5b>; + vdd-supply = <&vdd_amp>; + #sound-dai-cells = <0>; + sound-name-prefix = "Right Amp"; + }; + /* invensense,icm42607p at 0x68 */ }; @@ -1014,6 +1043,13 @@ touch1_irq: touch1-irq { }; }; + vdd-amp { + vdd_amp_h: vdd-amp-h { + rockchip,pins = + <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc-lcd { vdd_lcd0_h: vdd-lcd0-h { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233-pcb-12-11.dtso b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233-pcb-12-11.dtso new file mode 100644 index 000000000000..c7987171644c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233-pcb-12-11.dtso @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree overlay for TS233 board PCBs-12-11 revision. + * + * Copyright (C) 2025 Heiko Stuebner + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + /* + * The default hardware-state of this gpio causes the drive + * to be already running when entering the kernel. + * regulator-boot-on is needed to prevent one additional + * power-cycle on the drive. + * + * With regulator-boot-on we get the expected 1 cycle + * per boot, without it we end up with 2 cycles as seen + * via smartctl. + */ + hdd1_pwr: regulator-hdd1-power { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdd1_power_pin>; + regulator-name = "hdd1-power"; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; + + hdd2_pwr: regulator-hdd2-power { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdd2_power_pin>; + regulator-name = "hdd2-power"; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; +}; + +&gpio2 { + hdd1-present-hog { + gpios = ; + gpio-hog; + input; + line-name = "hdd1-present"; + }; + + hdd2-present-hog { + gpios = ; + gpio-hog; + input; + line-name = "hdd2-present"; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hdd1_present_pin &hdd2_present_pin>; + + hdd-power { + hdd1_power_pin: hdd1-power-pin { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd2_power_pin: hdd2-power-pin { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdd-present { + hdd1_present_pin: hdd1-present-pin { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd2_present_pin: hdd2-present-pin { + rockchip,pins = <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata1_port0 { + target-supply = <&hdd2_pwr>; +}; + +&sata2_port0 { + target-supply = <&hdd1_pwr>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso new file mode 100644 index 000000000000..ce0fdc9f2989 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433-pcb-12-10.dtso @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device tree overlay for TS433 board PCBs-12-10 revision. + * + * Copyright (C) 2025 Heiko Stuebner + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + /* + * The default hardware-state of this gpio causes the drive + * to be already running when entering the kernel. + * regulator-boot-on is needed to prevent one additional + * power-cycle on the drive. + * + * With regulator-boot-on we get the expected 1 cycle + * per boot, without it we end up with 2 cycles as seen + * via smartctl. + */ + hdd1_pwr: regulator-hdd1-power { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdd1_power_pin>; + regulator-name = "hdd1-power"; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; + + hdd2_pwr: regulator-hdd2-power { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdd2_power_pin>; + regulator-name = "hdd2-power"; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; + + /* + * HDD3+4 are connected to ports of the PCIe SATA controller. + * Currently there is no way to attach those, so keep them + * always on. + */ + hdd3_pwr: regulator-hdd3-power { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdd3_power_pin>; + regulator-name = "hdd3-power"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; + + hdd4_pwr: regulator-hdd4-power { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdd4_power_pin>; + regulator-name = "hdd4-power"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; +}; + +&gpio2 { + hdd1-present-hog { + gpios = ; + gpio-hog; + input; + line-name = "hdd1-present"; + }; + + hdd2-present-hog { + gpios = ; + gpio-hog; + input; + line-name = "hdd2-present"; + }; + + hdd3-present-hog { + gpios = ; + gpio-hog; + input; + line-name = "hdd3-present"; + }; + + hdd4-present-hog { + gpios = ; + gpio-hog; + input; + line-name = "hdd4-present"; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hdd1_present_pin &hdd2_present_pin &hdd3_present_pin + &hdd4_present_pin>; + + hdd-power { + hdd1_power_pin: hdd1-power-pin { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd2_power_pin: hdd2-power-pin { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd3_power_pin: hdd3-power-pin { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hdd4_power_pin: hdd4-power-pin { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdd-present { + hdd1_present_pin: hdd1-present-pin { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd2_present_pin: hdd2-present-pin { + rockchip,pins = <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd3_present_pin: hdd3-present-pin { + rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hdd4_present_pin: hdd4-present-pin { + rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sata1_port0 { + target-supply = <&hdd2_pwr>; +}; + +&sata2_port0 { + target-supply = <&hdd1_pwr>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso b/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso index 048933de2943..8cfce71dd318 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3568-wolfvision-pf5-io-expander.dtso @@ -11,6 +11,7 @@ #include #include #include +#include #include &{/} { @@ -134,3 +135,22 @@ &usb2phy0_host { phy-supply = <&usb_host_vbus>; status = "okay"; }; + +&vicap { + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>; + status = "okay"; +}; + +&vicap_dvp { + vicap_dvp_input: endpoint { + bus-type = ; + bus-width = <16>; + pclk-sample = ; + rockchip,dvp-clk-delay = <10>; + }; +}; + +&vicap_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 658097ed6971..3bc653f027f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -155,9 +155,11 @@ pcie3x1: pcie@fe270000 { bus-range = <0x10 0x1f>; clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, - <&cru CLK_PCIE30X1_AUX_NDFT>; + <&cru CLK_PCIE30X1_AUX_NDFT>, + <&cru CLK_PCIE30X1_PIPE_DFT>; clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type = "pci"; interrupts = , , @@ -208,9 +210,11 @@ pcie3x2: pcie@fe280000 { bus-range = <0x20 0x2f>; clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, - <&cru CLK_PCIE30X2_AUX_NDFT>; + <&cru CLK_PCIE30X2_AUX_NDFT>, + <&cru CLK_PCIE30X2_PIPE_DFT>; clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type = "pci"; interrupts = , , diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index a2c4957a5899..64bdd8b7754b 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. */ +#include #include #include #include @@ -221,11 +222,20 @@ sata1: sata@fc400000 { <&cru CLK_SATA1_RXOOB>; clock-names = "sata", "pmalive", "rxoob"; interrupts = ; - phys = <&combphy1 PHY_TYPE_SATA>; - phy-names = "sata-phy"; ports-implemented = <0x1>; power-domains = <&power RK3568_PD_PIPE>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; + + sata1_port0: sata-port@0 { + reg = <0>; + hba-port-cap = ; + phys = <&combphy1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; }; sata2: sata@fc800000 { @@ -235,11 +245,20 @@ sata2: sata@fc800000 { <&cru CLK_SATA2_RXOOB>; clock-names = "sata", "pmalive", "rxoob"; interrupts = ; - phys = <&combphy2 PHY_TYPE_SATA>; - phy-names = "sata-phy"; ports-implemented = <0x1>; power-domains = <&power RK3568_PD_PIPE>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; + + sata2_port0: sata-port@0 { + reg = <0>; + hba-port-cap = ; + phys = <&combphy2 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; }; usb_host0_xhci: usb@fcc00000 { @@ -1001,9 +1020,11 @@ pcie2x1: pcie@fe260000 { bus-range = <0x0 0xf>; clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, - <&cru CLK_PCIE20_AUX_NDFT>; + <&cru CLK_PCIE20_AUX_NDFT>, + <&cru CLK_PCIE20_PIPE_DFT>; clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", "aux"; + "aclk_dbi", "pclk", "aux", + "pipe"; device_type = "pci"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; @@ -1104,6 +1125,52 @@ rng: rng@fe388000 { status = "disabled"; }; + otp: efuse@fe38c000 { + compatible = "rockchip,rk3568-otp"; + reg = <0x0 0xfe38c000 0x0 0x4000>; + clocks = <&cru CLK_OTPC_NS_USR>, <&cru PCLK_OTPC_NS>, + <&cru PCLK_OTPPHY>, <&cru CLK_OTPC_NS_SBPI>; + clock-names = "otp", "apb_pclk", "phy", "sbpi"; + resets = <&cru SRST_OTPC_NS_USR>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPPHY>, <&cru SRST_OTPC_NS_SBPI>; + reset-names = "otp", "apb", "phy", "sbpi"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + + otp_id: id@a { + reg = <0x0a 0x10>; + }; + + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + + log_leakage: log-leakage@1b { + reg = <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x1>; + }; + + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x1>; + }; + }; + }; + i2s0_8ch: i2s@fe400000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x0 0xfe400000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index d372ba252af8..1c100ffd1518 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -21,6 +21,8 @@ / { aliases { ethernet0 = &gmac0; ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; }; chosen { diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index f5746bc2970b..fb0dd1bc5148 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -270,6 +270,7 @@ sound { simple-audio-card,frame-master = <&masterdai>; simple-audio-card,hp-det-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; simple-audio-card,mclk-fs = <256>; + simple-audio-card,pin-switches = "Headphones", "Speaker", "Main Mic", "Headset Mic"; simple-audio-card,routing = "Headphone Power INL", "LOUT1", "Headphone Power INR", "ROUT1", diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts new file mode 100644 index 000000000000..98d5d00d63b5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts @@ -0,0 +1,1071 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model = "Rockchip RK3576 EVB2 V10 Board"; + compatible = "rockchip,rk3576-evb2-v10", "rockchip,rk3576"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + dp-con { + compatible = "dp-connector"; + dp-pwr-supply = <&vcc3v3_dp_port>; + label = "DP OUT"; + type = "full-size"; + + port { + dp0_con_in: endpoint { + remote-endpoint = <&dp0_out_con>; + }; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-back { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + + button-menu { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + button-vol-down { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + button-vol-up { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + work_led: led-0 { + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwren>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + vbus5v0_usb0: regulator-vbus5v0-usb0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb3_host0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren>; + }; + + vbus5v0_usb1: regulator-vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb3_host1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_sys>; + }; + + vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc3v3_dp_port: regulator-vcc3v3-dp-port { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_dp_port"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s3>; + pinctrl-names = "default"; + pinctrl-0 = <&image_pwren>; + }; + + vcc3v3_pcie1: regulator-vcc3v3-pcie1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_sata_pwren: vcc3v3-sata-pwren { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_satapm"; + enable-active-high; + gpio = <&gpio4 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&satapm_pwren>; + }; + + vcc3v3_sd: regulator-vcc-3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s0>; + }; + + vcc5v0_device: regulator-vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_sys>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&dp { + pinctrl-0 = <&dpm0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp0_in { + dp0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dp0>; + }; +}; + +&dp0_out { + dp0_out_con: endpoint { + remote-endpoint = <&dp0_con_in>; + }; +}; + +&gmac0 { + clock_in_out = "output"; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <ð0m1_miim + ð0m1_tx_bus2 + ð0m1_rx_bus2 + ð0m1_rgmii_clk + ð0m1_rgmii_bus>; + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <ð1m0_miim + ð1m0_tx_bus2 + ð1m0_rx_bus2 + ð1m0_rgmii_clk + ð1m0_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk806: pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + wakeup-source; + #clock-cells = <0>; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dp { + image_pwren: image-pwren { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + network { + rgmii_phy0_rst: rgmii-phy0-rst { + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + rgmii_phy1_rst: rgmii-phy1-rst { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie1 { + pcie1_rst: pcie1-rst { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sata { + satapm_pwren: satapm-pwren { + rockchip,pins = <4 RK_PC7 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + sdmmc { + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_hub_reset: usb-hub-reset { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake: wifi-host-wake { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_pwren: wifi-pwren { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sai6 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&sata0 { + target-supply = <&vcc3v3_sata_pwren>; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1m0_bus4 &sdmmc1m0_clk &sdmmc1m0_cmd>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; +}; + +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_usb0>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vbus5v0_usb1>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn &uart4m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + +&ufshc { + vcc-supply = <&vcc_ufs_s0>; + vccq-supply = <&vcc1v2_ufs_vccq_s0>; + vccq2-supply = <&vcc1v8_ufs_vccq2_s0>; + status = "okay"; +}; + +&usbdp_phy { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_hub_reset>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb1a86,8091"; + reg = <1>; + reset-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + v5-supply = <&vcc_3v3_s0>; + vdd33-supply = <&vcc_3v3_s0>; + }; +}; + +&vop { + /* + * If no dedicated PLL was specified, the GPLL would be automatically + * assigned as the PLL source for dclk_vp1_src. As the frequency of GPLL + * is 1188 MHz, we can only get typical clock frequencies such as + * 74.25MHz, 148.5MHz, 297MHz, 594MHz. + * + * So here we set the parent clock of VP1 to VPLL so that we can get + * any frequency. + */ + assigned-clocks = <&cru DCLK_VP1_SRC>; + assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dp0: endpoint@a { + reg = ; + remote-endpoint = <&dp0_in_vp1>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts new file mode 100644 index 000000000000..68630379af63 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3576.dtsi" + +/ { + model = "Khadas Edge-2L"; + compatible = "khadas,edge-2l", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 49ccdf12ef7e..28175d8200d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1379,6 +1379,19 @@ vop_mmu: iommu@27d07e00 { status = "disabled"; }; + spdif_tx2: spdif-tx@27d20000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x27d20000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX2>, <&cru HCLK_SPDIF_TX2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 28>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sai5: sai@27d40000 { compatible = "rockchip,rk3576-sai"; reg = <0x0 0x27d40000 0x0 0x1000>; @@ -1483,6 +1496,73 @@ hdmi_out: port@1 { }; }; + dp: dp@27e40000 { + compatible = "rockchip,rk3576-dp"; + reg = <0x0 0x27e40000 0x0 0x30000>; + interrupts = ; + assigned-clocks = <&cru CLK_AUX16MHZ_0>; + assigned-clock-rates = <16000000>; + clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16MHZ_0>, + <&cru ACLK_DP0>; + clock-names = "apb", "aux", "hdcp"; + resets = <&cru SRST_DP0>; + phys = <&usbdp_phy PHY_TYPE_DP>; + power-domains = <&power RK3576_PD_VO1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp0_in: port@0 { + reg = <0>; + }; + + dp0_out: port@1 { + reg = <1>; + }; + }; + }; + + spdif_tx3: spdif-tx@27ea0000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x27ea0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX3>, <&cru HCLK_SPDIF_TX3>; + clock-names = "mclk", "hclk"; + dmas = <&dmac2 29>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx4: spdif-tx@27eb0000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x27eb0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX4>, <&cru HCLK_SPDIF_TX4>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 6>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx5: spdif-tx@27ec0000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x27ec0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX5>, <&cru HCLK_SPDIF_TX5>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 25>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sai7: sai@27ed0000 { compatible = "rockchip,rk3576-sai"; reg = <0x0 0x27ed0000 0x0 0x1000>; @@ -1868,8 +1948,9 @@ ufshc: ufshc@2a2d0000 { pinctrl-0 = <&ufs_refclk &ufs_rstgpio>; pinctrl-names = "default"; resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, - <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; - reset-names = "biu", "sys", "ufs", "grf"; + <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>, + <&cru SRST_MPHY_INIT>; + reset-names = "biu", "sys", "ufs", "grf", "mphy"; reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -2138,6 +2219,36 @@ &sai4m0_sdi status = "disabled"; }; + spdif_tx0: spdif-tx@2a670000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x2a670000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX0>, <&cru HCLK_SPDIF_TX0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 5>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@2a680000 { + compatible = "rockchip,rk3576-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0x2a680000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIF_TX1>, <&cru HCLK_SPDIF_TX1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 5>; + dma-names = "tx"; + power-domains = <&power RK3576_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@2a701000 { compatible = "arm,gic-400"; reg = <0x0 0x2a701000 0 0x10000>, diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 7fe9593d8c19..4fb8888c281c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -907,7 +907,7 @@ power-domain@RK3588_PD_VCODEC { #size-cells = <0>; #power-domain-cells = <0>; - power-domain@RK3588_PD_RKVDEC0 { + pd_rkvdec0: power-domain@RK3588_PD_RKVDEC0 { reg = ; clocks = <&cru HCLK_RKVDEC0>, <&cru HCLK_VDPU_ROOT>, @@ -917,7 +917,7 @@ power-domain@RK3588_PD_RKVDEC0 { pm_qos = <&qos_rkvdec0>; #power-domain-cells = <0>; }; - power-domain@RK3588_PD_RKVDEC1 { + pd_rkvdec1: power-domain@RK3588_PD_RKVDEC1 { reg = ; clocks = <&cru HCLK_RKVDEC1>, <&cru HCLK_VDPU_ROOT>, @@ -926,7 +926,7 @@ power-domain@RK3588_PD_RKVDEC1 { pm_qos = <&qos_rkvdec1>; #power-domain-cells = <0>; }; - power-domain@RK3588_PD_VENC0 { + pd_venc0: power-domain@RK3588_PD_VENC0 { reg = ; clocks = <&cru HCLK_RKVENC0>, <&cru ACLK_RKVENC0>; @@ -937,7 +937,7 @@ power-domain@RK3588_PD_VENC0 { #size-cells = <0>; #power-domain-cells = <0>; - power-domain@RK3588_PD_VENC1 { + pd_venc1: power-domain@RK3588_PD_VENC1 { reg = ; clocks = <&cru HCLK_RKVENC1>, <&cru HCLK_RKVENC0>, diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index c9d284cb738b..09bc7b68dcc0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -568,6 +568,22 @@ &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; +&pd_rkvdec0 { + domain-supply = <&vdd_vdenc_s0>; +}; + +&pd_rkvdec1 { + domain-supply = <&vdd_vdenc_s0>; +}; + +&pd_venc0 { + domain-supply = <&vdd_vdenc_s0>; +}; + +&pd_venc1 { + domain-supply = <&vdd_vdenc_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 952affaf455c..5f5d89a33a4a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -86,25 +86,16 @@ led-1 { }; }; - /* - * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE - * clock generator. - * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. - */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible = "fixed-clock"; + /* 100MHz PCIe reference clock from PI6C557-05BLE */ + pcie_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible = "gpio-gate-clock"; - clocks = <&pcie_refclk_gen>; - #clock-cells = <0>; + clock-output-names = "pcie-refclk-clock"; enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */ pinctrl-names = "default"; pinctrl-0 = <&pcie30x4_clkreqn_m0>; + vdd-supply = <&vcca_3v3_s0>; }; pps { @@ -588,7 +579,7 @@ led1_pin: led1-pin { pcie30x4 { pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; }; pcie30x4_perstn_m0: pcie30x4-perstn-m0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 90e7fe254491..84b6b53f016a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "rk3588.dtsi" @@ -89,6 +90,14 @@ usr_led: led-1 { }; }; + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 35 64 100 150 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + sound { compatible = "simple-audio-card"; pinctrl-names = "default"; @@ -590,6 +599,36 @@ &i2s6_8ch { status = "okay"; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_warm: package-warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_hot: package-hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&package_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l0 { reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc_3v3_pcie20>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index de154adb1497..f7dd01d6fa0a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -367,6 +367,18 @@ &hdmi1_sound { status = "okay"; }; +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>; + pinctrl-names = "default"; + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &hdptxphy1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index b3e76ad2d869..bf4a1d2e55ca 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -468,7 +468,8 @@ map1 { &pcie2x1l0 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_0_rst>; + pinctrl-0 = <&pcie2_0_rst>, <&pcie30x1m1_0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; status = "okay"; @@ -476,7 +477,8 @@ &pcie2x1l0 { &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie2_2_rst>, <&pcie20x1m0_clkreqn>; + supports-clkreq; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 27269b7b08aa..a0e97481afb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -47,23 +47,16 @@ led-1 { }; }; - /* - * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE - * clock generator. - * The clock output is gated via the OE pin on the clock generator. - * This is modeled as a fixed-clock plus a gpio-gate-clock. - */ - pcie_refclk_gen: pcie-refclk-gen-clock { - compatible = "fixed-clock"; + /* 100MHz PCIe reference clock from PI6C557-05BLE */ + pcie_refclk: pcie-clock-generator { + compatible = "gated-fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; - }; - - pcie_refclk: pcie-refclk-clock { - compatible = "gpio-gate-clock"; - clocks = <&pcie_refclk_gen>; - #clock-cells = <0>; + clock-output-names = "pcie-refclk-clock"; enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1_l>; + vdd-supply = <&vcca_3v3_s0>; }; vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { @@ -362,6 +355,12 @@ module_led_pin: module-led-pin { }; }; + pcie30x4 { + pcie30x4_clkreqn_m1_l: pcie30x4-clkreqn-m1-l { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb3 { usb3_id: usb3-id { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts index f82050597ab3..d6b62cd1b90b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts @@ -381,6 +381,22 @@ &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; +&pd_rkvdec0 { + domain-supply = <&vdd_vdenc_s0>; +}; + +&pd_rkvdec1 { + domain-supply = <&vdd_vdenc_s0>; +}; + +&pd_venc0 { + domain-supply = <&vdd_vdenc_s0>; +}; + +&pd_venc1 { + domain-supply = <&vdd_vdenc_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index e8ad525ba3f9..89618394c0bf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -60,8 +60,8 @@ axis@0 { reg = <0>; abs-flat = <40>; abs-fuzz = <30>; - abs-range = <0 4095>; - linux,code = ; + abs-range = <4095 0>; + linux,code = ; }; axis@1 { @@ -69,7 +69,7 @@ axis@1 { abs-flat = <40>; abs-fuzz = <30>; abs-range = <0 4095>; - linux,code = ; + linux,code = ; }; axis@2 { @@ -77,7 +77,7 @@ axis@2 { abs-flat = <40>; abs-fuzz = <30>; abs-range = <0 4095>; - linux,code = ; + linux,code = ; }; axis@3 { @@ -85,7 +85,7 @@ axis@3 { abs-flat = <40>; abs-fuzz = <30>; abs-range = <0 4095>; - linux,code = ; + linux,code = ; }; }; @@ -318,7 +318,7 @@ pwm_fan: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; cooling-levels = <0 120 150 180 210 240 255>; - fan-supply = <&vcc5v0_sys>; + fan-supply = <&vcc5v0_spk>; interrupt-parent = <&gpio4>; interrupts = ; pulses-per-revolution = <4>; diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi index cd078a16065e..4bfd58b26b51 100644 --- a/arch/arm64/boot/dts/st/stm32mp211.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi @@ -112,6 +112,22 @@ usart2: serial@400e0000 { }; }; + bsec: efuse@44000000 { + compatible = "st,stm32mp25-bsec"; + reg = <0x44000000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp@24 { + reg = <0x24 0x4>; + }; + + package_otp@1e8 { + reg = <0x1e8 0x1>; + bits = <0 3>; + }; + }; + syscfg: syscon@44230000 { compatible = "st,stm32mp21-syscfg", "syscon"; reg = <0x44230000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts index 7bdaeaa5ab0f..a1285abc80ca 100644 --- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts @@ -44,6 +44,10 @@ &arm_wdt { status = "okay"; }; +&bsec { + bootph-all; +}; + &usart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index b5d81d1ee153..9e1d240888ff 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -45,6 +45,12 @@ clk_dsi_txbyte: clock-0 { clock-frequency = <0>; }; + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; + clk_rcbsec: clk-64000000 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -354,7 +360,7 @@ i2c1: i2c@40120000 { #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C1>; resets = <&rcc I2C1_R>; dmas = <&hpdma 27 0x20 0x3012>, @@ -363,6 +369,7 @@ i2c1: i2c@40120000 { access-controllers = <&rifsc 41>; power-domains = <&cluster_pd>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -372,7 +379,7 @@ i2c2: i2c@40130000 { #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C2>; resets = <&rcc I2C2_R>; dmas = <&hpdma 30 0x20 0x3012>, @@ -381,6 +388,7 @@ i2c2: i2c@40130000 { access-controllers = <&rifsc 42>; power-domains = <&cluster_pd>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -390,7 +398,7 @@ i2c7: i2c@40180000 { #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C7>; resets = <&rcc I2C7_R>; dmas = <&hpdma 45 0x20 0x3012>, @@ -399,6 +407,7 @@ i2c7: i2c@40180000 { access-controllers = <&rifsc 47>; power-domains = <&cluster_pd>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -668,7 +677,7 @@ i2c8: i2c@46040000 { #address-cells = <1>; #size-cells = <0>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti2 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C8>; resets = <&rcc I2C8_R>; dmas = <&hpdma 168 0x20 0x3012>, @@ -677,6 +686,7 @@ i2c8: i2c@46040000 { access-controllers = <&rifsc 48>; power-domains = <&cluster_pd>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -970,6 +980,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible = "st,stm32mp23-syscfg", "syscon"; reg = <0x44230000 0x10000>; + #clock-cells = <0>; }; pinctrl: pinctrl@44240000 { @@ -1193,6 +1204,18 @@ exti2: interrupt-controller@46230000 { <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ }; + ltdc: display-controller@48010000 { + compatible = "st,stm32mp251-ltdc"; + reg = <0x48010000 0x400>; + interrupts = , + ; + clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; + clock-names = "lcd", "bus"; + resets = <&rcc LTDC_R>; + access-controllers = <&rifsc 80>; + status = "disabled"; + }; + intc: interrupt-controller@4ac10000 { compatible = "arm,gic-400"; reg = <0x4ac10000 0x1000>, diff --git a/arch/arm64/boot/dts/st/stm32mp235.dtsi b/arch/arm64/boot/dts/st/stm32mp235.dtsi index 2719c088dd59..7a87c344a4fe 100644 --- a/arch/arm64/boot/dts/st/stm32mp235.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp235.dtsi @@ -5,7 +5,25 @@ */ #include "stm32mp233.dtsi" +<dc { + compatible = "st,stm32mp255-ltdc"; + clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; + clock-names = "lcd", "bus", "ref", "lvds"; +}; + &rifsc { + lvds: lvds@48060000 { + compatible = "st,stm32mp255-lvds", "st,stm32mp25-lvds"; + reg = <0x48060000 0x2000>; + #clock-cells = <0>; + clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names = "pclk", "ref"; + resets = <&rcc LVDS_R>; + access-controllers = <&rifsc 84>; + power-domains = <&cluster_pd>; + status = "disabled"; + }; + vdec: vdec@480d0000 { compatible = "st,stm32mp25-vdec"; reg = <0x480d0000 0x3c8>; diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index 5ecc5ef61590..dd4efbe5a46e 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -77,6 +77,42 @@ u-boot { }; }; + panel_lvds: display { + compatible = "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + backlight = <&panel_lvds_backlight>; + power-supply = <&scmi_v3v3>; + width-mm = <156>; + height-mm = <92>; + data-mapping = "vesa-24"; + status = "okay"; + + panel-timing { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hback-porch = <150>; + hsync-len = <21>; + vfront-porch = <24>; + vback-porch = <24>; + vsync-len = <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -117,11 +153,105 @@ phy1_eth1: ethernet-phy@1 { }; }; +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_b>; + pinctrl-1 = <&i2c2_sleep_pins_b>; + i2c-scl-rising-time-ns = <108>; + i2c-scl-falling-time-ns = <12>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + ili2511: ili2511@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpioi 0 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <100000>; + status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +<dc { + status = "okay"; + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&lvds_in>; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + lvds_out0: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; + scmi_vddcore: regulator@11 { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg = ; + regulator-name = "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; + scmi_v5v_hdmi: regulator@21 { + reg = ; + regulator-name = "v5v_hdmi"; + }; + scmi_v5v_vconn: regulator@22 { + reg = ; + regulator-name = "v5v_vconn"; + }; scmi_vdd_sdcard: regulator@23 { reg = ; regulator-name = "vdd_sdcard"; diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index c34cd33cd855..456ece7f8ebc 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,7 @@ #include &pinctrl { + /omit-if-no-ref/ eth1_mdio_pins_a: eth1-mdio-0 { pins1 { pinmux = ; /* ETH_MDC */ @@ -21,6 +22,7 @@ pins2 { }; }; + /omit-if-no-ref/ eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 { pins1 { pinmux = , /* ETH_MDC */ @@ -28,6 +30,7 @@ pins1 { }; }; + /omit-if-no-ref/ eth1_rgmii_pins_a: eth1-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -62,6 +65,7 @@ pins4 { }; }; + /omit-if-no-ref/ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { pins { pinmux = , /* ETH_RGMII_TXD0 */ @@ -80,6 +84,7 @@ pins { }; }; + /omit-if-no-ref/ eth1_rgmii_pins_b: eth1-rgmii-1 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -114,6 +119,7 @@ pins4 { }; }; + /omit-if-no-ref/ eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 { pins { pinmux = , /* ETH_RGMII_TXD0 */ @@ -134,6 +140,7 @@ pins { }; }; + /omit-if-no-ref/ eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -175,6 +182,7 @@ pins5 { }; }; + /omit-if-no-ref/ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { pins { pinmux = , /* ETH_RGMII_TXD0 */ @@ -195,6 +203,7 @@ pins { }; }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { pinmux = , /* I2C2_SCL */ @@ -205,6 +214,7 @@ pins { }; }; + /omit-if-no-ref/ i2c2_sleep_pins_a: i2c2-sleep-0 { pins { pinmux = , /* I2C2_SCL */ @@ -212,6 +222,26 @@ pins { }; }; + /omit-if-no-ref/ + i2c2_pins_b: i2c2-1 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c2_sleep_pins_b: i2c2-sleep-1 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { pinmux = ; /* OSPI1_CLK */ @@ -221,12 +251,14 @@ pins { }; }; + /omit-if-no-ref/ ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 { pins { pinmux = ; /* OSPI1_CLK */ }; }; + /omit-if-no-ref/ ospi_port1_cs0_pins_a: ospi-port1-cs0-0 { pins { pinmux = ; /* OSPI_NCS0 */ @@ -236,12 +268,14 @@ pins { }; }; + /omit-if-no-ref/ ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 { pins { pinmux = ; /* OSPI_NCS0 */ }; }; + /omit-if-no-ref/ ospi_port1_io03_pins_a: ospi-port1-io03-0 { pins { pinmux = , /* OSPI_IO0 */ @@ -254,6 +288,7 @@ pins { }; }; + /omit-if-no-ref/ ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 { pins { pinmux = , /* OSPI_IO0 */ @@ -263,6 +298,7 @@ pins { }; }; + /omit-if-no-ref/ pcie_pins_a: pcie-0 { pins { pinmux = ; @@ -270,6 +306,7 @@ pins { }; }; + /omit-if-no-ref/ pcie_init_pins_a: pcie-init-0 { pins { pinmux = ; @@ -277,12 +314,14 @@ pins { }; }; + /omit-if-no-ref/ pcie_sleep_pins_a: pcie-sleep-0 { pins { pinmux = ; }; }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { pinmux = ; /* TIM3_CH2 */ @@ -292,12 +331,14 @@ pins { }; }; + /omit-if-no-ref/ pwm3_sleep_pins_a: pwm3-sleep-0 { pins { pinmux = ; /* TIM3_CH2 */ }; }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { pinmux = , /* TIM8_CH1 */ @@ -308,6 +349,7 @@ pins { }; }; + /omit-if-no-ref/ pwm8_sleep_pins_a: pwm8-sleep-0 { pins { pinmux = , /* TIM8_CH1 */ @@ -315,6 +357,7 @@ pins { }; }; + /omit-if-no-ref/ pwm12_pins_a: pwm12-0 { pins { pinmux = ; /* TIM12_CH2 */ @@ -324,12 +367,14 @@ pins { }; }; + /omit-if-no-ref/ pwm12_sleep_pins_a: pwm12-sleep-0 { pins { pinmux = ; /* TIM12_CH2 */ }; }; + /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -349,6 +394,7 @@ pins2 { }; }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -373,6 +419,7 @@ pins3 { }; }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -384,6 +431,7 @@ pins { }; }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { pinmux = , /* SPI3_SCK */ @@ -398,6 +446,7 @@ pins2 { }; }; + /omit-if-no-ref/ spi3_sleep_pins_a: spi3-sleep-0 { pins1 { pinmux = , /* SPI3_SCK */ @@ -406,6 +455,7 @@ pins1 { }; }; + /omit-if-no-ref/ tim10_counter_pins_a: tim10-counter-0 { pins { pinmux = ; /* TIM10_CH1 */ @@ -413,6 +463,7 @@ pins { }; }; + /omit-if-no-ref/ tim10_counter_sleep_pins_a: tim10-counter-sleep-0 { pins { pinmux = ; /* TIM10_CH1 */ @@ -420,6 +471,7 @@ pins { }; }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { pinmux = ; /* USART2_TX */ @@ -433,6 +485,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart2_idle_pins_a: usart2-idle-0 { pins1 { pinmux = ; /* USART2_TX */ @@ -443,6 +496,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart2_sleep_pins_a: usart2-sleep-0 { pins { pinmux = , /* USART2_TX */ @@ -450,6 +504,7 @@ pins { }; }; + /omit-if-no-ref/ usart6_pins_a: usart6-0 { pins1 { pinmux = , /* USART6_TX */ @@ -465,6 +520,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart6_idle_pins_a: usart6-idle-0 { pins1 { pinmux = , /* USART6_TX */ @@ -482,6 +538,7 @@ pins3 { }; }; + /omit-if-no-ref/ usart6_sleep_pins_a: usart6-sleep-0 { pins { pinmux = , /* USART6_TX */ @@ -493,6 +550,7 @@ pins { }; &pinctrl_z { + /omit-if-no-ref/ i2c8_pins_a: i2c8-0 { pins { pinmux = , /* I2C8_SCL */ @@ -503,15 +561,15 @@ pins { }; }; + /omit-if-no-ref/ i2c8_sleep_pins_a: i2c8-sleep-0 { pins { pinmux = , /* I2C8_SCL */ ; /* I2C8_SDA */ }; }; -}; -&pinctrl_z { + /omit-if-no-ref/ spi8_pins_a: spi8-0 { pins1 { pinmux = , /* SPI8_SCK */ @@ -526,6 +584,7 @@ pins2 { }; }; + /omit-if-no-ref/ spi8_sleep_pins_a: spi8-sleep-0 { pins1 { pinmux = , /* SPI8_SCK */ diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 8b925ed0d881..673fbc5632e6 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -773,7 +773,7 @@ i2c1: i2c@40120000 { compatible = "st,stm32mp25-i2c"; reg = <0x40120000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C1>; resets = <&rcc I2C1_R>; #address-cells = <1>; @@ -784,6 +784,7 @@ i2c1: i2c@40120000 { access-controllers = <&rifsc 41>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -791,7 +792,7 @@ i2c2: i2c@40130000 { compatible = "st,stm32mp25-i2c"; reg = <0x40130000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C2>; resets = <&rcc I2C2_R>; #address-cells = <1>; @@ -802,6 +803,7 @@ i2c2: i2c@40130000 { access-controllers = <&rifsc 42>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -809,7 +811,7 @@ i2c3: i2c@40140000 { compatible = "st,stm32mp25-i2c"; reg = <0x40140000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C3>; resets = <&rcc I2C3_R>; #address-cells = <1>; @@ -820,6 +822,7 @@ i2c3: i2c@40140000 { access-controllers = <&rifsc 43>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -827,7 +830,7 @@ i2c4: i2c@40150000 { compatible = "st,stm32mp25-i2c"; reg = <0x40150000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C4>; resets = <&rcc I2C4_R>; #address-cells = <1>; @@ -838,6 +841,7 @@ i2c4: i2c@40150000 { access-controllers = <&rifsc 44>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -845,7 +849,7 @@ i2c5: i2c@40160000 { compatible = "st,stm32mp25-i2c"; reg = <0x40160000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C5>; resets = <&rcc I2C5_R>; #address-cells = <1>; @@ -856,6 +860,7 @@ i2c5: i2c@40160000 { access-controllers = <&rifsc 45>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -863,7 +868,7 @@ i2c6: i2c@40170000 { compatible = "st,stm32mp25-i2c"; reg = <0x40170000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 49 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C6>; resets = <&rcc I2C6_R>; #address-cells = <1>; @@ -874,6 +879,7 @@ i2c6: i2c@40170000 { access-controllers = <&rifsc 46>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -881,7 +887,7 @@ i2c7: i2c@40180000 { compatible = "st,stm32mp25-i2c"; reg = <0x40180000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti1 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C7>; resets = <&rcc I2C7_R>; #address-cells = <1>; @@ -892,6 +898,7 @@ i2c7: i2c@40180000 { access-controllers = <&rifsc 47>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; @@ -1473,7 +1480,7 @@ i2c8: i2c@46040000 { compatible = "st,stm32mp25-i2c"; reg = <0x46040000 0x400>; interrupt-names = "event"; - interrupts = ; + interrupts-extended = <&exti2 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc CK_KER_I2C8>; resets = <&rcc I2C8_R>; #address-cells = <1>; @@ -1484,6 +1491,7 @@ i2c8: i2c@46040000 { access-controllers = <&rifsc 48>; power-domains = <&CLUSTER_PD>; i2c-analog-filter; + wakeup-source; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index 4135e7c0d9a3..8daf3dfd5133 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -84,6 +84,42 @@ u-boot { }; }; + panel_lvds: display { + compatible = "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + backlight = <&panel_lvds_backlight>; + power-supply = <&scmi_v3v3>; + width-mm = <156>; + height-mm = <92>; + data-mapping = "vesa-24"; + status = "okay"; + + panel-timing { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hback-porch = <150>; + hsync-len = <21>; + vfront-porch = <24>; + vback-porch = <24>; + vsync-len = <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 4 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -124,11 +160,105 @@ phy1_eth1: ethernet-phy@1 { }; }; +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_b>; + pinctrl-1 = <&i2c2_sleep_pins_b>; + i2c-scl-rising-time-ns = <108>; + i2c-scl-falling-time-ns = <12>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + ili2511: ili2511@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpioi 0 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_pins_a>; + pinctrl-1 = <&i2c8_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <100000>; + status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +<dc { + status = "okay"; + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&lvds_in>; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + lvds_out0: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; + scmi_vddcore: regulator@11 { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg = ; + regulator-name = "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; + scmi_v5v_hdmi: regulator@21 { + reg = ; + regulator-name = "v5v_hdmi"; + }; + scmi_v5v_vconn: regulator@22 { + reg = ; + regulator-name = "v5v_vconn"; + }; scmi_vdd_sdcard: regulator@23 { reg = ; regulator-name = "vdd_sdcard"; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 852a73b0c516..14e033f365e3 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -261,6 +261,9 @@ &i2c2 { i2c-scl-falling-time-ns = <13>; clock-frequency = <400000>; status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; imx335: camera@1a { compatible = "sony,imx335"; @@ -299,6 +302,9 @@ &i2c8 { i2c-scl-falling-time-ns = <7>; clock-frequency = <400000>; status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; }; &ommanager { diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index ba01a929e06f..5269c9619b65 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -19,11 +19,13 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-zinnia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo @@ -62,6 +64,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg0.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg1-dualemac-mii.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-pcie0-ep.dtbo @@ -132,6 +135,12 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-phyboard-izar.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am68-phyboard-izar-lvds-ph128800t006.dtb +k3-am68-phyboard-izar-lvds-ph128800t006-dtbs := k3-am68-phyboard-izar.dtb \ + k3-am68-phyboard-izar-lvds-ph128800t006.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-phyboard-izar-peb-av-15.dtb +k3-am68-phyboard-izar-peb-av-15-dtbs := k3-am68-phyboard-izar.dtb \ + k3-am68-phyboard-izar-peb-av-15.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb @@ -142,17 +151,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-usb0-type-a.dtbo # Boards with J722s SoC -k3-am67a-kontron-sa67-dtbs := k3-am67a-kontron-sa67-base.dtb \ - k3-am67a-kontron-sa67-rtc-rv8263.dtbo k3-am67a-kontron-sa67-gbe1.dtbo -k3-am67a-kontron-sa67-ads2-dtbs := k3-am67a-kontron-sa67.dtb k3-am67a-kontron-sa67-ads2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb -dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67.dtb -dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-base.dtb -dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-gbe1.dtbo -dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-gpios.dtbo -dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-rtc-rv8263.dtbo -dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-ads2.dtb -dtb-$(CONFIG_ARCH_K3) += k3-am67a-kontron-sa67-ads2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo @@ -218,6 +217,8 @@ k3-am62p5-sk-csi2-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-ov5640.dtbo k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo +k3-am642-evm-icssg0-dtbs := \ + k3-am642-evm.dtb k3-am642-evm-icssg0.dtbo k3-am642-evm-icssg1-dualemac-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg1-dualemac.dtbo k3-am642-evm-icssg1-dualemac-mii-dtbs := \ @@ -244,8 +245,6 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo -k3-am67a-kontron-sa67-base-gpios-dtbs := \ - k3-am67a-kontron-sa67-base.dtb k3-am67a-kontron-sa67-gpios.dtbo k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ @@ -306,6 +305,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-imx219.dtb \ k3-am62p5-sk-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-tevi-ov5640.dtb \ + k3-am642-evm-icssg0.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ k3-am642-evm-icssg1-dualemac-mii.dtb \ k3-am642-evm-pcie0-ep.dtb \ @@ -318,7 +318,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ - k3-am67a-kontron-sa67-base-gpios.dtb \ + k3-am68-phyboard-izar-lvds-ph128800t006.dtb \ + k3-am68-phyboard-izar-peb-av-15.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 3e2d8f669535..8a556fbbe08b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -88,13 +88,13 @@ main_mmc0_pins_default: main-mmc0-default-pins { AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (V3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (Y1) MMC0_CLK */ AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (V2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (V1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (W2) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (W1) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (Y2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (W3) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (W4) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (V4) MMC0_DAT7 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (V1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (W2) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (W1) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (Y2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (W3) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W4) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (V4) MMC0_DAT7 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index e15da771bc07..3baa653257bb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -37,6 +37,13 @@ reserved_memory: reserved-memory { #size-cells = <2>; ranges; + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + ramoops@9c700000 { compatible = "ramoops"; reg = <0x00 0x9c700000 0x00 0x00100000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi index ea69fab9b52b..ad247f53fe82 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi @@ -48,5 +48,6 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-zinnia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-zinnia.dtsi new file mode 100644 index 000000000000..0ce8357797ed --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-zinnia.dtsi @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin AM62 SoM on Zinnia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +#include +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_zinnia_leds>; + + /* LED1 Red - SODIMM 48 - LED1_R */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; + }; + + /* LED1 Blue - SODIMM 46 - LED1_B */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Red - SODIMM 44 - LED3_R */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Green - SODIMM 54 - LED3_G */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Blue - SODIMM 36 - LED3_B */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Red - SODIMM 34 - LED4_R */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&main_gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Green - SODIMM 32 - LED4_G */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Blue - SODIMM 30 - LED4_B */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>; + }; + }; + + zinnia-1v8-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_4 */ + io-channels = <&verdin_som_adc 4>; + full-ohms = <39000>; /* 12K + 27K */ + output-ohms = <27000>; + }; + + zinnia-3v3-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_3 */ + io-channels = <&verdin_som_adc 5>; + full-ohms = <54000>; /* 27K + 27K */ + output-ohms = <27000>; + }; + + zinnia-5v-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_2 */ + io-channels = <&verdin_som_adc 6>; + full-ohms = <39000>; /* 27K + 12K */ + output-ohms = <12000>; + }; + + /* Zinnia Power Supply Input Voltage */ + zinnia-input-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_1 */ + io-channels = <&verdin_som_adc 7>; + full-ohms = <204700>; /* 200K + 4.7K */ + output-ohms = <4700>; + }; +}; + +&main_pmx0 { + pinctrl_zinnia_leds: zinnia-leds-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ /* SODIMM 36 */ + AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (B20) MCASP0_AXR0.GPIO1_10 */ /* SODIMM 34 */ + AM62X_IOPAD(0x01a4, PIN_INPUT, 7) /* (A19) MCASP0_ACLKX.GPIO1_11 */ /* SODIMM 30 */ + AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (A20) MCASP0_AFSX.GPIO1_12 */ /* SODIMM 32 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 7) /* (L17) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + AM62X_IOPAD(0x0098, PIN_INPUT, 7) /* (R18) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; +}; + +&mcu_pmx0 { + pinctrl_zinnia_spi1_cs0_gpio: mcu-gpio0-11-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x002c, PIN_INPUT, 7) /* (C6) WKUP_UART0_CTSn.GPIO0_11 */ /* SODIMM 143 */ + >; + }; +}; + +/* Verdin ETH */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + cpsw3g_phy1: ethernet-phy@2 { + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <38 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + }; +}; + +/* Verdin ETH_1 */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&cpsw3g_phy1>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>, + <&pinctrl_qspi1_io0_gpio>; + gpio-line-names = + "", /* 0 */ + "", + "", + "DI3_RB", /* SODIMM 56 */ + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "DI2_EN", /* SODIMM 218 */ + "", + "", + "", + "DI2_RB", /* SODIMM 216 */ /* 40 */ + "DO3_EN", /* SODIMM 220 */ + "DI3_EN", /* SODIMM 222 */ + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + ""; +}; + +&main_gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-0 = <&pinctrl_spi1>, + <&pinctrl_zinnia_spi1_cs0_gpio>, + <&pinctrl_spi1_cs_gpio>; + cs-gpios = <&mcu_gpio0 11 GPIO_ACTIVE_LOW>, + <&main_gpio0 7 GPIO_ACTIVE_LOW>; + + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>, + <&pinctrl_pcie_1_reset>; + gpio-line-names = + "", + "DO1_EN", /* SODIMM 206 */ + "DI1_EN", /* SODIMM 208 */ + "DI1_RB", /* SODIMM 210 */ + "DO2_EN", /* SODIMM 212 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>, <&pinctrl_wkup_uart0_rts>; + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 2a7242a2fef8..e97b2b047d10 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -278,7 +278,7 @@ AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ }; /* Verdin SPI_1 CS as GPIO */ - pinctrl_qspi1_io4_gpio: main-gpio0-7-default-pins { + pinctrl_spi1_cs_gpio: main-gpio0-7-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x001c, PIN_INPUT, 7) /* (J23) OSPI0_D4.GPIO0_7 */ /* SODIMM 202 */ >; @@ -572,16 +572,16 @@ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM /* On-module eMMC */ pinctrl_sdhci0: main-mmc0-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; }; @@ -820,15 +820,27 @@ AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */ >; }; - /* Verdin UART_2 */ + /* Verdin UART_2 RX/TX */ pinctrl_wkup_uart0: wkup-uart0-default-pins { pinctrl-single,pins = < - AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ - AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ AM62X_MCU_IOPAD(0x0024, PIN_INPUT_PULLUP, 0) /* (B4) WKUP_UART0_RXD */ /* SODIMM 137 */ AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */ >; }; + + /* Verdin UART_2 CTS */ + pinctrl_wkup_uart0_cts: wkup-uart0-cts-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ + >; + }; + + /* Verdin UART_2 RTS */ + pinctrl_wkup_uart0_rts: wkup-uart0-rts-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ + >; + }; }; /* VERDIN I2S_1_MCLK */ @@ -1502,7 +1514,7 @@ &usb1 { /* Verdin UART_2 */ &wkup_uart0 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_uart0>; + pinctrl-0 = <&pinctrl_wkup_uart0>, <&pinctrl_wkup_uart0_cts>, <&pinctrl_wkup_uart0_rts>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-zinnia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-zinnia.dts new file mode 100644 index 000000000000..eba8d7a5b1bf --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-zinnia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin AM62 on Zinnia Board"; + compatible = "toradex,verdin-am62-nonwifi-zinnia", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-zinnia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-zinnia.dts new file mode 100644 index 000000000000..6f3f8eb42ed6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-zinnia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Zinnia Board"; + compatible = "toradex,verdin-am62-wifi-zinnia", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi index 950f4f37d477..06d4e815b167 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi @@ -66,6 +66,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -77,6 +78,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index e99bdbc2e0cb..c1e9067b3bdd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -282,6 +282,13 @@ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ bootph-all; }; + main_uart0_pins_wakeup: main-uart0-wakeup-pins { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1c8, PIN_INPUT | PIN_WKUP_EN, 0) /* (E14) UART0_RXD */ + AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ + >; + }; + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x01ac, PIN_INPUT, 2) /* (B21) MCASP0_AFSR.UART1_RXD */ @@ -398,7 +405,7 @@ AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */ vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins = < - AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + AM62AX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (N22) GPMC0_CLK.GPIO0_31 */ >; }; @@ -717,8 +724,12 @@ &main_gpio_intr { &main_uart0 { status = "okay"; - pinctrl-names = "default"; + pinctrl-names = "default", "wakeup"; pinctrl-0 = <&main_uart0_pins_default>; + pinctrl-1 = <&main_uart0_pins_wakeup>; + wakeup-source = <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; bootph-all; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index a5d5dc0a7bec..f5ceb6a1b5de 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -199,6 +199,42 @@ led-0 { &mcu_pmx0 { status = "okay"; + mcu_mcan0_tx_pins_default: mcu-mcan0-tx-default-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (C7) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan0_rx_pins_default: mcu-mcan0-rx-default-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (E8) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan0_rx_pins_wakeup: mcu-mcan0-rx-wakeup-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x0038, PIN_INPUT | PIN_WKUP_EN, 0) /* (E8) MCU_MCAN0_RX */ + >; + }; + + mcu_mcan1_tx_pins_default: mcu-mcan1-tx-default-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (D7) MCU_MCAN1_TX */ + >; + }; + + mcu_mcan1_rx_pins_default: mcu-mcan1-rx-default-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (B9) MCU_MCAN1_RX */ + >; + }; + + mcu_mcan1_rx_pins_wakeup: mcu-mcan1-rx-wakeup-pins { + pinctrl-single,pins = < + AM62DX_MCU_IOPAD(0x040, PIN_INPUT | PIN_WKUP_EN, 0) /* (B9) MCU_MCAN1_RX */ + >; + }; + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62DX_IOPAD(0x01f4, PIN_INPUT, 7) /* (F17) EXTINTn.GPIO1_31 */ @@ -228,6 +264,10 @@ AM62DX_MCU_IOPAD(0x0050, PIN_INPUT, 0) /* (E13) WKUP_I2C0_SDA */ &wkup_uart0 { pinctrl-names = "default"; pinctrl-0 = <&wkup_uart0_pins_default>; + wakeup-source = <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; bootph-all; status = "reserved"; }; @@ -241,6 +281,13 @@ AM62DX_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ bootph-all; }; + main_uart0_pins_wakeup: main-uart0-wakeup-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x01c8, PIN_INPUT | PIN_WKUP_EN, 0) /* (E14) UART0_RXD */ + AM62DX_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ + >; + }; + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62DX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ @@ -587,8 +634,12 @@ &main_gpio_intr { }; &main_uart0 { - pinctrl-names = "default"; + pinctrl-names = "default", "wakeup"; pinctrl-0 = <&main_uart0_pins_default>; + pinctrl-1 = <&main_uart0_pins_wakeup>; + wakeup-source = <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; bootph-all; status = "okay"; }; @@ -737,4 +788,33 @@ &c7x_0 { firmware-name = "am62d-c71_0-fw"; }; +&mcu_mcan0 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_default>; + pinctrl-1 = <&mcu_mcan0_tx_pins_default>, <&mcu_mcan0_rx_pins_wakeup>; + wakeup-source = <&system_partial_io>, + <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + +&mcu_mcan1 { + pinctrl-names = "default", "wakeup"; + pinctrl-0 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_default>; + pinctrl-1 = <&mcu_mcan1_tx_pins_default>, <&mcu_mcan1_rx_pins_wakeup>; + wakeup-source = <&system_partial_io>, + <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + +&mcu_uart0 { + wakeup-source = <&system_io_ddr>, + <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; +}; + #include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi index 883beb76ba9c..80615ca1e01a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62l-main.dtsi @@ -564,6 +564,13 @@ gpmc0: memory-controller@3b000000 { status = "disabled"; }; + rng: rng@3b100000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x3b100000 0x00 0x7d>; + interrupts = ; + status = "reserved"; /* Reserved for OP-TEE */ + }; + oc_sram: sram@70800000 { compatible = "mmio-sram"; reg = <0x00 0x70800000 0x00 0x10000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi index 61bfcdcfc66e..b5b70e71a0b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62l-wakeup.dtsi @@ -81,7 +81,7 @@ wkup_i2c0: i2c@2b200000 { status = "disabled"; }; - target-module@2b300050 { + wkup_uart0_target: target-module@2b300050 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x00 0x2b300050 0x00 0x4>, <0x00 0x2b300054 0x00 0x4>, @@ -127,6 +127,11 @@ chipid: chipid@14 { bootph-all; }; + opp_efuse_table: syscon@18 { + compatible = "ti,am62-opp-efuse-table", "syscon"; + reg = <0x18 0x4>; + }; + cpsw_mac_syscon: ethernet-mac-syscon@2000 { compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; reg = <0x2000 0x8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62l.dtsi b/arch/arm64/boot/dts/ti/k3-am62l.dtsi index 23acdbb301fe..28bb6ef2194f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62l.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62l.dtsi @@ -79,6 +79,7 @@ cbass_main: bus@f0000 { <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core Window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core Window */ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0 */ + <0x00 0x3b100000 0x00 0x3b100000 0x00 0x0000007d>, /* RNG */ <0x00 0x45810000 0x00 0x45810000 0x00 0x03170000>, /* DMSS */ <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC DATA */ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS DAT1 */ @@ -92,7 +93,7 @@ cbass_main: bus@f0000 { <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ - <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00200200>, /* Wakeup Peripheral Window */ <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ #address-cells = <2>; @@ -104,7 +105,7 @@ cbass_wakeup: bus@a80000 { <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00001400>, /* VTM */ <0x00 0x04080000 0x00 0x04080000 0x00 0x00008000>, /* PDCFG */ <0x00 0x04201000 0x00 0x04201000 0x00 0x00000100>, /* GPIO */ - <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00100100>, /* Wakeup Peripheral Window */ + <0x00 0x2b100000 0x00 0x2b100000 0x00 0x00200200>, /* Wakeup Peripheral Window */ <0x00 0x40800000 0x00 0x40800000 0x00 0x00014000>, /* DMA */ <0x00 0x43000000 0x00 0x43000000 0x00 0x00080000>; /* CTRL MMRs */ #address-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts index cae04cce3373..a1af4571a815 100644 --- a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts @@ -272,9 +272,9 @@ mmc1_pins_default: mmc1-default-pins { AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */ AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */ AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */ - AM62LX_IOPAD(0x0220, PIN_INPUT_PULLUP, 0) /* (Y4) MMC1_DAT1 */ - AM62LX_IOPAD(0x021c, PIN_INPUT_PULLUP, 0) /* (AA2) MMC1_DAT2 */ - AM62LX_IOPAD(0x0218, PIN_INPUT_PULLUP, 0) /* (AB2) MMC1_DAT3 */ + AM62LX_IOPAD(0x0220, PIN_INPUT, 0) /* (Y4) MMC1_DAT1 */ + AM62LX_IOPAD(0x021c, PIN_INPUT, 0) /* (AA2) MMC1_DAT2 */ + AM62LX_IOPAD(0x0218, PIN_INPUT, 0) /* (AB2) MMC1_DAT3 */ AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */ >; bootph-all; @@ -288,6 +288,13 @@ AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ bootph-all; }; + uart0_pins_wakeup: uart0-wakeup-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b4, PIN_INPUT | PIN_WKUP_EN, 0) /* (D13) UART0_RXD */ + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + >; + }; + usb1_default_pins: usb1-default-pins { pinctrl-single,pins = < AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */ @@ -306,6 +313,12 @@ AM62LX_IOPAD(0x0238, PIN_OUTPUT, 7) /* (D24) MMC1_SDWP.GPIO0_123 */ >; }; + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0000, PIN_INPUT, 0) /* (Y22) WKUP_UART0_RXD */ + AM62LX_IOPAD(0x0004, PIN_OUTPUT, 0) /* (AA23) WKUP_UART0_TXD */ + >; + }; }; &sdhci0 { @@ -329,7 +342,9 @@ &sdhci1 { &uart0 { pinctrl-0 = <&uart0_pins_default>; - pinctrl-names = "default"; + pinctrl-1 = <&uart0_pins_wakeup>; + pinctrl-names = "default", "wakeup"; + wakeup-source; status = "okay"; bootph-all; }; @@ -359,3 +374,12 @@ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&usb1_default_pins>; }; + +&wkup_uart0 { + pinctrl-0 = <&wkup_uart0_pins_default>; + pinctrl-names = "default"; +}; + +&wkup_uart0_target { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi index da220b851512..fc514e19f57d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62l3.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62l3.dtsi @@ -39,6 +39,8 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&scmi_clk 356>; }; cpu1: cpu@1 { @@ -53,6 +55,8 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + operating-points-v2 = <&a53_opp_table>; + clocks = <&scmi_clk 357>; }; }; @@ -64,4 +68,47 @@ l2_0: l2-cache0 { cache-line-size = <64>; cache-sets = <256>; }; + + a53_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + opp-shared; + syscon = <&opp_efuse_table>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x01 0x0003>; + clock-latency-ns = <6000000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-supported-hw = <0x01 0x0002>; + clock-latency-ns = <6000000>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-supported-hw = <0x01 0x0002>; + clock-latency-ns = <6000000>; + opp-suspend; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 0e1af2a69ca2..f130c7cb998d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -543,10 +543,9 @@ main_spi2: spi@20120000 { main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; reg = <0x00 0x00a00000 0x00 0x800>; - ti,intr-trigger-type = <1>; interrupt-controller; interrupt-parent = <&gic500>; - #interrupt-cells = <1>; + #interrupt-cells = <2>; ti,sci = <&dmsc>; ti,sci-dev-id = <3>; ti,interrupt-ranges = <0 32 16>; @@ -558,8 +557,9 @@ main_gpio0: gpio@600000 { gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; - interrupts = <190>, <191>, <192>, - <193>, <194>, <195>; + interrupts = <190 IRQ_TYPE_EDGE_RISING>, <191 IRQ_TYPE_EDGE_RISING>, + <192 IRQ_TYPE_EDGE_RISING>, <193 IRQ_TYPE_EDGE_RISING>, + <194 IRQ_TYPE_EDGE_RISING>, <195 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; ti,davinci-gpio-unbanked = <0>; @@ -574,8 +574,9 @@ main_gpio1: gpio@601000 { gpio-controller; #gpio-cells = <2>; interrupt-parent = <&main_gpio_intr>; - interrupts = <180>, <181>, <182>, - <183>, <184>, <185>; + interrupts = <180 IRQ_TYPE_EDGE_RISING>, <181 IRQ_TYPE_EDGE_RISING>, + <182 IRQ_TYPE_EDGE_RISING>, <183 IRQ_TYPE_EDGE_RISING>, + <184 IRQ_TYPE_EDGE_RISING>, <185 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; ti,davinci-gpio-unbanked = <0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi index d29a5dbe13ef..5d7f701420e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi @@ -45,6 +45,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -56,5 +57,6 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-zinnia.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-zinnia.dtsi new file mode 100644 index 000000000000..84ae99dcdda3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-zinnia.dtsi @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common dtsi for Verdin AM62P SoM on Zinnia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +#include +#include + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_zinnia_leds>; + + /* LED1 Red - SODIMM 48 - LED1_R */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; + }; + + /* LED1 Blue - SODIMM 46 - LED1_B */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Red - SODIMM 44 - LED3_R */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Green - SODIMM 54 - LED3_G */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + + /* LED3 Blue - SODIMM 36 - LED3_B */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + gpios = <&main_gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Red - SODIMM 34 - LED4_R */ + led-5 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&main_gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Green - SODIMM 32 - LED4_G */ + led-6 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + /* LED4 Blue - SODIMM 30 - LED4_B */ + led-7 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + gpios = <&main_gpio1 11 GPIO_ACTIVE_HIGH>; + }; + }; + + zinnia-1v8-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_4 */ + io-channels = <&som_adc 4>; + full-ohms = <39000>; /* 12K + 27K */ + output-ohms = <27000>; + }; + + zinnia-3v3-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_3 */ + io-channels = <&som_adc 5>; + full-ohms = <54000>; /* 27K + 27K */ + output-ohms = <27000>; + }; + + zinnia-5v-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_2 */ + io-channels = <&som_adc 6>; + full-ohms = <39000>; /* 27K + 12K */ + output-ohms = <12000>; + }; + + /* Zinnia Power Supply Input Voltage */ + zinnia-input-voltage { + compatible = "voltage-divider"; + /* Verdin ADC_1 */ + io-channels = <&som_adc 7>; + full-ohms = <204700>; /* 200K + 4.7K */ + output-ohms = <4700>; + }; +}; + +&main_pmx0 { + pinctrl_zinnia_leds: zinnia-leds-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x019c, PIN_INPUT, 7) /* (E24) MCASP0_AXR1.GPIO1_9 */ /* SODIMM 36 */ + AM62PX_IOPAD(0x01a0, PIN_INPUT, 7) /* (F23) MCASP0_AXR0.GPIO1_10 */ /* SODIMM 34 */ + AM62PX_IOPAD(0x01a4, PIN_INPUT, 7) /* (F24) MCASP0_ACLKX.GPIO1_11 */ /* SODIMM 30 */ + AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */ /* SODIMM 32 */ + AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 7) /* (AA24) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + AM62PX_IOPAD(0x008c, PIN_INPUT, 7) /* (T25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + AM62PX_IOPAD(0x002c, PIN_INPUT, 7) /* (M25) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; +}; + +&mcu_pmx0 { + pinctrl_zinnia_spi1_cs0_gpio: mcu-gpio0-11-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 7) /* (C7) WKUP_UART0_CTSn.GPIO0_11 */ /* SODIMM 143 */ + >; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; + + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + carrier_eth_phy: ethernet-phy@2 { + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&carrier_eth_phy>; + phy-mode = "rgmii-id"; + + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_1_reset>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>, + <&pinctrl_qspi1_io0_gpio>; + gpio-line-names = + "", /* 0 */ + "", + "", + "DI3_RB", /* SODIMM 56 */ + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "DI2_RB", /* SODIMM 216 */ + "DI2_EN", /* SODIMM 218 */ /* 50 */ + "DO3_EN", /* SODIMM 220 */ + "DI3_EN", /* SODIMM 222 */ + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 90 */ + ""; +}; + +&main_gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + ""; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-0 = <&pinctrl_main_spi1>, + <&pinctrl_zinnia_spi1_cs0_gpio>, + <&pinctrl_spi1_cs_gpio>; + cs-gpios = <&mcu_gpio0 11 GPIO_ACTIVE_LOW>, + <&main_gpio0 7 GPIO_ACTIVE_LOW>; + + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_4>, + <&pinctrl_gpio_3>; + gpio-line-names = + "", + "DO1_EN", /* SODIMM 206 */ + "DI1_EN", /* SODIMM 208 */ + "DI1_RB", /* SODIMM 210 */ + "DO2_EN", /* SODIMM 212 */ + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + ""; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>, + <&pinctrl_wkup_uart0_rts>; + rs485-rts-active-low; + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index 34954df692a3..7ee894d59113 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -247,6 +247,13 @@ AM62PX_IOPAD(0x0018, PIN_INPUT, 7) /* (M24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ >; }; + /* Verdin SPI_1_CS as GPIO */ + pinctrl_spi1_cs_gpio: main-gpio0-7-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x001c, PIN_OUTPUT, 7) /* (N21) OSPI0_D4.GPIO0_7 */ /* SODIMM 202 */ + >; + }; + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { pinctrl-single,pins = < @@ -767,15 +774,27 @@ AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ /* SODIMM 91 */ >; }; - /* Verdin UART_2 */ + /* Verdin UART_2 RX/TX */ pinctrl_wkup_uart0: wkup-uart0-default-pins { pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ /* SODIMM 143 */ - AM62PX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ /* SODIMM 141 */ AM62PX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ /* SODIMM 137 */ AM62PX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ /* SODIMM 139 */ >; }; + + /* Verdin UART_2 CTS */ + pinctrl_wkup_uart0_cts: wkup-uart0-cts-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ /* SODIMM 143 */ + >; + }; + + /* Verdin UART_2 RTS */ + pinctrl_wkup_uart0_rts: wkup-uart0-rts-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ /* SODIMM 141 */ + >; + }; }; /* Verdin I2S_1_MCLK */ @@ -1410,7 +1429,9 @@ som_eeprom: eeprom@50 { /* Verdin UART_2 */ &wkup_uart0 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_uart0>; + pinctrl-0 = <&pinctrl_wkup_uart0>, + <&pinctrl_wkup_uart0_cts>, + <&pinctrl_wkup_uart0_rts>; uart-has-rtscts; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 4f7f6f95b02e..b770ed82be9d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -271,9 +271,9 @@ main_mmc1_pins_default: main-mmc1-default-pins { AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ - AM62PX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H23) MMC1_DAT1 */ - AM62PX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (H22) MMC1_DAT2 */ - AM62PX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */ + AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */ + AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ >; bootph-all; @@ -336,6 +336,13 @@ AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ bootph-all; }; + main_uart0_pins_wakeup: main-uart0-wakeup-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT | PIN_WKUP_EN, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + }; + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ @@ -692,8 +699,12 @@ partition@3fc0000 { }; &main_uart0 { - pinctrl-names = "default"; + pinctrl-names = "default", "wakeup"; pinctrl-0 = <&main_uart0_pins_default>; + pinctrl-1 = <&main_uart0_pins_wakeup>; + wakeup-source = <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; status = "okay"; bootph-all; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-zinnia.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-zinnia.dts new file mode 100644 index 000000000000..8abf4fe60e99 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-nonwifi-zinnia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-nonwifi.dtsi" +#include "k3-am62p-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin AM62P on Zinnia Board"; + compatible = "toradex,verdin-am62p-nonwifi-zinnia", + "toradex,verdin-am62p-nonwifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-zinnia.dts b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-zinnia.dts new file mode 100644 index 000000000000..e1df7cffdf63 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-wifi-zinnia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/zinnia-carrier-board + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-wifi.dtsi" +#include "k3-am62p-verdin-zinnia.dtsi" + +/ { + model = "Toradex Verdin AM62P WB on Zinnia Board"; + compatible = "toradex,verdin-am62p-wifi-zinnia", + "toradex,verdin-am62p-wifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 50ed859ae06c..ab9e58c2d225 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -151,6 +151,13 @@ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ >; }; + main_uart0_pins_wakeup: main-uart0-wakeup-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT | PIN_WKUP_EN, 0) /* (D14/A13) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ + >; + }; + main_uart1_pins_default: main-uart1-default-pins { bootph-pre-ram; pinctrl-single,pins = < @@ -322,8 +329,12 @@ &wkup_uart0 { &main_uart0 { bootph-all; status = "okay"; - pinctrl-names = "default"; + pinctrl-names = "default", "wakeup"; pinctrl-0 = <&main_uart0_pins_default>; + pinctrl-1 = <&main_uart0_pins_wakeup>; + wakeup-source = <&system_deep_sleep>, + <&system_mcu_only>, + <&system_standby>; }; &main_uart1 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi index 6b10646ae64a..51fd9b68f58d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi @@ -126,6 +126,7 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -133,6 +134,7 @@ &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -144,6 +146,7 @@ &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -151,6 +154,7 @@ &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso new file mode 100644 index 000000000000..0c8e245e526c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-evm-icssg0.dtso @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT overlay for enabling ICSSG0 dual EMAC on AM642 EVM + * + * AM642 EVM Product link: https://www.ti.com/tool/TMDS64EVM + * DP83TG720 daughter card link: https://www.ti.com/tool/DP83TG720-IND-SPE-EVM + * + * Copyright (C) 2020-2026 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + icssg0_eth: icssg0-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&pru_icssg0_rgmii1_pins_default>, <&pru_icssg0_rgmii2_pins_default>; + sram = <&oc_sram>; + + dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */ + <&main_pktdma 0xc101 15>, /* egress slice 0 */ + <&main_pktdma 0xc102 15>, /* egress slice 0 */ + <&main_pktdma 0xc103 15>, /* egress slice 0 */ + <&main_pktdma 0xc104 15>, /* egress slice 1 */ + <&main_pktdma 0xc105 15>, /* egress slice 1 */ + <&main_pktdma 0xc106 15>, /* egress slice 1 */ + <&main_pktdma 0xc107 15>, /* egress slice 1 */ + <&main_pktdma 0x4100 15>, /* ingress slice 0 */ + <&main_pktdma 0x4101 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + interrupt-parent = <&icssg0_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>; + firmware-name = "ti-pruss/am64x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am64x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am64x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am64x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt = <&icssg0_mii_g_rt>; + ti,mii-rt = <&icssg0_mii_rt>; + ti,iep = <&icssg0_iep0>, <&icssg0_iep1>; + ti,pa-stats = <&icssg0_pa_stats>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + icssg0_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg0_phy00>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&main_conf 0x4100>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + icssg0_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg0_phy01>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&main_conf 0x4104>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; +}; + +&main_pmx0 { + pru_icssg0_mdio_pins_default: pru-icssg0-mdio-pins { + pinctrl-single,pins = < + /* (P3) PRG0_MDIO0_MDC */ + AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) + /* (P2) PRG0_MDIO0_MDIO */ + AM64X_IOPAD(0x0200, PIN_INPUT, 0) + /* (P16) GPIO0_32 - GPMC0_ADVn_ALE - GPIO_ETH0/1_RESETn# */ + AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) + >; + }; + + pru_icssg0_rgmii1_pins_default: pru-icssg0-rgmii1-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */ + AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */ + AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */ + AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */ + AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */ + AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */ + AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */ + AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */ + AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */ + AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */ + AM64X_IOPAD(0x01a0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */ + AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */ + >; + }; + + pru_icssg0_rgmii2_pins_default: pru-icssg0-rgmii2-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01b0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */ + AM64X_IOPAD(0x01b4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */ + AM64X_IOPAD(0x01b8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */ + AM64X_IOPAD(0x01bc, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */ + AM64X_IOPAD(0x01c8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */ + AM64X_IOPAD(0x01c0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */ + AM64X_IOPAD(0x01dc, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.PRG0_RGMII2_TD0 */ + AM64X_IOPAD(0x01e0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.PRG0_RGMII2_TD1 */ + AM64X_IOPAD(0x01e4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.PRG0_RGMII2_TD2 */ + AM64X_IOPAD(0x01e8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.PRG0_RGMII2_TD3 */ + AM64X_IOPAD(0x01f0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */ + AM64X_IOPAD(0x01ec, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.PRG0_RGMII2_TX_CTL */ + >; + }; + + icssg0_iep0_pins_default: icssg0-iep0-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x01ac, PIN_OUTPUT, 2) /* (W1) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */ + >; + }; +}; + +&icssg0_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pru_icssg0_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + + icssg0_phy00: ethernet-phy@0 { + reg = <0x0>; + }; + + icssg0_phy01: ethernet-phy@a { + reg = <0xa>; + }; +}; + +&icssg0_iep0 { + pinctrl-names = "default"; + pinctrl-0 = <&icssg0_iep0_pins_default>; +}; + +&main_gpio0 { + phy-line-hog { + gpio-hog; + gpios = <32 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "phy-hog-line"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 88093ab74502..bc4347cf7114 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -601,6 +601,7 @@ cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; + ti,min-output-impedance; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 34bfa99bd4b8..d28a38c87f32 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -519,12 +519,14 @@ cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; + ti,min-output-impedance; }; cpsw3g_phy1: ethernet-phy@1 { reg = <1>; ti,rx-internal-delay = ; ti,fifo-depth = ; + ti,min-output-impedance; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi index 61ab0357fc0d..e5f37cfd18bc 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi @@ -52,6 +52,7 @@ &mcu_r5fss0 { &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; status = "okay"; }; @@ -59,6 +60,7 @@ &mcu_r5fss0_core0 { &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index e0262c2743eb..ca1300e13093 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -583,6 +583,7 @@ phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; + ti,min-output-impedance; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-ads2.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-ads2.dtso deleted file mode 100644 index ae5e2b52594b..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-ads2.dtso +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Kontron SMARC-sa67 board on the Kontron Eval Carrier 2.2. - * - * Copyright (c) 2025 Kontron Europe GmbH - */ - -/dts-v1/; -/plugin/; - -#include -#include "k3-pinctrl.h" - -&{/} { - pwm-fan { - compatible = "pwm-fan"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm_fan_pins_default>; - interrupts-extended = <&main_gpio1 7 IRQ_TYPE_EDGE_FALLING>; - #cooling-cells = <2>; - pwms = <&epwm2 1 4000000 0>; - cooling-levels = <1 128 192 255>; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out Jack", - "Microphone", "Microphone Jack", - "Line", "Line In Jack"; - simple-audio-card,routing = - "Line Out Jack", "LINEOUTR", - "Line Out Jack", "LINEOUTL", - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "IN1L", "Line In Jack", - "IN1R", "Line In Jack", - "Microphone Jack", "MICBIAS", - "IN2L", "Microphone Jack", - "IN2R", "Microphone Jack"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - }; - - dailink0_master: simple-audio-card,codec { - sound-dai = <&wm8904>; - clocks = <&audio_refclk0>; - }; - }; - - cvcc_1p8v_i2s: regulator-carrier-0 { - compatible = "regulator-fixed"; - regulator-name = "V_1V8_S0_I2S"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - cvcc_1p8v_s0: regulator-carrier-1 { - compatible = "regulator-fixed"; - regulator-name = "V_1V8_S0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - cvcc_3p3v_s0: regulator-carrier-2 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&audio_refclk0 { - status = "okay"; -}; - -&epwm2 { - status = "okay"; -}; - -&main_pmx0 { - pwm_fan_pins_default: pwm-fan-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1ec, PIN_OUTPUT, 8) /* (A22) I2C1_SDA.EHRPWM2_B */ - J722S_IOPAD(0x194, PIN_INPUT, 0) /* (A25) MCASP0_AXR3.GPIO1_7 */ - >; - }; -}; - -&mcasp0 { - #sound-dai-cells = <0>; - status = "okay"; -}; - -&mcu_i2c0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - wm8904: audio-codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8904"; - reg = <0x1a>; - clocks = <&audio_refclk0>; - clock-names = "mclk"; - AVDD-supply = <&cvcc_1p8v_i2s>; - CPVDD-supply = <&cvcc_1p8v_i2s>; - DBVDD-supply = <&cvcc_1p8v_i2s>; - DCVDD-supply = <&cvcc_1p8v_i2s>; - MICVDD-supply = <&cvcc_1p8v_i2s>; - }; -}; - -&mcu_spi0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - m25p,fast-read; - vcc-supply = <&cvcc_1p8v_s0>; - }; -}; - -&wkup_i2c0 { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - /* SMARC Carrier EEPROM */ - eeprom@57 { - compatible = "atmel,24c32"; - reg = <0x57>; - pagesize = <32>; - vcc-supply = <&cvcc_3p3v_s0>; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts deleted file mode 100644 index 95234c8460ed..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts +++ /dev/null @@ -1,1091 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Kontron SMARC-sAM67 module - * - * Copyright (c) 2025 Kontron Europe GmbH - */ - -/dts-v1/; - -#include -#include -#include -#include "k3-j722s.dtsi" -#include "k3-serdes.h" - -/ { - compatible = "kontron,sa67", "ti,j722s"; - model = "Kontron SMARC-sAM67"; - - aliases { - serial0 = &mcu_uart0; - serial1 = &main_uart0; - serial2 = &main_uart5; - serial3 = &wkup_uart0; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - rtc0 = &wkup_rtc0; - }; - - lcd0_backlight: backlight-1 { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd0_backlight_pins_default>; - pwms = <&epwm1 0 50000 0>; - brightness-levels = <0 32 64 96 128 160 192 224 255>; - default-brightness-level = <8>; - enable-gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - lcd1_backlight: backlight-2 { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&lcd1_backlight_pins_default>; - pwms = <&epwm1 1 50000 0>; - brightness-levels = <0 32 64 96 128 160 192 224 255>; - default-brightness-level = <8>; - enable-gpios = <&main_gpio1 18 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - connector-1 { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_connector_pins_default>; - type = "micro"; - id-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; - vbus-supply = <&vcc_usb0_vbus>; - - port { - usb0_connector: endpoint { - remote-endpoint = <&usb0_hc>; - }; - }; - - }; - - memory@80000000 { - /* Filled in by bootloader */ - reg = <0x00000000 0x00000000 0x00000000 0x00000000>, - <0x00000000 0x00000000 0x00000000 0x00000000>; - device_type = "memory"; - bootph-pre-ram; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x00 0x10000000>; - linux,cma-default; - }; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; - no-map; - }; - - wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa0100000 0x00 0xf00000>; - no-map; - }; - }; - - vin_5p0: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "V_3V0_5V25_IN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - bootph-all; - }; - - vcc_3p3_s5: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S5"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vin_5p0>; - regulator-always-on; - regulator-boot-on; - bootph-all; - }; - - vcc_1p8_s5: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "V_1V8_S5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vin_5p0>; - regulator-always-on; - regulator-boot-on; - bootph-all; - }; - - vcc_3p3_s0: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_S0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3p3_s5>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpios = <&tps652g1 1 GPIO_ACTIVE_HIGH>; - bootph-all; - }; - - vcc_3p3_sd_s0: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "SDIO_PWR_EN"; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_3p3_sd_s0_pins_default>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; - bootph-all; - }; - - vcc_3p3_sd_vio_s0: regulator-6 { - compatible = "regulator-gpio"; - regulator-name = "V_3V3_1V8_SD_S0"; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_3p3_sd_vio_s0_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3p3_s0>; - regulator-boot-on; - enable-active-high; - enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; - gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; - states = <3300000 0x0>, - <1800000 0x1>; - bootph-all; - }; - - vcc_3p3_cam_s0: regulator-7 { - compatible = "regulator-fixed"; - regulator-name = "V_3V3_CAM_S0"; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_3p3_cam_s0_pins_default>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3p3_s5>; - enable-active-high; - interrupts-extended = <&main_gpio1 30 IRQ_TYPE_EDGE_FALLING>; - bootph-all; - }; - - vcc_1p1_s0: regulator-8 { - compatible = "regulator-fixed"; - regulator-name = "V_1V1_S0"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - vin-supply = <&vcc_1p1_s3>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - /* shared with V_0V75_0V85_CORE_S0 */ - gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>; - bootph-all; - }; - - vcc_0p85_vcore_s0: regulator-9 { - compatible = "regulator-fixed"; - regulator-name = "V_0V75_0V85_CORE_S0"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vin_5p0>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpios = <&tps652g1 4 GPIO_ACTIVE_HIGH>; - bootph-all; - }; - - vcc_lcd0_panel: regulator-10 { - compatible = "regulator-fixed"; - regulator-name = "LCD0_VDD_EN"; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_lcd0_panel_pins_default>; - enable-active-high; - gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; - }; - - vcc_lcd1_panel: regulator-11 { - compatible = "regulator-fixed"; - regulator-name = "LCD1_VDD_EN"; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_lcd1_panel_pins_default>; - enable-active-high; - gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; - }; - - vcc_usb0_vbus: regulator-12 { - compatible = "regulator-fixed"; - regulator-name = "USB0_EN_OC#"; - pinctrl-names = "default"; - pinctrl-0 = <&vcc_usb0_vbus_pins_default>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; - }; -}; - -&audio_refclk0 { - pinctrl-names = "default"; - pinctrl-0 = <&audio_refclk0_pins_default>; - status = "disabled"; -}; - -&audio_refclk1 { - pinctrl-names = "default"; - pinctrl-0 = <&audio_refclk1_pins_default>; - status = "disabled"; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw3g_pins_default>, <&rgmii1_pins_default>, - <&rgmii2_pins_default>; - status = "okay"; -}; - -&cpsw3g_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw3g_mdio_pins_default>; - status = "okay"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_port1 { - phy-connection-type = "rgmii-id"; - phy-handle = <&phy0>; - nvmem-cells = <&base_mac_address 0>; - nvmem-cell-names = "mac-address"; - status = "okay"; -}; - -&main_gpio0 { - gpio-line-names = - "", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL", - "RESET_OUT#", "I2C_MUX_RST#", "SPI_FLASH_CS#", "QPSI_CS0#", - "QSPI_CS1#", "BOOT_SEL1", "BRDCFG0", "BRDCFG1", "BRDCFG2", - "BRDCFG3", "BRDCFG4", "", "BRDREV0", "BRDREV1", "", "", "", "", - "", "", "LCD0_BKLT_EN", "LCD0_VDD_EN", "GBE_INT#", "DSI0_TE", - "CHARGING#", "USB0_OTG_ID", "PMIC_INT#", "RTC_INT#", - "EDP_BRIDGE_EN", "EDP_BRIDGE_IRQ#", "", "CHARGER_PRSNT#", "", - "", "", "", "BOOT_SEL2#", "CAM2_RST#", "CAM2_PWR#", "", - "CAM3_RST#", "CAM3_PWR#", "GPIO0", "GPIO1", "", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "GPIO10", "GPIO11", - "SLEEP#", "LID#"; - - bootph-all; - status = "okay"; -}; - -&main_gpio1 { - gpio-line-names = - "", "", "", "", "", "", "", "GPIO6", "GPIO7", "", "", "", "", - "GPIO8", "GPIO9", "PCIE_A_RST#", "", "BATLOW#", "LCD1_BKLT_EN", - "LCD1_VDD_EN", "", "", "", "", "GPIO2", "GPIO3", "", "", - "GPIO4", "GPIO5", "CAM_S0_FAULT#", "BOOT_SEL0#", "", "", "", "", - "", "", "", "", "", "", "", "", "", "", "", "", "SDIO_CD#", "", - "USB0_DRVVBUS", "USB1_DRVVBUS"; - - bootph-all; - status = "okay"; -}; - -/* I2C_LOCAL */ -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <100000>; - bootph-all; - status = "okay"; - - tps652g1: pmic@44 { - compatible = "ti,tps652g1"; - reg = <0x44>; - ti,primary-pmic; - system-power-controller; - - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = - "LPM_EN#", "EN_3V3_S0", "POWER_BTN#", "CARRIER_STBY#", - "EN_0V75_0V85_VCORE_S0", "PMIC_WAKEUP"; - - pinctrl-names = "default"; - pinctrl-0 = <&pmic_irq_pins_default>; - interrupts-extended = <&main_gpio0 35 IRQ_TYPE_EDGE_FALLING>; - - buck1-supply = <&vin_5p0>; - buck2-supply = <&vin_5p0>; - buck3-supply = <&vin_5p0>; - buck4-supply = <&vin_5p0>; - ldo1-supply = <&vin_5p0>; - ldo2-supply = <&vin_5p0>; - ldo3-supply = <&vin_5p0>; - - bootph-all; - - regulators { - vcc_0p85_s0: buck1 { - regulator-name = "V_0V85_S0"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_1p1_s3: buck2 { - regulator-name = "V_1V1_S3"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_1p8_s0: buck3 { - regulator-name = "V_1V8_S0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_1p2_s0: buck4 { - regulator-name = "V_1V2_S0"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_1p8_vda_pll_s0: ldo1 { - regulator-name = "V_1V8_VDA_PLL_S0"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_1p8_s3: ldo2 { - regulator-name = "V_1V8_S3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vcc_1p8_ret_s5: ldo3 { - regulator-name = "V_1V8_RET_S5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - system-controller@4a { - compatible = "kontron,sa67mcu", "kontron,sl28cpld"; - reg = <0x4a>; - #address-cells = <1>; - #size-cells = <0>; - - watchdog@4 { - compatible = "kontron,sa67mcu-wdt", "kontron,sl28cpld-wdt"; - reg = <0x4>; - kontron,assert-wdt-timeout-pin; - }; - - hwmon@8 { - compatible = "kontron,sa67mcu-hwmon"; - reg = <0x8>; - }; - }; -}; - -/* I2C_CAM */ -&main_i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c2_pins_default>; - clock-frequency = <100000>; - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-names = "default"; - pinctrl-0 = <&i2c_mux_pins_default>; - - vdd-supply = <&vcc_1p8_s0>; - reset-gpios = <&main_gpio0 10 GPIO_ACTIVE_LOW>; - - i2c_cam0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - i2c_cam1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - i2c_cam2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - i2c_cam3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -/* I2C_LCD */ -&main_i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c3_pins_default>; - clock-frequency = <100000>; - status = "okay"; -}; - -&main_pmx0 { - audio_refclk0_pins_default: audio-refclk0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x0c4, PIN_OUTPUT, 5) /* (W23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */ - >; - }; - - audio_refclk1_pins_default: audio-refclk1-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ - >; - }; - - cpsw3g_mdio_pins_default: cpsw3g-mdio-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ - J722S_IOPAD(0x15c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ - >; - }; - - cpsw3g_pins_default: cpsw3g-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1b8, PIN_OUTPUT, 1) /* (C20) SPI0_CS1.CP_GEMAC_CPTS0_TS_COMP */ - >; - }; - - edp_bridge_pins_default: edp-bridge-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x098, PIN_OUTPUT, 7) /* (V21) GPMC0_WAIT0.GPIO0_37 */ - J722S_IOPAD(0x09c, PIN_INPUT, 7) /* (W26) GPMC0_WAIT1.GPIO0_38 */ - >; - }; - - i2c_mux_pins_default: i2c-mux-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x028, PIN_OUTPUT, 7) /* (M27) OSPI0_D7.GPIO0_10 */ - >; - }; - - lcd0_backlight_pins_default: lcd0-backlight-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x074, PIN_OUTPUT, 7) /* (V22) GPMC0_AD14.GPIO0_29 */ - J722S_IOPAD(0x110, PIN_OUTPUT, 4) /* (G27) MMC2_DAT1.EHRPWM1_A */ - >; - }; - - lcd1_backlight_pins_default: lcd1-backlight-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (E19) SPI0_D0.GPIO1_18 */ - J722S_IOPAD(0x114, PIN_OUTPUT, 4) /* (G26) MMC2_DAT0.EHRPWM1_B */ - >; - }; - - main_i2c0_pins_default: main-i2c0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1e0, PIN_INPUT, 0) /* (D23) I2C0_SCL */ - J722S_IOPAD(0x1e4, PIN_INPUT, 0) /* (B22) I2C0_SDA */ - >; - bootph-all; - }; - - main_i2c2_pins_default: main-i2c2-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x0b0, PIN_INPUT, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ - J722S_IOPAD(0x0b4, PIN_INPUT, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ - >; - }; - - main_i2c3_pins_default: main-i2c3-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1d0, PIN_INPUT, 2) /* (E22) UART0_CTSn.I2C3_SCL */ - J722S_IOPAD(0x1d4, PIN_INPUT, 2) /* (B21) UART0_RTSn.I2C3_SDA */ - >; - }; - - main_i2c4_pins_default: main-i2c4-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x0a8, PIN_INPUT, 1) /* (R27) GPMC0_CSn0.I2C4_SCL */ - J722S_IOPAD(0x0ac, PIN_INPUT, 1) /* (P21) GPMC0_CSn1.I2C4_SDA */ - >; - }; - - main_uart0_pins_default: main-uart0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1c8, PIN_INPUT, 0) /* (F19) UART0_RXD */ - J722S_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (F20) UART0_TXD */ - >; - bootph-all; - }; - - main_uart5_pins_default: main-uart5-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x108, PIN_INPUT, 3) /* (J27) MMC2_DAT3.UART5_RXD */ - J722S_IOPAD(0x10c, PIN_OUTPUT, 3) /* (H27) MMC2_DAT2.UART5_TXD */ - J722S_IOPAD(0x008, PIN_INPUT, 5) /* (L22) OSPI0_DQS.UART5_CTSn */ - J722S_IOPAD(0x004, PIN_OUTPUT, 5) /* (L23) OSPI0_LBCLKO.UART5_RTSn */ - >; - }; - - mcasp0_pins_default: mcasp0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1a4, PIN_INPUT, 0) /* (D25) MCASP0_ACLKX */ - J722S_IOPAD(0x1a8, PIN_INPUT, 0) /* (C26) MCASP0_AFSX */ - J722S_IOPAD(0x1a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ - J722S_IOPAD(0x19c, PIN_OUTPUT, 0) /* (B25) MCASP0_AXR1 */ - >; - }; - - mcasp2_pins_default: mcasp2-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x070, PIN_INPUT, 3) /* (V24) GPMC0_AD13.MCASP2_ACLKX */ - J722S_IOPAD(0x06c, PIN_INPUT, 3) /* (V26) GPMC0_AD12.MCASP2_AFSX */ - J722S_IOPAD(0x05c, PIN_INPUT, 3) /* (U27) GPMC0_AD8.MCASP2_AXR0 */ - J722S_IOPAD(0x060, PIN_OUTPUT, 3) /* (U26) GPMC0_AD9.MCASP2_AXR1 */ - >; - }; - - oldi0_pins_default: oldi0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x260, PIN_OUTPUT, 0) /* (AF23) OLDI0_A0N */ - J722S_IOPAD(0x25c, PIN_OUTPUT, 0) /* (AG24) OLDI0_A0P */ - J722S_IOPAD(0x268, PIN_OUTPUT, 0) /* (AG22) OLDI0_A1N */ - J722S_IOPAD(0x264, PIN_OUTPUT, 0) /* (AG23) OLDI0_A1P */ - J722S_IOPAD(0x270, PIN_OUTPUT, 0) /* (AB20) OLDI0_A2N */ - J722S_IOPAD(0x26c, PIN_OUTPUT, 0) /* (AB21) OLDI0_A2P */ - J722S_IOPAD(0x278, PIN_OUTPUT, 0) /* (AG20) OLDI0_A3N */ - J722S_IOPAD(0x274, PIN_OUTPUT, 0) /* (AG21) OLDI0_A3P */ - J722S_IOPAD(0x2a0, PIN_OUTPUT, 0) /* (AF21) OLDI0_CLK0N */ - J722S_IOPAD(0x29c, PIN_OUTPUT, 0) /* (AE20) OLDI0_CLK0P */ - >; - }; - - oldi1_pins_default: oldi1-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x280, PIN_OUTPUT, 0) /* (AD21) OLDI0_A4N */ - J722S_IOPAD(0x27c, PIN_OUTPUT, 0) /* (AC21) OLDI0_A4P */ - J722S_IOPAD(0x288, PIN_OUTPUT, 0) /* (AF19) OLDI0_A5N */ - J722S_IOPAD(0x284, PIN_OUTPUT, 0) /* (AF18) OLDI0_A5P */ - J722S_IOPAD(0x290, PIN_OUTPUT, 0) /* (AG17) OLDI0_A6N */ - J722S_IOPAD(0x28c, PIN_OUTPUT, 0) /* (AG18) OLDI0_A6P */ - J722S_IOPAD(0x298, PIN_OUTPUT, 0) /* (AB19) OLDI0_A7N */ - J722S_IOPAD(0x294, PIN_OUTPUT, 0) /* (AA20) OLDI0_A7P */ - J722S_IOPAD(0x2a8, PIN_OUTPUT, 0) /* (AD20) OLDI0_CLK1N */ - J722S_IOPAD(0x2a4, PIN_OUTPUT, 0) /* (AE19) OLDI0_CLK1P */ - >; - }; - - ospi0_pins_default: ospi0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ - J722S_IOPAD(0x02c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ - J722S_IOPAD(0x030, PIN_OUTPUT, 0) /* (K23) OSPI0_CSn1 */ - J722S_IOPAD(0x034, PIN_OUTPUT, 0) /* (K22) OSPI0_CSn2 */ - J722S_IOPAD(0x00c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ - J722S_IOPAD(0x010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ - J722S_IOPAD(0x014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ - J722S_IOPAD(0x018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ - >; - bootph-all; - }; - - pcie0_rc_pins_default: pcie0-rc-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x2ac, PIN_OUTPUT, 0) /* (F25) PCIE0_CLKREQn */ - J722S_IOPAD(0x1b4, PIN_OUTPUT, 7) /* (B20) SPI0_CS0.GPIO1_15 */ - >; - }; - - pmic_irq_pins_default: pmic-irq-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x090, PIN_INPUT, 7) /* (P27) GPMC0_BE0n_CLE.GPIO0_35 */ - >; - }; - - rgmii1_pins_default: rgmii1-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x14c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ - J722S_IOPAD(0x150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ - J722S_IOPAD(0x154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ - J722S_IOPAD(0x158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ - J722S_IOPAD(0x148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ - J722S_IOPAD(0x144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ - J722S_IOPAD(0x134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ - J722S_IOPAD(0x138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ - J722S_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ - J722S_IOPAD(0x140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ - J722S_IOPAD(0x130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ - J722S_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ - >; - }; - - rgmii2_pins_default: rgmii2-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x0f8, PIN_INPUT, 2) /* (AB24) VOUT0_HSYNC.RGMII2_RD0 */ - J722S_IOPAD(0x0fc, PIN_INPUT, 2) /* (AC27) VOUT0_DE.RGMII2_RD1 */ - J722S_IOPAD(0x100, PIN_INPUT, 2) /* (AB23) VOUT0_VSYNC.RGMII2_RD2 */ - J722S_IOPAD(0x104, PIN_INPUT, 2) /* (AC26) VOUT0_PCLK.RGMII2_RD3 */ - J722S_IOPAD(0x0f4, PIN_INPUT, 2) /* (AB27) VOUT0_DATA15.RGMII2_RXC */ - J722S_IOPAD(0x0f0, PIN_INPUT, 2) /* (AB26) VOUT0_DATA14.RGMII2_RX_CTL */ - J722S_IOPAD(0x0e0, PIN_OUTPUT, 2) /* (AA25) VOUT0_DATA10.RGMII2_TD0 */ - J722S_IOPAD(0x0e4, PIN_OUTPUT, 2) /* (AB25) VOUT0_DATA11.RGMII2_TD1 */ - J722S_IOPAD(0x0e8, PIN_OUTPUT, 2) /* (AA23) VOUT0_DATA12.RGMII2_TD2 */ - J722S_IOPAD(0x0ec, PIN_OUTPUT, 2) /* (AA22) VOUT0_DATA13.RGMII2_TD3 */ - J722S_IOPAD(0x0dc, PIN_OUTPUT, 2) /* (AA27) VOUT0_DATA9.RGMII2_TXC */ - J722S_IOPAD(0x0d8, PIN_OUTPUT, 2) /* (AA24) VOUT0_DATA8.RGMII2_TX_CTL */ - >; - }; - - rtc_pins_default: rtc-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 */ - >; - }; - - sdhci1_pins_default: sdhci1-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x23c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ - J722S_IOPAD(0x234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ - J722S_IOPAD(0x230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ - J722S_IOPAD(0x22c, PIN_INPUT, 0) /* (H20) MMC1_DAT1 */ - J722S_IOPAD(0x228, PIN_INPUT, 0) /* (J23) MMC1_DAT2 */ - J722S_IOPAD(0x224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ - J722S_IOPAD(0x240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ - J722S_IOPAD(0x244, PIN_INPUT, 0) /* (A24) MMC1_SDWP */ - >; - bootph-all; - }; - - usb0_connector_pins_default: usb0-connector-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x08c, PIN_INPUT_PULLUP, 7) /* (N23) GPMC0_WEn.GPIO0_34 */ - >; - }; - - usb1_pins_default: usb1-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x258, PIN_OUTPUT, 0) /* (B27) USB1_DRVVBUS */ - >; - }; - - vcc_3p3_sd_s0_pins_default: vcc-3p3-sd-s0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x01c, PIN_OUTPUT, 7) /* (L21) OSPI0_D4.GPIO0_7 */ - >; - bootph-all; - }; - - vcc_3p3_sd_vio_s0_pins_default: vcc-3p3-sd-vio-s0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x020, PIN_OUTPUT, 7) /* (M26) OSPI0_D5.GPIO0_8 */ - >; - bootph-all; - }; - - vcc_3p3_cam_s0_pins_default: vcc-3p3-cam-s0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1f0, PIN_OUTPUT, 7) /* (A23) EXT_REFCLK1.GPIO1_30 */ - >; - }; - - vcc_lcd0_panel_pins_default: vcc-lcd0-panel-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x078, PIN_OUTPUT, 7) /* (V23) GPMC0_AD15.GPIO0_30 */ - >; - }; - - vcc_lcd1_panel_pins_default: vcc-lcd1-panel-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (E20) SPI0_D1.GPIO1_19 */ - >; - }; - - vcc_usb0_vbus_pins_default: vcc-usb0-vbus-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */ - >; - }; -}; - -/* SER1 */ -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; - bootph-all; - status = "okay"; -}; - -/* SER2 */ -&main_uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&main_uart5_pins_default>; - bootph-all; - status = "okay"; -}; - -/* I2S0 */ -&mcasp0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp0_pins_default>; - op-mode = <0>; /* I2S */ - tdm-slots = <2>; - serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; -}; - -/* I2S2 */ -&mcasp2 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mcasp2_pins_default>; - op-mode = <0>; /* I2S */ - tdm-slots = <2>; - serial-dir = <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; -}; - -/* CAN0 */ -&mcu_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan0_pins_default>; - status = "okay"; -}; - -/* CAN1 */ -&mcu_mcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_mcan1_pins_default>; - status = "okay"; -}; - -&mcu_gpio0 { - gpio-line-names = - "", "", "", "", "", "", "", "", "", "", "", /* 10 */ "GPIO12", - "MCU_INT#", "", "", "", "", "", "", "", "", "", "", "GPIO13"; -}; - -/* I2C_GP */ -&mcu_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_i2c0_pins_default>; - clock-frequency = <100000>; - status = "okay"; - - /* SMARC Module EEPROM */ - eeprom@50 { - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - vcc-supply = <&vcc_1p8_s0>; - }; -}; - -&mcu_pmx0 { - mcu_i2c0_pins_default: mcu-i2c0-default-pins { - pinctrl-single,pins = < - J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ - J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ - >; - }; - mcu_mcan0_pins_default: mcu-mcan0-default-pins { - pinctrl-single,pins = < - J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ - J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ - >; - }; - - mcu_mcan1_pins_default: mcu-mcan1-default-pins { - pinctrl-single,pins = < - J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ - J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /* (C1) MCU_MCAN1_TX */ - >; - }; - - mcu_uart0_pins_default: mcu-uart0-default-pins { - pinctrl-single,pins = < - J722S_MCU_IOPAD(0x014, PIN_INPUT, 0) /* (B8) MCU_UART0_RXD */ - J722S_MCU_IOPAD(0x018, PIN_OUTPUT, 0) /* (B4) MCU_UART0_TXD */ - J722S_MCU_IOPAD(0x01c, PIN_INPUT, 0) /* (B5) MCU_UART0_CTSn */ - J722S_MCU_IOPAD(0x020, PIN_OUTPUT, 0) /* (C5) MCU_UART0_RTSn */ - >; - bootph-all; - }; - - mcu_spi0_pins_default: mcu-spi0-default-pins { - pinctrl-single,pins = < - J722S_MCU_IOPAD(0x008, PIN_OUTPUT, 0) /* (A9) MCU_SPI0_CLK */ - J722S_MCU_IOPAD(0x000, PIN_OUTPUT, 0) /* (C12) MCU_SPI0_CS0 */ - J722S_MCU_IOPAD(0x004, PIN_OUTPUT, 0) /* (A10) MCU_SPI0_CS1 */ - J722S_MCU_IOPAD(0x00c, PIN_INPUT, 0) /* (B12) MCU_SPI0_D0 */ - J722S_MCU_IOPAD(0x010, PIN_OUTPUT, 0) /* (C11) MCU_SPI0_D1 */ - >; - }; - - wkup_uart0_pins_default: wkup-uart0-default-pins { - pinctrl-single,pins = < - J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B3) WKUP_UART0_RXD */ - J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_TXD */ - >; - bootph-all; - }; - - wkup_i2c0_pins_default: wkup-i2c0-default-pins { - pinctrl-single,pins = < - J722S_MCU_IOPAD(0x04c, PIN_INPUT, 0) /* (B9) WKUP_I2C0_SCL */ - J722S_MCU_IOPAD(0x050, PIN_INPUT, 0) /* (D11) WKUP_I2C0_SDA */ - >; - }; -}; - -/* SPI0 */ -&mcu_spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_spi0_pins_default>; -}; - -/* SER0 */ -&mcu_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_uart0_pins_default>; - bootph-all; - status = "okay"; -}; - -/* QSPI0 */ -&ospi0 { - pinctrl-0 = <&ospi0_pins_default>; - pinctrl-names = "default"; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <104000000>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <2>; - m25p,fast-read; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <3>; - vcc-supply = <&vcc_1p8_s0>; - bootph-all; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - reg = <0x000000 0x400000>; - label = "failsafe bootloader"; - read-only; - }; - }; - - otp-1 { - compatible = "user-otp"; - - nvmem-layout { - compatible = "kontron,sa67-vpd", "kontron,sl28-vpd"; - - serial_number: serial-number { - }; - - base_mac_address: base-mac-address { - #nvmem-cell-cells = <1>; - }; - }; - }; - }; -}; - -&pcie0_rc { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_rc_pins_default>; - - /* - * This is low active, but the driver itself is broken and already - * inverts the logic. - */ - reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; - phys = <&serdes1_pcie>; - phy-names = "pcie-phy"; - status = "okay"; -}; - -&sdhci0 { - disable-wp; - bootph-all; - ti,driver-strength-ohm = <50>; - status = "okay"; -}; - -/* SDIO */ -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&sdhci1_pins_default>; - vmmc-supply = <&vcc_3p3_sd_s0>; - vqmmc-supply = <&vcc_3p3_sd_vio_s0>; - bootph-all; - cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; - cd-debounce-delay-ms = <100>; - ti,fails-without-test-cd; - ti,driver-strength-ohm = <50>; - status = "okay"; -}; - -&serdes_ln_ctrl { - idle-states = , - ; -}; - -&serdes_wiz0 { - status = "okay"; -}; - -&serdes_wiz1 { - status = "okay"; -}; - -&serdes0 { - serdes0_usb3: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&serdes_wiz0 1>; - cdns,num-lanes = <1>; - cdns,phy-type = ; - }; -}; - -&serdes1 { - serdes1_pcie: phy@0 { - reg = <0>; - #phy-cells = <0>; - resets = <&serdes_wiz1 1>; - cdns,num-lanes = <1>; - cdns,phy-type = ; - }; -}; - -&usb0 { - /* dual role is implemented but not a full featured OTG */ - adp-disable; - hnp-disable; - srp-disable; - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - status = "okay"; - - port { - usb0_hc: endpoint { - remote-endpoint = <&usb0_connector>; - }; - }; -}; - -&usb0_phy_ctrl { - /* - * Keep this node in the SPL to be able to use the USB controller to - * boot via DFU. - */ - bootph-all; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_default>; - - dr_mode = "host"; - maximum-speed = "super-speed"; - phys = <&serdes0_usb3>; - phy-names = "cdns3,usb3-phy"; -}; - -&usbss0 { - ti,vbus-divider; - status = "okay"; -}; - -&usbss1 { - ti,vbus-divider; - status = "okay"; -}; - -/* I2C_PM */ -&wkup_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <100000>; - status = "okay"; -}; - -/* SER3 */ -&wkup_uart0 { - /* WKUP UART0 is used by Device Manager firmware */ - pinctrl-names = "default"; - pinctrl-0 = <&wkup_uart0_pins_default>; - bootph-all; - status = "reserved"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso deleted file mode 100644 index 5dfb0b8f10d2..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Second ethernet port GBE1. - * - * Copyright (c) 2025 Kontron Europe GmbH - */ - -/dts-v1/; -/plugin/; - -&cpsw3g_mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&cpsw_port2 { - phy-connection-type = "rgmii-id"; - phy-handle = <&phy1>; - nvmem-cells = <&base_mac_address 1>; - nvmem-cell-names = "mac-address"; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gpios.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gpios.dtso deleted file mode 100644 index a6ae758e0b3a..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gpios.dtso +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * SMARC GPIOs. - * - * Copyright (c) 2025 Kontron Europe GmbH - */ - -/dts-v1/; -/plugin/; - -#include -#include "k3-pinctrl.h" - -&main_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_gpio0_pins_default>; -}; - -&main_gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&main_gpio1_pins_default>; -}; - -&main_pmx0 { - main_gpio0_pins_default: main-gpio0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x0d0, PIN_INPUT, 7) /* (Y26) VOUT0_DATA6.GPIO0_51 */ - J722S_IOPAD(0x0d4, PIN_INPUT, 7) /* (Y27) VOUT0_DATA7.GPIO0_52 */ - J722S_IOPAD(0x118, PIN_INPUT, 7) /* (H26) MMC2_CLK.GPIO0_69 */ - J722S_IOPAD(0x120, PIN_INPUT, 7) /* (F27) MMC2_CMD.GPIO0_70 */ - >; - }; - - main_gpio1_pins_default: main-gpio1-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x194, PIN_INPUT, 7) /* (A25) MCASP0_AXR3.GPIO1_7 */ - J722S_IOPAD(0x198, PIN_INPUT, 7) /* (A26) MCASP0_AXR2.GPIO1_8 */ - J722S_IOPAD(0x1ac, PIN_INPUT, 7) /* (C27) MCASP0_AFSR.GPIO1_13 */ - J722S_IOPAD(0x1b0, PIN_INPUT, 7) /* (F24) MCASP0_ACLKR.GPIO1_14 */ - J722S_IOPAD(0x1d8, PIN_INPUT, 7) /* (D22) MCAN0_TX.GPIO1_24 */ - J722S_IOPAD(0x1dc, PIN_INPUT, 7) /* (C22) MCAN0_RX.GPIO1_25 */ - J722S_IOPAD(0x1e8, PIN_INPUT, 7) /* (C24) I2C1_SCL.GPIO1_28 */ - J722S_IOPAD(0x1ec, PIN_INPUT, 7) /* (A22) I2C1_SDA.GPIO1_29 */ - >; - }; -}; - -&mcu_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&mcu_gpio0_pins_default>; -}; - -&mcu_pmx0 { - mcu_gpio0_pins_default: mcu-gpio0-default-pins { - pinctrl-single,pins = < - J722S_IOPAD(0x02c, PIN_INPUT, 7) /* (C4) WKUP_UART0_CTSn.MCU_GPIO0_11 */ - J722S_IOPAD(0x084, PIN_INPUT, 7) /* (F12) WKUP_CLKOUT0.MCU_GPIO0_23 */ - >; - }; - -}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso deleted file mode 100644 index 0a3e9f614c4c..000000000000 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only OR MIT -/* - * Microcrystal RV8263 RTC variant. - * - * Copyright (c) 2025 Kontron Europe GmbH - */ - -/dts-v1/; -/plugin/; - -#include - -&{/} { - aliases { - rtc0 = "/bus@f0000/i2c@20000000/rtc@51"; /* &rtc */ - rtc1 = "/bus@f0000/bus@b00000/rtc@2b1f0000"; /* &wkup_rtc0 */ - }; -}; - -&main_i2c0 { - #address-cells = <1>; - #size-cells = <0>; - - rtc: rtc@51 { - compatible = "microcrystal,rv8263"; - reg = <0x51>; - pinctrl-names = "default"; - pinctrl-0 = <&rtc_pins_default>; - interrupts-extended = <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>; - }; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006.dtso b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006.dtso new file mode 100644 index 000000000000..9eb28aa9e8ef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-lvds-ph128800t006.dtso @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + backlight_lvds: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <6>; + enable-gpios = <&exp2 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins_default>; + power-supply = <&bl_12v>; + pwms = <&main_ehrpwm0 1 44000 0>; + }; + + bl_12v: regulator-backlight { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&exp2 13 GPIO_ACTIVE_HIGH>; + regulator-name = "BL_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + panel-lvds { + compatible = "powertip,ph128800t006-zhc01"; + backlight = <&backlight_lvds>; + power-supply = <&vcc_5v0>; + + port { + panel_in: endpoint { + remote-endpoint = <&panel_bridge_out>; + }; + }; + }; +}; + +&main_pmx0 { + backlight_pins_default: backlight-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x064, PIN_OUTPUT, 9) /* (W28) MCAN0_TX.EHRPWM0_B */ + >; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_out: endpoint { + remote-endpoint = <&panel_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&main_ehrpwm0 { + status = "okay"; +}; + +&sn65dsi83 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + panel_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-peb-av-15.dtso b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-peb-av-15.dtso new file mode 100644 index 000000000000..92007bfd5d53 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-peb-av-15.dtso @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + audio_refclk1: audio-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + hdmi: hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&main_i2c2>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <<8912b_out>; + }; + }; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_AUDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "PEB-AV-15"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + + link0_cpu: simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&audio_codec>; + clocks = <&audio_refclk1>; + }; + }; + +}; + +&dphy_tx1 { + status = "okay"; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi1_ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dsi1_out: endpoint { + remote-endpoint = <<8912b_in>; + }; + }; + + port@1 { + reg = <1>; + dsi1_in: endpoint { + remote-endpoint = <&dpi3_out>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + dpi3_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + + #sound-dai-cells = <0>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 2 0 0 1 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + + tx-num-evt = <32>; + rx-num-evt = <32>; + status = "okay"; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + audio_codec: audio-codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + #sound-dai-cells = <0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_audio_3v3>; + IOVDD-supply = <®_audio_3v3>; + DRVDD-supply = <®_audio_3v3>; + DVDD-supply = <®_audio_1v8>; + }; + + bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt8912b_in: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&dsi1_out>; + }; + }; + + port@1 { + reg = <1>; + lt8912b_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&main_pmx0 { + mcasp0_pins: mcasp0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x03c, PIN_INPUT, 1) /* (U27) WCLK, MCASP0_AFSX.MCASP0_AFSX */ + J721S2_IOPAD(0x038, PIN_INPUT, 1) /* (AB28) BCLK, MCASP0_ACLKX.MCASP0_ACLKX */ + J721S2_IOPAD(0x040, PIN_OUTPUT, 1) /* (AC28) DOUT, MCASP0_AXR0.MCASP0_AXR0 */ + J721S2_IOPAD(0x07c, PIN_INPUT, 1) /* (T27) DIN, MCASP0_AXR3.MCASP0_AXR3 */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts index e221ccb30e95..225fe7a7803b 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts @@ -298,6 +298,23 @@ phy0: ethernet-phy@0 { }; }; +&dss { + /* + * VP0 - Displayport + * VP1 - DPI0 + * VP2 - DSI0 + * VP3 - DPI1/DSI1 + */ + assigned-clocks = <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + assigned-clock-parents = <&k3_clks 158 3>, + <&k3_clks 158 7>, + <&k3_clks 158 16>, + <&k3_clks 158 22>; +}; + &i2c_som_rtc { trickle-resistor-ohms = <3000>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi index 0ff511028f81..ab87767419fe 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -151,6 +151,12 @@ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27) WKUP_I2C0_SDA */ >; bootph-all; }; + + wkup_sn65dsi83_pins_default: wkup-sn65dsi83-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x084, PIN_OUTPUT, 7) /* (F25) WKUP_GPIO0_11 */ + >; + }; }; &main_cpsw { @@ -183,6 +189,17 @@ &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; + sn65dsi83: bridge@2d { + compatible = "ti,sn65dsi83"; + reg = <0x2d>; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_sn65dsi83_pins_default>; + enable-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_LOW>; + vcc-supply = <&bucka4>; + /* enabled in panel overlay */ + status = "disabled"; + }; + temperature-sensor@48 { compatible = "ti,tmp102"; reg = <0x48>; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts index ec8ff4587715..dc0d3cf2f985 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts @@ -26,7 +26,7 @@ reg_3v3_dp: regulator-3v3-dp { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_21_dp>; /* Aquila GPIO_21_DP (AQUILA B57) */ - gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + gpio = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts b/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts index f48601ae38b7..d3677c2c2547 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts @@ -33,7 +33,7 @@ reg_3v3_dp: regulator-3v3-dp { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_21_dp>; /* Aquila GPIO_21_DP (AQUILA B57) */ - gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; + gpio = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 3e5efdfe87f1..54dea36b153b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -331,6 +331,7 @@ phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; + ti,min-output-impedance; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 628ff89dd72f..67fde5667b8d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -25,9 +25,8 @@ atf-sram@0 { }; }; - scm_conf: scm-conf@100000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00100000 0x00 0x1c000>; + scm_conf: bus@100000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi index 9477f1efbbc6..d65f68c7d432 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi @@ -100,6 +100,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -107,6 +108,7 @@ &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -119,6 +121,7 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -126,5 +129,6 @@ &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 47702fb279a4..53e7fbcef52b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -777,6 +777,7 @@ phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; + ti,min-output-impedance; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi index 40c6cc99c405..5d4fc26b413b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi @@ -219,6 +219,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; }; &mcu_r5fss0_core1 { @@ -226,6 +227,7 @@ &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss0 { @@ -238,6 +240,7 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss0_core1 { @@ -245,6 +248,7 @@ &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss1 { @@ -257,6 +261,7 @@ &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss1_core1 { @@ -264,6 +269,7 @@ &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + memory-region-names = "dma", "firmware"; }; &c66_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 4fea99519113..19c5157510b2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -530,6 +530,48 @@ flash@0 { cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "qspi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "qspi.phypattern"; + reg = <0x3fc0000 0x40000>; + bootph-all; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 80c51b11ac9f..1228ac5711bf 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -37,9 +37,8 @@ l3cache-sram@200000 { }; }; - scm_conf: syscon@104000 { - compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; - reg = <0x00 0x00104000 0x00 0x18000>; + scm_conf: bus@104000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00104000 0x18000>; @@ -175,7 +174,7 @@ main_gpio_intr: interrupt-controller@a00000 { }; main_pmx0: pinctrl@11c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x0 0x11c000 0x0 0x120>; #pinctrl-cells = <1>; @@ -185,7 +184,7 @@ main_pmx0: pinctrl@11c000 { /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ main_timerio_input: pinctrl@104200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x104200 0x00 0x50>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -194,7 +193,7 @@ main_timerio_input: pinctrl@104200 { /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ main_timerio_output: pinctrl@104280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x104280 0x00 0x20>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -1815,6 +1814,19 @@ dphy_tx0: phy@4480000 { status = "disabled"; }; + dphy_tx1: phy@4481000 { + compatible = "ti,j721e-dphy"; + reg = <0x00 0x04481000 0x00 0x00001000>; + clocks = <&k3_clks 364 8>, <&k3_clks 364 14>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 364 14>; + assigned-clock-parents = <&k3_clks 364 15>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + dsi0: dsi@4800000 { compatible = "ti,j721e-dsi"; reg = <0x00 0x04800000 0x00 0x00100000>, @@ -1841,6 +1853,32 @@ port@1 { }; }; + dsi1: dsi@4900000 { + compatible = "ti,j721e-dsi"; + reg = <0x00 0x04900000 0x00 0x00100000>, + <0x00 0x04720000 0x00 0x00000100>; + clocks = <&k3_clks 155 4>, <&k3_clks 155 1>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + phys = <&dphy_tx1>; + phy-names = "dphy"; + status = "disabled"; + + dsi1_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 32ee8031cfcb..27b8e7440246 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -76,7 +76,7 @@ mcu_ram: sram@41c00000 { }; wkup_pmx0: pinctrl@4301c000 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c000 0x00 0x034>; #pinctrl-cells = <1>; @@ -85,7 +85,7 @@ wkup_pmx0: pinctrl@4301c000 { }; wkup_pmx1: pinctrl@4301c038 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x02c>; #pinctrl-cells = <1>; @@ -94,7 +94,7 @@ wkup_pmx1: pinctrl@4301c038 { }; wkup_pmx2: pinctrl@4301c068 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0x120>; #pinctrl-cells = <1>; @@ -103,7 +103,7 @@ wkup_pmx2: pinctrl@4301c068 { }; wkup_pmx3: pinctrl@4301c190 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; @@ -113,7 +113,7 @@ wkup_pmx3: pinctrl@4301c190 { /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ mcu_timerio_input: pinctrl@40f04200 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x40f04200 0x00 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; @@ -124,7 +124,7 @@ mcu_timerio_input: pinctrl@40f04200 { /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ mcu_timerio_output: pinctrl@40f04280 { - compatible = "pinctrl-single"; + compatible = "ti,j7200-padconf", "pinctrl-single"; reg = <0x00 0x40f04280 0x00 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi index ebab0cc580bb..5253d028da09 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi @@ -190,6 +190,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -197,6 +198,7 @@ &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -209,6 +211,7 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -216,6 +219,7 @@ &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -228,6 +232,7 @@ &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -235,6 +240,7 @@ &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 9ee5d0c8ffd1..ddf20e44f0ea 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -154,6 +154,19 @@ usb1: usb@31200000 { }; }; + main_i2c4: i2c@fe80000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x0fe80000 0x00 0x100>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <178 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 257 2>; + clock-names = "fck"; + status = "disabled"; + }; + ti_csi2rx1: ticsi2rx@30122000 { compatible = "ti,j721e-csi2rx-shim"; reg = <0x00 0x30122000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi index cb7cd385a165..a59c3648d805 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi @@ -123,6 +123,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -134,6 +135,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; @@ -145,6 +147,7 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index 059c65ece183..1b36dcf37925 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -160,7 +160,8 @@ cbass_main: bus@f0000 { <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ - <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x0fe00000 0x00 0x0fe00000 0x00 0x000f0400>, /* Third peripheral window */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Fourth peripheral window */ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi index 455397227d4a..d08fd3ff8a89 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi @@ -262,6 +262,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; }; &mcu_r5fss0_core1 { @@ -269,6 +270,7 @@ &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss0 { @@ -281,6 +283,7 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss0_core1 { @@ -288,6 +291,7 @@ &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss1 { @@ -300,6 +304,7 @@ &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss1_core1 { @@ -307,6 +312,7 @@ &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss2 { @@ -319,6 +325,7 @@ &main_r5fss2_core0 { mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; memory-region = <&main_r5fss2_core0_dma_memory_region>, <&main_r5fss2_core0_memory_region>; + memory-region-names = "dma", "firmware"; }; &main_r5fss2_core1 { @@ -326,6 +333,7 @@ &main_r5fss2_core1 { mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; memory-region = <&main_r5fss2_core1_dma_memory_region>, <&main_r5fss2_core1_memory_region>; + memory-region-names = "dma", "firmware"; }; &c71_0 { diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index dc8e03ae74c8..4491898d8294 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -8,23 +8,23 @@ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H -#define WKUP_LVL_EN_SHIFT (7) -#define WKUP_LVL_POL_SHIFT (8) +#define WKUP_LVL_EN_SHIFT (7) +#define WKUP_LVL_POL_SHIFT (8) +#define DEBOUNCE_SHIFT (11) #define ST_EN_SHIFT (14) +#define FORCE_DS_EN_SHIFT (15) #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) -#define DRV_STR_SHIFT (19) -#define ISO_OVERRIDE_EN_SHIFT (22) -#define ISO_BYPASS_EN_SHIFT (23) -#define DEBOUNCE_SHIFT (11) -#define FORCE_DS_EN_SHIFT (15) +#define DRV_STR_SHIFT (19) +#define ISO_OVERRIDE_EN_SHIFT (22) +#define ISO_BYPASS_EN_SHIFT (23) #define DS_EN_SHIFT (24) #define DS_OUT_DIS_SHIFT (25) #define DS_OUT_VAL_SHIFT (26) #define DS_PULLUD_EN_SHIFT (27) #define DS_PULLTYPE_SEL_SHIFT (28) -#define WKUP_EN_SHIFT (29) +#define WKUP_EN_SHIFT (29) /* Schmitt trigger configuration */ #define ST_DISABLE (0 << ST_EN_SHIFT) @@ -39,28 +39,28 @@ #define INPUT_EN (1 << RXACTIVE_SHIFT) #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) -#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT) -#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT) +#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT) -#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) -#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) +#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) +#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) -#define DS_STATE_EN (1 << DS_EN_SHIFT) -#define DS_STATE_DISABLE (0 << DS_EN_SHIFT) +#define DS_STATE_EN (1 << DS_EN_SHIFT) +#define DS_STATE_DISABLE (0 << DS_EN_SHIFT) -#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT | DS_STATE_EN) -#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT | DS_STATE_EN) +#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT | DS_STATE_EN) +#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT | DS_STATE_EN) -#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) -#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) +#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) /* Configuration to enable wake-up on pin activity */ -#define WKUP_ENABLE (1 << WKUP_EN_SHIFT) -#define WKUP_DISABLE (0 << WKUP_EN_SHIFT) -#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT) -#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT) -#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT) -#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT) +#define WKUP_ENABLE (1 << WKUP_EN_SHIFT) +#define WKUP_DISABLE (0 << WKUP_EN_SHIFT) +#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT) +#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT) +#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT) +#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT) /* Only these macros are expected be used directly in device tree files */ #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) @@ -82,14 +82,14 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) -#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT) -#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT) -#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT) #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) -#define PIN_DS_ISO_OVERRIDE_DISABLE (0 << ISO_OVERRIDE_EN_SHIFT) -#define PIN_DS_ISO_OVERRIDE_ENABLE (1 << ISO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_DISABLE (0 << ISO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_ENABLE (1 << ISO_OVERRIDE_EN_SHIFT) #define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) @@ -98,18 +98,18 @@ #define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT) #define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT) #define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT) -#define PIN_DS_ISO_BYPASS (1 << ISO_BYPASS_EN_SHIFT) -#define PIN_DS_ISO_BYPASS_DISABLE (0 << ISO_BYPASS_EN_SHIFT) +#define PIN_DS_ISO_BYPASS (1 << ISO_BYPASS_EN_SHIFT) +#define PIN_DS_ISO_BYPASS_DISABLE (0 << ISO_BYPASS_EN_SHIFT) -#define PIN_DS_OUTPUT_LOW (DS_INPUT_DISABLE | DS_OUT_VALUE_ZERO) -#define PIN_DS_OUTPUT_HIGH (DS_INPUT_DISABLE | DS_OUT_VALUE_ONE) -#define PIN_DS_INPUT (DS_INPUT_EN | DS_PULL_DISABLE) -#define PIN_DS_INPUT_PULLUP (DS_INPUT_EN | DS_PULL_UP) -#define PIN_DS_INPUT_PULLDOWN (DS_INPUT_EN | DS_PULL_DOWN) +#define PIN_DS_OUTPUT_LOW (DS_INPUT_DISABLE | DS_OUT_VALUE_ZERO) +#define PIN_DS_OUTPUT_HIGH (DS_INPUT_DISABLE | DS_OUT_VALUE_ONE) +#define PIN_DS_INPUT (DS_INPUT_EN | DS_PULL_DISABLE) +#define PIN_DS_INPUT_PULLUP (DS_INPUT_EN | DS_PULL_UP) +#define PIN_DS_INPUT_PULLDOWN (DS_INPUT_EN | DS_PULL_DOWN) -#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_LOW) -#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH) -#define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE) +#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_LOW) +#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH) +#define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE) /* Default mux configuration for gpio-ranges to use with pinctrl */ #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 570624e1d0ee..6e820d4931dd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -482,6 +482,7 @@ CONFIG_TOUCHSCREEN_APPLE_Z2=m CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_GOODIX=m CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m +CONFIG_TOUCHSCREEN_ILI210X=m CONFIG_TOUCHSCREEN_ELAN=m CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m @@ -977,6 +978,8 @@ CONFIG_DRM_SUN8I_DW_HDMI=m CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m +CONFIG_DRM_STM=m +CONFIG_DRM_STM_LVDS=m CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m @@ -1053,6 +1056,7 @@ CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_APPLE_DWI=m CONFIG_BACKLIGHT_QCOM_WLED=m CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_GPIO=m CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 345ed7a48cc1..43f91cbf338b 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb -dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-disco-kit.dtb -dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb -dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb -dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb -dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb -dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb -dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-beaglev-fire.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-disco-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-icicle-kit-prod.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-m100pfsevp.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-polarberry.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-sev-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += mpfs-tysom-m.dtb +dtb-$(CONFIG_ARCH_MICROCHIP) += pic64gx-curiosity-kit.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index f44ad8e6f4e4..0e1b0b8d394b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -164,6 +164,35 @@ imx219_0: endpoint { }; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &mac0 { status = "okay"; phy-mode = "sgmii"; diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts index c068b9bb5bfd..f769c9d5d7b4 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts @@ -97,24 +97,10 @@ &core_pwm0 { }; &gpio1 { - interrupts = <27>, <28>, <29>, <30>, - <31>, <32>, <33>, <47>, - <35>, <36>, <37>, <38>, - <39>, <40>, <41>, <42>, - <43>, <44>, <45>, <46>, - <47>, <48>, <49>, <50>; status = "okay"; }; &gpio2 { - interrupts = <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; status = "okay"; }; @@ -130,6 +116,35 @@ &ihc { status = "okay"; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &mac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index e01a216e6c3a..7816408343a3 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -3,7 +3,6 @@ /dts-v1/; -#include "mpfs.dtsi" #include "mpfs-icicle-kit-fabric.dtsi" #include #include @@ -77,14 +76,6 @@ &core_pwm0 { }; &gpio2 { - interrupts = <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; status = "okay"; }; @@ -136,6 +127,35 @@ &ihc { status = "okay"; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &mac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 71f724325578..2d14e92f068d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -1,6 +1,9 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright (c) 2020-2021 Microchip Technology Inc */ +#include "mpfs.dtsi" +#include "mpfs-pinctrl.dtsi" + / { core_pwm0: pwm@40000000 { compatible = "microchip,corepwm-rtl-v4"; @@ -80,6 +83,16 @@ refclk_ccc: clock-cccref { }; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_fabric>; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&ikrd_can1_cfg>; +}; + &ccc_nw { clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>; @@ -87,3 +100,53 @@ &ccc_nw { "dll0_ref", "dll1_ref"; status = "okay"; }; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_fabric>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_mssio>; +}; + +&mmuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_fabric>; +}; + +&mmuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_fabric>; +}; + +&mmuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_fabric>; +}; + +&mmuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_fabric>; +}; + +&mssio { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_mssio>, <&can1_mssio>, <&mdio0_mssio>, <&mdio1_mssio>; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_fabric>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_fabric>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&ikrd_spi1_cfg>; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts index a8d623ee9fa4..86234968df48 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts @@ -52,11 +52,36 @@ &i2c1 { status = "okay"; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &gpio0 { - interrupts = <13>, <14>, <15>, <16>, - <17>, <18>, <19>, <20>, - <21>, <22>, <23>, <24>, - <25>, <26>; ngpios = <14>; status = "okay"; @@ -75,14 +100,6 @@ mmc-sel-hog { }; &gpio2 { - interrupts = <13>, <14>, <15>, <16>, - <17>, <18>, <19>, <20>, - <21>, <22>, <23>, <24>, - <25>, <26>, <27>, <28>, - <29>, <30>, <31>, <32>, - <33>, <34>, <35>, <36>, - <37>, <38>, <39>, <40>, - <41>, <42>, <43>, <44>; status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi b/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi new file mode 100644 index 000000000000..d37cabc6438a --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-pinctrl.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +&iomux0 { + spi0_fabric: mux-spi0-fabric { + function = "spi0"; + groups = "spi0_fabric"; + }; + + spi0_mssio: mux-spi0-mssio { + function = "spi0"; + groups = "spi0_mssio"; + }; + + spi1_fabric: mux-spi1-fabric { + function = "spi1"; + groups = "spi1_fabric"; + }; + + spi1_mssio: mux-spi1-mssio { + function = "spi1"; + groups = "spi1_mssio"; + }; + + i2c0_fabric: mux-i2c0-fabric { + function = "i2c0"; + groups = "i2c0_fabric"; + }; + + i2c0_mssio: mux-i2c0-mssio { + function = "i2c0"; + groups = "i2c0_mssio"; + }; + + i2c1_fabric: mux-i2c1-fabric { + function = "i2c1"; + groups = "i2c1_fabric"; + }; + + i2c1_mssio: mux-i2c1-mssio { + function = "i2c1"; + groups = "i2c1_mssio"; + }; + + can0_fabric: mux-can0-fabric { + function = "can0"; + groups = "can0_fabric"; + }; + + can0_mssio: mux-can0-mssio { + function = "can0"; + groups = "can0_mssio"; + }; + + can1_fabric: mux-can1-fabric { + function = "can1"; + groups = "can1_fabric"; + }; + + can1_mssio: mux-can1-mssio { + function = "can1"; + groups = "can1_mssio"; + }; + + qspi_fabric: mux-qspi-fabric { + function = "qspi"; + groups = "qspi_fabric"; + }; + + qspi_mssio: mux-qspi-mssio { + function = "qspi"; + groups = "qspi_mssio"; + }; + + uart0_fabric: mux-uart0-fabric { + function = "uart0"; + groups = "uart0_fabric"; + }; + + uart0_mssio: mux-uart0-mssio { + function = "uart0"; + groups = "uart0_mssio"; + }; + + uart1_fabric: mux-uart1-fabric { + function = "uart1"; + groups = "uart1_fabric"; + }; + + uart1_mssio: mux-uart1-mssio { + function = "uart1"; + groups = "uart1_mssio"; + }; + + uart2_fabric: mux-uart2-fabric { + function = "uart2"; + groups = "uart2_fabric"; + }; + + uart2_mssio: mux-uart2-mssio { + function = "uart2"; + groups = "uart2_mssio"; + }; + + uart3_fabric: mux-uart3-fabric { + function = "uart3"; + groups = "uart3_fabric"; + }; + + uart3_mssio: mux-uart3-mssio { + function = "uart3"; + groups = "uart3_mssio"; + }; + + uart4_fabric: mux-uart4-fabric { + function = "uart4"; + groups = "uart4_fabric"; + }; + + uart4_mssio: mux-uart4-mssio { + function = "uart4"; + groups = "uart4_mssio"; + }; + + mdio0_fabric: mux-mdio0-fabric { + function = "mdio0"; + groups = "mdio0_fabric"; + }; + + mdio0_mssio: mux-mdio0-mssio { + function = "mdio0"; + groups = "mdio0_mssio"; + }; + + mdio1_fabric: mux-mdio1-fabric { + function = "mdio1"; + groups = "mdio1_fabric"; + }; + + mdio1_mssio: mux-mdio1-mssio { + function = "mdio1"; + groups = "mdio1_mssio"; + }; +}; + +&mssio { + ikrd_can1_cfg: ikrd-can1-cfg { + can1-pins { + pins = <34>, <35>, <36>; + function = "can"; + bias-pull-up; + drive-strength = <8>; + power-source = <3300000>; + microchip,ibufmd = <0x1>; + }; + }; + + ikrd_spi1_cfg: ikrd-spi1-cfg { + spi1-pins { + pins = <30>, <31>, <32>, <33>; + function = "spi"; + bias-pull-up; + drive-strength = <8>; + power-source = <3300000>; + microchip,ibufmd = <0x1>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts index ea0808ab1042..510d59153cd0 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -30,6 +30,35 @@ ddrc_cache_hi: memory@1000000000 { }; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + /* * phy0 is connected to mac0, but the port itself is on the (optional) carrier * board. diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts index f9a890579438..8f1908a10567 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts @@ -56,15 +56,36 @@ &i2c0 { status = "okay"; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &gpio2 { - interrupts = <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts index d1120f5f2c01..bc15530a2979 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -69,13 +69,36 @@ hwmon: hwmon@45 { }; }; +&irqmux { + interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>, + <3 &plic 16>, <4 &plic 17>, <5 &plic 18>, + <6 &plic 19>, <7 &plic 20>, <8 &plic 21>, + <9 &plic 22>, <10 &plic 23>, <11 &plic 24>, + <12 &plic 25>, <13 &plic 26>, + + <32 &plic 27>, <33 &plic 28>, <34 &plic 29>, + <35 &plic 30>, <36 &plic 31>, <37 &plic 32>, + <38 &plic 33>, <39 &plic 34>, <40 &plic 35>, + <41 &plic 36>, <42 &plic 37>, <43 &plic 38>, + <44 &plic 39>, <45 &plic 40>, <46 &plic 41>, + <47 &plic 42>, <48 &plic 43>, <49 &plic 44>, + <50 &plic 45>, <51 &plic 46>, <52 &plic 47>, + <53 &plic 48>, <54 &plic 49>, <55 &plic 50>, + + <64 &plic 53>, <65 &plic 53>, <66 &plic 53>, + <67 &plic 53>, <68 &plic 53>, <69 &plic 53>, + <70 &plic 53>, <71 &plic 53>, <72 &plic 53>, + <73 &plic 53>, <74 &plic 53>, <75 &plic 53>, + <76 &plic 53>, <77 &plic 53>, <78 &plic 53>, + <79 &plic 53>, <80 &plic 53>, <81 &plic 53>, + <82 &plic 53>, <83 &plic 53>, <84 &plic 53>, + <85 &plic 53>, <86 &plic 53>, <87 &plic 53>, + <88 &plic 53>, <89 &plic 53>, <90 &plic 53>, + <91 &plic 53>, <92 &plic 53>, <93 &plic 53>, + <94 &plic 53>, <95 &plic 53>; +}; + &gpio1 { - interrupts = <27>, <28>, <29>, <30>, - <31>, <32>, <33>, <47>, - <35>, <36>, <37>, <38>, - <39>, <40>, <41>, <42>, - <43>, <44>, <45>, <46>, - <47>, <48>, <49>, <50>; status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index a0ffedc2d344..d535d4c72763 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -254,7 +254,31 @@ pdma: dma-controller@3000000 { mss_top_sysreg: syscon@20002000 { compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; reg = <0x0 0x20002000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; #reset-cells = <1>; + + irqmux: interrupt-controller@54 { + compatible = "microchip,mpfs-irqmux"; + reg = <0x54 0x4>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x7f>; + }; + + iomux0: pinctrl@200 { + compatible = "microchip,mpfs-pinctrl-iomux0"; + reg = <0x200 0x4>; + pinctrl-use-default; + + }; + + mssio: pinctrl@204 { + compatible = "microchip,mpfs-pinctrl-mssio"; + reg = <0x204 0x7c>; + /* on icicle ref design at least */ + pinctrl-use-default; + }; }; sysreg_scb: syscon@20003000 { @@ -450,8 +474,8 @@ mac0: ethernet@20110000 { interrupt-parent = <&plic>; interrupts = <64>, <65>, <66>, <67>, <68>, <69>; local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>; + clock-names = "pclk", "hclk", "tsu_clk"; resets = <&mss_top_sysreg CLK_MAC0>; status = "disabled"; }; @@ -464,8 +488,8 @@ mac1: ethernet@20112000 { interrupt-parent = <&plic>; interrupts = <70>, <71>, <72>, <73>, <74>, <75>; local-mac-address = [00 00 00 00 00 00]; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>, <&refclk>; + clock-names = "pclk", "hclk", "tsu_clk"; resets = <&mss_top_sysreg CLK_MAC1>; status = "disabled"; }; @@ -473,36 +497,57 @@ mac1: ethernet@20112000 { gpio0: gpio@20120000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20120000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>, + <12>, <13>; clocks = <&clkcfg CLK_GPIO0>; gpio-controller; #gpio-cells = <2>; + ngpios = <14>; status = "disabled"; }; gpio1: gpio@20121000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20121000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <32>, <33>, <34>, <35>, + <36>, <37>, <38>, <39>, + <40>, <41>, <42>, <43>, + <44>, <45>, <46>, <47>, + <48>, <49>, <50>, <51>, + <52>, <53>, <54>, <55>; clocks = <&clkcfg CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; + ngpios = <24>; status = "disabled"; }; gpio2: gpio@20122000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20122000 0x0 0x1000>; - interrupt-parent = <&plic>; + interrupt-parent = <&irqmux>; interrupt-controller; #interrupt-cells = <1>; + interrupts = <64>, <65>, <66>, <67>, + <68>, <69>, <70>, <71>, + <72>, <73>, <74>, <75>, + <76>, <77>, <78>, <79>, + <80>, <81>, <82>, <83>, + <84>, <85>, <86>, <87>, + <88>, <89>, <90>, <91>, + <92>, <93>, <94>, <95>; clocks = <&clkcfg CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; + ngpios = <32>; status = "disabled"; }; diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts new file mode 100644 index 000000000000..2f2ccd77af30 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for the PIC64GX Curiosity Kit + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Pierre-Henry Moussay + * + * The Curiosity-GX10000 (PIC64GX SoC Curiosity Kit) is a compact SoC + * prototyping board featuring a Microchip PIC64GX SoC + * PIC64GX-1000. Features include: + * - 1 GB DDR4 SDRAM + * - Gigabit Ethernet + * - microSD-card slot + * + * https://www.microchip.com/en-us/development-tool/curiosity-pic64gx1000-kit-es + */ + +/dts-v1/; + +#include "pic64gx.dtsi" +#include "pic64gx-pinctrl.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PIC64GX Curiosity Kit"; + compatible = "microchip,pic64gx-curiosity-kit", "microchip,pic64gx"; + + aliases { + ethernet0 = &mac0; + serial1 = &mmuart1; + serial2 = &mmuart2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss: hss-buffer@bfc00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&gpio0 { + interrupts = <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>; + status ="okay"; + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "MIPI_CAM_RESET", "MIPI_CAM_STANDBY"; +}; + +&gpio1 { + interrupts = <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <34>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status ="okay"; + gpio-line-names = + "", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6", + "LED7", "LED8", "", "", "", "", "", "", + "", "", "", "", "HDMI_HPD", "", "", "GPIO_1_23"; +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>, + <&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>; + status ="okay"; + gpio-line-names = + "", "", "", "", "", "", "SWITCH2", "USR_IO12", + "DIP1", "DIP2", "", "DIP3", "USR_IO1", "USR_IO2", "USR_IO7", "USR_IO8", + "USR_IO3", "USR_IO4", "USR_IO5", "USR_IO6", "", "", "USR_IO9", "USR_IO10", + "DIP4", "USR_IO11", "", "", "SWITCH1", "", "", ""; +}; + +&mac0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_default>; + + phy0: ethernet-phy@b { + reg = <0xb>; + }; +}; + +&mbox { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + sdhci-caps-mask = <0x00000007 0x00000000>; + status = "okay"; +}; + +&mmuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_fio>; + status = "okay"; +}; + +&mmuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_default>; + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi b/arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi new file mode 100644 index 000000000000..cf73b0556633 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/pic64gx-pinctrl.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +&iomux0 { + spi0_fio: mux-spi0-fabric { + function = "spi0"; + groups = "spi0_fabric"; + }; + + spi1_mssio: mux-spi1-mssio { + function = "spi1"; + groups = "spi1_mssio"; + }; + + i2c0_mssio: mux-i2c0-mssio { + function = "i2c0"; + groups = "i2c0_mssio"; + }; + + i2c1_mssio: mux-i2c1-mssio { + function = "i2c1"; + groups = "i2c1_mssio"; + }; + + can0_fio: mux-can0-fabric { + function = "can0"; + groups = "can0_fabric"; + }; + + can1_fio: mux-can1-fabric { + function = "can1"; + groups = "can1_fabric"; + }; + + qspi_fio: mux-qspi-fabric { + function = "qspi"; + groups = "qspi_fabric"; + }; + + uart0_mssio: mux-uart0-mssio { + function = "uart0"; + groups = "uart0_mssio"; + }; + + uart1_fio: mux-uart1-fabric { + function = "uart1"; + groups = "uart1_fabric"; + }; + + uart2_fio: mux-uart2-fabric { + function = "uart2"; + groups = "uart2_fabric"; + }; + + uart3_fio: mux-uart3-fabric { + function = "uart3"; + groups = "uart3_fabric"; + }; + + uart4_fio: mux-uart4-fabric { + function = "uart4"; + groups = "uart4_fabric"; + }; + + mdio0_fio: mux-mdio0-fabric { + function = "mdio0"; + groups = "mdio0_fabric"; + }; + + mdio1_fio: mux-mdio1-fabric { + function = "mdio1"; + groups = "mdio1_fabric"; + }; +}; + +&gpio2_pinctrl { + //TODO rethink the labels, since a bunch of these are not defaults or + //just outright remove the non-default groups + mdio0_default: mux-mac0 { + function = "mdio0"; + groups = "mdio0"; + }; + + mdio0_gpio: mux-mac0-gpio2 { + function = "gpio"; + groups = "gpio_mdio0"; + }; + + mdio1_default: mux-mac1 { + function = "mdio1"; + groups = "mdio1"; + }; + + mdio1_gpio: mux-mac1-gpio2 { + function = "gpio"; + groups = "gpio_mdio1"; + }; + + spi0_default: mux-spi0 { + function = "spi0"; + groups = "spi0"; + }; + + spi0_gpio: mux-spi0-gpio2 { + function = "gpio"; + groups = "gpio_spi0"; + }; + + can0_default: mux-can0 { + function = "can0"; + groups = "can0"; + }; + + can0_gpio: mux-can0-gpio2 { + function = "gpio"; + groups = "gpio_can0"; + }; + + pcie_default: mux-pcie { + function = "pcie"; + groups = "pcie"; + }; + + pcie_gpio: mux-pcie-gpio2 { + function = "gpio"; + groups = "gpio_pcie"; + }; + + qspi_default: mux-qspi { + function = "qspi"; + groups = "qspi"; + }; + + qspi_gpio: mux-qspi-gpio2 { + function = "gpio"; + groups = "gpio_qspi"; + }; + + uart3_default: mux-uart3 { + function = "uart3"; + groups = "uart3"; + }; + + uart3_gpio: mux-uart3-gpio2 { + function = "gpio"; + groups = "gpio_uart3"; + }; + + uart4_default: mux-uart4 { + function = "uart4"; + groups = "uart4"; + }; + + uart4_gpio: mux-uart4-gpio2 { + function = "gpio"; + groups = "gpio_uart4"; + }; + + can1_default: mux-can1 { + function = "can1"; + groups = "can1"; + }; + + can1_gpio: mux-can1-gpio2 { + function = "gpio"; + groups = "gpio_can1"; + }; + + uart2_default: mux-uart2 { + function = "uart2"; + groups = "uart2"; + }; + + uart2_gpio: mux-uart2-gpio2 { + function = "gpio"; + groups = "gpio_uart2"; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi new file mode 100644 index 000000000000..c164d7bc270a --- /dev/null +++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi @@ -0,0 +1,630 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree Source for the PIC64GX SoCs + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Pierre-Henry Moussay + * + * PIC64GX is a series RISC-V multicore SoCs: + * https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx + */ + +/dts-v1/; +#include "dt-bindings/clock/microchip,mpfs-clock.h" + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PIC64GX SoC"; + compatible = "microchip,pic64gx"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + clocks = <&clkcfg CLK_CPU>; + status = "disabled"; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", + "zicsr", "zifencei", "zihpm"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + next-level-cache = <&cctrllr>; + status = "okay"; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", + "zicsr", "zifencei", "zihpm"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + next-level-cache = <&cctrllr>; + status = "okay"; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", + "zicsr", "zifencei", "zihpm"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + next-level-cache = <&cctrllr>; + status = "okay"; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu4: cpu@4 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", + "zicsr", "zifencei", "zihpm"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + next-level-cache = <&cctrllr>; + status = "okay"; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; + }; + + scbclk: clock-80000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <80000000>; + }; + + refclk: mssrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + axiclk: axi-aclk0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + videoclk: video-aclk0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + syscontroller: syscontroller { + compatible = "microchip,pic64gx-sys-controller"; + mboxes = <&mbox 0>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + clint: clint@2000000 { + compatible = "microchip,pic64gx-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = <&cpu0_intc 0xffffffff>, <&cpu0_intc 0xffffffff>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + + cctrllr: cache-controller@2010000 { + compatible = "microchip,pic64gx-ccache", "microchip,mpfs-ccache", + "sifive,fu540-c000-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic>; + interrupts = <1>, <3>, <4>, <2>; + }; + + pdma: dma-controller@3000000 { + compatible = "microchip,pic64gx-pdma", "microchip,mpfs-pdma", + "sifive,pdma0"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <5 6>, <7 8>, <9 10>, <11 12>; + #dma-cells = <1>; + }; + + plic: interrupt-controller@c000000 { + compatible = "microchip,pic64gx-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; + riscv,ndev = <186>; + }; + + mmuart0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <90>; + current-speed = <115200>; + clocks = <&clkcfg CLK_MMUART0>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_mssio>; + status = "disabled"; /* Reserved for the HSS */ + }; + + mss_top_sysreg: syscon@20002000 { + compatible = "microchip,pic64gx-mss-top-sysreg", + "microchip,mpfs-mss-top-sysreg", + "syscon", "simple-mfd"; + reg = <0x0 0x20002000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #reset-cells = <1>; + + iomux0: pinctrl@200 { + compatible = "microchip,pic64gx-pinctrl-iomux0", + "microchip,mpfs-pinctrl-iomux0"; + reg = <0x200 0x4>; + pinctrl-use-default; + }; + + mssio: pinctrl@204 { + compatible = "microchip,pic64gx-pinctrl-mssio", + "microchip,mpfs-pinctrl-mssio"; + reg = <0x204 0x7c>; + /* on icicle ref design at least */ + pinctrl-use-default; + }; + }; + + sysreg_scb: syscon@20003000 { + compatible = "microchip,pic64gx-sysreg-scb", + "microchip,mpfs-sysreg-scb", + "syscon"; + reg = <0x0 0x20003000 0x0 0x1000>; + }; + + /* Common node entry for emmc/sd */ + mmc: mmc@20008000 { + compatible = "microchip,pic64gx-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + clocks = <&clkcfg CLK_MMC>; + max-frequency = <200000000>; + status = "disabled"; + }; + + mmuart1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <91>; + current-speed = <115200>; + clocks = <&clkcfg CLK_MMUART1>; + status = "disabled"; + }; + + mmuart2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <92>; + current-speed = <115200>; + clocks = <&clkcfg CLK_MMUART2>; + status = "disabled"; + }; + + mmuart3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <93>; + current-speed = <115200>; + clocks = <&clkcfg CLK_MMUART3>; + status = "disabled"; + }; + + mmuart4: serial@20106000 { + compatible = "ns16550a"; + reg = <0x0 0x20106000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <94>; + clocks = <&clkcfg CLK_MMUART4>; + current-speed = <115200>; + status = "disabled"; + }; + + spi0: spi@20108000 { + compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20108000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <54>; + clocks = <&clkcfg CLK_SPI0>; + status = "disabled"; + }; + + spi1: spi@20109000 { + compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20109000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <55>; + clocks = <&clkcfg CLK_SPI1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_mssio>; + status = "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible = "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7"; + reg = <0x0 0x2010a000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_mssio>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7"; + reg = <0x0 0x2010b000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_mssio>; + status = "disabled"; + }; + + can0: can@2010c000 { + compatible = "microchip,pic64gx-can", "microchip,mpfs-can"; + reg = <0x0 0x2010c000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; + interrupt-parent = <&plic>; + interrupts = <56>; + resets = <&mss_top_sysreg CLK_CAN0>; + status = "disabled"; + }; + + can1: can@2010d000 { + compatible = "microchip,pic64gx-can", "microchip,mpfs-can"; + reg = <0x0 0x2010d000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; + interrupt-parent = <&plic>; + interrupts = <57>; + resets = <&mss_top_sysreg CLK_CAN1>; + status = "disabled"; + }; + + mac0: ethernet@20110000 { + compatible = "microchip,pic64gx-macb", "microchip,mpfs-macb", + "cdns,macb"; + reg = <0x0 0x20110000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <64>, <65>, <66>, <67>, <68>, <69>; + /* Filled in by a bootloader */ + local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + resets = <&mss_top_sysreg CLK_MAC0>; + status = "disabled"; + }; + + mac1: ethernet@20112000 { + compatible = "microchip,pic64gx-macb", "microchip,mpfs-macb", + "cdns,macb"; + reg = <0x0 0x20112000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <70>, <71>, <72>, <73>, <74>, <75>; + /* Filled in by a bootloader */ + local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + resets = <&mss_top_sysreg CLK_MAC1>; + status = "disabled"; + }; + + gpio0: gpio@20120000 { + compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg = <0x0 0x20120000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <14>; + status = "disabled"; + }; + + gpio1: gpio@20121000 { + compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg = <0x0 0x20121000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <24>; + status = "disabled"; + }; + + gpio2: gpio@20122000 { + compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + status = "disabled"; + }; + + rtc: rtc@20124000 { + compatible = "microchip,pic64gx-rtc", "microchip,mpfs-rtc"; + reg = <0x0 0x20124000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <80>, <81>; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; + status = "disabled"; + }; + + usb: usb@20201000 { + compatible = "microchip,pic64gx-musb", "microchip,mpfs-musb"; + reg = <0x0 0x20201000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <86>, <87>; + clocks = <&clkcfg CLK_USB>; + interrupt-names = "dma", "mc"; + status = "disabled"; + }; + + qspi: spi@21000000 { + compatible = "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21000000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <85>; + clocks = <&clkcfg CLK_QSPI>; + status = "disabled"; + }; + + control_scb: syscon@37020000 { + compatible = "microchip,pic64gx-control-scb", + "microchip,mpfs-control-scb", + "syscon"; + reg = <0x0 0x37020000 0x0 0x100>; + }; + + syscontroller_qspi: spi@37020100 { + compatible = "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x37020100 0x0 0x100>; + interrupt-parent = <&plic>; + interrupts = <110>; + clocks = <&scbclk>; + status = "disabled"; + }; + + mbox: mailbox@37020800 { + compatible = "microchip,pic64gx-mailbox", "microchip,mpfs-mailbox"; + reg = <0x0 0x37020800 0x0 0x100>; + interrupt-parent = <&plic>; + interrupts = <96>; + #mbox-cells = <1>; + status = "disabled"; + }; + + ccc_se: clock-controller@38010000 { + compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; + reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, + <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_ne: clock-controller@38040000 { + compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; + reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, + <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_nw: clock-controller@38100000 { + compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; + reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, + <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_sw: clock-controller@38400000 { + compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; + reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, + <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + clkcfg: clkcfg@3e001000 { + compatible = "microchip,pic64gx-clkcfg", "microchip,mpfs-clkcfg"; + reg = <0x0 0x3e001000 0x0 0x1000>; + clocks = <&refclk>; + #clock-cells = <1>; + }; + + gpio2_pinctrl: pinctrl@41000000 { + compatible = "microchip,pic64gx-pinctrl-gpio2"; + reg = <0x0 0x41000000 0x0 0x4>; + pinctrl-use-default; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_fio>, <&mdio1_fio>, <&spi0_fio>, <&qspi_fio>, + <&uart3_fio>, <&uart4_fio>, <&can1_fio>, <&can0_fio>, + <&uart2_fio>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 5971605754b3..5790d927b93d 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -33,7 +33,7 @@ led1 { }; }; - pcie_vcc_3v3: pcie-vcc3v3 { + pcie_vcc_3v3: regulator-pcie-vcc3v3 { compatible = "regulator-fixed"; regulator-name = "PCIE_VCC3V3"; regulator-min-microvolt = <3300000>; @@ -41,7 +41,7 @@ pcie_vcc_3v3: pcie-vcc3v3 { regulator-always-on; }; - reg_dc_in: dc-in-12v { + reg_dc_in: regulator-dc-in-12v { compatible = "regulator-fixed"; regulator-name = "dc_in_12v"; regulator-min-microvolt = <12000000>; @@ -50,7 +50,7 @@ reg_dc_in: dc-in-12v { regulator-always-on; }; - reg_vcc_4v: vcc-4v { + reg_vcc_4v: regulator-vcc-4v { compatible = "regulator-fixed"; regulator-name = "vcc_4v"; regulator-min-microvolt = <4000000>; @@ -60,7 +60,7 @@ reg_vcc_4v: vcc-4v { vin-supply = <®_dc_in>; }; - usb3-vbus-5v { + regulator-usb3-vbus-5v { compatible = "regulator-fixed"; regulator-name = "USB30_VBUS"; regulator-min-microvolt = <5000000>; @@ -70,7 +70,7 @@ usb3-vbus-5v { enable-active-high; }; - usb3_hub_5v: usb3-hub-5v { + usb3_hub_5v: regulator-usb3-hub-5v { compatible = "regulator-fixed"; regulator-name = "USB30_HUB"; regulator-min-microvolt = <5000000>; @@ -81,8 +81,6 @@ usb3_hub_5v: usb3-hub-5v { }; &combo_phy { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_3_cfg>; status = "okay"; }; @@ -190,7 +188,15 @@ pmic@41 { compatible = "spacemit,p1"; reg = <0x41>; interrupts = <64>; - vin-supply = <®_vcc_4v>; + vin1-supply = <®_vcc_4v>; + vin2-supply = <®_vcc_4v>; + vin3-supply = <®_vcc_4v>; + vin4-supply = <®_vcc_4v>; + vin5-supply = <®_vcc_4v>; + vin6-supply = <®_vcc_4v>; + aldoin-supply = <®_vcc_4v>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; regulators { buck1 { @@ -221,7 +227,7 @@ buck4 { regulator-always-on; }; - buck5 { + buck5: buck5 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3450000>; regulator-ramp-delay = <5000>; @@ -305,6 +311,7 @@ &pcie1_phy { &pcie1_port { phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; }; &pcie1 { @@ -320,6 +327,7 @@ &pcie2_phy { &pcie2_port { phys = <&pcie2_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; }; &pcie2 { diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 800a112d5d70..afaad59e6bce 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -15,13 +15,42 @@ aliases { ethernet0 = ð0; ethernet1 = ð1; serial0 = &uart0; + i2c2 = &i2c2; + i2c8 = &i2c8; }; chosen { stdout-path = "serial0"; }; - reg_dc_in: dc-in-12v { + leds { + compatible = "gpio-leds"; + + led1 { + label = "pwr-led"; + gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "on"; + }; + + led2 { + label = "hdd-led"; + gpios = <&gpio K1_GPIO(92) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "pcie_vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_dc_in>; + }; + + reg_dc_in: regulator-dc-in-12v { compatible = "regulator-fixed"; regulator-name = "dc_in_12v"; regulator-min-microvolt = <12000000>; @@ -30,7 +59,7 @@ reg_dc_in: dc-in-12v { regulator-always-on; }; - reg_vcc_4v: vcc-4v { + reg_vcc_4v: regulator-vcc-4v { compatible = "regulator-fixed"; regulator-name = "vcc_4v"; regulator-min-microvolt = <4000000>; @@ -39,6 +68,41 @@ reg_vcc_4v: vcc-4v { regulator-always-on; vin-supply = <®_dc_in>; }; + + reg_vcc_5v: regulator-vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_dc_in>; + }; + + regulator-usb3-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_vcc_5v>; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb3_hub_5v: regulator-usb3-hub-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc_5v>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&combo_phy { + status = "okay"; }; ð0 { @@ -91,6 +155,28 @@ &pdma { status = "okay"; }; +&i2c2 { + pinctrl-0 = <&i2c2_0_cfg>; + pinctrl-names = "default"; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; /* EEPROM_VCC18 */ + pagesize = <16>; + read-only; + size = <512>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + product-name { + }; + }; + }; +}; + &i2c8 { pinctrl-0 = <&i2c8_cfg>; pinctrl-names = "default"; @@ -100,7 +186,15 @@ pmic@41 { compatible = "spacemit,p1"; reg = <0x41>; interrupts = <64>; - vin-supply = <®_vcc_4v>; + vin1-supply = <®_vcc_4v>; + vin2-supply = <®_vcc_4v>; + vin3-supply = <®_vcc_4v>; + vin4-supply = <®_vcc_4v>; + vin5-supply = <®_vcc_4v>; + vin6-supply = <®_vcc_4v>; + aldoin-supply = <®_vcc_4v>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; regulators { buck1 { @@ -124,14 +218,14 @@ buck3_1v8: buck3 { regulator-always-on; }; - buck4 { + buck4_3v3: buck4 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3300000>; regulator-ramp-delay = <5000>; regulator-always-on; }; - buck5 { + buck5: buck5 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3450000>; regulator-ramp-delay = <5000>; @@ -207,8 +301,108 @@ dldo7 { }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; +}; + +&pcie1 { + vpcie3v3-supply = <&pcie_vcc_3v3>; + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; +}; + +&pcie2 { + vpcie3v3-supply = <&pcie_vcc_3v3>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <&buck4_3v3>; /* QSPI_VCC1833 */ + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x0 0x10000>; + }; + private@10000 { + reg = <0x10000 0x10000>; + }; + fsbl@20000 { + reg = <0x20000 0x40000>; + }; + env@60000 { + reg = <0x60000 0x10000>; + }; + opensbi@70000 { + reg = <0x70000 0x30000>; + }; + uboot@a00000 { + reg = <0xa0000 0x760000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; + vdd-supply = <&usb3_hub_5v>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; + vdd-supply = <&usb3_hub_5v>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 529ec68e9c23..f0bad6855c97 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -359,6 +359,60 @@ syscon_rcpu2: system-controller@c0888000 { #reset-cells = <1>; }; + usbphy2: phy@c0a30000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0x0 0xc0a30000 0x0 0x200>; + clocks = <&syscon_apmu CLK_USB30>; + #phy-cells = <0>; + status = "disabled"; + }; + + combo_phy: phy@c0b10000 { + compatible = "spacemit,k1-combo-phy"; + reg = <0x0 0xc0b10000 0x0 0x1000>; + clocks = <&vctcxo_24m>, + <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names = "refclk", + "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, + <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names = "phy", + "dbi", + "mstr", + "slv"; + #phy-cells = <1>; + spacemit,apmu = <&syscon_apmu>; + status = "disabled"; + }; + + pcie1_phy: phy@c0c10000 { + compatible = "spacemit,k1-pcie-phy"; + reg = <0x0 0xc0c10000 0x0 0x1000>; + clocks = <&vctcxo_24m>; + clock-names = "refclk"; + resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie2_phy: phy@c0d10000 { + compatible = "spacemit,k1-pcie-phy"; + reg = <0x0 0xc0d10000 0x0 0x1000>; + clocks = <&vctcxo_24m>; + clock-names = "refclk"; + resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@d4010800 { compatible = "spacemit,k1-i2c"; reg = <0x0 0xd4010800 0x0 0x38>; @@ -429,60 +483,6 @@ i2c5: i2c@d4013800 { status = "disabled"; }; - usbphy2: phy@c0a30000 { - compatible = "spacemit,k1-usb2-phy"; - reg = <0x0 0xc0a30000 0x0 0x200>; - clocks = <&syscon_apmu CLK_USB30>; - #phy-cells = <0>; - status = "disabled"; - }; - - combo_phy: phy@c0b10000 { - compatible = "spacemit,k1-combo-phy"; - reg = <0x0 0xc0b10000 0x0 0x1000>; - clocks = <&vctcxo_24m>, - <&syscon_apmu CLK_PCIE0_DBI>, - <&syscon_apmu CLK_PCIE0_MASTER>, - <&syscon_apmu CLK_PCIE0_SLAVE>; - clock-names = "refclk", - "dbi", - "mstr", - "slv"; - resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, - <&syscon_apmu RESET_PCIE0_DBI>, - <&syscon_apmu RESET_PCIE0_MASTER>, - <&syscon_apmu RESET_PCIE0_SLAVE>; - reset-names = "phy", - "dbi", - "mstr", - "slv"; - #phy-cells = <1>; - spacemit,apmu = <&syscon_apmu>; - status = "disabled"; - }; - - pcie1_phy: phy@c0c10000 { - compatible = "spacemit,k1-pcie-phy"; - reg = <0x0 0xc0c10000 0x0 0x1000>; - clocks = <&vctcxo_24m>; - clock-names = "refclk"; - resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; - reset-names = "phy"; - #phy-cells = <0>; - status = "disabled"; - }; - - pcie2_phy: phy@c0d10000 { - compatible = "spacemit,k1-pcie-phy"; - reg = <0x0 0xc0d10000 0x0 0x1000>; - clocks = <&vctcxo_24m>; - clock-names = "refclk"; - resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; - reset-names = "phy"; - #phy-cells = <0>; - status = "disabled"; - }; - syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; @@ -1033,6 +1033,7 @@ pcie-bus { #size-cells = <2>; dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; + pcie0: pcie@ca000000 { device_type = "pci"; compatible = "spacemit,k1-pcie"; @@ -1044,6 +1045,7 @@ pcie0: pcie@ca000000 { "atu", "config", "link"; + linux,pci-domain = <0>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, @@ -1087,6 +1089,7 @@ pcie1: pcie@ca400000 { "atu", "config", "link"; + linux,pci-domain = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, @@ -1130,6 +1133,7 @@ pcie2: pcie@ca800000 { "atu", "config", "link"; + linux,pci-domain = <2>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b691304d4b74..4486dc1fe114 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -3,14 +3,17 @@ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd * Copyright (c) 2026 Guodong Xu */ +#include #include "k3.dtsi" +#include "k3-pinctrl.dtsi" / { model = "SpacemiT K3 Pico-ITX"; compatible = "spacemit,k3-pico-itx", "spacemit,k3"; aliases { + ethernet0 = ð0; serial0 = &uart0; }; @@ -22,8 +25,175 @@ memory@100000000 { device_type = "memory"; reg = <0x1 0x00000000 0x4 0x00000000>; }; + + reg_aux_vcc5v: regulator-aux-vcc5v { + compatible = "regulator-fixed"; + regulator-name = "AUX_VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; + + p1@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + vin1-supply = <®_aux_vcc5v>; + vin2-supply = <®_aux_vcc5v>; + vin3-supply = <®_aux_vcc5v>; + vin4-supply = <®_aux_vcc5v>; + vin5-supply = <®_aux_vcc5v>; + vin6-supply = <®_aux_vcc5v>; + aldoin-supply = <®_aux_vcc5v>; + dldoin1-supply = <&buck4>; + dldoin2-supply = <&buck4>; + + regulators { + buck1: buck1 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2: buck2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3: buck3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4: buck4 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6: buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1: aldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo2: aldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + aldo3: aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4: aldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo1: dldo1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo2: dldo2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo3: dldo3 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo4: dldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + dldo5: dldo5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo6: dldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + dldo7: dldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + status = "okay"; + + mdio { + phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_0_cfg>; status = "okay"; }; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi new file mode 100644 index 000000000000..23899d3f308a --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2026 Yixun Lan + */ + +#include + +#define K3_PADCONF(pin, func) (((pin) << 16) | (func)) + +/* Map GPIO pin to each bank's */ +#define K3_GPIO(x) (x / 32) (x % 32) + +&pinctrl { + gmac0_rgmii_0_cfg: gmac0-rgmii-0-cfg { + gmac0-rgmii-0-pins { + pinmux = , /* gmac0_rxdv */ + , /* gmac0_rx_d0 */ + , /* gmac0_rx_d1 */ + , /* gmac0_rx_clk */ + , /* gmac0_rx_d2 */ + , /* gmac0_rx_d3 */ + , /* gmac0_tx_d0 */ + , /* gmac0_tx_d1 */ + , /* gmac0_tx_clk */ + , /* gmac0_tx_d2 */ + , /* gmac0_tx_d3 */ + , /* gmac0_tx_en */ + , /* gmac0_mdc */ + ; /* gmac0_mdio */ + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + + }; + + gmac0_phy_0_cfg: gmac0-phy-0-cfg { + gmac0-phy-0-pins { + pinmux = ; /* gmac0_int */ + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + }; + + /omit-if-no-ref/ + i2c8_cfg: i2c8-cfg { + i2c8-pins { + pinmux = , /* i2c8 scl */ + ; /* i2c8 sda */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { + pinmux = , /* uart0 tx */ + ; /* uart0 rx */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index b69cf81b5d55..815debd16409 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -4,6 +4,8 @@ * Copyright (c) 2026 Guodong Xu */ +#include +#include #include /dts-v1/; @@ -398,6 +400,36 @@ core3 { }; }; + clocks { + vctcxo_1m: clock-1m { + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "vctcxo_1m"; + #clock-cells = <0>; + }; + + vctcxo_24m: clock-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "vctcxo_24m"; + #clock-cells = <0>; + }; + + vctcxo_3m: clock-3m { + compatible = "fixed-clock"; + clock-frequency = <3000000>; + clock-output-names = "vctcxo_3m"; + #clock-cells = <0>; + }; + + osc_32k: clock-32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + clock-output-names = "osc_32k"; + #clock-cells = <0>; + }; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&saplic>; @@ -406,12 +438,211 @@ soc: soc { dma-noncoherent; ranges; + eth0: ethernet@cac80000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac80000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, + <&syscon_apmu CLK_APMU_EMAC0_1588>, + <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, + <276 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC0>; + reset-names = "stmmaceth"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac0_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac0_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + /* max axi burst len is 256 */ + snps,blen = <256 128 64 32 16 0 0>; + }; + }; + + eth1: ethernet@cac82000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac82000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, + <&syscon_apmu CLK_APMU_EMAC1_1588>, + <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, + <277 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC1>; + reset-names = "stmmaceth"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac1_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac1_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + /* max axi burst len is 256 */ + snps,blen = <256 128 64 32 16 0 0>; + }; + }; + + eth2: ethernet@cac8e000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac8e000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, + <&syscon_apmu CLK_APMU_EMAC2_1588>, + <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, + <278 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC2>; + reset-names = "stmmaceth"; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac2_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x248 0x24c>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac2_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + /* max axi burst len is 256 */ + snps,blen = <256 128 64 32 16 0 0>; + }; + }; + + i2c0: i2c@d4010800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4010800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI0>, + <&syscon_apbc CLK_APBC_TWSI0_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI0>; + status = "disabled"; + }; + + i2c1: i2c@d4011000 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4011000 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI1>, + <&syscon_apbc CLK_APBC_TWSI1_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI1>; + status = "disabled"; + }; + + i2c2: i2c@d4012000 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4012000 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI2>, + <&syscon_apbc CLK_APBC_TWSI2_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI2>; + status = "disabled"; + }; + + i2c4: i2c@d4012800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4012800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI4>, + <&syscon_apbc CLK_APBC_TWSI4_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI4>; + status = "disabled"; + }; + + i2c5: i2c@d4013800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4013800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI5>, + <&syscon_apbc CLK_APBC_TWSI5_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI5>; + status = "disabled"; + }; + + syscon_apbc: system-controller@d4015000 { + compatible = "spacemit,k3-syscon-apbc"; + reg = <0x0 0xd4015000 0x0 0x1000>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart0: serial@d4017000 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd4017000 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART0>, + <&syscon_apbc CLK_APBC_UART0_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART0>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -421,7 +652,10 @@ uart2: serial@d4017100 { reg = <0x0 0xd4017100 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART2>, + <&syscon_apbc CLK_APBC_UART2_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART2>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -431,7 +665,10 @@ uart3: serial@d4017200 { reg = <0x0 0xd4017200 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART3>, + <&syscon_apbc CLK_APBC_UART3_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART3>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -441,7 +678,10 @@ uart4: serial@d4017300 { reg = <0x0 0xd4017300 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART4>, + <&syscon_apbc CLK_APBC_UART4_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART4>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -451,7 +691,10 @@ uart5: serial@d4017400 { reg = <0x0 0xd4017400 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART5>, + <&syscon_apbc CLK_APBC_UART5_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART5>; interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -461,7 +704,10 @@ uart6: serial@d4017500 { reg = <0x0 0xd4017500 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART6>, + <&syscon_apbc CLK_APBC_UART6_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART6>; interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -471,7 +717,10 @@ uart7: serial@d4017600 { reg = <0x0 0xd4017600 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART7>, + <&syscon_apbc CLK_APBC_UART7_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART7>; interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -481,7 +730,10 @@ uart8: serial@d4017700 { reg = <0x0 0xd4017700 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART8>, + <&syscon_apbc CLK_APBC_UART8_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART8>; interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -491,21 +743,116 @@ uart9: serial@d4017800 { reg = <0x0 0xd4017800 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART9>, + <&syscon_apbc CLK_APBC_UART9_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART9>; interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + i2c6: i2c@d4018800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd4018800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI6>, + <&syscon_apbc CLK_APBC_TWSI6_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI6>; + status = "disabled"; + }; + + gpio: gpio@d4019000 { + compatible = "spacemit,k3-gpio"; + reg = <0x0 0xd4019000 0x0 0x100>; + clocks = <&syscon_apbc CLK_APBC_GPIO>, + <&syscon_apbc CLK_APBC_GPIO_BUS>; + clock-names = "core", "bus"; + gpio-controller; + #gpio-cells = <3>; + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-ranges = <&pinctrl 0 0 0 32>, + <&pinctrl 1 0 32 32>, + <&pinctrl 2 0 64 32>, + <&pinctrl 3 0 96 32>; + }; + + i2c8: i2c@d401d800 { + compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; + reg = <0x0 0xd401d800 0x0 0x38>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apbc CLK_APBC_TWSI8>, + <&syscon_apbc CLK_APBC_TWSI8_BUS>; + clock-names = "func", "bus"; + clock-frequency = <400000>; + resets = <&syscon_apbc RESET_APBC_TWSI8>; + status = "disabled"; + }; + + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k3-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x1000>; + clocks = <&syscon_apbc CLK_APBC_AIB>, + <&syscon_apbc CLK_APBC_AIB_BUS>; + clock-names = "func", "bus"; + }; + uart10: serial@d401f000 { compatible = "spacemit,k3-uart", "intel,xscale-uart"; reg = <0x0 0xd401f000 0x0 0x100>; reg-shift = <2>; reg-io-width = <4>; - clock-frequency = <14700000>; + clocks = <&syscon_apbc CLK_APBC_UART10>, + <&syscon_apbc CLK_APBC_UART10_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_UART10>; interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + syscon_mpmu: system-controller@d4050000 { + compatible = "spacemit,k3-syscon-mpmu"; + reg = <0x0 0xd4050000 0x0 0x10000>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + pll: clock-controller@d4090000 { + compatible = "spacemit,k3-pll"; + reg = <0x0 0xd4090000 0x0 0x10000>; + clocks = <&vctcxo_24m>; + spacemit,mpmu = <&syscon_mpmu>; + #clock-cells = <1>; + }; + + syscon_apmu: system-controller@d4282800 { + compatible = "spacemit,k3-syscon-apmu"; + reg = <0x0 0xd4282800 0x0 0x400>; + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + + syscon_dciu: system-controller@d8440000 { + compatible = "spacemit,k3-syscon-dciu"; + reg = <0x0 0xd8440000 0x0 0xc000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + simsic: interrupt-controller@e0400000 { compatible = "spacemit,k3-imsics", "riscv,imsics"; reg = <0x0 0xe0400000 0x0 0x200000>; @@ -545,6 +892,8 @@ clint: timer@e081c000 { <&cpu7_intc 3>, <&cpu7_intc 7>; }; + /* sec_i2c3: 0xf0614000, not available from Linux */ + mimsic: interrupt-controller@f1000000 { compatible = "spacemit,k3-imsics", "riscv,imsics"; reg = <0x0 0xf1000000 0x0 0x10000>; diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index 21c33f165ba9..91f3f9b987bc 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -75,6 +75,17 @@ led-5 { label = "led5"; }; }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; }; &osc { @@ -236,6 +247,20 @@ &sdio0 { status = "okay"; }; +&dpu { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out_port { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index c58c2085ca92..7cb7d28683bc 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -29,6 +29,17 @@ chosen { stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + thermal-zones { cpu-thermal { polling-delay = <1000>; @@ -121,6 +132,20 @@ rx-pins { }; }; +&dpu { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out_port { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index bd5d33840884..5e91dc1d2b9b 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -585,6 +585,72 @@ clk_vo: clock-controller@ffef528050 { #clock-cells = <1>; }; + hdmi: hdmi@ffef540000 { + compatible = "thead,th1520-dw-hdmi"; + reg = <0xff 0xef540000 0x0 0x40000>; + reg-io-width = <4>; + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vo CLK_HDMI_PCLK>, + <&clk_vo CLK_HDMI_SFR>, + <&clk_vo CLK_HDMI_CEC>, + <&clk_vo CLK_HDMI_PIXCLK>; + clock-names = "iahb", "isfr", "cec", "pix"; + resets = <&rst TH1520_RESET_ID_HDMI>, + <&rst TH1520_RESET_ID_HDMI_APB>; + reset-names = "main", "apb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in: endpoint { + remote-endpoint = <&dpu_out_dp1>; + }; + }; + + hdmi_out_port: port@1 { + reg = <1>; + }; + }; + }; + + dpu: display@ffef600000 { + compatible = "thead,th1520-dc8200", "verisilicon,dc"; + reg = <0xff 0xef600000 0x0 0x100000>; + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vo CLK_DPU_CCLK>, + <&clk_vo CLK_DPU_ACLK>, + <&clk_vo CLK_DPU_HCLK>, + <&clk_vo CLK_DPU_PIXELCLK0>, + <&clk_vo CLK_DPU_PIXELCLK1>; + clock-names = "core", "axi", "ahb", "pix0", "pix1"; + resets = <&rst TH1520_RESET_ID_DPU_CORE>, + <&rst TH1520_RESET_ID_DPU_AXI>, + <&rst TH1520_RESET_ID_DPU_AHB>; + reset-names = "core", "axi", "ahb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dpu_port1: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dpu_out_dp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; + dmac0: dma-controller@ffefc00000 { compatible = "snps,axi-dma-1.01a"; reg = <0xff 0xefc00000 0x0 0x1000>; @@ -753,6 +819,10 @@ pvt: pvt@fffff4e000 { reg-names = "common", "ts", "pd", "vm"; clocks = <&aonsys_clk>; #thermal-sensor-cells = <1>; + moortec,ts-coeff-g = <42740>; + moortec,ts-coeff-h = <220500>; + moortec,ts-coeff-j = <(-160)>; + moortec,ts-coeff-cal5 = <4094>; }; gpio@fffff52000 { diff --git a/include/dt-bindings/clock/axis,artpec9-clk.h b/include/dt-bindings/clock/axis,artpec9-clk.h new file mode 100644 index 000000000000..c6787be8d686 --- /dev/null +++ b/include/dt-bindings/clock/axis,artpec9-clk.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + * + * Device Tree binding constants for ARTPEC-9 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H +#define _DT_BINDINGS_CLOCK_ARTPEC9_H + +/* CMU_CMU */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_DOUT_SHARED0_DIV2 2 +#define CLK_DOUT_SHARED0_DIV3 3 +#define CLK_DOUT_SHARED0_DIV4 4 +#define CLK_FOUT_SHARED1_PLL 5 +#define CLK_DOUT_SHARED1_DIV2 6 +#define CLK_DOUT_SHARED1_DIV3 7 +#define CLK_DOUT_SHARED1_DIV4 8 +#define CLK_FOUT_AUDIO_PLL 9 +#define CLK_DOUT_CMU_ADD 10 +#define CLK_DOUT_CMU_BUS 11 +#define CLK_DOUT_CMU_CDC_CORE 12 +#define CLK_DOUT_CMU_CORE_MAIN 13 +#define CLK_DOUT_CMU_CPUCL_SWITCH 14 +#define CLK_DOUT_CMU_DLP_CORE 15 +#define CLK_DOUT_CMU_FSYS0_BUS 16 +#define CLK_DOUT_CMU_FSYS0_IP 17 +#define CLK_DOUT_CMU_FSYS1_BUS 18 +#define CLK_DOUT_CMU_FSYS1_SCAN0 19 +#define CLK_DOUT_CMU_FSYS1_SCAN1 20 +#define CLK_DOUT_CMU_GPU_3D 21 +#define CLK_DOUT_CMU_GPU_2D 22 +#define CLK_DOUT_CMU_IMEM_ACLK 23 +#define CLK_DOUT_CMU_IMEM_CA5 24 +#define CLK_DOUT_CMU_IMEM_JPEG 25 +#define CLK_DOUT_CMU_IMEM_SSS 26 +#define CLK_DOUT_CMU_IPA_CORE 27 +#define CLK_DOUT_CMU_LCPU 28 +#define CLK_DOUT_CMU_MIF_SWITCH 29 +#define CLK_DOUT_CMU_MIF_BUSP 30 +#define CLK_DOUT_CMU_PERI_DISP 31 +#define CLK_DOUT_CMU_PERI_IP 32 +#define CLK_DOUT_CMU_RSP_CORE 33 +#define CLK_DOUT_CMU_TRFM 34 +#define CLK_DOUT_CMU_VIO_CORE_L 35 +#define CLK_DOUT_CMU_VIO_CORE 36 +#define CLK_DOUT_CMU_VIP0 37 +#define CLK_DOUT_CMU_VIP1 38 +#define CLK_DOUT_CMU_VPP_CORE 39 +#define CLK_DOUT_CMU_VIO_AUDIO 40 + +/* CMU_BUS */ +#define CLK_MOUT_BUS_ACLK_USER 1 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_ACLK_USER 1 + +/* CMU_CPUCL */ +#define CLK_FOUT_CPUCL_PLL0 1 +#define CLK_MOUT_CPUCL_PLL0 2 +#define CLK_FOUT_CPUCL_PLL1 3 +#define CLK_MOUT_CPUCL_PLL_SCU 4 +#define CLK_MOUT_CPUCL_SWITCH_SCU_USER 5 +#define CLK_MOUT_CPUCL_SWITCH_USER 6 +#define CLK_DOUT_CPUCL_CPU 7 +#define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK 8 +#define CLK_DOUT_CPUCL_CLUSTER_GICCLK 9 +#define CLK_DOUT_CPUCL_CLUSTER_PCLK 10 +#define CLK_DOUT_CPUCL_CMUREF 11 +#define CLK_DOUT_CPUCL_CLUSTER_ATCLK 12 +#define CLK_DOUT_CPUCL_CLUSTER_SCU 13 +#define CLK_DOUT_CPUCL_DBG 14 +#define CLK_GOUT_CPUCL_SHORTSTOP 15 +#define CLK_GOUT_CPUCL_CLUSTER_CPU 16 +#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK 17 +#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG 18 + +/* CMU_FSYS0 */ +#define CLK_MOUT_FSYS0_BUS_USER 1 +#define CLK_MOUT_FSYS0_IP_USER 2 +#define CLK_MOUT_FSYS0_MAIN_USER 3 +#define CLK_DOUT_FSYS0_125 4 +#define CLK_DOUT_FSYS0_ADC 5 +#define CLK_DOUT_FSYS0_BUS_300 6 +#define CLK_DOUT_FSYS0_EQOS0 7 +#define CLK_DOUT_FSYS0_EQOS1 8 +#define CLK_DOUT_FSYS0_MMC_CARD0 9 +#define CLK_DOUT_FSYS0_MMC_CARD1 10 +#define CLK_DOUT_FSYS0_MMC_CARD2 11 +#define CLK_DOUT_FSYS0_QSPI 12 +#define CLK_DOUT_FSYS0_SFMC_NAND 13 +#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 14 +#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I 15 +#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250 16 +#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK 17 +#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250 18 +#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK 19 +#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I 20 +#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I 21 +#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK 22 +#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK 23 +#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK 24 +#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK 25 +#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK 26 +#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK 27 +#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK 28 +#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK 29 +#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN 30 +#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN 31 +#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN 32 +#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK 33 +#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK 34 +#define CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND 35 +#define CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK 36 +#define CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK 37 +#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK 38 +#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK 39 +#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK 40 +#define CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0 41 + +/* CMU_FSYS1 */ +#define CLK_FOUT_FSYS1_PLL 1 +#define CLK_MOUT_FSYS1_SCAN0_USER 2 +#define CLK_MOUT_FSYS1_SCAN1_USER 3 +#define CLK_MOUT_FSYS1_BUS_USER 4 +#define CLK_DOUT_FSYS1_200 5 +#define CLK_DOUT_FSYS1_BUS_300 6 +#define CLK_DOUT_FSYS1_OTP_MEM 7 +#define CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL 8 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100 9 +#define CLK_GOUT_FSYS1_UART0_PCLK 10 +#define CLK_GOUT_FSYS1_UART0_SCLK_UART 11 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300 12 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC 13 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC 14 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC 15 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC 16 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC 17 +#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC 18 +#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20 19 +#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY 20 +#define CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK 21 +#define CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK 22 + +/* CMU_IMEM */ +#define CLK_MOUT_IMEM_ACLK_USER 1 +#define CLK_MOUT_IMEM_CA5_USER 2 +#define CLK_MOUT_IMEM_SSS_USER 3 +#define CLK_MOUT_IMEM_JPEG_USER 4 +#define CLK_DOUT_IMEM_PCLK 5 +#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK 6 +#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN 7 +#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG 8 +#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK 9 +#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN 10 +#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG 11 +#define CLK_GOUT_IMEM_MCT0_PCLK 12 +#define CLK_GOUT_IMEM_MCT1_PCLK 13 +#define CLK_GOUT_IMEM_MCT2_PCLK 14 +#define CLK_GOUT_IMEM_MCT3_PCLK 15 +#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF 16 + +/* CMU_PERI */ +#define CLK_MOUT_PERI_IP_USER 1 +#define CLK_MOUT_PERI_DISP_USER 2 +#define CLK_DOUT_PERI_125 3 +#define CLK_DOUT_PERI_PCLK 4 +#define CLK_DOUT_PERI_SPI 5 +#define CLK_DOUT_PERI_UART1 6 +#define CLK_DOUT_PERI_UART2 7 +#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK 8 +#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK 9 +#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK 10 +#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK 11 +#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK 12 +#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK 13 +#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK 14 +#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK 15 +#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK 16 +#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK 17 +#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS 18 +#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK 19 +#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK 20 +#define CLK_GOUT_PERI_SPI0_PCLK 21 +#define CLK_GOUT_PERI_SPI0_SCLK_SPI 22 +#define CLK_GOUT_PERI_UART1_PCLK 23 +#define CLK_GOUT_PERI_UART1_SCLK_UART 24 +#define CLK_GOUT_PERI_UART2_PCLK 25 +#define CLK_GOUT_PERI_UART2_SCLK_UART 26 + +#endif /* _DT_BINDINGS_CLOCK_ARTPEC9_H */ diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6125.h b/include/dt-bindings/clock/qcom,dispcc-sm6125.h index 4ff974f4fcc3..f58b85d2c814 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sm6125.h +++ b/include/dt-bindings/clock/qcom,dispcc-sm6125.h @@ -6,6 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_MDSS_AHB_CLK 1 #define DISP_CC_MDSS_AHB_CLK_SRC 2 @@ -35,7 +36,10 @@ #define DISP_CC_MDSS_VSYNC_CLK_SRC 26 #define DISP_CC_XO_CLK 27 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 + +/* GDSCs */ #define MDSS_GDSC 0 #endif diff --git a/include/dt-bindings/clock/qcom,eliza-gcc.h b/include/dt-bindings/clock/qcom,eliza-gcc.h new file mode 100644 index 000000000000..4d27b329ae99 --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-gcc.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 1 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 2 +#define GCC_BOOT_ROM_AHB_CLK 3 +#define GCC_CAM_BIST_MCLK_AHB_CLK 4 +#define GCC_CAMERA_AHB_CLK 5 +#define GCC_CAMERA_HF_AXI_CLK 6 +#define GCC_CAMERA_SF_AXI_CLK 7 +#define GCC_CAMERA_XO_CLK 8 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10 +#define GCC_CNOC_PCIE_SF_AXI_CLK 11 +#define GCC_DDRSS_GPU_AXI_CLK 12 +#define GCC_DDRSS_PCIE_SF_QTB_CLK 13 +#define GCC_DISP_AHB_CLK 14 +#define GCC_DISP_HF_AXI_CLK 15 +#define GCC_GP1_CLK 16 +#define GCC_GP1_CLK_SRC 17 +#define GCC_GP2_CLK 18 +#define GCC_GP2_CLK_SRC 19 +#define GCC_GP3_CLK 20 +#define GCC_GP3_CLK_SRC 21 +#define GCC_GPLL0 22 +#define GCC_GPLL0_OUT_EVEN 23 +#define GCC_GPLL4 24 +#define GCC_GPLL7 25 +#define GCC_GPLL8 26 +#define GCC_GPLL9 27 +#define GCC_GPU_CFG_AHB_CLK 28 +#define GCC_GPU_GEMNOC_GFX_CLK 29 +#define GCC_GPU_GPLL0_CPH_CLK_SRC 30 +#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 31 +#define GCC_GPU_SMMU_VOTE_CLK 32 +#define GCC_MMU_TCU_VOTE_CLK 33 +#define GCC_PCIE_0_AUX_CLK 34 +#define GCC_PCIE_0_AUX_CLK_SRC 35 +#define GCC_PCIE_0_CFG_AHB_CLK 36 +#define GCC_PCIE_0_MSTR_AXI_CLK 37 +#define GCC_PCIE_0_PHY_RCHNG_CLK 38 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 39 +#define GCC_PCIE_0_PIPE_CLK 40 +#define GCC_PCIE_0_PIPE_CLK_SRC 41 +#define GCC_PCIE_0_PIPE_DIV2_CLK 42 +#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC 43 +#define GCC_PCIE_0_SLV_AXI_CLK 44 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 +#define GCC_PCIE_1_AUX_CLK 46 +#define GCC_PCIE_1_AUX_CLK_SRC 47 +#define GCC_PCIE_1_CFG_AHB_CLK 48 +#define GCC_PCIE_1_MSTR_AXI_CLK 49 +#define GCC_PCIE_1_PHY_RCHNG_CLK 50 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 51 +#define GCC_PCIE_1_PIPE_CLK 52 +#define GCC_PCIE_1_PIPE_CLK_SRC 53 +#define GCC_PCIE_1_PIPE_DIV2_CLK 54 +#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 55 +#define GCC_PCIE_1_SLV_AXI_CLK 56 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57 +#define GCC_PCIE_RSCC_CFG_AHB_CLK 58 +#define GCC_PCIE_RSCC_XO_CLK 59 +#define GCC_PDM2_CLK 60 +#define GCC_PDM2_CLK_SRC 61 +#define GCC_PDM_AHB_CLK 62 +#define GCC_PDM_XO4_CLK 63 +#define GCC_QMIP_CAMERA_CMD_AHB_CLK 64 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 65 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 66 +#define GCC_QMIP_GPU_AHB_CLK 67 +#define GCC_QMIP_PCIE_AHB_CLK 68 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 71 +#define GCC_QUPV3_WRAP1_CORE_CLK 72 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 73 +#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 74 +#define GCC_QUPV3_WRAP1_S0_CLK 75 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 76 +#define GCC_QUPV3_WRAP1_S1_CLK 77 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 78 +#define GCC_QUPV3_WRAP1_S2_CLK 79 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 80 +#define GCC_QUPV3_WRAP1_S3_CLK 81 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 82 +#define GCC_QUPV3_WRAP1_S4_CLK 83 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 84 +#define GCC_QUPV3_WRAP1_S5_CLK 85 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 86 +#define GCC_QUPV3_WRAP1_S6_CLK 87 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 88 +#define GCC_QUPV3_WRAP1_S7_CLK 89 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 90 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 91 +#define GCC_QUPV3_WRAP2_CORE_CLK 92 +#define GCC_QUPV3_WRAP2_S0_CLK 93 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 94 +#define GCC_QUPV3_WRAP2_S1_CLK 95 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 96 +#define GCC_QUPV3_WRAP2_S2_CLK 97 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 98 +#define GCC_QUPV3_WRAP2_S3_CLK 99 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 100 +#define GCC_QUPV3_WRAP2_S4_CLK 101 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 102 +#define GCC_QUPV3_WRAP2_S5_CLK 103 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 104 +#define GCC_QUPV3_WRAP2_S6_CLK 105 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 106 +#define GCC_QUPV3_WRAP2_S7_CLK 107 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 108 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 109 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 110 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 111 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 112 +#define GCC_SDCC1_AHB_CLK 113 +#define GCC_SDCC1_APPS_CLK 114 +#define GCC_SDCC1_APPS_CLK_SRC 115 +#define GCC_SDCC1_ICE_CORE_CLK 116 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 117 +#define GCC_SDCC2_AHB_CLK 118 +#define GCC_SDCC2_APPS_CLK 119 +#define GCC_SDCC2_APPS_CLK_SRC 120 +#define GCC_UFS_PHY_AHB_CLK 121 +#define GCC_UFS_PHY_AXI_CLK 122 +#define GCC_UFS_PHY_AXI_CLK_SRC 123 +#define GCC_UFS_PHY_ICE_CORE_CLK 124 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 125 +#define GCC_UFS_PHY_PHY_AUX_CLK 126 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 127 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 128 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 129 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 130 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 131 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 132 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 133 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 134 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135 +#define GCC_USB30_PRIM_ATB_CLK 136 +#define GCC_USB30_PRIM_MASTER_CLK 137 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 138 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 139 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 140 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 141 +#define GCC_USB30_PRIM_SLEEP_CLK 142 +#define GCC_USB3_PRIM_PHY_AUX_CLK 143 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 144 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 145 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 146 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 147 +#define GCC_VIDEO_AHB_CLK 148 +#define GCC_VIDEO_AXI0_CLK 149 +#define GCC_VIDEO_AXI1_CLK 150 +#define GCC_VIDEO_XO_CLK 151 + +/* GCC power domains */ +#define GCC_PCIE_0_GDSC 0 +#define GCC_PCIE_0_PHY_GDSC 1 +#define GCC_PCIE_1_GDSC 2 +#define GCC_PCIE_1_PHY_GDSC 3 +#define GCC_UFS_MEM_PHY_GDSC 4 +#define GCC_UFS_PHY_GDSC 5 +#define GCC_USB30_PRIM_GDSC 6 +#define GCC_USB3_PHY_GDSC 7 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_1_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_PHY_BCR 13 +#define GCC_PCIE_PHY_CFG_AHB_BCR 14 +#define GCC_PCIE_PHY_COM_BCR 15 +#define GCC_PCIE_RSCC_BCR 16 +#define GCC_PDM_BCR 17 +#define GCC_QUPV3_WRAPPER_1_BCR 18 +#define GCC_QUPV3_WRAPPER_2_BCR 19 +#define GCC_QUSB2PHY_PRIM_BCR 20 +#define GCC_QUSB2PHY_SEC_BCR 21 +#define GCC_SDCC1_BCR 22 +#define GCC_SDCC2_BCR 23 +#define GCC_UFS_PHY_BCR 24 +#define GCC_USB30_PRIM_BCR 25 +#define GCC_USB3_DP_PHY_PRIM_BCR 26 +#define GCC_USB3_DP_PHY_SEC_BCR 27 +#define GCC_USB3_PHY_PRIM_BCR 28 +#define GCC_USB3_PHY_SEC_BCR 29 +#define GCC_USB3PHY_PHY_PRIM_BCR 30 +#define GCC_USB3PHY_PHY_SEC_BCR 31 +#define GCC_VIDEO_AXI0_CLK_ARES 32 +#define GCC_VIDEO_AXI1_CLK_ARES 33 +#define GCC_VIDEO_BCR 34 + +#endif diff --git a/include/dt-bindings/clock/qcom,eliza-tcsr.h b/include/dt-bindings/clock/qcom,eliza-tcsr.h new file mode 100644 index 000000000000..aeb5e2b1a47b --- /dev/null +++ b/include/dt-bindings/clock/qcom,eliza-tcsr.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_ELIZA_H +#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_ELIZA_H + +/* TCSR_CC clocks */ +#define TCSR_HDMI_CLKREF_EN 0 +#define TCSR_PCIE_0_CLKREF_EN 1 +#define TCSR_PCIE_1_CLKREF_EN 2 +#define TCSR_UFS_CLKREF_EN 3 +#define TCSR_USB2_CLKREF_EN 4 +#define TCSR_USB3_CLKREF_EN 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,ipq5210-gcc.h b/include/dt-bindings/clock/qcom,ipq5210-gcc.h new file mode 100644 index 000000000000..84116f34ee4d --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5210-gcc.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H + +#define GCC_ADSS_PWM_CLK 0 +#define GCC_ADSS_PWM_CLK_SRC 1 +#define GCC_CMN_12GPLL_AHB_CLK 2 +#define GCC_CMN_12GPLL_SYS_CLK 3 +#define GCC_CNOC_LPASS_CFG_CLK 4 +#define GCC_CNOC_PCIE0_1LANE_S_CLK 5 +#define GCC_CNOC_PCIE1_2LANE_S_CLK 6 +#define GCC_CNOC_USB_CLK 7 +#define GCC_GEPHY_SYS_CLK 8 +#define GCC_LPASS_AXIM_CLK_SRC 9 +#define GCC_LPASS_CORE_AXIM_CLK 10 +#define GCC_LPASS_SWAY_CLK 11 +#define GCC_LPASS_SWAY_CLK_SRC 12 +#define GCC_MDIO_AHB_CLK 13 +#define GCC_MDIO_GEPHY_AHB_CLK 14 +#define GCC_NSS_TS_CLK 15 +#define GCC_NSS_TS_CLK_SRC 16 +#define GCC_NSSCC_CLK 17 +#define GCC_NSSCFG_CLK 18 +#define GCC_NSSNOC_ATB_CLK 19 +#define GCC_NSSNOC_MEMNOC_1_CLK 20 +#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 +#define GCC_NSSNOC_MEMNOC_CLK 22 +#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 +#define GCC_NSSNOC_NSSCC_CLK 24 +#define GCC_NSSNOC_PCNOC_1_CLK 25 +#define GCC_NSSNOC_QOSGEN_REF_CLK 26 +#define GCC_NSSNOC_SNOC_1_CLK 27 +#define GCC_NSSNOC_SNOC_CLK 28 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 29 +#define GCC_NSSNOC_XO_DCD_CLK 30 +#define GCC_PCIE0_AHB_CLK 31 +#define GCC_PCIE0_AUX_CLK 32 +#define GCC_PCIE0_AXI_M_CLK 33 +#define GCC_PCIE0_AXI_M_CLK_SRC 34 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 35 +#define GCC_PCIE0_AXI_S_CLK 36 +#define GCC_PCIE0_AXI_S_CLK_SRC 37 +#define GCC_PCIE0_PIPE_CLK 38 +#define GCC_PCIE0_PIPE_CLK_SRC 39 +#define GCC_PCIE0_RCHNG_CLK 40 +#define GCC_PCIE0_RCHNG_CLK_SRC 41 +#define GCC_PCIE1_AHB_CLK 42 +#define GCC_PCIE1_AUX_CLK 43 +#define GCC_PCIE1_AXI_M_CLK 44 +#define GCC_PCIE1_AXI_M_CLK_SRC 45 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 46 +#define GCC_PCIE1_AXI_S_CLK 47 +#define GCC_PCIE1_AXI_S_CLK_SRC 48 +#define GCC_PCIE1_PIPE_CLK 49 +#define GCC_PCIE1_PIPE_CLK_SRC 50 +#define GCC_PCIE1_RCHNG_CLK 51 +#define GCC_PCIE1_RCHNG_CLK_SRC 52 +#define GCC_PCIE_AUX_CLK_SRC 53 +#define GCC_PCNOC_BFDCD_CLK_SRC 54 +#define GCC_PON_APB_CLK 55 +#define GCC_PON_TM_CLK 56 +#define GCC_PON_TM2X_CLK 57 +#define GCC_PON_TM2X_CLK_SRC 58 +#define GCC_QDSS_AT_CLK 59 +#define GCC_QDSS_AT_CLK_SRC 60 +#define GCC_QDSS_DAP_CLK 61 +#define GCC_QDSS_TSCTR_CLK_SRC 62 +#define GCC_QPIC_AHB_CLK 63 +#define GCC_QPIC_CLK 64 +#define GCC_QPIC_CLK_SRC 65 +#define GCC_QPIC_IO_MACRO_CLK 66 +#define GCC_QPIC_IO_MACRO_CLK_SRC 67 +#define GCC_QRNG_AHB_CLK 68 +#define GCC_QUPV3_AHB_MST_CLK 69 +#define GCC_QUPV3_AHB_SLV_CLK 70 +#define GCC_QUPV3_WRAP_SE0_CLK 71 +#define GCC_QUPV3_WRAP_SE0_CLK_SRC 72 +#define GCC_QUPV3_WRAP_SE1_CLK 73 +#define GCC_QUPV3_WRAP_SE1_CLK_SRC 74 +#define GCC_QUPV3_WRAP_SE2_CLK 75 +#define GCC_QUPV3_WRAP_SE2_CLK_SRC 76 +#define GCC_QUPV3_WRAP_SE3_CLK 77 +#define GCC_QUPV3_WRAP_SE3_CLK_SRC 78 +#define GCC_QUPV3_WRAP_SE4_CLK 79 +#define GCC_QUPV3_WRAP_SE4_CLK_SRC 80 +#define GCC_QUPV3_WRAP_SE5_CLK 81 +#define GCC_QUPV3_WRAP_SE5_CLK_SRC 82 +#define GCC_SDCC1_AHB_CLK 83 +#define GCC_SDCC1_APPS_CLK 84 +#define GCC_SDCC1_APPS_CLK_SRC 85 +#define GCC_SDCC1_ICE_CORE_CLK 86 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 87 +#define GCC_SLEEP_CLK_SRC 88 +#define GCC_SNOC_LPASS_CLK 89 +#define GCC_SNOC_PCIE0_AXI_M_CLK 90 +#define GCC_SNOC_PCIE1_AXI_M_CLK 91 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92 +#define GCC_UNIPHY0_AHB_CLK 93 +#define GCC_UNIPHY0_SYS_CLK 94 +#define GCC_UNIPHY1_AHB_CLK 95 +#define GCC_UNIPHY1_SYS_CLK 96 +#define GCC_UNIPHY2_AHB_CLK 97 +#define GCC_UNIPHY2_SYS_CLK 98 +#define GCC_UNIPHY_SYS_CLK_SRC 99 +#define GCC_USB0_AUX_CLK 100 +#define GCC_USB0_AUX_CLK_SRC 101 +#define GCC_USB0_MASTER_CLK 102 +#define GCC_USB0_MASTER_CLK_SRC 103 +#define GCC_USB0_MOCK_UTMI_CLK 104 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 105 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106 +#define GCC_USB0_PHY_CFG_AHB_CLK 107 +#define GCC_USB0_PIPE_CLK 108 +#define GCC_USB0_PIPE_CLK_SRC 109 +#define GCC_USB0_SLEEP_CLK 110 +#define GCC_XO_CLK_SRC 111 +#define GPLL0_MAIN 112 +#define GPLL0 113 +#define GPLL2_MAIN 114 +#define GPLL2 115 +#define GPLL4_MAIN 116 +#endif diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h index d1a6c45b5029..ab8d312ade37 100644 --- a/include/dt-bindings/clock/qcom,sm6115-dispcc.h +++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h @@ -6,7 +6,7 @@ #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H -/* DISP_CC clocks */ +/* Clocks */ #define DISP_CC_PLL0 0 #define DISP_CC_PLL0_OUT_MAIN 1 #define DISP_CC_MDSS_AHB_CLK 2 @@ -30,7 +30,10 @@ #define DISP_CC_SLEEP_CLK 20 #define DISP_CC_SLEEP_CLK_SRC 21 -/* DISP_CC GDSCR */ +/* Resets */ +#define DISP_CC_MDSS_CORE_BCR 0 + +/* GDSCs */ #define MDSS_GDSC 0 #endif diff --git a/include/dt-bindings/clock/renesas,r9a08g046-cpg.h b/include/dt-bindings/clock/renesas,r9a08g046-cpg.h new file mode 100644 index 000000000000..018b0a1e4340 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a08g046-cpg.h @@ -0,0 +1,342 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ + +#include + +/* R9A08G046 CPG Core Clocks */ +#define R9A08G046_CLK_I 0 +#define R9A08G046_CLK_IC0 1 +#define R9A08G046_CLK_IC1 2 +#define R9A08G046_CLK_IC2 3 +#define R9A08G046_CLK_IC3 4 +#define R9A08G046_CLK_P0 5 +#define R9A08G046_CLK_P1 6 +#define R9A08G046_CLK_P2 7 +#define R9A08G046_CLK_P3 8 +#define R9A08G046_CLK_P4 9 +#define R9A08G046_CLK_P5 10 +#define R9A08G046_CLK_P6 11 +#define R9A08G046_CLK_P7 12 +#define R9A08G046_CLK_P8 13 +#define R9A08G046_CLK_P9 14 +#define R9A08G046_CLK_P10 15 +#define R9A08G046_CLK_P13 16 +#define R9A08G046_CLK_P14 17 +#define R9A08G046_CLK_P15 18 +#define R9A08G046_CLK_P16 19 +#define R9A08G046_CLK_P17 20 +#define R9A08G046_CLK_P18 21 +#define R9A08G046_CLK_P19 22 +#define R9A08G046_CLK_P20 23 +#define R9A08G046_CLK_M0 24 +#define R9A08G046_CLK_M1 25 +#define R9A08G046_CLK_M2 26 +#define R9A08G046_CLK_M3 27 +#define R9A08G046_CLK_M4 28 +#define R9A08G046_CLK_M5 29 +#define R9A08G046_CLK_M6 30 +#define R9A08G046_CLK_AT 31 +#define R9A08G046_CLK_B 32 +#define R9A08G046_CLK_ETHTX01 33 +#define R9A08G046_CLK_ETHTX02 34 +#define R9A08G046_CLK_ETHRX01 35 +#define R9A08G046_CLK_ETHRX02 36 +#define R9A08G046_CLK_ETHRM0 37 +#define R9A08G046_CLK_ETHTX11 38 +#define R9A08G046_CLK_ETHTX12 39 +#define R9A08G046_CLK_ETHRX11 40 +#define R9A08G046_CLK_ETHRX12 41 +#define R9A08G046_CLK_ETHRM1 42 +#define R9A08G046_CLK_G 43 +#define R9A08G046_CLK_HP 44 +#define R9A08G046_CLK_SD0 45 +#define R9A08G046_CLK_SD1 46 +#define R9A08G046_CLK_SD2 47 +#define R9A08G046_CLK_SPI0 48 +#define R9A08G046_CLK_SPI1 49 +#define R9A08G046_CLK_S0 50 +#define R9A08G046_CLK_SWD 51 +#define R9A08G046_OSCCLK 52 +#define R9A08G046_OSCCLK2 53 +#define R9A08G046_MIPI_DSI_PLLCLK 54 +#define R9A08G046_USB_SCLK 55 + +/* R9A08G046 Module Clocks */ +#define R9A08G046_CA55_SCLK 0 +#define R9A08G046_CA55_PCLK 1 +#define R9A08G046_CA55_ATCLK 2 +#define R9A08G046_CA55_GICCLK 3 +#define R9A08G046_CA55_PERICLK 4 +#define R9A08G046_CA55_ACLK 5 +#define R9A08G046_CA55_TSCLK 6 +#define R9A08G046_CA55_CORECLK0 7 +#define R9A08G046_CA55_CORECLK1 8 +#define R9A08G046_CA55_CORECLK2 9 +#define R9A08G046_CA55_CORECLK3 10 +#define R9A08G046_SRAM_ACPU_ACLK0 11 +#define R9A08G046_SRAM_ACPU_ACLK1 12 +#define R9A08G046_SRAM_ACPU_ACLK2 13 +#define R9A08G046_GIC600_GICCLK 14 +#define R9A08G046_IA55_CLK 15 +#define R9A08G046_IA55_PCLK 16 +#define R9A08G046_MHU_PCLK 17 +#define R9A08G046_SYC_CNT_CLK 18 +#define R9A08G046_DMAC_ACLK 19 +#define R9A08G046_DMAC_PCLK 20 +#define R9A08G046_OSTM0_PCLK 21 +#define R9A08G046_OSTM1_PCLK 22 +#define R9A08G046_OSTM2_PCLK 23 +#define R9A08G046_MTU_X_MCK_MTU3 24 +#define R9A08G046_POE3_CLKM_POE 25 +#define R9A08G046_GPT_PCLK 26 +#define R9A08G046_POEG_A_CLKP 27 +#define R9A08G046_POEG_B_CLKP 28 +#define R9A08G046_POEG_C_CLKP 29 +#define R9A08G046_POEG_D_CLKP 30 +#define R9A08G046_WDT0_PCLK 31 +#define R9A08G046_WDT0_CLK 32 +#define R9A08G046_WDT1_PCLK 33 +#define R9A08G046_WDT1_CLK 34 +#define R9A08G046_WDT2_PCLK 35 +#define R9A08G046_WDT2_CLK 36 +#define R9A08G046_XSPI_HCLK 37 +#define R9A08G046_XSPI_ACLK 38 +#define R9A08G046_XSPI_CLK 39 +#define R9A08G046_XSPI_CLKX2 40 +#define R9A08G046_SDHI0_IMCLK 41 +#define R9A08G046_SDHI0_IMCLK2 42 +#define R9A08G046_SDHI0_CLK_HS 43 +#define R9A08G046_SDHI0_IACLKS 44 +#define R9A08G046_SDHI0_IACLKM 45 +#define R9A08G046_SDHI1_IMCLK 46 +#define R9A08G046_SDHI1_IMCLK2 47 +#define R9A08G046_SDHI1_CLK_HS 48 +#define R9A08G046_SDHI1_IACLKS 49 +#define R9A08G046_SDHI1_IACLKM 50 +#define R9A08G046_SDHI2_IMCLK 51 +#define R9A08G046_SDHI2_IMCLK2 52 +#define R9A08G046_SDHI2_CLK_HS 53 +#define R9A08G046_SDHI2_IACLKS 54 +#define R9A08G046_SDHI2_IACLKM 55 +#define R9A08G046_GE3D_CLK 56 +#define R9A08G046_GE3D_AXI_CLK 57 +#define R9A08G046_GE3D_ACE_CLK 58 +#define R9A08G046_ISU_ACLK 59 +#define R9A08G046_ISU_PCLK 60 +#define R9A08G046_H264_CLK_A 61 +#define R9A08G046_H264_CLK_P 62 +#define R9A08G046_CRU_SYSCLK 63 +#define R9A08G046_CRU_VCLK 64 +#define R9A08G046_CRU_PCLK 65 +#define R9A08G046_CRU_ACLK 66 +#define R9A08G046_MIPI_DSI_SYSCLK 67 +#define R9A08G046_MIPI_DSI_ACLK 68 +#define R9A08G046_MIPI_DSI_PCLK 69 +#define R9A08G046_MIPI_DSI_VCLK 70 +#define R9A08G046_MIPI_DSI_LPCLK 71 +#define R9A08G046_LVDS_PLLCLK 72 +#define R9A08G046_LVDS_CLK_DOT0 73 +#define R9A08G046_LCDC_CLK_A 74 +#define R9A08G046_LCDC_CLK_D 75 +#define R9A08G046_LCDC_CLK_P 76 +#define R9A08G046_SSI0_PCLK2 77 +#define R9A08G046_SSI0_PCLK_SFR 78 +#define R9A08G046_SSI1_PCLK2 79 +#define R9A08G046_SSI1_PCLK_SFR 80 +#define R9A08G046_SSI2_PCLK2 81 +#define R9A08G046_SSI2_PCLK_SFR 82 +#define R9A08G046_SSI3_PCLK2 83 +#define R9A08G046_SSI3_PCLK_SFR 84 +#define R9A08G046_USB_U2H0_HCLK 85 +#define R9A08G046_USB_U2H1_HCLK 86 +#define R9A08G046_USB_U2P0_EXR_CPUCLK 87 +#define R9A08G046_USB_U2P1_EXR_CPUCLK 88 +#define R9A08G046_USB_PCLK 89 +#define R9A08G046_ETH0_CLK_AXI 90 +#define R9A08G046_ETH0_CLK_CHI 91 +#define R9A08G046_ETH0_CLK_TX_I 92 +#define R9A08G046_ETH0_CLK_RX_I 93 +#define R9A08G046_ETH0_CLK_TX_180_I 94 +#define R9A08G046_ETH0_CLK_RX_180_I 95 +#define R9A08G046_ETH0_CLK_RMII_I 96 +#define R9A08G046_ETH0_CLK_PTP_REF_I 97 +#define R9A08G046_ETH0_CLK_TX_I_RMII 98 +#define R9A08G046_ETH0_CLK_RX_I_RMII 99 +#define R9A08G046_ETH1_CLK_AXI 100 +#define R9A08G046_ETH1_CLK_CHI 101 +#define R9A08G046_ETH1_CLK_TX_I 102 +#define R9A08G046_ETH1_CLK_RX_I 103 +#define R9A08G046_ETH1_CLK_TX_180_I 104 +#define R9A08G046_ETH1_CLK_RX_180_I 105 +#define R9A08G046_ETH1_CLK_RMII_I 106 +#define R9A08G046_ETH1_CLK_PTP_REF_I 107 +#define R9A08G046_ETH1_CLK_TX_I_RMII 108 +#define R9A08G046_ETH1_CLK_RX_I_RMII 109 +#define R9A08G046_I2C0_PCLK 110 +#define R9A08G046_I2C1_PCLK 111 +#define R9A08G046_I2C2_PCLK 112 +#define R9A08G046_I2C3_PCLK 113 +#define R9A08G046_SCIF0_CLK_PCK 114 +#define R9A08G046_SCIF1_CLK_PCK 115 +#define R9A08G046_SCIF2_CLK_PCK 116 +#define R9A08G046_SCIF3_CLK_PCK 117 +#define R9A08G046_SCIF4_CLK_PCK 118 +#define R9A08G046_SCIF5_CLK_PCK 119 +#define R9A08G046_RSCI0_PCLK 120 +#define R9A08G046_RSCI0_TCLK 121 +#define R9A08G046_RSCI1_PCLK 122 +#define R9A08G046_RSCI1_TCLK 123 +#define R9A08G046_RSCI2_PCLK 124 +#define R9A08G046_RSCI2_TCLK 125 +#define R9A08G046_RSCI3_PCLK 126 +#define R9A08G046_RSCI3_TCLK 127 +#define R9A08G046_RSPI0_PCLK 128 +#define R9A08G046_RSPI0_TCLK 129 +#define R9A08G046_RSPI1_PCLK 130 +#define R9A08G046_RSPI1_TCLK 131 +#define R9A08G046_RSPI2_PCLK 132 +#define R9A08G046_RSPI2_TCLK 133 +#define R9A08G046_CANFD_PCLK 134 +#define R9A08G046_CANFD_CLK_RAM 135 +#define R9A08G046_GPIO_HCLK 136 +#define R9A08G046_ADC0_ADCLK 137 +#define R9A08G046_ADC0_PCLK 138 +#define R9A08G046_ADC1_ADCLK 139 +#define R9A08G046_ADC1_PCLK 140 +#define R9A08G046_TSU_PCLK 141 +#define R9A08G046_PDM_PCLK 142 +#define R9A08G046_PDM_CCLK 143 +#define R9A08G046_PCI_ACLK 144 +#define R9A08G046_PCI_CLKL1PM 145 +#define R9A08G046_PCI_CLK_PMU 146 +#define R9A08G046_SPDIF_PCLK 147 +#define R9A08G046_I3C_TCLK 148 +#define R9A08G046_I3C_PCLK 149 +#define R9A08G046_VBAT_BCLK 150 +#define R9A08G046_BSC_X_BCK_BSC 151 + +/* R9A08G046 Resets */ +#define R9A08G046_CA55_RST0_0 0 +#define R9A08G046_CA55_RST0_1 1 +#define R9A08G046_CA55_RST0_2 2 +#define R9A08G046_CA55_RST0_3 3 +#define R9A08G046_CA55_RST4_0 4 +#define R9A08G046_CA55_RST4_1 5 +#define R9A08G046_CA55_RST4_2 6 +#define R9A08G046_CA55_RST4_3 7 +#define R9A08G046_CA55_RST8 8 +#define R9A08G046_CA55_RST9 9 +#define R9A08G046_CA55_RST10 10 +#define R9A08G046_CA55_RST11 11 +#define R9A08G046_CA55_RST12 12 +#define R9A08G046_CA55_RST13 13 +#define R9A08G046_CA55_RST14 14 +#define R9A08G046_CA55_RST15 15 +#define R9A08G046_CA55_RST16 16 +#define R9A08G046_SRAM_ACPU_ARESETN0 17 +#define R9A08G046_SRAM_ACPU_ARESETN1 18 +#define R9A08G046_SRAM_ACPU_ARESETN2 19 +#define R9A08G046_GIC600_GICRESET_N 20 +#define R9A08G046_GIC600_DBG_GICRESET_N 21 +#define R9A08G046_IA55_RESETN 22 +#define R9A08G046_MHU_RESETN 23 +#define R9A08G046_SYC_RESETN 24 +#define R9A08G046_DMAC_ARESETN 25 +#define R9A08G046_DMAC_RST_ASYNC 26 +#define R9A08G046_GTM0_PRESETZ 27 +#define R9A08G046_GTM1_PRESETZ 28 +#define R9A08G046_GTM2_PRESETZ 29 +#define R9A08G046_MTU_X_PRESET_MTU3 30 +#define R9A08G046_POE3_RST_M_REG 31 +#define R9A08G046_GPT_RST_C 32 +#define R9A08G046_POEG_A_RST 33 +#define R9A08G046_POEG_B_RST 34 +#define R9A08G046_POEG_C_RST 35 +#define R9A08G046_POEG_D_RST 36 +#define R9A08G046_WDT0_PRESETN 37 +#define R9A08G046_WDT1_PRESETN 38 +#define R9A08G046_WDT2_PRESETN 39 +#define R9A08G046_XSPI_HRESETN 40 +#define R9A08G046_XSPI_ARESETN 41 +#define R9A08G046_SDHI0_IXRST 42 +#define R9A08G046_SDHI1_IXRST 43 +#define R9A08G046_SDHI2_IXRST 44 +#define R9A08G046_SDHI0_IXRSTAXIM 45 +#define R9A08G046_SDHI0_IXRSTAXIS 46 +#define R9A08G046_SDHI1_IXRSTAXIM 47 +#define R9A08G046_SDHI1_IXRSTAXIS 48 +#define R9A08G046_SDHI2_IXRSTAXIM 49 +#define R9A08G046_SDHI2_IXRSTAXIS 50 +#define R9A08G046_GE3D_RESETN 51 +#define R9A08G046_GE3D_AXI_RESETN 52 +#define R9A08G046_GE3D_ACE_RESETN 53 +#define R9A08G046_ISU_ARESETN 54 +#define R9A08G046_ISU_PRESETN 55 +#define R9A08G046_H264_X_RESET_VCP 56 +#define R9A08G046_H264_CP_PRESET_P 57 +#define R9A08G046_CRU_CMN_RSTB 58 +#define R9A08G046_CRU_PRESETN 59 +#define R9A08G046_CRU_ARESETN 60 +#define R9A08G046_MIPI_DSI_CMN_RSTB 61 +#define R9A08G046_MIPI_DSI_ARESET_N 62 +#define R9A08G046_MIPI_DSI_PRESET_N 63 +#define R9A08G046_LCDC_RESET_N 64 +#define R9A08G046_SSI0_RST_M2_REG 65 +#define R9A08G046_SSI1_RST_M2_REG 66 +#define R9A08G046_SSI2_RST_M2_REG 67 +#define R9A08G046_SSI3_RST_M2_REG 68 +#define R9A08G046_USB_U2H0_HRESETN 69 +#define R9A08G046_USB_U2H1_HRESETN 70 +#define R9A08G046_USB_U2P0_EXL_SYSRST 71 +#define R9A08G046_USB_PRESETN 72 +#define R9A08G046_USB_U2P1_EXL_SYSRST 73 +#define R9A08G046_ETH0_ARESET_N 74 +#define R9A08G046_ETH1_ARESET_N 75 +#define R9A08G046_I2C0_MRST 76 +#define R9A08G046_I2C1_MRST 77 +#define R9A08G046_I2C2_MRST 78 +#define R9A08G046_I2C3_MRST 79 +#define R9A08G046_SCIF0_RST_SYSTEM_N 80 +#define R9A08G046_SCIF1_RST_SYSTEM_N 81 +#define R9A08G046_SCIF2_RST_SYSTEM_N 82 +#define R9A08G046_SCIF3_RST_SYSTEM_N 83 +#define R9A08G046_SCIF4_RST_SYSTEM_N 84 +#define R9A08G046_SCIF5_RST_SYSTEM_N 85 +#define R9A08G046_RSPI0_PRESETN 86 +#define R9A08G046_RSPI1_PRESETN 87 +#define R9A08G046_RSPI2_PRESETN 88 +#define R9A08G046_RSPI0_TRESETN 89 +#define R9A08G046_RSPI1_TRESETN 90 +#define R9A08G046_RSPI2_TRESETN 91 +#define R9A08G046_CANFD_RSTP_N 92 +#define R9A08G046_CANFD_RSTC_N 93 +#define R9A08G046_GPIO_RSTN 94 +#define R9A08G046_GPIO_PORT_RESETN 95 +#define R9A08G046_GPIO_SPARE_RESETN 96 +#define R9A08G046_ADC0_PRESETN 97 +#define R9A08G046_ADC0_ADRST_N 98 +#define R9A08G046_ADC1_PRESETN 99 +#define R9A08G046_ADC1_ADRST_N 100 +#define R9A08G046_TSU_PRESETN 101 +#define R9A08G046_PDM_PRESETN 102 +#define R9A08G046_PCI_ARESETN 103 +#define R9A08G046_SPDIF_RST 104 +#define R9A08G046_I3C_TRESETN 105 +#define R9A08G046_I3C_PRESETN 106 +#define R9A08G046_VBAT_BRESETN 107 +#define R9A08G046_RSCI0_PRESETN 108 +#define R9A08G046_RSCI1_PRESETN 109 +#define R9A08G046_RSCI2_PRESETN 110 +#define R9A08G046_RSCI3_PRESETN 111 +#define R9A08G046_RSCI0_TRESETN 112 +#define R9A08G046_RSCI1_TRESETN 113 +#define R9A08G046_RSCI2_TRESETN 114 +#define R9A08G046_RSCI3_TRESETN 115 +#define R9A08G046_LVDS_RESET_N 116 +#define R9A08G046_BSC_X_PRESET_BSC 117 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G046_CPG_H__ */ diff --git a/include/dt-bindings/clock/rockchip,rv1103b-cru.h b/include/dt-bindings/clock/rockchip,rv1103b-cru.h new file mode 100644 index 000000000000..35afdee7e961 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rv1103b-cru.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H + +#define PLL_GPLL 0 +#define ARMCLK 1 +#define PLL_DPLL 2 +#define XIN_OSC0_HALF 3 +#define CLK_GPLL_DIV24 4 +#define CLK_GPLL_DIV12 5 +#define CLK_GPLL_DIV6 6 +#define CLK_GPLL_DIV4 7 +#define CLK_GPLL_DIV3 8 +#define CLK_GPLL_DIV2P5 9 +#define CLK_GPLL_DIV2 10 +#define CLK_UART0_SRC 11 +#define CLK_UART1_SRC 12 +#define CLK_UART2_SRC 13 +#define CLK_UART0_FRAC 14 +#define CLK_UART1_FRAC 15 +#define CLK_UART2_FRAC 16 +#define CLK_SAI_SRC 17 +#define CLK_SAI_FRAC 18 +#define LSCLK_NPU_SRC 19 +#define CLK_NPU_SRC 20 +#define ACLK_VEPU_SRC 21 +#define CLK_VEPU_SRC 22 +#define ACLK_VI_SRC 23 +#define CLK_ISP_SRC 24 +#define DCLK_VICAP 25 +#define CCLK_EMMC 26 +#define CCLK_SDMMC0 27 +#define SCLK_SFC_2X 28 +#define LSCLK_PERI_SRC 29 +#define ACLK_PERI_SRC 30 +#define HCLK_HPMCU 31 +#define SCLK_UART0 32 +#define SCLK_UART1 33 +#define SCLK_UART2 34 +#define CLK_I2C_PMU 35 +#define CLK_I2C_PERI 36 +#define CLK_SPI0 37 +#define CLK_PWM0_SRC 38 +#define CLK_PWM1 39 +#define CLK_PWM2 40 +#define DCLK_DECOM_SRC 41 +#define CCLK_SDMMC1 42 +#define CLK_CORE_CRYPTO 43 +#define CLK_PKA_CRYPTO 44 +#define CLK_CORE_RGA 45 +#define MCLK_SAI_SRC 46 +#define CLK_FREQ_PWM0_SRC 47 +#define CLK_COUNTER_PWM0_SRC 48 +#define PCLK_TOP_ROOT 49 +#define CLK_REF_MIPI0 50 +#define CLK_MIPI0_OUT2IO 51 +#define CLK_REF_MIPI1 52 +#define CLK_MIPI1_OUT2IO 53 +#define MCLK_SAI_OUT2IO 54 +#define ACLK_NPU_ROOT 55 +#define HCLK_RKNN 56 +#define ACLK_RKNN 57 +#define LSCLK_VEPU_ROOT 58 +#define HCLK_VEPU 59 +#define ACLK_VEPU 60 +#define CLK_CORE_VEPU 61 +#define PCLK_IOC_VCCIO3 62 +#define PCLK_ACODEC 63 +#define PCLK_USBPHY 64 +#define LSCLK_VI_100M 65 +#define LSCLK_VI_ROOT 66 +#define HCLK_ISP 67 +#define ACLK_ISP 68 +#define CLK_CORE_ISP 69 +#define ACLK_VICAP 70 +#define HCLK_VICAP 71 +#define ISP0CLK_VICAP 72 +#define PCLK_CSI2HOST0 73 +#define PCLK_CSI2HOST1 74 +#define HCLK_EMMC 75 +#define HCLK_SFC 76 +#define HCLK_SFC_XIP 77 +#define HCLK_SDMMC0 78 +#define PCLK_CSIPHY 79 +#define PCLK_GPIO1 80 +#define DBCLK_GPIO1 81 +#define PCLK_IOC_VCCIO47 82 +#define LSCLK_DDR_ROOT 83 +#define CLK_TIMER_DDRMON 84 +#define LSCLK_PMU_ROOT 85 +#define PCLK_PMU 86 +#define XIN_RC_DIV 87 +#define CLK_32K 88 +#define PCLK_PMU_GPIO0 89 +#define DBCLK_PMU_GPIO0 90 +#define CLK_DDR_FAIL_SAFE 91 +#define PCLK_PMU_HP_TIMER 92 +#define CLK_PMU_32K_HP_TIMER 93 +#define PCLK_PWM0 94 +#define CLK_PWM0 95 +#define CLK_OSC_PWM0 96 +#define CLK_RC_PWM0 97 +#define CLK_FREQ_PWM0 98 +#define CLK_COUNTER_PWM0 99 +#define PCLK_I2C0 100 +#define CLK_I2C0 101 +#define PCLK_UART0 102 +#define PCLK_IOC_PMUIO0 103 +#define CLK_REFOUT 104 +#define CLK_PREROLL 105 +#define CLK_PREROLL_32K 106 +#define CLK_LPMCU_PMU 107 +#define PCLK_SPI2AHB 108 +#define HCLK_SPI2AHB 109 +#define SCLK_SPI2AHB 110 +#define PCLK_WDT_LPMCU 111 +#define TCLK_WDT_LPMCU 112 +#define HCLK_SFC_PMU1 113 +#define HCLK_SFC_XIP_PMU1 114 +#define SCLK_SFC_2X_PMU1 115 +#define CLK_LPMCU 116 +#define CLK_LPMCU_RTC 117 +#define PCLK_LPMCU_MAILBOX 118 +#define PCLK_IOC_PMUIO1 119 +#define PCLK_CRU_PMU1 120 +#define PCLK_PERI_ROOT 121 +#define PCLK_RTC_ROOT 122 +#define CLK_TIMER_ROOT 123 +#define PCLK_TIMER 124 +#define CLK_TIMER0 125 +#define CLK_TIMER1 126 +#define CLK_TIMER2 127 +#define CLK_TIMER3 128 +#define CLK_TIMER4 129 +#define CLK_TIMER5 130 +#define PCLK_STIMER 131 +#define CLK_STIMER0 132 +#define CLK_STIMER1 133 +#define PCLK_WDT_NS 134 +#define TCLK_WDT_NS 135 +#define PCLK_WDT_S 136 +#define TCLK_WDT_S 137 +#define PCLK_WDT_HPMCU 138 +#define TCLK_WDT_HPMCU 139 +#define PCLK_I2C1 140 +#define CLK_I2C1 141 +#define PCLK_I2C2 142 +#define CLK_I2C2 143 +#define PCLK_I2C3 144 +#define CLK_I2C3 145 +#define PCLK_I2C4 146 +#define CLK_I2C4 147 +#define PCLK_SPI0 148 +#define PCLK_PWM1 149 +#define CLK_OSC_PWM1 150 +#define PCLK_PWM2 151 +#define CLK_OSC_PWM2 152 +#define PCLK_UART2 153 +#define PCLK_UART1 154 +#define ACLK_RKDMA 155 +#define PCLK_TSADC 156 +#define CLK_TSADC 157 +#define CLK_TSADC_TSEN 158 +#define PCLK_SARADC 159 +#define CLK_SARADC 160 +#define PCLK_GPIO2 161 +#define DBCLK_GPIO2 162 +#define PCLK_IOC_VCCIO6 163 +#define ACLK_USBOTG 164 +#define CLK_REF_USBOTG 165 +#define HCLK_SDMMC1 166 +#define HCLK_SAI 167 +#define MCLK_SAI 168 +#define ACLK_CRYPTO 169 +#define HCLK_CRYPTO 170 +#define HCLK_RK_RNG_NS 171 +#define HCLK_RK_RNG_S 172 +#define PCLK_OTPC_NS 173 +#define CLK_OTPC_ROOT_NS 174 +#define CLK_SBPI_OTPC_NS 175 +#define CLK_USER_OTPC_NS 176 +#define PCLK_OTPC_S 177 +#define CLK_OTPC_ROOT_S 178 +#define CLK_SBPI_OTPC_S 179 +#define CLK_USER_OTPC_S 180 +#define CLK_OTPC_ARB 181 +#define PCLK_OTP_MASK 182 +#define HCLK_RGA 183 +#define ACLK_RGA 184 +#define ACLK_MAC 185 +#define PCLK_MAC 186 +#define CLK_MACPHY 187 +#define ACLK_SPINLOCK 188 +#define HCLK_CACHE 189 +#define PCLK_HPMCU_MAILBOX 190 +#define PCLK_HPMCU_INTMUX 191 +#define CLK_HPMCU 192 +#define CLK_HPMCU_RTC 193 +#define DCLK_DECOM 194 +#define ACLK_DECOM 195 +#define PCLK_DECOM 196 +#define ACLK_SYS_SRAM 197 +#define PCLK_DMA2DDR 198 +#define ACLK_DMA2DDR 199 +#define PCLK_DCF 200 +#define ACLK_DCF 201 +#define MCLK_ACODEC_TX 202 +#define SCLK_UART0_SRC 203 +#define SCLK_UART1_SRC 204 +#define SCLK_UART2_SRC 205 +#define XIN_RC_SRC 206 +#define CLK_UTMI_USBOTG 207 +#define CLK_REF_USBPHY 208 + +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H diff --git a/include/dt-bindings/interconnect/qcom,eliza-rpmh.h b/include/dt-bindings/interconnect/qcom,eliza-rpmh.h new file mode 100644 index 000000000000..95db2fe647de --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,eliza-rpmh.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_ELIZA_H + +#define MASTER_QSPI_0 0 +#define MASTER_QUP_1 1 +#define MASTER_UFS_MEM 2 +#define MASTER_USB3_0 3 +#define SLAVE_A1NOC_SNOC 4 + +#define MASTER_QUP_2 0 +#define MASTER_CRYPTO 1 +#define MASTER_IPA 2 +#define MASTER_SOCCP_AGGR_NOC 3 +#define MASTER_QDSS_ETR 4 +#define MASTER_QDSS_ETR_1 5 +#define MASTER_SDCC_1 6 +#define MASTER_SDCC_2 7 +#define SLAVE_A2NOC_SNOC 8 + +#define MASTER_QUP_CORE_1 0 +#define MASTER_QUP_CORE_2 1 +#define SLAVE_QUP_CORE_1 2 +#define SLAVE_QUP_CORE_2 3 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_AHB2PHY_SOUTH 1 +#define SLAVE_AHB2PHY_NORTH 2 +#define SLAVE_CAMERA_CFG 3 +#define SLAVE_CLK_CTL 4 +#define SLAVE_CRYPTO_0_CFG 5 +#define SLAVE_DISPLAY_CFG 6 +#define SLAVE_GFX3D_CFG 7 +#define SLAVE_I3C_IBI0_CFG 8 +#define SLAVE_I3C_IBI1_CFG 9 +#define SLAVE_IMEM_CFG 10 +#define SLAVE_CNOC_MSS 11 +#define SLAVE_PCIE_0_CFG 12 +#define SLAVE_PRNG 13 +#define SLAVE_QDSS_CFG 14 +#define SLAVE_QSPI_0 15 +#define SLAVE_QUP_1 16 +#define SLAVE_QUP_2 17 +#define SLAVE_SDCC_2 18 +#define SLAVE_TCSR 19 +#define SLAVE_TLMM 20 +#define SLAVE_UFS_MEM_CFG 21 +#define SLAVE_USB3_0 22 +#define SLAVE_VENUS_CFG 23 +#define SLAVE_VSENSE_CTRL_CFG 24 +#define SLAVE_CNOC_MNOC_HF_CFG 25 +#define SLAVE_CNOC_MNOC_SF_CFG 26 +#define SLAVE_PCIE_ANOC_CFG 27 +#define SLAVE_QDSS_STM 28 +#define SLAVE_TCU 29 + +#define MASTER_GEM_NOC_CNOC 0 +#define MASTER_GEM_NOC_PCIE_SNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_IPA_CFG 3 +#define SLAVE_IPC_ROUTER_CFG 4 +#define SLAVE_SOCCP 5 +#define SLAVE_TME_CFG 6 +#define SLAVE_APPSS 7 +#define SLAVE_CNOC_CFG 8 +#define SLAVE_DDRSS_CFG 9 +#define SLAVE_BOOT_IMEM 10 +#define SLAVE_IMEM 11 +#define SLAVE_BOOT_IMEM_2 12 +#define SLAVE_SERVICE_CNOC 13 +#define SLAVE_PCIE_0 14 +#define SLAVE_PCIE_1 15 + +#define MASTER_GPU_TCU 0 +#define MASTER_SYS_TCU 1 +#define MASTER_APPSS_PROC 2 +#define MASTER_GFX3D 3 +#define MASTER_LPASS_GEM_NOC 4 +#define MASTER_MSS_PROC 5 +#define MASTER_MNOC_HF_MEM_NOC 6 +#define MASTER_MNOC_SF_MEM_NOC 7 +#define MASTER_COMPUTE_NOC 8 +#define MASTER_ANOC_PCIE_GEM_NOC 9 +#define MASTER_SNOC_SF_MEM_NOC 10 +#define MASTER_WLAN_Q6 11 +#define MASTER_GIC 12 +#define SLAVE_GEM_NOC_CNOC 13 +#define SLAVE_LLCC 14 +#define SLAVE_MEM_NOC_PCIE_SNOC 15 + +#define MASTER_LPIAON_NOC 0 +#define SLAVE_LPASS_GEM_NOC 1 + +#define MASTER_LPASS_LPINOC 0 +#define SLAVE_LPIAON_NOC_LPASS_AG_NOC 1 + +#define MASTER_LPASS_PROC 0 +#define SLAVE_LPICX_NOC_LPIAON_NOC 1 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_NRT_ICP_SF 0 +#define MASTER_CAMNOC_RT_CDM_SF 1 +#define MASTER_CAMNOC_SF 2 +#define MASTER_VIDEO_MVP 3 +#define MASTER_VIDEO_V_PROC 4 +#define MASTER_CNOC_MNOC_SF_CFG 5 +#define MASTER_CAMNOC_HF 6 +#define MASTER_MDP 7 +#define MASTER_CNOC_MNOC_HF_CFG 8 +#define SLAVE_MNOC_SF_MEM_NOC 9 +#define SLAVE_SERVICE_MNOC_SF 10 +#define SLAVE_MNOC_HF_MEM_NOC 11 +#define SLAVE_SERVICE_MNOC_HF 12 + +#define MASTER_CDSP_PROC 0 +#define SLAVE_CDSP_MEM_NOC 1 + +#define MASTER_PCIE_ANOC_CFG 0 +#define MASTER_PCIE_0 1 +#define MASTER_PCIE_1 2 +#define SLAVE_ANOC_PCIE_GEM_NOC 3 +#define SLAVE_SERVICE_PCIE_ANOC 4 + +#define MASTER_A1NOC_SNOC 0 +#define MASTER_A2NOC_SNOC 1 +#define MASTER_CNOC_SNOC 2 +#define MASTER_NSINOC_SNOC 3 +#define SLAVE_SNOC_GEM_NOC_SF 4 + +#endif diff --git a/include/dt-bindings/reset/qcom,ipq5210-gcc.h b/include/dt-bindings/reset/qcom,ipq5210-gcc.h new file mode 100644 index 000000000000..09890a09087c --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq5210-gcc.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H +#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_ARES 1 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES 3 +#define GCC_APSS_AHB_ARES 4 +#define GCC_APSS_ATB_ARES 5 +#define GCC_APSS_AXI_ARES 6 +#define GCC_APSS_TS_ARES 7 +#define GCC_BOOT_ROM_AHB_ARES 8 +#define GCC_BOOT_ROM_BCR 9 +#define GCC_GEPHY_BCR 10 +#define GCC_GEPHY_SYS_ARES 11 +#define GCC_GP1_ARES 12 +#define GCC_GP2_ARES 13 +#define GCC_GP3_ARES 14 +#define GCC_MDIO_AHB_ARES 15 +#define GCC_MDIO_BCR 16 +#define GCC_MDIO_GEPHY_AHB_ARES 17 +#define GCC_NSS_BCR 18 +#define GCC_NSS_TS_ARES 19 +#define GCC_NSSCC_ARES 20 +#define GCC_NSSCFG_ARES 21 +#define GCC_NSSNOC_ATB_ARES 22 +#define GCC_NSSNOC_MEMNOC_1_ARES 23 +#define GCC_NSSNOC_MEMNOC_ARES 24 +#define GCC_NSSNOC_NSSCC_ARES 25 +#define GCC_NSSNOC_PCNOC_1_ARES 26 +#define GCC_NSSNOC_QOSGEN_REF_ARES 27 +#define GCC_NSSNOC_SNOC_1_ARES 28 +#define GCC_NSSNOC_SNOC_ARES 29 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 30 +#define GCC_NSSNOC_XO_DCD_ARES 31 +#define GCC_PCIE0_AHB_ARES 32 +#define GCC_PCIE0_AUX_ARES 33 +#define GCC_PCIE0_AXI_M_ARES 34 +#define GCC_PCIE0_AXI_S_BRIDGE_ARES 35 +#define GCC_PCIE0_AXI_S_ARES 36 +#define GCC_PCIE0_BCR 37 +#define GCC_PCIE0_LINK_DOWN_BCR 38 +#define GCC_PCIE0_PHY_BCR 39 +#define GCC_PCIE0_PIPE_ARES 40 +#define GCC_PCIE0PHY_PHY_BCR 41 +#define GCC_PCIE1_AHB_ARES 42 +#define GCC_PCIE1_AUX_ARES 43 +#define GCC_PCIE1_AXI_M_ARES 44 +#define GCC_PCIE1_AXI_S_BRIDGE_ARES 45 +#define GCC_PCIE1_AXI_S_ARES 46 +#define GCC_PCIE1_BCR 47 +#define GCC_PCIE1_LINK_DOWN_BCR 48 +#define GCC_PCIE1_PHY_BCR 49 +#define GCC_PCIE1_PIPE_ARES 50 +#define GCC_PCIE1PHY_PHY_BCR 51 +#define GCC_QRNG_AHB_ARES 52 +#define GCC_QRNG_BCR 53 +#define GCC_QUPV3_2X_CORE_ARES 54 +#define GCC_QUPV3_AHB_MST_ARES 55 +#define GCC_QUPV3_AHB_SLV_ARES 56 +#define GCC_QUPV3_BCR 57 +#define GCC_QUPV3_CORE_ARES 58 +#define GCC_QUPV3_WRAP_SE0_ARES 59 +#define GCC_QUPV3_WRAP_SE0_BCR 60 +#define GCC_QUPV3_WRAP_SE1_ARES 61 +#define GCC_QUPV3_WRAP_SE1_BCR 62 +#define GCC_QUPV3_WRAP_SE2_ARES 63 +#define GCC_QUPV3_WRAP_SE2_BCR 64 +#define GCC_QUPV3_WRAP_SE3_ARES 65 +#define GCC_QUPV3_WRAP_SE3_BCR 66 +#define GCC_QUPV3_WRAP_SE4_ARES 67 +#define GCC_QUPV3_WRAP_SE4_BCR 68 +#define GCC_QUPV3_WRAP_SE5_ARES 69 +#define GCC_QUPV3_WRAP_SE5_BCR 70 +#define GCC_QUSB2_0_PHY_BCR 71 +#define GCC_SDCC1_AHB_ARES 72 +#define GCC_SDCC1_APPS_ARES 73 +#define GCC_SDCC1_ICE_CORE_ARES 74 +#define GCC_SDCC_BCR 75 +#define GCC_TLMM_AHB_ARES 76 +#define GCC_TLMM_ARES 77 +#define GCC_TLMM_BCR 78 +#define GCC_UNIPHY0_AHB_ARES 79 +#define GCC_UNIPHY0_BCR 80 +#define GCC_UNIPHY0_SYS_ARES 81 +#define GCC_UNIPHY1_AHB_ARES 82 +#define GCC_UNIPHY1_BCR 83 +#define GCC_UNIPHY1_SYS_ARES 84 +#define GCC_UNIPHY2_AHB_ARES 85 +#define GCC_UNIPHY2_BCR 86 +#define GCC_UNIPHY2_SYS_ARES 87 +#define GCC_USB0_AUX_ARES 88 +#define GCC_USB0_MASTER_ARES 89 +#define GCC_USB0_MOCK_UTMI_ARES 90 +#define GCC_USB0_PHY_BCR 91 +#define GCC_USB0_PHY_CFG_AHB_ARES 92 +#define GCC_USB0_PIPE_ARES 93 +#define GCC_USB0_SLEEP_ARES 94 +#define GCC_USB3PHY_0_PHY_BCR 95 +#define GCC_USB_BCR 96 +#define GCC_PCIE0_PIPE_RESET 97 +#define GCC_PCIE0_CORE_STICKY_RESET 98 +#define GCC_PCIE0_AXI_S_STICKY_RESET 99 +#define GCC_PCIE0_AXI_S_RESET 100 +#define GCC_PCIE0_AXI_M_STICKY_RESET 101 +#define GCC_PCIE0_AXI_M_RESET 102 +#define GCC_PCIE0_AUX_RESET 103 +#define GCC_PCIE0_AHB_RESET 104 +#define GCC_PCIE1_PIPE_RESET 105 +#define GCC_PCIE1_CORE_STICKY_RESET 106 +#define GCC_PCIE1_AXI_S_STICKY_RESET 107 +#define GCC_PCIE1_AXI_S_RESET 108 +#define GCC_PCIE1_AXI_M_STICKY_RESET 109 +#define GCC_PCIE1_AXI_M_RESET 110 +#define GCC_PCIE1_AUX_RESET 111 +#define GCC_PCIE1_AHB_RESET 112 +#define GCC_UNIPHY0_XPCS_ARES 113 +#define GCC_UNIPHY1_XPCS_ARES 114 +#define GCC_UNIPHY2_XPCS_ARES 115 +#define GCC_QDSS_BCR 116 + +#endif