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m68k: coldfire: use ColdFire specifc IO access in system code

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Convert all ColdFire specific system setup code to only use the
newly created internal register access methods. This is replacing the
mixed and inconsistent use of readx/writex and __raw_readx/__raw_writex
for internal SoC registers.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
This commit is contained in:
Greg Ungerer 2026-04-17 23:52:10 +10:00 committed by Greg Ungerer
parent 69f78f9621
commit e629342493
4 changed files with 38 additions and 38 deletions
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8
arch/m68k/coldfire/clk.c
View File

@ -42,12 +42,12 @@ void __clk_init_disabled(struct clk *clk)
static void __clk_enable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR0);
mcf_write8(clk->slot, MCFPM_PPMCR0);
}
static void __clk_disable0(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR0);
mcf_write8(clk->slot, MCFPM_PPMSR0);
}
struct clk_ops clk_ops0 = {
@ -58,12 +58,12 @@ struct clk_ops clk_ops0 = {
#ifdef MCFPM_PPMCR1
static void __clk_enable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMCR1);
mcf_write8(clk->slot, MCFPM_PPMCR1);
}
static void __clk_disable1(struct clk *clk)
{
__raw_writeb(clk->slot, MCFPM_PPMSR1);
mcf_write8(clk->slot, MCFPM_PPMSR1);
}
struct clk_ops clk_ops1 = {

8
arch/m68k/coldfire/device.c
View File

@ -669,13 +669,13 @@ static void __init mcf_uart_set_irq(void)
{
#ifdef MCFUART_UIVR
/* UART0 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
mcf_write8(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
mcf_write8(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
/* UART1 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
mcf_write8(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
mcf_write8(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
#endif
}

56
arch/m68k/coldfire/pci.c
View File

@ -68,24 +68,24 @@ static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
}
addr = mcf_mk_pcicar(bus->number, devfn, where);
__raw_writel(PCICAR_E | addr, PCICAR);
__raw_readl(PCICAR);
mcf_write32(PCICAR_E | addr, PCICAR);
mcf_read32(PCICAR);
addr = iospace + (where & 0x3);
switch (size) {
case 1:
*value = __raw_readb(addr);
*value = mcf_read8(addr);
break;
case 2:
*value = le16_to_cpu(__raw_readw(addr));
*value = le16_to_cpu(mcf_read16(addr));
break;
default:
*value = le32_to_cpu(__raw_readl(addr));
*value = le32_to_cpu(mcf_read32(addr));
break;
}
__raw_writel(0, PCICAR);
__raw_readl(PCICAR);
mcf_write32(0, PCICAR);
mcf_read32(PCICAR);
return PCIBIOS_SUCCESSFUL;
}
@ -100,24 +100,24 @@ static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
}
addr = mcf_mk_pcicar(bus->number, devfn, where);
__raw_writel(PCICAR_E | addr, PCICAR);
__raw_readl(PCICAR);
mcf_write32(PCICAR_E | addr, PCICAR);
mcf_read32(PCICAR);
addr = iospace + (where & 0x3);
switch (size) {
case 1:
__raw_writeb(value, addr);
mcf_write8(value, addr);
break;
case 2:
__raw_writew(cpu_to_le16(value), addr);
mcf_write16(cpu_to_le16(value), addr);
break;
default:
__raw_writel(cpu_to_le32(value), addr);
mcf_write32(cpu_to_le32(value), addr);
break;
}
__raw_writel(0, PCICAR);
__raw_readl(PCICAR);
mcf_write32(0, PCICAR);
mcf_read32(PCICAR);
return PCIBIOS_SUCCESSFUL;
}
@ -175,44 +175,44 @@ static int __init mcf_pci_init(void)
pr_info("ColdFire: PCI bus initialization...\n");
/* Reset the external PCI bus */
__raw_writel(PCIGSCR_RESET, PCIGSCR);
__raw_writel(0, PCITCR);
mcf_write32(PCIGSCR_RESET, PCIGSCR);
mcf_write32(0, PCITCR);
request_resource(&iomem_resource, &mcf_pci_mem);
request_resource(&iomem_resource, &mcf_pci_io);
/* Configure PCI arbiter */
__raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
mcf_write32(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
PACR_EXTMINTE(0x1f), PACR);
/* Set required multi-function pins for PCI bus use */
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
__raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
mcf_write16(0x3ff, MCFGPIO_PAR_PCIBG);
mcf_write16(0x3ff, MCFGPIO_PAR_PCIBR);
/* Set up config space for local host bus controller */
__raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
mcf_write32(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
PCI_COMMAND_INVALIDATE, PCISCR);
__raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
__raw_writel(0, PCICR2);
mcf_write32(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
mcf_write32(0, PCICR2);
/*
* Set up the initiator windows for memory and IO mapping.
* These give the CPU bus access onto the PCI bus. One for each of
* PCI memory and IO address spaces.
*/
__raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
mcf_write32(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
PCIIW0BTAR);
__raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
mcf_write32(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
PCIIW1BTAR);
__raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
mcf_write32(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
/*
* Set up the target windows for access from the PCI bus back to the
* CPU bus. All we need is access to system RAM (for mastering).
*/
__raw_writel(CONFIG_RAMBASE, PCIBAR1);
__raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
mcf_write32(CONFIG_RAMBASE, PCIBAR1);
mcf_write32(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
/* Keep a virtual mapping to IO/config space active */
iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
@ -224,7 +224,7 @@ static int __init mcf_pci_init(void)
(u32) iospace);
/* Turn of PCI reset, and wait for devices to settle */
__raw_writel(0, PCIGSCR);
mcf_write32(0, PCIGSCR);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(msecs_to_jiffies(200));

4
arch/m68k/coldfire/reset.c
View File

@ -27,7 +27,7 @@ static void mcf_cpu_reset(void)
{
local_irq_disable();
/* Set watchdog to soft reset, and enabled */
__raw_writeb(0xc0, MCFSIM_SYPCR);
mcf_write8(0xc0, MCFSIM_SYPCR);
for (;;)
/* wait for watchdog to timeout */;
}
@ -37,7 +37,7 @@ static void mcf_cpu_reset(void)
static void mcf_cpu_reset(void)
{
local_irq_disable();
__raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
mcf_write8(MCF_RCR_SWRESET, MCF_RCR);
}
#endif