From e61846793759bb9b5006b06e0a7cd01cea311004 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Tue, 9 Jan 2018 15:54:50 +0800 Subject: [PATCH] arm64: dts: rockchip: Enable display output on rk3326 evb board Change-Id: I6cc78f6c9178f45d2e8c913179eb8d2df4fd7803 Signed-off-by: Wyon Bi --- .../arm64/boot/dts/rockchip/px30-android.dtsi | 27 -- .../boot/dts/rockchip/rk3326-evb-lp3-v10.dts | 255 +++++++++++------- 2 files changed, 160 insertions(+), 122 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-android.dtsi b/arch/arm64/boot/dts/rockchip/px30-android.dtsi index 1727d844b952..f6d93afff376 100644 --- a/arch/arm64/boot/dts/rockchip/px30-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-android.dtsi @@ -43,16 +43,6 @@ vendor { }; }; - lvds_panel: lvds-panel { - status = "disabled"; - /* pinctrl-0 = <&lcd_cs>; */ - ports { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out_panel>; - }; - }; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -90,20 +80,3 @@ route_dsi: route-dsi { }; }; }; - -&lvds { - status = "disabled"; - ports { - lvds_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_out_panel: endpoint@0 { - reg = <0>; - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - diff --git a/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10.dts b/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10.dts index b74ae8c19337..2029d3dc1e62 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v10.dts @@ -56,6 +56,46 @@ backlight: backlight { default-brightness-level = <200>; }; + panel { + compatible = "auo,b101ew05", "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + disable-delay-ms = <10>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + rockchip,data-mapping = "jeida"; + rockchip,data-width = <24>; + rockchip,output = "lvds"; + status = "disabled"; + + display-timings { + native-mode = <&b101ew05_timing>; + + b101ew05_timing: timing0 { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <220>; + hfront-porch = <110>; + vback-porch = <20>; + vfront-porch = <5>; + hsync-len = <40>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + rk_key: rockchip-key { compatible = "rockchip,key"; status = "okay"; @@ -208,45 +248,136 @@ &display_subsystem { status = "okay"; }; -&lvds_panel { - compatible ="simple-panel"; - bus-format = ; - //backlight = <&backlight>; - //enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; - //delay,disable = <10>; - //power-supply = <&vcc_lcd>; - rockchip,data-mapping = "jeida"; - rockchip,data-width = <24>; - rockchip,output = "lvds"; +&dsi { status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <71000000>; - hactive = <800>; - vactive = <1280>; - hback-porch = <100>; - hfront-porch = <18>; - vback-porch = <8>; - vfront-porch = <6>; - hsync-len = <10>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&st7703_timing>; + + st7703_timing: timing0 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; }; }; }; -&lvds { - pinctrl-names = "lcdc"; - pinctrl-0 = <&lcdc_lcdc>; +&dsi_in_vopl { + status = "disabled"; +}; +&lvds { + //pinctrl-names = "lcdc"; + //pinctrl-0 = <&lcdc_rgb_dclk_pin &lcdc_rgb_m0_den_pin &lcdc_rgb_m0_hsync_pin &lcdc_rgb_m0_vsync_pin &lcdc_rgb666_m0_data_pins>; + //pinctrl-0 = <&lcdc_rgb_dclk_pin &lcdc_rgb666_m1_data_pins>; + status = "disabled"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vopl { + status = "disabled"; +}; + +&mipi_dphy { status = "okay"; }; +&route_dsi { + status = "okay"; +}; + +&route_lvds { + status = "disabled"; +}; + &vopb { status = "okay"; }; @@ -264,72 +395,6 @@ &vopl_mmu { }; &pinctrl { - lcdc { - lcdc_lcdc: lcdc-ctl { - rockchip,pins = - /* depend on hardware design */ - /* den */ - <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, - /* vsync */ - <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, - /* hsync */ - <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, - /* dclk */ - <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, - /* data3 */ - <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, - /* data2 */ - <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, - /* data1 */ - <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, - /* data0 */ - <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, - - /* data7 */ - <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, - /* data6 */ - <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, - /* data5 */ - <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, - /* data4 */ - <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, - /* data11 */ - <3 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, - /* data10 */ - <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, - /* data9 */ - <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, - /* data8 */ - <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, - - /* data15 */ - <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, - /* data14 */ - <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, - /* data13 */ - <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, - /* data12 */ - <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, - /* data19 */ - <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none>, - /* data18 */ - <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none>, - /* data17 */ - <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, - /* data16 */ - <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, - - /* data23 */ - <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, - /* data22 */ - <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, - /* data21 */ - <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, - /* data20 */ - <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;