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bpf, arm64: Add support for lse atomics in bpf_arena
When LSE atomics are available, BPF atomic instructions are implemented as single ARM64 atomic instructions, therefore it is easy to enable these in bpf_arena using the currently available exception handling setup. LL_SC atomics use loops and therefore would need more work to enable in bpf_arena. Enable LSE atomics based instructions in bpf_arena and use the bpf_jit_supports_insn() callback to reject atomics in bpf_arena if LSE atomics are not available. All atomics and arena_atomics selftests are passing: [root@ip-172-31-2-216 bpf]# ./test_progs -a atomics,arena_atomics #3/1 arena_atomics/add:OK #3/2 arena_atomics/sub:OK #3/3 arena_atomics/and:OK #3/4 arena_atomics/or:OK #3/5 arena_atomics/xor:OK #3/6 arena_atomics/cmpxchg:OK #3/7 arena_atomics/xchg:OK #3 arena_atomics:OK #10/1 atomics/add:OK #10/2 atomics/sub:OK #10/3 atomics/and:OK #10/4 atomics/or:OK #10/5 atomics/xor:OK #10/6 atomics/cmpxchg:OK #10/7 atomics/xchg:OK #10 atomics:OK Summary: 2/14 PASSED, 0 SKIPPED, 0 FAILED Signed-off-by: Puranjay Mohan <puranjay@kernel.org> Link: https://lore.kernel.org/r/20240426161116.441-1-puranjay@kernel.org Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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@ -494,20 +494,26 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
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static int emit_lse_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx)
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{
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const u8 code = insn->code;
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const u8 arena_vm_base = bpf2a64[ARENA_VM_START];
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const u8 dst = bpf2a64[insn->dst_reg];
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const u8 src = bpf2a64[insn->src_reg];
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const u8 tmp = bpf2a64[TMP_REG_1];
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const u8 tmp2 = bpf2a64[TMP_REG_2];
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const bool isdw = BPF_SIZE(code) == BPF_DW;
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const bool arena = BPF_MODE(code) == BPF_PROBE_ATOMIC;
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const s16 off = insn->off;
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u8 reg;
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u8 reg = dst;
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if (!off) {
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reg = dst;
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} else {
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emit_a64_mov_i(1, tmp, off, ctx);
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emit(A64_ADD(1, tmp, tmp, dst), ctx);
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reg = tmp;
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if (off || arena) {
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if (off) {
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emit_a64_mov_i(1, tmp, off, ctx);
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emit(A64_ADD(1, tmp, tmp, dst), ctx);
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reg = tmp;
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}
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if (arena) {
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emit(A64_ADD(1, tmp, reg, arena_vm_base), ctx);
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reg = tmp;
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}
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}
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switch (insn->imm) {
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@ -576,6 +582,12 @@ static int emit_ll_sc_atomic(const struct bpf_insn *insn, struct jit_ctx *ctx)
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u8 reg;
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s32 jmp_offset;
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if (BPF_MODE(code) == BPF_PROBE_ATOMIC) {
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/* ll_sc based atomics don't support unsafe pointers yet. */
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pr_err_once("unknown atomic opcode %02x\n", code);
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return -EINVAL;
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}
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if (!off) {
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reg = dst;
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} else {
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@ -777,7 +789,8 @@ static int add_exception_handler(const struct bpf_insn *insn,
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if (BPF_MODE(insn->code) != BPF_PROBE_MEM &&
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BPF_MODE(insn->code) != BPF_PROBE_MEMSX &&
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BPF_MODE(insn->code) != BPF_PROBE_MEM32)
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BPF_MODE(insn->code) != BPF_PROBE_MEM32 &&
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BPF_MODE(insn->code) != BPF_PROBE_ATOMIC)
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return 0;
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if (!ctx->prog->aux->extable ||
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@ -1474,12 +1487,18 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
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case BPF_STX | BPF_ATOMIC | BPF_W:
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case BPF_STX | BPF_ATOMIC | BPF_DW:
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case BPF_STX | BPF_PROBE_ATOMIC | BPF_W:
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case BPF_STX | BPF_PROBE_ATOMIC | BPF_DW:
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if (cpus_have_cap(ARM64_HAS_LSE_ATOMICS))
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ret = emit_lse_atomic(insn, ctx);
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else
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ret = emit_ll_sc_atomic(insn, ctx);
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if (ret)
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return ret;
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ret = add_exception_handler(insn, ctx, dst);
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if (ret)
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return ret;
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break;
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default:
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@ -2527,6 +2546,19 @@ bool bpf_jit_supports_arena(void)
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return true;
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}
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bool bpf_jit_supports_insn(struct bpf_insn *insn, bool in_arena)
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{
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if (!in_arena)
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return true;
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switch (insn->code) {
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case BPF_STX | BPF_ATOMIC | BPF_W:
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case BPF_STX | BPF_ATOMIC | BPF_DW:
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if (!cpus_have_cap(ARM64_HAS_LSE_ATOMICS))
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return false;
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}
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return true;
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}
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void bpf_jit_free(struct bpf_prog *prog)
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{
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if (prog->jited) {
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@ -10,4 +10,3 @@ fill_link_info/kprobe_multi_link_info # bpf_program__attach_kprobe_mu
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fill_link_info/kretprobe_multi_link_info # bpf_program__attach_kprobe_multi_opts unexpected error: -95
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fill_link_info/kprobe_multi_invalid_ubuff # bpf_program__attach_kprobe_multi_opts unexpected error: -95
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missed/kprobe_recursion # missed_kprobe_recursion__attach unexpected error: -95 (errno 95)
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arena_atomics
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