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drm/ast: dp501: Fix open-coded register access

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Replace all open-coded access to SCU registers in DP501 support with
the appropriate calls to ast_moutdwm() and ast_mindwm(). Use SCU register
constants. Name variables according to registers.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patch.msgid.link/20260327133532.79696-15-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann 2026-03-27 14:33:06 +01:00
parent 562aa0d24d
commit e60dccc256
2 changed files with 56 additions and 58 deletions
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108
drivers/gpu/drm/ast/ast_dp501.c
View File

@ -347,68 +347,65 @@ static int ast_dp512_read_edid_block(void *data, u8 *buf, unsigned int block, si
static bool ast_init_dvo(struct ast_device *ast)
{
u8 jreg;
u32 data;
ast_write32(ast, 0xf004, AST_REG_MCR00);
ast_write32(ast, 0xf000, 0x1);
ast_write32(ast, 0x12000, 0x1688a8a8);
u32 scu02c;
ast_moutdwm(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY);
jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
if (!(jreg & 0x80)) {
u32 scu008;
/* Init SCU DVO Settings */
data = ast_read32(ast, 0x12008);
/* delay phase */
data &= 0xfffff8ff;
data |= 0x00000500;
ast_write32(ast, 0x12008, data);
scu008 = ast_mindwm(ast, AST_REG_SCU008);
scu008 &= 0xfffff8ff;
scu008 |= 0x00000500; /* delay phase */
ast_moutdwm(ast, AST_REG_SCU008, scu008);
if (IS_AST_GEN4(ast)) {
data = ast_read32(ast, 0x12084);
/* multi-pins for DVO single-edge */
data |= 0xfffe0000;
ast_write32(ast, 0x12084, data);
u32 scu084, scu088, scu090;
data = ast_read32(ast, 0x12088);
/* multi-pins for DVO single-edge */
data |= 0x000fffff;
ast_write32(ast, 0x12088, data);
scu084 = ast_mindwm(ast, AST_REG_SCU084);
scu084 |= 0xfffe0000; /* multi-pins for DVO single-edge */
ast_moutdwm(ast, AST_REG_SCU084, scu084);
data = ast_read32(ast, 0x12090);
/* multi-pins for DVO single-edge */
data &= 0xffffffcf;
data |= 0x00000020;
ast_write32(ast, 0x12090, data);
scu088 = ast_mindwm(ast, AST_REG_SCU088);
scu088 |= 0x000fffff; /* multi-pins for DVO single-edge */
ast_moutdwm(ast, AST_REG_SCU088, scu088);
scu090 = ast_mindwm(ast, AST_REG_SCU090);
scu090 &= 0xffffffcf;
scu090 |= 0x00000020; /* multi-pins for DVO single-edge */
ast_moutdwm(ast, AST_REG_SCU090, scu090);
} else { /* AST GEN5+ */
data = ast_read32(ast, 0x12088);
/* multi-pins for DVO single-edge */
data |= 0x30000000;
ast_write32(ast, 0x12088, data);
u32 scu088, scu08c, scu0a4, scu0a8, scu094;
data = ast_read32(ast, 0x1208c);
/* multi-pins for DVO single-edge */
data |= 0x000000cf;
ast_write32(ast, 0x1208c, data);
scu088 = ast_mindwm(ast, AST_REG_SCU088);
scu088 |= 0x30000000; /* multi-pins for DVO single-edge */
ast_moutdwm(ast, AST_REG_SCU088, scu088);
data = ast_read32(ast, 0x120a4);
/* multi-pins for DVO single-edge */
data |= 0xffff0000;
ast_write32(ast, 0x120a4, data);
scu08c = ast_mindwm(ast, AST_REG_SCU08C);
scu08c |= 0x000000cf; /* multi-pins for DVO single-edge */
ast_moutdwm(ast, AST_REG_SCU08C, scu08c);
data = ast_read32(ast, 0x120a8);
/* multi-pins for DVO single-edge */
data |= 0x0000000f;
ast_write32(ast, 0x120a8, data);
scu0a4 = ast_mindwm(ast, AST_REG_SCU0A4);
scu0a4 |= 0xffff0000; /* multi-pins for DVO single-edge */
ast_moutdwm(ast, AST_REG_SCU0A4, scu0a4);
data = ast_read32(ast, 0x12094);
/* multi-pins for DVO single-edge */
data |= 0x00000002;
ast_write32(ast, 0x12094, data);
scu0a8 = ast_mindwm(ast, AST_REG_SCU0A8);
scu0a8 |= 0x0000000f; /* multi-pins for DVO single-edge */
ast_moutdwm(ast, AST_REG_SCU0A8, scu0a8);
scu094 = ast_mindwm(ast, AST_REG_SCU094);
scu094 |= 0x00000002; /* multi-pins for DVO single-edge */
ast_moutdwm(ast, AST_REG_SCU094, scu094);
}
}
/* Force to DVO */
data = ast_read32(ast, 0x1202c);
data &= 0xfffbffff;
ast_write32(ast, 0x1202c, data);
scu02c = ast_mindwm(ast, AST_REG_SCU02C);
scu02c &= 0xfffbffff;
ast_moutdwm(ast, AST_REG_SCU02C, scu02c);
/* Init VGA DVO Settings */
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
@ -418,25 +415,20 @@ static bool ast_init_dvo(struct ast_device *ast)
static void ast_init_analog(struct ast_device *ast)
{
u32 data;
u32 scu02c;
/*
* Set DAC source to VGA mode in SCU2C via the P2A
* bridge. First configure the P2U to target the SCU
* in case it isn't at this stage.
* bridge.
*/
ast_write32(ast, 0xf004, AST_REG_MCR00);
ast_write32(ast, 0xf000, 0x1);
/* Then unlock the SCU with the magic password */
ast_write32(ast, 0x12000, 0x1688a8a8);
ast_write32(ast, 0x12000, 0x1688a8a8);
ast_write32(ast, 0x12000, 0x1688a8a8);
/* Unlock the SCU with the magic password */
ast_moutdwm_poll(ast, AST_REG_SCU000, AST_REG_SCU000_PROTECTION_KEY, 0x01);
/* Finally, clear bits [17:16] of SCU2c */
data = ast_read32(ast, 0x1202c);
data &= 0xfffcffff;
ast_write32(ast, 0x1202c, data);
/* Clear bits [17:16] of SCU2C */
scu02c = ast_mindwm(ast, AST_REG_SCU02C);
scu02c &= 0xfffcffff;
ast_moutdwm(ast, AST_REG_SCU02C, scu02c);
/* Disable DVO */
ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x00);

6
drivers/gpu/drm/ast/ast_reg.h
View File

@ -187,11 +187,17 @@
#define AST_REG_SCU008 AST_REG_SCU(0x008)
#define AST_REG_SCU00C AST_REG_SCU(0x00c)
#define AST_REG_SCU020 AST_REG_SCU(0x020)
#define AST_REG_SCU02C AST_REG_SCU(0x02c)
#define AST_REG_SCU040 AST_REG_SCU(0x040)
#define AST_REG_SCU070 AST_REG_SCU(0x070)
#define AST_REG_SCU07C AST_REG_SCU(0x07c)
#define AST_REG_SCU084 AST_REG_SCU(0x084)
#define AST_REG_SCU088 AST_REG_SCU(0x088)
#define AST_REG_SCU08C AST_REG_SCU(0x08c)
#define AST_REG_SCU090 AST_REG_SCU(0x090)
#define AST_REG_SCU094 AST_REG_SCU(0x094)
#define AST_REG_SCU0A4 AST_REG_SCU(0x0a4)
#define AST_REG_SCU0A8 AST_REG_SCU(0x0a8)
#define AST_REG_SCU100 AST_REG_SCU(0x100)
#define AST_REG_SCU104 AST_REG_SCU(0x104)
#define AST_REG_SCU160 AST_REG_SCU(0x160)