From 3011e0c8139323af4e449bb4c7dce63aedc33808 Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Mon, 5 Jun 2023 13:23:58 +0200 Subject: [PATCH 1/7] arm64: zynqmp: Add L2 cache nodes Describe SoC L2 cache hierarchy. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/130e5a6acbee94809b63a61cde5450fbff88cc9c.1685964230.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 02cfcc716936..394db49ac6cb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -33,6 +33,7 @@ cpu0: cpu@0 { operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +43,7 @@ cpu1: cpu@1 { reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ cpu2: cpu@2 { reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +63,13 @@ cpu3: cpu@3 { reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { From ee6c637f383fc6d1e1c358c829bd762240ccf259 Mon Sep 17 00:00:00 2001 From: Manikanta Guntupalli Date: Thu, 8 Jun 2023 14:35:24 +0200 Subject: [PATCH 2/7] arm64: zynqmp: Fix open drain warning on ZynqMP Mark both GPIO lines as GPIO_OPEN_DRAIN which is required by i2c-gpio DT binding. Similar change was done by commit 8df80c1801c9 ("ARM: dts: exynos: Convert to new i2c-gpio bindings"). Signed-off-by: Manikanta Guntupalli Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a0faf488dde310e1c1c1a676c371e223db6bdca6.1686227712.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 8 ++++---- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 8 ++++---- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 8 ++++---- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 8 ++++---- 12 files changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 603839c82599..e06c6824dea4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -27,8 +27,8 @@ &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* u14 - 0x40 - ina260 */ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a91d09e7da4b..030e2c93f0e6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -22,8 +22,8 @@ &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* u14 - 0x40 - ina260 */ /* u43 - 0x2d - usb5744 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index dfd1a18f5a10..c1f21b0e1760 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -245,8 +245,8 @@ &i2c1 { status = "okay"; bootph-all; clock-frequency = <400000>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ bootph-all; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index d9d1de5f313c..e821d55d8d5a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -119,8 +119,8 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 6503f4985f8d..b59e11316b4b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -110,8 +110,8 @@ &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index b1e933b8a2cd..0d2ea9c09a0a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -91,8 +91,8 @@ &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c1 { @@ -100,8 +100,8 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 44d1f351bb75..d0091d3cb764 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -180,8 +180,8 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 8767f147cbe3..84952c14f021 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -233,8 +233,8 @@ &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -497,8 +497,8 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index e185709c0d84..5084ddcee00f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -140,8 +140,8 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 7fceebd1815c..b273bd1d920a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -145,8 +145,8 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 27b2416cb6d8..50c384aa253e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -245,8 +245,8 @@ &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -508,8 +508,8 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 6224365826d8..617cb0405a7d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -205,8 +205,8 @@ &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; @@ -385,8 +385,8 @@ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; From 3175b52251f230713fd54686a76cf2f1365e94de Mon Sep 17 00:00:00 2001 From: Varalaxmi Bingi Date: Thu, 8 Jun 2023 14:36:10 +0200 Subject: [PATCH 3/7] arm64: zynqmp: Setting default i2c clock frequency to 400kHz Setting default i2c clock frequency for ZynqMP to maximum rate of 400kHz. Current default value is 100kHz. Signed-off-by: Varalaxmi Bingi Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3034ec006c8b11e025904d4cc2524255523636f6.1686227766.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 394db49ac6cb..675b88190845 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -648,6 +648,7 @@ i2c0: i2c@ff020000 { status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; + clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -659,6 +660,7 @@ i2c1: i2c@ff030000 { status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; + clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; From 233e6e9dbe169d68d422e0f3eccb26539ff0c512 Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Thu, 8 Jun 2023 14:51:23 +0200 Subject: [PATCH 4/7] arm64: zynqmp: Assign TSU clock frequency for GEMs Allow changing TSU clock for all GEMs. Kria SOM is using this functionality that's why set TSU clock frequency as 250MHz (minimum when running at 1G) to allow PTP functionality. Signed-off-by: Harini Katakam Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3b9285b50a2a4abb136ecb0873343a4e84626581.1686228675.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + 3 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index f04716841a0c..ccaca29200bb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -146,24 +146,28 @@ &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gpio { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index e06c6824dea4..ae1b9b2bdbee 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -145,6 +145,7 @@ &gem3 { /* required by spec */ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 030e2c93f0e6..b59e48be6465 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -128,6 +128,7 @@ &gem3 { /* required by spec */ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; From 0dffb878ea99de9c30a24cdd8a73bc3f318baa88 Mon Sep 17 00:00:00 2001 From: Sharath Kumar Dasari Date: Mon, 12 Jun 2023 09:41:45 +0200 Subject: [PATCH 5/7] arm64: zynqmp: Add memory reserved node for k26 Kria SOM board PMUFW (Power Management Unit firmware) requires top 1MB of the lower DDR memory reserved for its operation, this is missing in k26 SM static dts file. Bootloader or kernel shouldn't access this location. Signed-off-by: Sharath Kumar Dasari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8ddc7fb4bf40faead7a015ad7e095f3f7d2ec191.1686555698.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index c1f21b0e1760..c4774a42d5fc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -50,6 +50,17 @@ memory@0 { reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pmu_region: pmu@7ff00000 { + reg = <0x0 0x7ff00000 0x0 0x100000>; + no-map; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; From 04d54a0e98e7cba699f618fde829609cc2436342 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 19 Jun 2023 09:37:54 +0200 Subject: [PATCH 6/7] arm64: zynqmp: Fix dwc3 usb interrupt description Based on DT binding dwc_usb3 is single entry without anything else. That's why combination dwc3_usb3, otg is not allowed. That's why split it to host and peripheral pair which both points to the same IRQ. DWC3 code is reading these two properties first before generic dwc_usb3. Reviewed-by: Laurent Pinchart Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6544d13afd9f3d8f5413e32684aa16e4d155e331.1687160244.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 675b88190845..74898f3a3537 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -900,8 +900,8 @@ dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "dwc_usb3", "otg"; - interrupts = <0 65 4>, <0 69 4>; + interrupt-names = "host", "peripheral", "otg"; + interrupts = <0 65 4>, <0 65 4>, <0 69 4>; clock-names = "bus_early", "ref"; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; @@ -927,8 +927,8 @@ dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "dwc_usb3", "otg"; - interrupts = <0 70 4>, <0 74 4>; + interrupt-names = "host", "peripheral", "otg"; + interrupts = <0 70 4>, <0 70 4>, <0 74 4>; clock-names = "bus_early", "ref"; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; From cf0e27cd011775f63001e1e925969106c9464fca Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Jul 2023 12:52:19 +0200 Subject: [PATCH 7/7] arm64: zynqmp: Describe interrupts by using macros Use arm-gic.h and irq.h for interrupt description. It helps to improve readability of device tree file. Suggested-by: Laurent Pinchart Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/9d5bd17f37772be186cab17b06cc21351d36ff62.1688986332.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 185 +++++++++++++++---------- 1 file changed, 110 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 74898f3a3537..b61fc99cd911 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -14,6 +14,8 @@ #include #include +#include +#include #include #include @@ -131,7 +133,7 @@ zynqmp_ipi: zynqmp_ipi { bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = ; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; @@ -161,10 +163,10 @@ dcc: dcc { pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; - interrupts = <0 143 4>, - <0 144 4>, - <0 145 4>, - <0 146 4>; + interrupts = , + , + , + ; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, @@ -187,7 +189,7 @@ zynqmp_power: zynqmp-power { bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = ; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; @@ -231,10 +233,10 @@ modepin_gpio: gpio { timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = , + , + , + ; }; fpga_full: fpga-full { @@ -274,7 +276,7 @@ can0: can@ff060000 { status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <0 23 4>; + interrupts = ; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -286,7 +288,7 @@ can1: can@ff070000 { status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <0 24 4>; + interrupts = ; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -305,11 +307,11 @@ pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; - interrupts = <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>; + interrupts = , + , + , + , + ; }; }; @@ -319,7 +321,7 @@ fpd_dma_chan1: dma-controller@fd500000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 124 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -332,7 +334,7 @@ fpd_dma_chan2: dma-controller@fd510000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 125 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -345,7 +347,7 @@ fpd_dma_chan3: dma-controller@fd520000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 126 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -358,7 +360,7 @@ fpd_dma_chan4: dma-controller@fd530000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 127 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -371,7 +373,7 @@ fpd_dma_chan5: dma-controller@fd540000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 128 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -384,7 +386,7 @@ fpd_dma_chan6: dma-controller@fd550000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 129 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -397,7 +399,7 @@ fpd_dma_chan7: dma-controller@fd560000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 130 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -410,7 +412,7 @@ fpd_dma_chan8: dma-controller@fd570000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 131 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -427,7 +429,7 @@ gic: interrupt-controller@f9010000 { <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; + interrupts = ; }; gpu: gpu@fd4b0000 { @@ -435,8 +437,12 @@ gpu: gpu@fd4b0000 { compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; - interrupts = <0 132 4>, <0 132 4>, <0 132 4>, - <0 132 4>, <0 132 4>, <0 132 4>; + interrupts = , + , + , + , + , + ; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; @@ -451,7 +457,7 @@ lpd_dma_chan1: dma-controller@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 77 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -464,7 +470,7 @@ lpd_dma_chan2: dma-controller@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 78 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -477,7 +483,7 @@ lpd_dma_chan3: dma-controller@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 79 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -490,7 +496,7 @@ lpd_dma_chan4: dma-controller@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 80 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -503,7 +509,7 @@ lpd_dma_chan5: dma-controller@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 81 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -516,7 +522,7 @@ lpd_dma_chan6: dma-controller@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 82 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -529,7 +535,7 @@ lpd_dma_chan7: dma-controller@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 83 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -542,7 +548,7 @@ lpd_dma_chan8: dma-controller@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 84 4>; + interrupts = ; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -554,7 +560,7 @@ mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; - interrupts = <0 112 4>; + interrupts = ; }; nand0: nand-controller@ff100000 { @@ -563,7 +569,7 @@ nand0: nand-controller@ff100000 { reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; - interrupts = <0 14 4>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; @@ -574,7 +580,8 @@ gem0: ethernet@ff0b0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 57 4>, <0 57 4>; + interrupts = , + ; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -589,7 +596,8 @@ gem1: ethernet@ff0c0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 59 4>, <0 59 4>; + interrupts = , + ; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -604,7 +612,8 @@ gem2: ethernet@ff0d0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 61 4>, <0 61 4>; + interrupts = , + ; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -619,7 +628,8 @@ gem3: ethernet@ff0e0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 63 4>, <0 63 4>; + interrupts = , + ; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -636,7 +646,7 @@ gpio: gpio@ff0a0000 { #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; - interrupts = <0 16 4>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; @@ -647,7 +657,7 @@ i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 17 4>; + interrupts = ; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; @@ -659,7 +669,7 @@ i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 18 4>; + interrupts = ; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; @@ -676,11 +686,11 @@ pcie: pcie@fd0e0000 { msi-controller; device_type = "pci"; interrupt-parent = <&gic>; - interrupts = <0 118 4>, - <0 117 4>, - <0 116 4>, - <0 115 4>, /* MSI_1 [63...32] */ - <0 114 4>; /* MSI_0 [31...0] */ + interrupts = , + , + , + , /* MSI_1 [63...32] */ + ; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; @@ -710,7 +720,7 @@ qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; - interrupts = <0 15 4>; + interrupts = ; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, @@ -735,7 +745,8 @@ rtc: rtc@ffa60000 { status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; + interrupts = , + ; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; @@ -745,7 +756,7 @@ sata: ahci@fd0c0000 { status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; - interrupts = <0 133 4>; + interrupts = ; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, @@ -757,7 +768,7 @@ sdhci0: mmc@ff160000 { compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 48 4>; + interrupts = ; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; @@ -772,7 +783,7 @@ sdhci1: mmc@ff170000 { compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 49 4>; + interrupts = ; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; @@ -789,18 +800,30 @@ smmu: iommu@fd800000 { status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; - interrupts = <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 19 4>; + interrupts = ; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -812,7 +835,7 @@ spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 20 4>; + interrupts = ; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -824,7 +847,9 @@ ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 36 4>, <0 37 4>, <0 38 4>; + interrupts = , + , + ; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; @@ -834,7 +859,9 @@ ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 39 4>, <0 40 4>, <0 41 4>; + interrupts = , + , + ; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; @@ -844,7 +871,9 @@ ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 42 4>, <0 43 4>, <0 44 4>; + interrupts = , + , + ; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; @@ -854,7 +883,9 @@ ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 45 4>, <0 46 4>, <0 47 4>; + interrupts = , + , + ; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; @@ -865,7 +896,7 @@ uart0: serial@ff000000 { compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 21 4>; + interrupts = ; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; @@ -876,7 +907,7 @@ uart1: serial@ff010000 { compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 22 4>; + interrupts = ; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; @@ -901,7 +932,9 @@ dwc3_0: usb@fe200000 { reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; - interrupts = <0 65 4>, <0 65 4>, <0 69 4>; + interrupts = , + , + ; clock-names = "bus_early", "ref"; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; @@ -928,7 +961,9 @@ dwc3_1: usb@fe300000 { reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; - interrupts = <0 70 4>, <0 70 4>, <0 74 4>; + interrupts = , + , + ; clock-names = "bus_early", "ref"; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; @@ -941,7 +976,7 @@ watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 113 1>; + interrupts = ; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; @@ -951,7 +986,7 @@ lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 52 1>; + interrupts = ; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; @@ -960,7 +995,7 @@ xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 56 4>; + interrupts = ; reg = <0x0 0xffa50000 0x0 0x800>; #address-cells = <1>; #size-cells = <1>; @@ -986,7 +1021,7 @@ zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; - interrupts = <0 122 4>; + interrupts = ; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; @@ -1002,7 +1037,7 @@ zynqmp_dpsub: display@fd4a0000 { <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; - interrupts = <0 119 4>; + interrupts = ; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";