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arm64: dts: Update cache properties for broadcom

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The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221122163208.3810985-3-pierre.gondois@arm.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
Pierre Gondois 2022-11-22 17:32:07 +01:00 committed by Florian Fainelli
parent b5a17c35c7
commit e567e58d68
9 changed files with 12 additions and 0 deletions
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1
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
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@ -63,6 +63,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
View File

@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
View File

@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
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@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
View File

@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
View File

@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
View File

@ -50,6 +50,7 @@ B53_3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
};
};

1
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View File

@ -79,6 +79,7 @@ A57_3: cpu@3 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
cache-level = <2>;
};
};

4
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View File

@ -108,18 +108,22 @@ cpu@301 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
cache-level = <2>;
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
cache-level = <2>;
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
cache-level = <2>;
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
cache-level = <2>;
};
};