From 50c98ff64feb77bebd995719afe84421db12b553 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 23 Sep 2026 02:37:32 +0530 Subject: [PATCH 01/31] dt-bindings: arm: qcom,ids: Add SoC ID for SM8975 Add the ID for the Qualcomm SM8975 SoC which represents the Hawi platform. Signed-off-by: Mukesh Ojha Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260923-hawi-socinfo-v1-1-f0d1aaee9323@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index b63e4a0b8e54..4259f8960447 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -301,6 +301,7 @@ #define QCOM_ID_QCS9075 676 #define QCOM_ID_QCS615 680 #define QCOM_ID_SA8797P 690 +#define QCOM_ID_SM8975 707 #define QCOM_ID_CQ7790M 731 #define QCOM_ID_CQ7790S 732 #define QCOM_ID_CQ2390M 756 From 06bf7462ed7ffe823e595b6de939023bedaa1c61 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 23 Sep 2026 02:37:33 +0530 Subject: [PATCH 02/31] soc: qcom: socinfo: Add SM8975 SoC ID Add SoC ID for Qualcomm SM8975 which represents the Hawi platform. Signed-off-by: Mukesh Ojha Link: https://patch.msgid.link/20260923-hawi-socinfo-v1-2-f0d1aaee9323@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 63ee5cd561a2..ddc717382797 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -542,6 +542,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QCS9075) }, { qcom_board_id(QCS615) }, { qcom_board_id(SA8797P) }, + { qcom_board_id(SM8975) }, { qcom_board_id(CQ7790M) }, { qcom_board_id(CQ7790S) }, { qcom_board_id(CQ2390M) }, From 60d4a6edea9ec617725db6dd1e66d96a13bc8d0a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Tue, 22 Sep 2026 01:26:34 +0530 Subject: [PATCH 03/31] firmware: qcom: tzmem: Use DO_ONCE_SLEEPABLE() in qcom_tzmem_enable() qcom_tzmem_enable() is called from qcom_scm_probe() in a sleepable process context. The helper it wraps, qcom_tzmem_init(), calls qcom_scm_shm_bridge_enable() -> qcom_scm_call(), which invokes might_sleep() and later acquires the qcom_scm_lock mutex via __scm_smc_do(). DO_ONCE() takes the once_lock spinlock with IRQs disabled, so invoking qcom_tzmem_init() from inside DO_ONCE() runs a sleepable call chain in atomic context. CONFIG_DEBUG_ATOMIC_SLEEP=y catches this on boot: BUG: sleeping function called from invalid context at drivers/firmware/qcom/qcom_scm.c:334 in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 49, name: kworker/u16:2 ... __might_resched+0x148/0x24c __might_sleep+0x48/0x7c qcom_scm_call+0x30/0xc0 __qcom_scm_is_call_available+0x98/0x100 qcom_scm_shm_bridge_enable+0x60/0xbc qcom_tzmem_enable+0xf8/0x118 qcom_scm_probe+0x2d0/0x680 [ BUG: Invalid wait context ] ... kworker/u16:2/49 is trying to lock: ffffa83e8a485e38 (qcom_scm_lock){....}-{4:4}, at: __scm_smc_do+0x70/0x488 Switch to DO_ONCE_SLEEPABLE(), which guards the one-shot init with a mutex-style path (__do_once_sleepable_start/done) that is safe to hold across sleeping callees. All callers of qcom_tzmem_enable() are in process context (driver probe), so this is safe. Fixes: 9941fe8a04f3 ("firmware: qcom: scm: Fix tzmem state on probe retry") Reported-by: Marek Szyprowski Closes: https://lore.kernel.org/lkml/5ea74dd3-7471-4c7c-9242-c2005312b1ab@samsung.com/ Reviewed-by: Bartosz Golaszewski Signed-off-by: Mukesh Ojha Link: https://patch.msgid.link/20260921195636.1925869-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_tzmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_tzmem.c b/drivers/firmware/qcom/qcom_tzmem.c index 0fd9581275f1..ebcdee3c5975 100644 --- a/drivers/firmware/qcom/qcom_tzmem.c +++ b/drivers/firmware/qcom/qcom_tzmem.c @@ -518,7 +518,7 @@ int qcom_tzmem_enable(struct device *dev) static int result; qcom_tzmem_dev = dev; - DO_ONCE(qcom_tzmem_do_init, &result); + DO_ONCE_SLEEPABLE(qcom_tzmem_do_init, &result); return result; } EXPORT_SYMBOL_GPL(qcom_tzmem_enable); From 324103eb65ba26704c2293d9daaa15c0dc022930 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Tue, 22 Sep 2026 01:26:35 +0530 Subject: [PATCH 04/31] firmware: qcom_scm: handle empty PAS resource table The PAS resource-table query may successfully return a zero-sized table. kmemdup() with a zero length returns ZERO_SIZE_PTR, which is stored in rproc->table_ptr. The remoteproc core then dereferences this invalid pointer while processing resources. Treat a zero-sized result as an absent resource table and return NULL after releasing the TrustZone memory buffer. This allows the remoteproc core to skip resource-table processing. Fixes: 8b9d2050cfa0 ("firmware: qcom_scm: Add qcom_scm_pas_get_rsc_table() to get resource table") Signed-off-by: Mukesh Ojha Reviewed-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260921195636.1925869-2-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 162444f8bc8b..7bc97096d63b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -865,6 +865,14 @@ static void *__qcom_scm_pas_get_rsc_table2(struct device *dev, goto free_input_rt; } + *output_rt_size = size; + + /* A zero-sized table means that TrustZone has no resource table. */ + if (!size) { + tbl_ptr = NULL; + goto free_output_rt; + } + tbl_ptr = kmemdup(output_rt_tzm, size, GFP_KERNEL); if (!tbl_ptr) { qcom_tzmem_free(output_rt_tzm); @@ -872,7 +880,7 @@ static void *__qcom_scm_pas_get_rsc_table2(struct device *dev, goto free_input_rt; } - *output_rt_size = size; +free_output_rt: qcom_tzmem_free(output_rt_tzm); free_input_rt: From 57e43df2e426ac5561ee3832d425e1071772e963 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Tue, 22 Sep 2026 01:26:36 +0530 Subject: [PATCH 05/31] firmware: qcom_scm: align PAS resource table retry The initial PAS resource-table buffer can be too small. TrustZone returns the required size and the wrapper retries the SCM call. Although qcom_tzmem_alloc() aligns the allocated buffer, the size passed to TrustZone remained unaligned. Align the retry size to a page boundary so that both the buffer and its advertised size satisfy the PAS/TrustZone contract. Fixes: 8b9d2050cfa0 ("firmware: qcom_scm: Add qcom_scm_pas_get_rsc_table() to get resource table") Signed-off-by: Mukesh Ojha Reviewed-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260921195636.1925869-3-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 7bc97096d63b..d309689de266 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -854,12 +854,14 @@ static void *__qcom_scm_pas_get_rsc_table2(struct device *dev, output_rt_tzm = __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id, input_rt_tzm, input_rt_size, &size); - if (PTR_ERR(output_rt_tzm) == -EOVERFLOW) - /* Try again with the size requested by the TZ */ + if (PTR_ERR(output_rt_tzm) == -EOVERFLOW) { + /* Try again with a page-aligned size requested by the TZ. */ + size = PAGE_ALIGN(size); output_rt_tzm = __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id, input_rt_tzm, input_rt_size, &size); + } if (IS_ERR(output_rt_tzm)) { ret = PTR_ERR(output_rt_tzm); goto free_input_rt; From 9b79d37cfacbd8b525c728bb6e0b00777e37293a Mon Sep 17 00:00:00 2001 From: Muzaffer Kadir Date: Mon, 21 Sep 2026 21:19:02 +0300 Subject: [PATCH 06/31] dt-bindings: firmware: qcom,scm: Document MSM8952 SCM Document the scm compatible for msm8952 SoC. Signed-off-by: Muzaffer Kadir Link: https://patch.msgid.link/20260921-msm8952-initial-support-v3-11-b96fd3fe298b@mainlining.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index ecee5aef65a7..40a267c54b00 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -45,6 +45,7 @@ properties: - qcom,scm-msm8660 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -153,6 +154,7 @@ allOf: - qcom,scm-msm8660 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -199,6 +201,7 @@ allOf: - qcom,scm-msm8226 - qcom,scm-msm8916 - qcom,scm-msm8937 + - qcom,scm-msm8952 - qcom,scm-msm8953 - qcom,scm-msm8974 - qcom,scm-msm8976 From 012cfa80370d199bb1c946524594b982bf2a5c01 Mon Sep 17 00:00:00 2001 From: Muzaffer Kadir Date: Mon, 21 Sep 2026 21:19:05 +0300 Subject: [PATCH 07/31] soc: qcom: ubwc: Add UBWC config for MSM8952 MSM8952 uses Adreno 405 and predates ubwc just like MSM8939. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Muzaffer Kadir Link: https://patch.msgid.link/20260921-msm8952-initial-support-v3-14-b96fd3fe298b@mainlining.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/ubwc_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 36c90f72943f..53c1df3ca641 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -130,6 +130,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,msm8937", .data = &ubwc_1_0_hbb14 }, { .compatible = "qcom,msm8929", .data = &no_ubwc_data }, { .compatible = "qcom,msm8939", .data = &no_ubwc_data }, + { .compatible = "qcom,msm8952", .data = &no_ubwc_data }, { .compatible = "qcom,msm8953", .data = &ubwc_1_0_hbb14 }, { .compatible = "qcom,msm8956", .data = &no_ubwc_data }, { .compatible = "qcom,msm8974", .data = &no_ubwc_data }, From 1cd31ba4f9bc87fe851b5894cb76da379709c95c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 18 Sep 2026 22:18:32 +0800 Subject: [PATCH 08/31] soc: qcom: use assign_bit() where applicable Convert open-coded if/else with set_bit/clear_bit and their non-atomic __set_bit/__clear_bit variants to the assign_bit/__assign_bit API. Done with Coccinelle semantic patch: // set_bit -> clear_bit => assign_bit @@ expression cond, bit, addr; @@ -if (cond) - set_bit(bit, addr); -else - clear_bit(bit, addr); +assign_bit(bit, addr, cond); // clear_bit -> set_bit => assign_bit @@ expression cond, bit, addr; @@ -if (cond) - clear_bit(bit, addr); -else - set_bit(bit, addr); +assign_bit(bit, addr, !cond); Signed-off-by: Peng Fan Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://patch.msgid.link/20260918141833.3023124-1-peng.fan@oss.nxp.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smp2p.c | 10 ++-------- drivers/soc/qcom/smsm.c | 16 ++++------------ 2 files changed, 6 insertions(+), 20 deletions(-) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index 3104e31f91c9..01b8580c9f27 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -411,15 +411,9 @@ static int smp2p_set_irq_type(struct irq_data *irqd, unsigned int type) if (!(type & IRQ_TYPE_EDGE_BOTH)) return -EINVAL; - if (type & IRQ_TYPE_EDGE_RISING) - set_bit(irq, entry->irq_rising); - else - clear_bit(irq, entry->irq_rising); + assign_bit(irq, entry->irq_rising, type & IRQ_TYPE_EDGE_RISING); - if (type & IRQ_TYPE_EDGE_FALLING) - set_bit(irq, entry->irq_falling); - else - clear_bit(irq, entry->irq_falling); + assign_bit(irq, entry->irq_falling, type & IRQ_TYPE_EDGE_FALLING); return 0; } diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index ac3c85a2597a..bb487bf6bf03 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -277,10 +277,8 @@ static void smsm_unmask_irq(struct irq_data *irqd) u32 val; /* Make sure our last cached state is up-to-date */ - if (readl(entry->remote_state) & BIT(irq)) - set_bit(irq, &entry->last_value); - else - clear_bit(irq, &entry->last_value); + assign_bit(irq, &entry->last_value, + readl(entry->remote_state) & BIT(irq)); set_bit(irq, entry->irq_enabled); @@ -304,15 +302,9 @@ static int smsm_set_irq_type(struct irq_data *irqd, unsigned int type) if (!(type & IRQ_TYPE_EDGE_BOTH)) return -EINVAL; - if (type & IRQ_TYPE_EDGE_RISING) - set_bit(irq, entry->irq_rising); - else - clear_bit(irq, entry->irq_rising); + assign_bit(irq, entry->irq_rising, type & IRQ_TYPE_EDGE_RISING); - if (type & IRQ_TYPE_EDGE_FALLING) - set_bit(irq, entry->irq_falling); - else - clear_bit(irq, entry->irq_falling); + assign_bit(irq, entry->irq_falling, type & IRQ_TYPE_EDGE_FALLING); return 0; } From 0c79a829af36a94143c747a0ab8f0a8563b17cfa Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 20 Jul 2026 16:39:02 +0200 Subject: [PATCH 09/31] soc: qcom: pmic_glink: Avoid losing early rpmsg probe The PMIC GLINK rpmsg device can appear before the platform device has finished probing. In that case pmic_glink_rpmsg_probe() sees __pmic_glink as NULL and returns -ENODEV, which is treated as a fatal probe failure for the rpmsg endpoint. If this race is hit, pg->ept is never installed and PMIC GLINK clients never receive the service-up notification. This may leave the system with no Type-C functionality and without battery/power supply management. Return -EPROBE_DEFER when the rpmsg endpoint arrives before the platform device is ready. Fixes: 58ef4ece1e41 ("soc: qcom: pmic_glink: Introduce base PMIC GLINK driver") Assisted-by: Codex:GPT-5.5 Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://patch.msgid.link/20260720-topic-pmic_glink_defer-v1-1-94c0f233f2f7@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_glink.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index 3042261578aa..84fd0c82c0c4 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -250,7 +250,8 @@ static int pmic_glink_rpmsg_probe(struct rpmsg_device *rpdev) guard(mutex)(&__pmic_glink_lock); pg = __pmic_glink; if (!pg) - return dev_err_probe(&rpdev->dev, -ENODEV, "no pmic_glink device to attach to\n"); + return dev_err_probe(&rpdev->dev, -EPROBE_DEFER, + "no pmic_glink device to attach to\n"); dev_set_drvdata(&rpdev->dev, pg); pg->pdr_available = rpdev->id.driver_data; From 33cd898a0f06b6fed0b9f46af000e4e915432120 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 27 Jul 2026 21:17:35 +0530 Subject: [PATCH 10/31] dt-bindings: sram: describe the IPQ5424 IMEM as mmio-sram MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit IMEM shouldn’t be treated as a syscon or simple-mfd because it’s really just on‑chip SRAM, not a block of control registers or a device with multiple hardware functions. Describing it as generic mmio‑sram keeps the model simple and closer to what the hardware actually is. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy Link: https://patch.msgid.link/20260727-wdt_reset_reason-v11-1-eeedb22beefe@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 - Documentation/devicetree/bindings/sram/sram.yaml | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index b4f082f2af3a..2f120376a8f4 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -18,7 +18,6 @@ properties: items: - enum: - qcom,apq8064-imem - - qcom,ipq5424-imem - qcom,msm8226-imem - qcom,msm8974-imem - qcom,msm8976-imem diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index b83fc6831947..0acb7593045c 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -37,6 +37,7 @@ properties: - qcom,eliza-imem - qcom,glymur-imem - qcom,hawi-imem + - qcom,ipq5424-imem - qcom,kaanapali-imem - qcom,maili-imem - qcom,milos-imem From 02171d1103d3489dd7920534df4f96b6d101db01 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Thu, 10 Sep 2026 18:30:43 +0530 Subject: [PATCH 11/31] dt-bindings: cache: qcom,llcc: Add Nord compatible Nord has four DDR slices with four MACH9 LLCC banks each, so it exposes sixteen bank regions plus the shared broadcast OR/AND pair. Add its compatible with a matching reg/reg-names group and raise the top level maxItems to eighteen. Signed-off-by: Anurag Pateriya Reviewed-by: Shawn Guo Reviewed-by: Komal Bajaj Link: https://patch.msgid.link/20260910-nord_llcc-v1-1-30fd1cca65fe@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/cache/qcom,llcc.yaml | 55 ++++++++++++++++++- 1 file changed, 53 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index a1340226a0d0..2141e5d4de63 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -26,6 +26,7 @@ properties: - qcom,hawi-llcc - qcom,ipq5424-llcc - qcom,kaanapali-llcc + - qcom,nord-llcc - qcom,qcs615-llcc - qcom,qcs8300-llcc - qcom,qdu1000-llcc @@ -56,11 +57,11 @@ properties: reg: minItems: 1 - maxItems: 14 + maxItems: 18 reg-names: minItems: 1 - maxItems: 14 + maxItems: 18 interrupts: maxItems: 1 @@ -355,6 +356,56 @@ allOf: - const: llcc3_base - const: llcc_broadcast_base - const: llcc_broadcast_and_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC8 base register region + - description: LLCC9 base register region + - description: LLCC10 base register region + - description: LLCC11 base register region + - description: LLCC12 base register region + - description: LLCC13 base register region + - description: LLCC14 base register region + - description: LLCC15 base register region + - description: LLCC broadcast OR register region + - description: LLCC broadcast AND register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc8_base + - const: llcc9_base + - const: llcc10_base + - const: llcc11_base + - const: llcc12_base + - const: llcc13_base + - const: llcc14_base + - const: llcc15_base + - const: llcc_broadcast_base + - const: llcc_broadcast_and_base + - if: properties: compatible: From c3a652c41a8778b9e114fb16ad7998c4c6f65895 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Thu, 10 Sep 2026 18:30:44 +0530 Subject: [PATCH 12/31] soc: qcom: llcc: Add LLCC configuration for Nord Add the sub-cache table for Nord, derived from the Nord AU (Safe IVI) SCT table and limited to the POR use cases that have a unique SCID and a usecase ID in llcc-qcom.h. Nord has the CFG0/CFG1 pairs and the full ALGO_ALLOC0..3 set, so it uses the v6 register offsets. num_banks is set explicitly because LLCC_LB_CNT in LLCC_COMMON_STATUS0 is four bits wide and cannot report sixteen banks; a wrong count makes the driver map a bank aperture in place of the broadcast region and abort on the first broadcast read. no_edac is set because the bootloader leaves the LLCC EDAC registers locked, as on Glymur. Signed-off-by: Anurag Pateriya Tested-by: Zhangfei Gao Reviewed-by: Shawn Guo Reviewed-by: Abel Vesa Reviewed-by: Komal Bajaj Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260910-nord_llcc-v1-2-30fd1cca65fe@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/llcc-qcom.c | 139 +++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 2 + 2 files changed, 141 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 5e45a10663c4..d7a42a8040a1 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1054,6 +1054,128 @@ static const struct llcc_slice_config kaanapali_data[] = { }, }; +static const struct llcc_slice_config nord_data[] = { + { + .usecase_id = LLCC_CPUSS, + .slice_id = 1, + .max_cap = 3072, + .priority = 0, + .bonus_ways = 0xff, + .activate_on_init = true, + .write_scid_en = true, + .write_scid_cacheable_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_CMPT, + .slice_id = 34, + .max_cap = 0, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, { + .usecase_id = LLCC_GPUHTW, + .slice_id = 11, + .max_cap = 512, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, { + .usecase_id = LLCC_GPU, + .slice_id = 12, + .max_cap = 2048, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .write_scid_en = true, + .write_scid_cacheable_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_MMUHWT, + .slice_id = 13, + .max_cap = 1024, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_CAMFW, + .slice_id = 20, + .max_cap = 512, + .priority = 2, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, { + .usecase_id = LLCC_ECC, + .slice_id = 26, + .max_cap = 1536, + .priority = 3, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .write_scid_en = true, + .write_scid_cacheable_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_WRCACHE, + .slice_id = 31, + .max_cap = 2048, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_LCPDARE, + .slice_id = 30, + .max_cap = 512, + .priority = 3, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .alloc_oneway_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_COMPUTE1, + .slice_id = 22, + .max_cap = 0, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, { + .usecase_id = LLCC_PCIE_TCU, + .slice_id = 15, + .max_cap = 0, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .activate_on_init = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_GPU_LITTLE, + .slice_id = 9, + .max_cap = 2048, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .write_scid_en = true, + .write_scid_cacheable_en = true, + .vict_prio = true, + }, { + .usecase_id = LLCC_GPUHTW_LITTLE, + .slice_id = 14, + .max_cap = 512, + .priority = 1, + .fixed_size = true, + .bonus_ways = 0xff, + .vict_prio = true, + }, +}; + static const struct llcc_slice_config sa8775p_data[] = { { .usecase_id = LLCC_CPUSS, @@ -4484,6 +4606,17 @@ static const struct qcom_llcc_config glymur_cfg[] = { }, }; +static const struct qcom_llcc_config nord_cfg[] = { + { + .sct_data = nord_data, + .size = ARRAY_SIZE(nord_data), + .reg_offset = llcc_v6_reg_offset, + .edac_reg_offset = &llcc_v6_edac_reg_offset, + .num_banks = 16, + .no_edac = true, + }, +}; + static const struct qcom_llcc_config qcs615_cfg[] = { { .sct_data = qcs615_data, @@ -4751,6 +4884,11 @@ static const struct qcom_sct_config glymur_cfgs = { .num_config = ARRAY_SIZE(glymur_cfg), }; +static const struct qcom_sct_config nord_cfgs = { + .llcc_config = nord_cfg, + .num_config = ARRAY_SIZE(nord_cfg), +}; + static const struct qcom_sct_config qcs615_cfgs = { .llcc_config = qcs615_cfg, .num_config = ARRAY_SIZE(qcs615_cfg), @@ -5693,6 +5831,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,hawi-llcc", .data = &hawi_sct_cfgs }, { .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs}, { .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs}, + { .compatible = "qcom,nord-llcc", .data = &nord_cfgs}, { .compatible = "qcom,qcs615-llcc", .data = &qcs615_cfgs}, { .compatible = "qcom,qcs8300-llcc", .data = &qcs8300_cfgs}, { .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs}, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 1ccc429401e8..713cb0221b14 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -74,6 +74,7 @@ #define LLCC_CAMSRTIP 73 #define LLCC_CAMRTRF 74 #define LLCC_CAMSRTRF 75 +#define LLCC_GPU_LITTLE 80 #define LLCC_OOBM_NS 81 #define LLCC_OOBM_S 82 #define LLCC_VIDEO_APV 83 @@ -85,6 +86,7 @@ #define LLCC_CAM_OFE_STROV 93 #define LLCC_CPUSS_HEU 94 #define LLCC_PCIE_TCU 97 +#define LLCC_GPUHTW_LITTLE 98 #define LLCC_MDM_PNG_FIXED 100 #define LLCC_PPE_RXDESC 101 #define LLCC_PPE_RXFILL 102 From 50508d3e0abd83bf0ff82f53cc89a987728853a9 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sun, 13 Sep 2026 13:30:49 -0400 Subject: [PATCH 13/31] firmware: qcom: scm: Hide QCOM_SCM instead of depending on ARCH_QCOM imx_v6_v7_defconfig fails to link: arm-linux-gnueabihf-ld: drivers/firmware/qcom/qcom_scm.o: in function `qcom_scm_pas_init_image': qcom_scm.c:(.text+0xecc): undefined reference to `qcom_tzmem_alloc' qcom_scm.c:(.text+0x2b0): undefined reference to `qcom_tzmem_free' qcom_scm.c:(.text+0x1514): undefined reference to `qcom_tzmem_to_phys' QCOM_SCM gained a "depends on ARCH_QCOM || COMPILE_TEST", but it is selected from 20 places in the tree and several of those are reachable without ARCH_QCOM. DRM_MSM is one of them, via SOC_IMX5, which is how imx_v6_v7_defconfig ends up here: WARNING: unmet direct dependencies detected for QCOM_SCM Depends on [n]: ARCH_QCOM [=n] || COMPILE_TEST [=n] Selected by [y]: - DRM_MSM [=y] && ... && (ARCH_QCOM [=n] || SOC_IMX5 [=y] || COMPILE_TEST [=n]) && ... kconfig still honours the select and sets QCOM_SCM=y, but it does not propagate the selects of a symbol whose own dependencies are unmet, so QCOM_TZMEM is left unset, qcom_tzmem.c is not built, and the unconditional qcom_tzmem_*() calls in qcom_scm.c and qcom_scm-smc.c have nothing to bind to. The point of the dependency was only to stop asking the user about Qualcomm firmware interfaces when configuring a non-Qualcomm kernel. Express that as a prompt condition, which is what the same commit already did for QCOM_PAS: the symbol stays invisible, but it no longer carries a dependency that silently drops its selects. Found by KernelCI builds of the linux-next tree. Fixes: 8fecd3194de3 ("firmware: QCOM interfaces should depend on ARCH_QCOM") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202609120634.g0HMAp3g-lkp@intel.com/ Assisted-by: LLM Signed-off-by: Sasha Levin Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260913173049.1168963-1-sashal@kernel.org Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index 691db0ded8e8..b50e1309ced5 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -26,8 +26,7 @@ config QCOM_PAS_TEE by the firmware TEE implementation as the backend. config QCOM_SCM - tristate "Qualcomm PAS SCM interface driver" - depends on ARCH_QCOM || COMPILE_TEST + tristate "Qualcomm PAS SCM interface driver" if ARCH_QCOM || COMPILE_TEST select QCOM_PAS select QCOM_TZMEM default y if ARCH_QCOM From 17a46b6ffa2f7227e166a0b4b82f159c983b2d84 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Mon, 3 Aug 2026 02:03:45 +0700 Subject: [PATCH 14/31] dt-bindings: mfd: syscon: add qcom,msm8960-sps-sic Add compat for Smart Peripheral System (SPS) Interrupt Controller (SIC) present on Qualcomm MSM8960 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Antony Kurniawan Soemardi Link: https://patch.msgid.link/20260803-msm8960-wifi-v4-1-5ffa27aea39d@smankusors.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 945a168b613d..33e0b1bad5ab 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -107,6 +107,7 @@ properties: - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic + - qcom,msm8960-sps-sic - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos From 803f9950a6c6e0b37ed7f24925feed823703467e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 23 Sep 2026 10:51:45 +0200 Subject: [PATCH 15/31] soc: qcom: geni-se: provide PROG_RAM_DEPTH for I2C HUB Serial Engines The I2C Hub serial elements lacks DMA, so the SE_HW_PARAM_2 register which is in the DMA register space doesn't exist for those instances. Provide the ram depth in the compatible data to be used instead of the reading the missing SE_HW_PARAM_2 register. Fixes: 522bfb4f33c0 ("soc: qcom: geni-se: Use HW PROG_RAM_DEPTH to validate firmware size") Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Neil Armstrong Link: https://patch.msgid.link/20260923-topic-sm8x50-i2c-hub-fw-ram-v3-1-44287b4e814b@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom-geni-se.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 6ac2bdc16984..08e05ba70f73 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -101,22 +101,26 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(geni_se_regs); * @base: Base address of this instance of QUP wrapper core * @clks: Handle to the primary & optional secondary AHB clocks * @num_clks: Count of clocks + * @prog_ram_depth: Available CFG RAM depth for instance without SE_HW_PARAM_2 */ struct geni_wrapper { struct device *dev; void __iomem *base; struct clk_bulk_data clks[MAX_CLKS]; unsigned int num_clks; + unsigned int prog_ram_depth; }; /** * struct geni_se_desc - Data structure to represent the QUP Wrapper resources * @clks: Name of the primary & optional secondary AHB clocks * @num_clks: Count of clock names + * @prog_ram_depth: Available CFG RAM depth for instance without SE_HW_PARAM_2 */ struct geni_se_desc { unsigned int num_clks; const char * const *clks; + unsigned int prog_ram_depth; }; static const char * const icc_path_names[] = {"qup-core", "qup-config", @@ -1244,6 +1248,7 @@ static const struct se_fw_hdr *geni_find_protocol_fw(struct geni_se *se, const s enum geni_se_protocol_type protocol, u32 *fw_size_out) { + struct geni_wrapper *wrapper = se->wrapper; struct device *dev = se->dev; const struct elf32_hdr *ehdr; const struct elf32_phdr *phdrs; @@ -1308,8 +1313,11 @@ static const struct se_fw_hdr *geni_find_protocol_fw(struct geni_se *se, const s cfg_val_end = le16_to_cpu(sefw->cfg_val_offset) + le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u32); - prog_ram_depth = FIELD_GET(PROG_RAM_DEPTH_MSK, - readl_relaxed(se->base + SE_HW_PARAM_2)); + if (wrapper->prog_ram_depth) + prog_ram_depth = wrapper->prog_ram_depth; + else + prog_ram_depth = FIELD_GET(PROG_RAM_DEPTH_MSK, + readl_relaxed(se->base + SE_HW_PARAM_2)); if (fw_size >= prog_ram_depth) { dev_err(dev, "Firmware size (%u) exceeds RAM size (%u)\n", fw_size, prog_ram_depth); @@ -1620,6 +1628,7 @@ static int geni_se_probe(struct platform_device *pdev) return PTR_ERR(wrapper->base); desc = device_get_match_data(&pdev->dev); + wrapper->prog_ram_depth = desc->prog_ram_depth; if (!has_acpi_companion(&pdev->dev) && desc->num_clks) { int i; @@ -1672,6 +1681,7 @@ static const char * const i2c_master_hub_clks[] = { static const struct geni_se_desc i2c_master_hub_desc = { .clks = i2c_master_hub_clks, .num_clks = ARRAY_SIZE(i2c_master_hub_clks), + .prog_ram_depth = 1020, }; static const struct of_device_id geni_se_dt_match[] = { From c8f9c5192c39db9b88550d7392e3f656b6560d75 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Tue, 22 Sep 2026 16:06:19 -0700 Subject: [PATCH 16/31] dt-bindings: arm: qcom,ids: Add SoC ID for SM8950 Add the ID for the Qualcomm SM8950 SoC which represents the Maili platform. Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260922-maili-socinfo-v1-1-a82bd7d4ca77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 4259f8960447..135297027580 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -304,6 +304,7 @@ #define QCOM_ID_SM8975 707 #define QCOM_ID_CQ7790M 731 #define QCOM_ID_CQ7790S 732 +#define QCOM_ID_SM8950 735 #define QCOM_ID_CQ2390M 756 #define QCOM_ID_CQ2390S 758 #define QCOM_ID_IQ2390S 759 From 5ce6f7de57c0efa4075eaf76245e622f962d0cfe Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Tue, 22 Sep 2026 16:06:20 -0700 Subject: [PATCH 17/31] soc: qcom: socinfo: Add SM8950 SoC ID Add SoC ID for Qualcomm SM8950 which represents the Maili platform. Signed-off-by: Jingyi Wang Link: https://patch.msgid.link/20260922-maili-socinfo-v1-2-a82bd7d4ca77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index ddc717382797..38efc5db7fa8 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -545,6 +545,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SM8975) }, { qcom_board_id(CQ7790M) }, { qcom_board_id(CQ7790S) }, + { qcom_board_id(SM8950) }, { qcom_board_id(CQ2390M) }, { qcom_board_id(CQ2390S) }, { qcom_board_id(IQ2390S) }, From af0730a79096af88a8801740bf92795beb172ce4 Mon Sep 17 00:00:00 2001 From: Hemanth Selam Date: Mon, 7 Sep 2026 11:47:41 +0530 Subject: [PATCH 18/31] firmware: qcom: fix typo "uninterruptable" in comment Correct "uninterruptable" to "uninterruptible", reported by scripts/checkpatch.pl using the misspelling list in scripts/spelling.txt. Only touches comments, no code changes. Assisted-by: Cursor:claude-opus-5 Signed-off-by: Hemanth Selam Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260907061742.10954-2-hemanth.selam@gmail.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm-legacy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm-legacy.c b/drivers/firmware/qcom/qcom_scm-legacy.c index 029e6d117cb8..fe751ee512da 100644 --- a/drivers/firmware/qcom/qcom_scm-legacy.c +++ b/drivers/firmware/qcom/qcom_scm-legacy.c @@ -219,7 +219,7 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, * @res: SCM call return values * * This shall only be used with commands that are guaranteed to be - * uninterruptable, atomic and SMP safe. + * uninterruptible, atomic and SMP safe. */ int scm_legacy_call_atomic(struct device *unused, const struct qcom_scm_desc *desc, From d2bcd688b74857d4c12315a7426302c192671ec8 Mon Sep 17 00:00:00 2001 From: Hemanth Selam Date: Mon, 7 Sep 2026 11:47:42 +0530 Subject: [PATCH 19/31] soc: qcom: fix typo "upto" in comment Correct "upto" to "up to", reported by scripts/checkpatch.pl using the misspelling list in scripts/spelling.txt. Only touches comments, no code changes. Assisted-by: Cursor:claude-opus-5 Signed-off-by: Hemanth Selam Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260907061742.10954-3-hemanth.selam@gmail.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom-geni-se.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 08e05ba70f73..7ad002b111c8 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -42,7 +42,7 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(geni_se_regs); * * GENI based QUP is a highly-flexible and programmable module for supporting * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single - * QUP module can provide upto 8 serial interfaces, using its internal + * QUP module can provide up to 8 serial interfaces, using its internal * serial engines. The actual configuration is determined by the target * platform configuration. The protocol supported by each interface is * determined by the firmware loaded to the serial engine. Each SE consists From ed0c12e25cce898db1a42eb2b9e1d5e87c56d315 Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Mon, 7 Sep 2026 19:17:53 +0530 Subject: [PATCH 20/31] dt-bindings: soc: qcom: stats: Add compatible for Shikra SoC LPM stats are present in RPM MSGRAM and subsystem LPM stats are present in SMEM for Shikra. A generic "qcom,rpm-stats" compatible only reads SoC LPM stats like vmin and vlow. Document shikra rpm compatible to read subsystem LPM stats too along with SoC LPM stats. Keep "qcom,rpm-stats" as a fallback for RPM targets, so that SoC level stats are still shown even without subsystem level stats support. A plain enum can't express that, since it caps compatible at one item. Add a oneOf branch with items for this pattern. Signed-off-by: Sneh Mankad Reviewed-by: Komal Bajaj Link: https://patch.msgid.link/20260907-shikra_stats-v4-1-3825351f9740@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/soc/qcom/qcom-stats.yaml | 25 ++++++++++++------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml index 686a7ef2f48a..b384a5983d43 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom-stats.yaml @@ -18,15 +18,22 @@ description: properties: compatible: - enum: - - qcom,rpmh-stats - - qcom,sdm845-rpmh-stats - - qcom,rpm-stats - # For older RPM firmware versions with fixed offset for the sleep stats - - qcom,apq8084-rpm-stats - - qcom,msm8226-rpm-stats - - qcom,msm8916-rpm-stats - - qcom,msm8974-rpm-stats + oneOf: + - enum: + - qcom,rpmh-stats + - qcom,sdm845-rpmh-stats + - qcom,rpm-stats + # For older RPM firmware versions with fixed offset for the sleep stats + - qcom,apq8084-rpm-stats + - qcom,msm8226-rpm-stats + - qcom,msm8916-rpm-stats + - qcom,msm8974-rpm-stats + # SoC-specific compatibles that also read subsystem-level stats, + # falling back to "qcom,rpm-stats" for SoC-level stats only + - items: + - enum: + - qcom,shikra-rpm-stats + - const: qcom,rpm-stats reg: maxItems: 1 From c98d40a52c9e13578521f4a7ea91427117ec806e Mon Sep 17 00:00:00 2001 From: Sneh Mankad Date: Mon, 7 Sep 2026 19:17:54 +0530 Subject: [PATCH 21/31] soc: qcom: stats: Add stats compatible and config for Shikra SoC LPM stats are present in RPM MSGRAM and subsystem LPM stats are present in SMEM for Shikra. For earlier targets using RPM processor like msm8974, rpm_master_stat.c was used for subsystem LPM stats since those stats were populated in RPM MSGRAM. Here is a brief summary of previous targets and their stats configuration, along with the drivers used to display them. +---------------|----------------------------|---------------------------+ | SoC | subsystem LPM stats | SoC LPM stats | |---------------|----------------------------|---------------------------| | msm8974, | RPM processor MSGRAM | RPM processor MSGRAM | | msm8226 | (rpm_master_stat.c) | (qcom_stats.c) | |---------------|----------------------------|---------------------------| | sm6350, | SMEM (DDR) | AOP processor MSGRAM | | sdm845, etc. | (qcom_stats.c) | (qcom_stats.c) | |---------------|----------------------------|---------------------------| | Shikra | SMEM (DDR) | RPM processor MSGRAM | | | (qcom_stats.c) | (qcom_stats.c) | +---------------|----------------------------|---------------------------+ qcom_stats.c supports both the configurations for shikra, reading subsystem LPM stats from SMEM and reading SoC LPM stats from RPM MSGRAM. A generic "qcom,rpm-stats" compatible only reads SoC LPM stats like vmin and vlow. Add shikra rpm compatible and config to read subsystem LPM stats too along with SoC LPM stats. Below is an example showing LPM stats for "apss" subsystem with this change: cat /sys/kernel/debug/qcom_stats/apss Count: 2192 Last Entered At: 5498618336 Last Exited At: 5498708046 Accumulated Duration: 2046572620. Reviewed-by: Konrad Dybcio Reviewed-by: Maulik Shah Signed-off-by: Sneh Mankad Reviewed-by: Komal Bajaj Reviewed-by: Abel Vesa Link: https://patch.msgid.link/20260907-shikra_stats-v4-2-3825351f9740@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_stats.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/soc/qcom/qcom_stats.c b/drivers/soc/qcom/qcom_stats.c index 06923408bfce..3422d6df7b51 100644 --- a/drivers/soc/qcom/qcom_stats.c +++ b/drivers/soc/qcom/qcom_stats.c @@ -371,6 +371,14 @@ static const struct stats_config rpm_data_dba0 = { .subsystem_stats_in_smem = false, }; +static const struct stats_config rpm_data_shikra = { + .stats_offset = 0, + .num_records = 2, + .appended_stats_avail = true, + .dynamic_offset = true, + .subsystem_stats_in_smem = true, +}; + static const struct stats_config rpmh_data_sdm845 = { .stats_offset = 0x48, .num_records = 2, @@ -396,6 +404,7 @@ static const struct of_device_id qcom_stats_table[] = { { .compatible = "qcom,rpm-stats", .data = &rpm_data }, { .compatible = "qcom,rpmh-stats", .data = &rpmh_data }, { .compatible = "qcom,sdm845-rpmh-stats", .data = &rpmh_data_sdm845 }, + { .compatible = "qcom,shikra-rpm-stats", .data = &rpm_data_shikra }, { } }; MODULE_DEVICE_TABLE(of, qcom_stats_table); From d745bbeb0f780d7e2dbe9a5ba08db3ee89eec8c0 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Tue, 8 Sep 2026 23:40:54 -0700 Subject: [PATCH 22/31] firmware: qcom: scm: Allow QSEECOM on the Glymur QCB Add Glymur QCB board to the QSEECOM allowlist for enabling access to efivars and uefi bootloader. Reviewed-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Signed-off-by: Gopikrishna Garmidi Link: https://patch.msgid.link/20260908-glymur-qcb-v3-3-c194c0219218@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index d309689de266..56d54c4f09e2 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2340,6 +2340,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "microsoft,romulus13", }, { .compatible = "microsoft,romulus15", }, { .compatible = "qcom,glymur-crd" }, + { .compatible = "qcom,glymur-qcb" }, { .compatible = "qcom,hamoa-iot-evk" }, { .compatible = "qcom,mahua-crd" }, { .compatible = "qcom,purwa-iot-evk" }, From cbab6ecf312831a2fc55ec21c168ef895514d8c5 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Wed, 9 Sep 2026 00:18:17 -0700 Subject: [PATCH 23/31] firmware: qcom: scm: Allow QSEECOM on Kalambo CRD Add Kalambo CRD board to the QSEECOM allowlist for enabling access to efivars. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Gopikrishna Garmidi Link: https://patch.msgid.link/20260909-b4-kalambo-crd-v7-4-f5685804478a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 56d54c4f09e2..1ac77eb6ac65 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2342,6 +2342,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "qcom,glymur-crd" }, { .compatible = "qcom,glymur-qcb" }, { .compatible = "qcom,hamoa-iot-evk" }, + { .compatible = "qcom,kalambo-crd" }, { .compatible = "qcom,mahua-crd" }, { .compatible = "qcom,purwa-iot-evk" }, { .compatible = "qcom,sc8180x-primus" }, From 1337776a5388a0641c4ad12c30c8da7381971f37 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Wed, 9 Sep 2026 00:18:18 -0700 Subject: [PATCH 24/31] soc: qcom: ubwc: Add Kalambo UBWC config Qualcomm Kalambo is a derivative of the Mahua SoC and shares the same Universal Bandwidth Compression (UBWC) configuration. Add the Kalambo compatible to the UBWC configuration table to enable support. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Gopikrishna Garmidi Link: https://patch.msgid.link/20260909-b4-kalambo-crd-v7-5-f5685804478a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/ubwc_config.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 53c1df3ca641..a4d8769f8550 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -121,6 +121,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = { { .compatible = "qcom,glymur", .data = &glymur_data}, { .compatible = "qcom,hawi", .data = &ubwc_7_0_hbb16 }, { .compatible = "qcom,kaanapali", .data = &ubwc_6_0_hbb16 }, + { .compatible = "qcom,kalambo", .data = &glymur_data }, { .compatible = "qcom,mahua", .data = &glymur_data }, { .compatible = "qcom,maili", .data = &ubwc_7_0_hbb16, }, { .compatible = "qcom,milos", .data = &milos_data }, From e2467151dcab02a7b134eac32b74fb8267bc2a24 Mon Sep 17 00:00:00 2001 From: Vitalii Skorkin Date: Thu, 10 Sep 2026 15:27:22 +0300 Subject: [PATCH 25/31] firmware: qcom: tzmem: disable SHM bridge for SM7125 platform Currently SHM bridge causes RCU stalls when booting. Disable it for SM7125 until a fix is available. Signed-off-by: Vitalii Skorkin Reviewed-by: Dmitry Baryshkov Acked-by: Bartosz Golaszewski Signed-off-by: Erikas Bitovtas Link: https://patch.msgid.link/20260910-sm7125-samsung-v3-2-c467bea0fb9c@gmail.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_tzmem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom/qcom_tzmem.c b/drivers/firmware/qcom/qcom_tzmem.c index ebcdee3c5975..44cf80c84d7f 100644 --- a/drivers/firmware/qcom/qcom_tzmem.c +++ b/drivers/firmware/qcom/qcom_tzmem.c @@ -82,6 +82,7 @@ static const char *const qcom_tzmem_blacklist[] = { "qcom,sc8180x", "qcom,sdm670", /* failure in GPU firmware loading */ "qcom,sdm845", /* reset in rmtfs memory assignment */ + "qcom,sm7125", /* hang in rmtfs memory assignment */ "qcom,sm7150", /* reset in rmtfs memory assignment */ "qcom,sm8150", /* reset in rmtfs memory assignment */ NULL From ceab390aeefaa28e4c91ccdc60f53d18f8b76c79 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Thu, 17 Sep 2026 10:07:30 +0530 Subject: [PATCH 26/31] ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra Add support for the modem_apps GLINK channel on Shikra, as audio processing is handled through the modem DSP. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Mohammad Rafi Shaik Link: https://patch.msgid.link/20260917-shikra_audio_dts-v3-1-9a49e1ca6370@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index e51acdcaafaf..01250b556985 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -120,7 +120,9 @@ allOf: properties: qcom,glink-channels: items: - - const: adsp_apps + - enum: + - adsp_apps + - modem_apps power-domains: false else: properties: From 66894a1c51366cc2d5c498178105dfe3bcccc1e4 Mon Sep 17 00:00:00 2001 From: Yibo Tan Date: Sun, 13 Sep 2026 00:12:10 +0800 Subject: [PATCH 27/31] soc: qcom: pmic_pdcharger_ulog: prevent work requeue during remove pmic_pdcharger_ulog_rpmsg_remove() cancels the delayed worker while the RPMsg endpoint can still deliver callbacks. The RPMsg core invokes the driver remove callback before destroying the endpoint, so a response callback can run after cancel_delayed_work_sync() returns and queue the worker again. Device cleanup then frees the devm-allocated pmic_pdcharger_ulog while the requeued delayed work still embeds and dereferences that object. KASAN reports a slab-use-after-free in pmic_pdcharger_ulog_work(). Use disable_delayed_work_sync() to drain the worker and reject queue attempts that race with removal. The issue was reproduced in four of four runs with the real target driver, RPMsg bus removal, endpoint teardown, workqueue code and devres cleanup. The test provider delivered a valid response in the window between the driver remove callback and endpoint destruction. With this change, the same late callback occurred in four of four runs without a KASAN report, warning, Oops or panic. The reproducer uses a test RPMsg provider to control the teardown timing. No unprivileged trigger or physical Qualcomm-device result is claimed. Fixes: 086fdb48bc65 ("soc: qcom: add ADSP PDCharger ULOG driver") Assisted-by: Codex:GPT-5 Signed-off-by: Yibo Tan Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://patch.msgid.link/20260912161210.1683266-1-lhfff@tju.edu.cn Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_pdcharger_ulog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/pmic_pdcharger_ulog.c b/drivers/soc/qcom/pmic_pdcharger_ulog.c index 39f412bbf2c1..06cd9c4411c2 100644 --- a/drivers/soc/qcom/pmic_pdcharger_ulog.c +++ b/drivers/soc/qcom/pmic_pdcharger_ulog.c @@ -143,7 +143,7 @@ static void pmic_pdcharger_ulog_rpmsg_remove(struct rpmsg_device *rpdev) { struct pmic_pdcharger_ulog *pg = dev_get_drvdata(&rpdev->dev); - cancel_delayed_work_sync(&pg->ulog_work); + disable_delayed_work_sync(&pg->ulog_work); } static const struct rpmsg_device_id pmic_pdcharger_ulog_rpmsg_id_match[] = { From a46b914f6aa4056673727e72747874aa8b7a4975 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Mon, 31 Aug 2026 20:53:44 -0700 Subject: [PATCH 28/31] dt-bindings: spmi: glymur-spmi-pmic-arb: Add compatible for Qualcomm Maili SoC The PMIC arbiter in the Qualcomm Maili SoC is version v8.5, which is the same with Hawi and compatible with Glymur. Hence, add a string for "qcom,maili-spmi-pmic-arb" as a compatible entry for "qcom,glymur-spmi-pmic-arb". Reviewed-by: Yijie Yang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Fenglin Wu Reviewed-by: Abel Vesa Link: https://patch.msgid.link/20260831-maili-spmi-binding-v2-1-37a25ef3921c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml index 1593a1183a36..44c864fd5fc7 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml +++ b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml @@ -27,6 +27,7 @@ properties: - enum: - qcom,hawi-spmi-pmic-arb - qcom,kaanapali-spmi-pmic-arb + - qcom,maili-spmi-pmic-arb - const: qcom,glymur-spmi-pmic-arb - enum: - qcom,glymur-spmi-pmic-arb From ccd9552a96f3b0e2f55c397368f575446c0e6acd Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 7 Sep 2026 14:07:18 +0530 Subject: [PATCH 29/31] dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller Document the CPU Control Processor (CPUCP) mailbox controller for the Qualcomm Maili SoC. It is software compatible with the X1E80100 CPUCP mailbox controller and uses it as a fallback compatible string. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das Reviewed-by: Maria Yu Link: https://patch.msgid.link/20260907-maili_initial_clock-v5-1-e79bb6b93a49@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 03359479d926..2185920e1b5d 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -21,6 +21,7 @@ properties: - qcom,glymur-cpucp-mbox - qcom,hawi-cpucp-mbox - qcom,kaanapali-cpucp-mbox + - qcom,maili-cpucp-mbox - qcom,nord-cpucp-mbox - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox From 73fa037209f9c2e50681a1cd04a4ef5f76f87873 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 28 Sep 2026 15:51:22 +0100 Subject: [PATCH 30/31] firmware: qcom: scm: Allow QSEECOM on ThinkPad T14s Gen 7 Allow the use of QSEECOM on the Mahua-based Lenovo ThinkPad T14s Gen 7, matching the pattern established for the Yoga Slim 7x Gen 11. Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Srinivas Kandagatla Link: https://patch.msgid.link/20260928145122.1337186-4-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 1ac77eb6ac65..ca5d7bd4af8e 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2329,6 +2329,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "lenovo,ideacentre-mini-01q8x10" }, { .compatible = "lenovo,thinkbook-16" }, { .compatible = "lenovo,thinkpad-t14s" }, + { .compatible = "lenovo,thinkpad-t14s-gen7" }, { .compatible = "lenovo,thinkpad-x13s", }, { .compatible = "lenovo,yoga-slim7x" }, { .compatible = "lenovo,yoga-slim7x-gen11" }, From f44ee24f4a96ad97c2f0191e503c91477d9b530b Mon Sep 17 00:00:00 2001 From: Somesh Dey Date: Wed, 30 Sep 2026 13:31:54 +0530 Subject: [PATCH 31/31] soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get() geni_icc_get() takes an icc_ddr string argument but never uses it: the DDR interconnect path is looked up with the "qup-memory" string literal directly, and the sole caller passes that same literal. The parameter carries no information. Drop the icc_ddr parameter and update the prototype and call site accordingly. Signed-off-by: Somesh Dey Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260930-icc-ddr-param-remove-v1-1-61223714c9bc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom-geni-se.c | 4 ++-- include/linux/soc/qcom/geni-se.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 7ad002b111c8..074087c592cc 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -924,7 +924,7 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) } EXPORT_SYMBOL_GPL(geni_se_rx_dma_unprep); -int geni_icc_get(struct geni_se *se, const char *icc_ddr) +int geni_icc_get(struct geni_se *se) { struct geni_icc_path *icc_paths = se->icc_paths; @@ -1221,7 +1221,7 @@ int geni_se_resources_init(struct geni_se *se) se->has_opp = (ret == 0); - ret = geni_icc_get(se, "qup-memory"); + ret = geni_icc_get(se); if (ret) return ret; diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 29a53bbc0dd4..95c0cc4d4ea1 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -573,7 +573,7 @@ void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); -int geni_icc_get(struct geni_se *se, const char *icc_ddr); +int geni_icc_get(struct geni_se *se); int geni_icc_set_bw(struct geni_se *se); int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 ddr_ab);