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dt-bindings: PCI: tegra194: Convert to json-schema
Convert the Tegra194 PCIe bindings from the free-form text format to json-schema. Link: https://lore.kernel.org/r/20220721142052.25971-2-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Vidya Sagar
Bjorn Helgaas
parent
e8fbd344a5
commit
e4dffb674c
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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- Vidya Sagar <vidyas@nvidia.com>
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description: |
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This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
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inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
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of the controller instances are dual mode; they can work either in Root
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Port mode or Endpoint mode but one at a time.
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On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
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Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
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operate in the Endpoint mode because of the way the platform is designed.
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properties:
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compatible:
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enum:
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- nvidia,tegra194-pcie-ep
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reg:
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items:
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- description: controller's application logic registers
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- description: iATU and DMA registers. This is where the iATU (internal
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Address Translation Unit) registers of the PCIe core are made
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available for software access.
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- description: aperture where the Root Port's own configuration
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registers are available.
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- description: aperture used to map the remote Root Complex address space
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reg-names:
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items:
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- const: appl
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- const: atu_dma
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- const: dbi
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- const: addr_space
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interrupts:
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items:
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- description: controller interrupt
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interrupt-names:
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items:
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- const: intr
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clocks:
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items:
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- description: module clock
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clock-names:
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items:
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- const: core
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resets:
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items:
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- description: APB bus interface reset
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- description: module reset
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reset-names:
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items:
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- const: apb
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- const: core
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reset-gpios:
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description: Must contain a phandle to a GPIO controller followed by GPIO
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that is being used as PERST input signal. Please refer to pci.txt.
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phys:
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minItems: 1
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maxItems: 8
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phy-names:
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minItems: 1
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items:
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- const: p2u-0
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- const: p2u-1
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- const: p2u-2
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- const: p2u-3
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- const: p2u-4
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- const: p2u-5
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- const: p2u-6
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- const: p2u-7
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power-domains:
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maxItems: 1
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description: |
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A phandle to the node that controls power to the respective PCIe
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controller and a specifier name for the PCIe controller.
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Specifiers defined in "include/dt-bindings/power/tegra194-powergate.h".
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interconnects:
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items:
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- description: memory read client
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- description: memory write client
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interconnect-names:
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items:
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- const: dma-mem # read
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- const: write
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dma-coherent: true
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nvidia,bpmp:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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Must contain a pair of phandles to BPMP controller node followed by
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controller ID. Following are the controller IDs for each controller:
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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items:
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- items:
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- description: phandle to BPMP controller node
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- description: PCIe controller ID
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maximum: 5
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nvidia,aspm-cmrt-us:
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description: Common Mode Restore Time for proper operation of ASPM to be
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specified in microseconds
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nvidia,aspm-pwr-on-t-us:
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description: Power On time for proper operation of ASPM to be specified in
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microseconds
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nvidia,aspm-l0s-entrance-latency-us:
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description: ASPM L0s entrance latency to be specified in microseconds
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vddio-pex-ctl-supply:
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description: A phandle to the regulator supply for PCIe side band signals
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nvidia,refclk-select-gpios:
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maxItems: 1
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description: GPIO used to enable REFCLK to controller from the host
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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unevaluatedProperties: false
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required:
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- reset-gpios
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- vddio-pex-ctl-supply
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- num-lanes
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- phys
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- phy-names
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- nvidia,bpmp
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examples:
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- |
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/gpio/tegra194-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/tegra194-powergate.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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bus@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x8 0x0>;
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pcie-ep@141a0000 {
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compatible = "nvidia,tegra194-pcie-ep";
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reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
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<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
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<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
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<0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
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reg-names = "appl", "atu_dma", "dbi", "addr_space";
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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interrupt-names = "intr";
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clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
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clock-names = "core";
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resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
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<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
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reset-names = "apb", "core";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
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pinctrl-names = "default";
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pinctrl-0 = <&clkreq_c5_bi_dir_state>;
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nvidia,bpmp = <&bpmp 5>;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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vddio-pex-ctl-supply = <&vdd_1v8ao>;
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reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
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nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
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GPIO_ACTIVE_HIGH>;
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num-lanes = <8>;
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phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
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<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
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<&p2u_nvhs_6>, <&p2u_nvhs_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
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"p2u-5", "p2u-6", "p2u-7";
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};
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};
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@ -1,245 +0,0 @@
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NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
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This PCIe controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in snps,dw-pcie.yaml and
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snps,dw-pcie-ep.yaml.
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Some of the controller instances are dual mode where in they can work either
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in root port mode or endpoint mode but one at a time.
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Required properties:
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- power-domains: A phandle to the node that controls power to the respective
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PCIe controller and a specifier name for the PCIe controller. Following are
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the specifiers for the different PCIe controllers
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TEGRA194_POWER_DOMAIN_PCIEX8B: C0
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TEGRA194_POWER_DOMAIN_PCIEX1A: C1
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TEGRA194_POWER_DOMAIN_PCIEX1A: C2
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TEGRA194_POWER_DOMAIN_PCIEX1A: C3
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TEGRA194_POWER_DOMAIN_PCIEX4A: C4
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TEGRA194_POWER_DOMAIN_PCIEX8A: C5
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these specifiers are defined in
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"include/dt-bindings/power/tegra194-powergate.h" file.
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- reg: A list of physical base address and length pairs for each set of
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controller registers. Must contain an entry for each entry in the reg-names
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property.
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- reg-names: Must include the following entries:
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"appl": Controller's application logic registers
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"config": As per the definition in snps,dw-pcie.yaml
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"atu_dma": iATU and DMA registers. This is where the iATU (internal Address
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Translation Unit) registers of the PCIe core are made available
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for SW access.
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"dbi": The aperture where root port's own configuration registers are
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available
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The Tegra interrupt that is asserted for controller interrupts
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- core
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- apb
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- core
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- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane.
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"p2u-N": where N ranges from 0 to one less than the total number of lanes
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- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
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by controller-id. Following are the controller ids for each controller.
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
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RC mode:
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- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
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- device_type: Must be "pci" for RC mode
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- interrupt-names: Must include the following entries:
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"msi": The Tegra interrupt that is asserted when an MSI is received
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- bus-range: Range of bus numbers associated with this controller
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- #address-cells: Address representation for root ports (must be 3)
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- cell 0 specifies the bus and device numbers of the root port:
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[23:16]: bus number
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[15:11]: device number
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- cell 1 denotes the upper 32 address bits and should be 0
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- cell 2 contains the lower 32 address bits and is used to translate to the
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CPU address space
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- #size-cells: Size representation for root ports (must be 2)
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- ranges: Describes the translation of addresses for root ports and standard
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PCI regions. The entries must be 7 cells each, where the first three cells
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correspond to the address as described for the #address-cells property
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above, the fourth and fifth cells are for the physical CPU address to
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translate to and the sixth and seventh cells are as described for the
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#size-cells property above.
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- Entries setup the mapping for the standard I/O, memory and
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prefetchable PCI regions. The first cell determines the type of region
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that is setup:
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- 0x81000000: I/O memory region
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- 0x82000000: non-prefetchable memory region
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- 0xc2000000: prefetchable memory region
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- #interrupt-cells: Size representation for interrupts (must be 1)
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- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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EP mode:
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In Tegra194, Only controllers C0, C4 & C5 support EP mode.
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- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
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- reg-names: Must include the following entries:
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"addr_space": Used to map remote RC address space
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- reset-gpios: Must contain a phandle to a GPIO controller followed by
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GPIO that is being used as PERST input signal. Please refer to pci.txt
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document.
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Optional properties:
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- pinctrl-names: A list of pinctrl state names.
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It is mandatory for C5 controller and optional for other controllers.
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- "default": Configures PCIe I/O for proper operation.
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- pinctrl-0: phandle for the 'default' state of pin configuration.
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It is mandatory for C5 controller and optional for other controllers.
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- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
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- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
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improve performance when a platform is designed in such a way that it
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satisfies at least one of the following conditions thereby enabling root
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port to exchange optimum number of FC (Flow Control) credits with
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downstream devices
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1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
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2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
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a) speed is Gen-2 and MPS is 256B
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b) speed is >= Gen-3 with any MPS
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- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
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to be specified in microseconds
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- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
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specified in microseconds
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- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
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specified in microseconds
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RC mode:
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- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
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if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
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in p2972-0000 platform).
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- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
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if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
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in p2972-0000 platform).
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EP mode:
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- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
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followed by GPIO that is being used to enable REFCLK to controller from host
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NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
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operate in the endpoint mode because of the way the platform is designed.
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Examples:
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=========
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Tegra194 RC mode:
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-----------------
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pcie@14180000 {
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compatible = "nvidia,tegra194-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
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reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
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0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
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reg-names = "appl", "config", "atu_dma";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <8>;
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linux,pci-domain = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
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clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
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clock-names = "core";
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resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
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<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
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reset-names = "apb", "core";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,bpmp = <&bpmp 0>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
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0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
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0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
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vddio-pex-ctl-supply = <&vdd_1v8ao>;
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vpcie3v3-supply = <&vdd_3v3_pcie>;
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vpcie12v-supply = <&vdd_12v_pcie>;
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phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
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<&p2u_hsio_5>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
|
||||
Tegra194 EP mode:
|
||||
-----------------
|
||||
|
||||
pcie-ep@141a0000 {
|
||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
||||
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
|
||||
0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
|
||||
0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
|
||||
0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
|
||||
reg-names = "appl", "atu_dma", "dbi", "addr_space";
|
||||
|
||||
num-lanes = <8>;
|
||||
num-ib-windows = <2>;
|
||||
num-ob-windows = <8>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clkreq_c5_bi_dir_state>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX1_CORE_5>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
interrupt-names = "intr";
|
||||
|
||||
nvidia,bpmp = <&bpmp 5>;
|
||||
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
|
||||
reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
|
||||
|
||||
nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
|
||||
phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
|
||||
<&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
|
||||
<&p2u_nvhs_6>, <&p2u_nvhs_7>;
|
||||
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
251
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
Normal file
251
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
Normal file
|
|
@ -0,0 +1,251 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Vidya Sagar <vidyas@nvidia.com>
|
||||
|
||||
description: |
|
||||
This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
|
||||
inherits all the common properties defined in snps,dw-pcie.yaml. Some of
|
||||
the controller instances are dual mode where in they can work either in
|
||||
Root Port mode or Endpoint mode but one at a time.
|
||||
|
||||
See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
|
||||
tree bindings.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: controller's application logic registers
|
||||
- description: configuration registers
|
||||
- description: iATU and DMA registers. This is where the iATU (internal
|
||||
Address Translation Unit) registers of the PCIe core are made
|
||||
available for software access.
|
||||
- description: aperture where the Root Port's own configuration
|
||||
registers are available.
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: appl
|
||||
- const: config
|
||||
- const: atu_dma
|
||||
- const: dbi
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: controller interrupt
|
||||
- description: MSI interrupt
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: intr
|
||||
- const: msi
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: APB bus interface reset
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: apb
|
||||
- const: core
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: p2u-0
|
||||
- const: p2u-1
|
||||
- const: p2u-2
|
||||
- const: p2u-3
|
||||
- const: p2u-4
|
||||
- const: p2u-5
|
||||
- const: p2u-6
|
||||
- const: p2u-7
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: |
|
||||
A phandle to the node that controls power to the respective PCIe
|
||||
controller and a specifier name for the PCIe controller.
|
||||
|
||||
specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: |
|
||||
Must contain a pair of phandles to BPMP controller node followed by
|
||||
controller ID. Following are the controller IDs for each controller:
|
||||
|
||||
0: C0
|
||||
1: C1
|
||||
2: C2
|
||||
3: C3
|
||||
4: C4
|
||||
5: C5
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to BPMP controller node
|
||||
- description: PCIe controller ID
|
||||
maximum: 5
|
||||
|
||||
nvidia,update-fc-fixup:
|
||||
description: |
|
||||
This is a boolean property and needs to be present to improve performance
|
||||
when a platform is designed in such a way that it satisfies at least one
|
||||
of the following conditions thereby enabling Root Port to exchange
|
||||
optimum number of FC (Flow Control) credits with downstream devices:
|
||||
|
||||
1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
|
||||
2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
|
||||
a) speed is Gen-2 and MPS is 256B
|
||||
b) speed is >= Gen-3 with any MPS
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nvidia,aspm-cmrt-us:
|
||||
description: Common Mode Restore Time for proper operation of ASPM to be
|
||||
specified in microseconds
|
||||
|
||||
nvidia,aspm-pwr-on-t-us:
|
||||
description: Power On time for proper operation of ASPM to be specified in
|
||||
microseconds
|
||||
|
||||
nvidia,aspm-l0s-entrance-latency-us:
|
||||
description: ASPM L0s entrance latency to be specified in microseconds
|
||||
|
||||
vddio-pex-ctl-supply:
|
||||
description: A phandle to the regulator supply for PCIe side band signals.
|
||||
|
||||
vpcie3v3-supply:
|
||||
description: A phandle to the regulator node that supplies 3.3V to the slot
|
||||
if the platform has one such slot, e.g., x16 slot owned by C5 controller
|
||||
in p2972-0000 platform.
|
||||
|
||||
vpcie12v-supply:
|
||||
description: A phandle to the regulator node that supplies 12V to the slot
|
||||
if the platform has one such slot, e.g., x16 slot owned by C5 controller
|
||||
in p2972-0000 platform.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- interrupt-map
|
||||
- interrupt-map-mask
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
- vddio-pex-ctl-supply
|
||||
- num-lanes
|
||||
- phys
|
||||
- phy-names
|
||||
- nvidia,bpmp
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra194-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/tegra194-powergate.h>
|
||||
#include <dt-bindings/reset/tegra194-reset.h>
|
||||
|
||||
bus@0 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x0 0x0 0x0 0x8 0x0>;
|
||||
|
||||
pcie@14180000 {
|
||||
compatible = "nvidia,tegra194-pcie";
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||
reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <8>;
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
|
||||
clock-names = "core";
|
||||
|
||||
resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
|
||||
<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
|
||||
reset-names = "apb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
|
||||
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
nvidia,bpmp = <&bpmp 0>;
|
||||
|
||||
supports-clkreq;
|
||||
nvidia,aspm-cmrt-us = <60>;
|
||||
nvidia,aspm-pwr-on-t-us = <20>;
|
||||
nvidia,aspm-l0s-entrance-latency-us = <3>;
|
||||
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
|
||||
<0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
|
||||
<0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
|
||||
|
||||
vddio-pex-ctl-supply = <&vdd_1v8ao>;
|
||||
vpcie3v3-supply = <&vdd_3v3_pcie>;
|
||||
vpcie12v-supply = <&vdd_12v_pcie>;
|
||||
|
||||
phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
|
||||
<&p2u_hsio_5>;
|
||||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
|
||||
};
|
||||
};
|
||||
|
|
@ -34,8 +34,8 @@ properties:
|
|||
minItems: 2
|
||||
maxItems: 5
|
||||
items:
|
||||
enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
|
||||
ulreg, smu, mpu, apb, phy ]
|
||||
enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
|
||||
parf, cfg, link, ulreg, smu, mpu, apb, phy ]
|
||||
|
||||
num-lanes:
|
||||
description: |
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user