dt-bindings: phy: samsung,usb3-drd-phy: add exynos2200 support

Document support for Exynos2200. As the USBDRD 3.2 4nm controller
consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will
be handled by external drivers, define only the bus clocked used
by the link controller.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Ivaylo Ivanov 2025-05-04 17:45:19 +03:00 committed by Vinod Koul
parent 59cf754607
commit e4c9a7b475

View File

@ -26,6 +26,7 @@ properties:
compatible:
enum:
- google,gs101-usb31drd-phy
- samsung,exynos2200-usb32drd-phy
- samsung,exynos5250-usbdrd-phy
- samsung,exynos5420-usbdrd-phy
- samsung,exynos5433-usbdrd-phy
@ -34,24 +35,32 @@ properties:
- samsung,exynos850-usbdrd-phy
clocks:
minItems: 2
minItems: 1
maxItems: 5
clock-names:
minItems: 2
minItems: 1
maxItems: 5
description: |
At least two clocks::
Typically two clocks:
- Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
for register access.
- PHY reference clock (usually crystal clock), used for PHY operations,
associated by phy name. It is used to determine bit values for clock
settings register. For Exynos5420 this is given as 'sclk_usbphy30'
in the CMU.
in the CMU. It's not needed for Exynos2200.
"#phy-cells":
const: 1
phys:
maxItems: 1
description:
USBDRD-underlying high-speed PHY
phy-names:
const: hs
port:
$ref: /schemas/graph.yaml#/properties/port
description:
@ -151,6 +160,27 @@ allOf:
- vdda-usbdp-supply
- vddh-usbdp-supply
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos2200-usb32drd-phy
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: phy
reg:
maxItems: 1
reg-names:
maxItems: 1
required:
- phys
- phy-names
- if:
properties:
compatible: