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Merge branch 'qed-new-fw'

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Prabhakar Kushwaha says:

====================
qed: new firmware version 8.59.1.0 support

This series integrate new firmware version 8.59.1.0, along with updated
HSI (hardware software interface) to use the FW, into the family of
qed drivers (fastlinq devices). This FW does not reside in the NVRAM.
It needs to be programmed to device during driver load as the part of
initialization sequence.

Similar to previous FW support series, this FW is tightly linked to
software and pf function driver. This means FW release is not backward
compatible, and driver should always run with the FW it was designed
against.

FW binary blob is already submitted & accepted in linux-firmware repo.

Patches in the series include:
patch 1     - qed: Fix kernel-doc warnings
patch 2     - qed: Remove e4_ and _e4 from FW HSI
patch 3     - qed: split huge qed_hsi.h header file
patch 4-8   - HSI (hardware software interface) changes
patch 9     - qed: Add '_GTT' suffix to the IRO RAM macros
patch 10    - qed: Update debug related changes
patch 11    - qed: rdma: Update TCP silly-window-syndrome timeout
patch 12    - qed: Update the TCP active termination 2  MSL timer
patch 13    - qed: fix ll2 establishment during load of RDMA driver

In addition, this patch series also fixes existing checkpatch warnings
and checks which are missing.

Changes for v2:
 - Incorporated Jakub's comments.
   - New patch introduced to fix all kernel-doc issue in qed driver.
   - Fixed warning: ‘qed_mfw_ext_20g’ defined but not used.
   - Fixed warning related to kernel-doc wrt to this series.
   - Removed inline function declaration.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2021-10-04 12:55:49 +01:00
commit e4addd4ed9
66 changed files with 13415 additions and 10283 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/infiniband/hw/qedr/main.c
View File

@ -272,7 +272,7 @@ static int qedr_register_device(struct qedr_dev *dev)
static int qedr_alloc_mem_sb(struct qedr_dev *dev,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
int rc;

44
drivers/net/ethernet/qlogic/qed/qed.h
View File

@ -23,6 +23,8 @@
#include <linux/qed/qed_if.h>
#include "qed_debug.h"
#include "qed_hsi.h"
#include "qed_dbg_hsi.h"
#include "qed_mfw_hsi.h"
extern const struct qed_common_ops qed_common_ops_pass;
@ -89,14 +91,14 @@ static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
}
#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
((sizeof(type_name) + (u32)(1 << ((p_hwfn)->cdev->cache_shift)) - 1) & \
~((1 << (p_hwfn->cdev->cache_shift)) - 1))
#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
#define for_each_hwfn(cdev, i) for (i = 0; i < (cdev)->num_hwfns; i++)
#define D_TRINE(val, cond1, cond2, true1, true2, def) \
(val == (cond1) ? true1 : \
(val == (cond2) ? true2 : def))
((val) == (cond1) ? true1 : \
((val) == (cond2) ? true2 : def))
/* forward */
struct qed_ptt_pool;
@ -510,7 +512,7 @@ enum qed_hsi_def_type {
struct qed_simd_fp_handler {
void *token;
void (*func)(void *);
void (*func)(void *cookie);
};
enum qed_slowpath_wq_flag {
@ -703,8 +705,6 @@ struct qed_dev {
#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))
#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
#define QED_IS_K2(dev) QED_IS_AH(dev)
#define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev))
#define QED_IS_E5(dev) ((dev)->type == QED_DEV_TYPE_E5)
u16 vendor_id;
@ -875,14 +875,14 @@ u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
#define NUM_OF_BTB_BLOCKS(dev) \
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
/**
* @brief qed_concrete_to_sw_fid - get the sw function id from
* the concrete value.
* qed_concrete_to_sw_fid(): Get the sw function id from
* the concrete value.
*
* @param concrete_fid
* @cdev: Qed dev pointer.
* @concrete_fid: Concrete fid.
*
* @return inline u8
* Return: inline u8.
*/
static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
u32 concrete_fid)
@ -902,7 +902,6 @@ static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
}
#define PKT_LB_TC 9
#define MAX_NUM_VOQS_E4 20
int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
@ -914,7 +913,7 @@ int qed_device_num_engines(struct qed_dev *cdev);
void qed_set_fw_mac_addr(__le16 *fw_msb,
__le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
#define QED_LEADING_HWFN(dev) (&(dev)->hwfns[0])
#define QED_IS_CMT(dev) ((dev)->num_hwfns > 1)
/* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */
#define QED_FIR_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->fir_affin])
@ -935,7 +934,7 @@ void qed_set_fw_mac_addr(__le16 *fw_msb,
#define PQ_FLAGS_LLT (BIT(7))
#define PQ_FLAGS_MTC (BIT(8))
/* physical queue index for cm context intialization */
/* physical queue index for cm context initialization */
u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
@ -947,12 +946,18 @@ void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
#define GET_GTT_REG_ADDR(__base, __offset, __idx) \
((__base) + __offset ## _GTT_OFFSET((__idx)))
#define GET_GTT_BDQ_REG_ADDR(__base, __offset, __idx, __bdq_idx) \
((__base) + __offset ## _GTT_OFFSET((__idx), (__bdq_idx)))
/* Other Linux specific common definitions */
#define DP_NAME(cdev) ((cdev)->name)
#define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
(cdev->regview) + \
(offset))
#define REG_ADDR(cdev, offset) ((void __iomem *)((u8 __iomem *)\
((cdev)->regview) + \
(offset)))
#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
@ -960,7 +965,7 @@ bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
#define DOORBELL(cdev, db_addr, val) \
writel((u32)val, (void __iomem *)((u8 __iomem *)\
(cdev->doorbells) + (db_addr)))
((cdev)->doorbells) + (db_addr)))
#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
qed_device_num_ports((_p_hwfn)->cdev))
@ -998,4 +1003,5 @@ int qed_llh_add_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port);
void qed_llh_remove_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
void qed_llh_remove_dst_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
void qed_llh_clear_all_filters(struct qed_dev *cdev);
unsigned long qed_get_epoch_time(void);
#endif /* _QED_H */

16
drivers/net/ethernet/qlogic/qed/qed_cxt.c
View File

@ -54,22 +54,22 @@
/* connection context union */
union conn_context {
struct e4_core_conn_context core_ctx;
struct e4_eth_conn_context eth_ctx;
struct e4_iscsi_conn_context iscsi_ctx;
struct e4_fcoe_conn_context fcoe_ctx;
struct e4_roce_conn_context roce_ctx;
struct core_conn_context core_ctx;
struct eth_conn_context eth_ctx;
struct iscsi_conn_context iscsi_ctx;
struct fcoe_conn_context fcoe_ctx;
struct roce_conn_context roce_ctx;
};
/* TYPE-0 task context - iSCSI, FCOE */
union type0_task_context {
struct e4_iscsi_task_context iscsi_ctx;
struct e4_fcoe_task_context fcoe_ctx;
struct iscsi_task_context iscsi_ctx;
struct fcoe_task_context fcoe_ctx;
};
/* TYPE-1 task context - ROCE */
union type1_task_context {
struct e4_rdma_task_context roce_ctx;
struct rdma_task_context roce_ctx;
};
struct src_ent {

143
drivers/net/ethernet/qlogic/qed/qed_cxt.h
View File

@ -28,24 +28,23 @@ struct qed_tid_mem {
};
/**
* @brief qedo_cid_get_cxt_info - Returns the context info for a specific cid
* qed_cxt_get_cid_info(): Returns the context info for a specific cidi.
*
* @p_hwfn: HW device data.
* @p_info: In/out.
*
* @param p_hwfn
* @param p_info in/out
*
* @return int
* Return: Int.
*/
int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn,
struct qed_cxt_info *p_info);
/**
* @brief qed_cxt_get_tid_mem_info
* qed_cxt_get_tid_mem_info(): Returns the tid mem info.
*
* @param p_hwfn
* @param p_info
* @p_hwfn: HW device data.
* @p_info: in/out.
*
* @return int
* Return: int.
*/
int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn,
struct qed_tid_mem *p_info);
@ -64,142 +63,155 @@ u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,
enum protocol_type type, u32 *vf_cid);
/**
* @brief qed_cxt_set_pf_params - Set the PF params for cxt init
* qed_cxt_set_pf_params(): Set the PF params for cxt init.
*
* @param p_hwfn
* @param rdma_tasks - requested maximum
* @return int
* @p_hwfn: HW device data.
* @rdma_tasks: Requested maximum.
*
* Return: int.
*/
int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn, u32 rdma_tasks);
/**
* @brief qed_cxt_cfg_ilt_compute - compute ILT init parameters
* qed_cxt_cfg_ilt_compute(): Compute ILT init parameters.
*
* @param p_hwfn
* @param last_line
* @p_hwfn: HW device data.
* @last_line: Last_line.
*
* @return int
* Return: Int
*/
int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *last_line);
/**
* @brief qed_cxt_cfg_ilt_compute_excess - how many lines can be decreased
* qed_cxt_cfg_ilt_compute_excess(): How many lines can be decreased.
*
* @param p_hwfn
* @param used_lines
* @p_hwfn: HW device data.
* @used_lines: Used lines.
*
* Return: Int.
*/
u32 qed_cxt_cfg_ilt_compute_excess(struct qed_hwfn *p_hwfn, u32 used_lines);
/**
* @brief qed_cxt_mngr_alloc - Allocate and init the context manager struct
* qed_cxt_mngr_alloc(): Allocate and init the context manager struct.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_cxt_mngr_free
* qed_cxt_mngr_free() - Context manager free.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn);
/**
* @brief qed_cxt_tables_alloc - Allocate ILT shadow, Searcher T2, acquired map
* qed_cxt_tables_alloc(): Allocate ILT shadow, Searcher T2, acquired map.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_cxt_mngr_setup - Reset the acquired CIDs
* qed_cxt_mngr_setup(): Reset the acquired CIDs.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*/
void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn);
/**
* @brief qed_cxt_hw_init_common - Initailze ILT and DQ, common phase, per path.
* qed_cxt_hw_init_common(): Initailze ILT and DQ, common phase, per path.
*
* @p_hwfn: HW device data.
*
*
* @param p_hwfn
* Return: Void.
*/
void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn);
/**
* @brief qed_cxt_hw_init_pf - Initailze ILT and DQ, PF phase, per path.
* qed_cxt_hw_init_pf(): Initailze ILT and DQ, PF phase, per path.
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* Return: Void.
*/
void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
/**
* @brief qed_qm_init_pf - Initailze the QM PF phase, per path
* qed_qm_init_pf(): Initailze the QM PF phase, per path.
*
* @param p_hwfn
* @param p_ptt
* @param is_pf_loading
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @is_pf_loading: Is pf pending.
*
* Return: Void.
*/
void qed_qm_init_pf(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, bool is_pf_loading);
/**
* @brief Reconfigures QM pf on the fly
* qed_qm_reconf(): Reconfigures QM pf on the fly.
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* @return int
* Return: Int.
*/
int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
#define QED_CXT_PF_CID (0xff)
/**
* @brief qed_cxt_release - Release a cid
* qed_cxt_release_cid(): Release a cid.
*
* @param p_hwfn
* @param cid
* @p_hwfn: HW device data.
* @cid: Cid.
*
* Return: Void.
*/
void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid);
/**
* @brief qed_cxt_release - Release a cid belonging to a vf-queue
* _qed_cxt_release_cid(): Release a cid belonging to a vf-queue.
*
* @param p_hwfn
* @param cid
* @param vfid - engine relative index. QED_CXT_PF_CID if belongs to PF
* @p_hwfn: HW device data.
* @cid: Cid.
* @vfid: Engine relative index. QED_CXT_PF_CID if belongs to PF.
*
* Return: Void.
*/
void _qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid, u8 vfid);
/**
* @brief qed_cxt_acquire - Acquire a new cid of a specific protocol type
* qed_cxt_acquire_cid(): Acquire a new cid of a specific protocol type.
*
* @param p_hwfn
* @param type
* @param p_cid
* @p_hwfn: HW device data.
* @type: Type.
* @p_cid: Pointer cid.
*
* @return int
* Return: Int.
*/
int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
enum protocol_type type, u32 *p_cid);
/**
* @brief _qed_cxt_acquire - Acquire a new cid of a specific protocol type
* for a vf-queue
* _qed_cxt_acquire_cid(): Acquire a new cid of a specific protocol type
* for a vf-queue.
*
* @param p_hwfn
* @param type
* @param p_cid
* @param vfid - engine relative index. QED_CXT_PF_CID if belongs to PF
* @p_hwfn: HW device data.
* @type: Type.
* @p_cid: Pointer cid.
* @vfid: Engine relative index. QED_CXT_PF_CID if belongs to PF.
*
* @return int
* Return: Int.
*/
int _qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn,
enum protocol_type type, u32 *p_cid, u8 vfid);
@ -334,7 +346,10 @@ struct qed_cxt_mngr {
/* Maximal number of L2 steering filters */
u32 arfs_count;
u8 task_type_id;
u16 iscsi_task_pages;
u16 fcoe_task_pages;
u16 roce_task_pages;
u16 eth_task_pages;
u16 task_ctx_size;
u16 conn_ctx_size;
};

1491
drivers/net/ethernet/qlogic/qed/qed_dbg_hsi.h Normal file
View File

File diff suppressed because it is too large Load Diff

11
drivers/net/ethernet/qlogic/qed/qed_dcbx.h
View File

@ -84,16 +84,17 @@ struct qed_dcbx_mib_meta_data {
extern const struct qed_eth_dcbnl_ops qed_dcbnl_ops_pass;
#ifdef CONFIG_DCB
int qed_dcbx_get_config_params(struct qed_hwfn *, struct qed_dcbx_set *);
int qed_dcbx_get_config_params(struct qed_hwfn *p_hwfn,
struct qed_dcbx_set *params);
int qed_dcbx_config_params(struct qed_hwfn *,
struct qed_ptt *, struct qed_dcbx_set *, bool);
int qed_dcbx_config_params(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
struct qed_dcbx_set *params, bool hw_commit);
#endif
/* QED local interface routines */
int
qed_dcbx_mib_update_event(struct qed_hwfn *,
struct qed_ptt *, enum qed_mib_read_type);
qed_dcbx_mib_update_event(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
enum qed_mib_read_type type);
int qed_dcbx_info_alloc(struct qed_hwfn *p_hwfn);
void qed_dcbx_info_free(struct qed_hwfn *p_hwfn);

1396
drivers/net/ethernet/qlogic/qed/qed_debug.c
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File diff suppressed because it is too large Load Diff

7
drivers/net/ethernet/qlogic/qed/qed_debug.h
View File

@ -1,11 +1,11 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/* QLogic qed NIC Driver
* Copyright (c) 2015 QLogic Corporation
* Copyright (c) 2019-2020 Marvell International Ltd.
* Copyright (c) 2019-2021 Marvell International Ltd.
*/
#ifndef _QED_DEBUGFS_H
#define _QED_DEBUGFS_H
#ifndef _QED_DEBUG_H
#define _QED_DEBUG_H
enum qed_dbg_features {
DBG_FEATURE_GRC,
@ -45,6 +45,7 @@ int qed_dbg_ilt_size(struct qed_dev *cdev);
int qed_dbg_mcp_trace(struct qed_dev *cdev, void *buffer,
u32 *num_dumped_bytes);
int qed_dbg_mcp_trace_size(struct qed_dev *cdev);
int qed_dbg_phy_size(struct qed_dev *cdev);
int qed_dbg_all_data(struct qed_dev *cdev, void *buffer);
int qed_dbg_all_data_size(struct qed_dev *cdev);
u8 qed_get_debug_engine(struct qed_dev *cdev);

122
drivers/net/ethernet/qlogic/qed/qed_dev.c
View File

@ -25,6 +25,7 @@
#include "qed_dev_api.h"
#include "qed_fcoe.h"
#include "qed_hsi.h"
#include "qed_iro_hsi.h"
#include "qed_hw.h"
#include "qed_init_ops.h"
#include "qed_int.h"
@ -1396,12 +1397,13 @@ void qed_resc_free(struct qed_dev *cdev)
qed_rdma_info_free(p_hwfn);
}
qed_spq_unregister_async_cb(p_hwfn, PROTOCOLID_COMMON);
qed_iov_free(p_hwfn);
qed_l2_free(p_hwfn);
qed_dmae_info_free(p_hwfn);
qed_dcbx_info_free(p_hwfn);
qed_dbg_user_data_free(p_hwfn);
qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
qed_fw_overlay_mem_free(p_hwfn, &p_hwfn->fw_overlay_mem);
/* Destroy doorbell recovery mechanism */
qed_db_recovery_teardown(p_hwfn);
@ -1483,8 +1485,8 @@ static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
/* num RLs can't exceed resource amount of rls or vports */
num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
RESC_NUM(p_hwfn, QED_VPORT));
num_pf_rls = (u16)min_t(u32, RESC_NUM(p_hwfn, QED_RL),
RESC_NUM(p_hwfn, QED_VPORT));
/* Make sure after we reserve there's something left */
if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
@ -1532,8 +1534,8 @@ static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
bool four_port;
/* pq and vport bases for this PF */
qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);
qm_info->start_vport = (u8)RESC_START(p_hwfn, QED_VPORT);
/* rate limiting and weighted fair queueing are always enabled */
qm_info->vport_rl_en = true;
@ -1628,9 +1630,9 @@ static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
*/
/* flags for pq init */
#define PQ_INIT_SHARE_VPORT (1 << 0)
#define PQ_INIT_PF_RL (1 << 1)
#define PQ_INIT_VF_RL (1 << 2)
#define PQ_INIT_SHARE_VPORT BIT(0)
#define PQ_INIT_PF_RL BIT(1)
#define PQ_INIT_VF_RL BIT(2)
/* defines for pq init */
#define PQ_INIT_DEFAULT_WRR_GROUP 1
@ -2290,7 +2292,7 @@ int qed_resc_alloc(struct qed_dev *cdev)
goto alloc_no_mem;
}
rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
rc = qed_eq_alloc(p_hwfn, (u16)n_eqes);
if (rc)
goto alloc_err;
@ -2375,6 +2377,49 @@ int qed_resc_alloc(struct qed_dev *cdev)
return rc;
}
static int qed_fw_err_handler(struct qed_hwfn *p_hwfn,
u8 opcode,
u16 echo,
union event_ring_data *data, u8 fw_return_code)
{
if (fw_return_code != COMMON_ERR_CODE_ERROR)
goto eqe_unexpected;
if (data->err_data.recovery_scope == ERR_SCOPE_FUNC &&
le16_to_cpu(data->err_data.entity_id) >= MAX_NUM_PFS) {
qed_sriov_vfpf_malicious(p_hwfn, &data->err_data);
return 0;
}
eqe_unexpected:
DP_ERR(p_hwfn,
"Skipping unexpected eqe 0x%02x, FW return code 0x%x, echo 0x%x\n",
opcode, fw_return_code, echo);
return -EINVAL;
}
static int qed_common_eqe_event(struct qed_hwfn *p_hwfn,
u8 opcode,
__le16 echo,
union event_ring_data *data,
u8 fw_return_code)
{
switch (opcode) {
case COMMON_EVENT_VF_PF_CHANNEL:
case COMMON_EVENT_VF_FLR:
return qed_sriov_eqe_event(p_hwfn, opcode, echo, data,
fw_return_code);
case COMMON_EVENT_FW_ERROR:
return qed_fw_err_handler(p_hwfn, opcode,
le16_to_cpu(echo), data,
fw_return_code);
default:
DP_INFO(p_hwfn->cdev, "Unknown eqe event 0x%02x, echo 0x%x\n",
opcode, echo);
return -EINVAL;
}
}
void qed_resc_setup(struct qed_dev *cdev)
{
int i;
@ -2403,6 +2448,8 @@ void qed_resc_setup(struct qed_dev *cdev)
qed_l2_setup(p_hwfn);
qed_iov_setup(p_hwfn);
qed_spq_register_async_cb(p_hwfn, PROTOCOLID_COMMON,
qed_common_eqe_event);
#ifdef CONFIG_QED_LL2
if (p_hwfn->using_ll2)
qed_ll2_setup(p_hwfn);
@ -2430,9 +2477,8 @@ int qed_final_cleanup(struct qed_hwfn *p_hwfn,
u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
int rc = -EBUSY;
addr = GTT_BAR0_MAP_REG_USDM_RAM +
USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
addr = GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_USDM_RAM,
USTORM_FLR_FINAL_ACK, p_hwfn->rel_pf_id);
if (is_vf)
id += 0x10;
@ -2592,7 +2638,7 @@ static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
cache_line_size);
}
if (L1_CACHE_BYTES > wr_mbs)
if (wr_mbs < L1_CACHE_BYTES)
DP_INFO(p_hwfn,
"The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
L1_CACHE_BYTES, wr_mbs);
@ -2608,13 +2654,21 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, int hw_mode)
{
struct qed_qm_info *qm_info = &p_hwfn->qm_info;
struct qed_qm_common_rt_init_params params;
struct qed_qm_common_rt_init_params *params;
struct qed_dev *cdev = p_hwfn->cdev;
u8 vf_id, max_num_vfs;
u16 num_pfs, pf_id;
u32 concrete_fid;
int rc = 0;
params = kzalloc(sizeof(*params), GFP_KERNEL);
if (!params) {
DP_NOTICE(p_hwfn->cdev,
"Failed to allocate common init params\n");
return -ENOMEM;
}
qed_init_cau_rt_data(cdev);
/* Program GTT windows */
@ -2627,16 +2681,15 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
qm_info->pf_wfq_en = true;
}
memset(&params, 0, sizeof(params));
params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
params.pf_rl_en = qm_info->pf_rl_en;
params.pf_wfq_en = qm_info->pf_wfq_en;
params.global_rl_en = qm_info->vport_rl_en;
params.vport_wfq_en = qm_info->vport_wfq_en;
params.port_params = qm_info->qm_port_params;
params->max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
params->max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
params->pf_rl_en = qm_info->pf_rl_en;
params->pf_wfq_en = qm_info->pf_wfq_en;
params->global_rl_en = qm_info->vport_rl_en;
params->vport_wfq_en = qm_info->vport_wfq_en;
params->port_params = qm_info->qm_port_params;
qed_qm_common_rt_init(p_hwfn, &params);
qed_qm_common_rt_init(p_hwfn, params);
qed_cxt_hw_init_common(p_hwfn);
@ -2644,7 +2697,7 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
if (rc)
return rc;
goto out;
qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
@ -2663,7 +2716,7 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)concrete_fid);
qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
@ -2672,6 +2725,9 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
/* pretend to original PF */
qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
out:
kfree(params);
return rc;
}
@ -2784,7 +2840,7 @@ qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
qed_rdma_dpm_bar(p_hwfn, p_ptt);
}
p_hwfn->wid_count = (u16) n_cpus;
p_hwfn->wid_count = (u16)n_cpus;
DP_INFO(p_hwfn,
"doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n",
@ -3503,8 +3559,8 @@ static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
static void get_function_id(struct qed_hwfn *p_hwfn)
{
/* ME Register */
p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
PXP_PF_ME_OPAQUE_ADDR);
p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn,
PXP_PF_ME_OPAQUE_ADDR);
p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
@ -3670,12 +3726,14 @@ u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type)
return qed_hsi_def_val[type][chip_id];
}
static int
qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
u32 resc_max_val, mcp_resp;
u8 res_id;
int rc;
for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
switch (res_id) {
case QED_LL2_RAM_QUEUE:
@ -3921,7 +3979,7 @@ static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
* resources allocation queries should be atomic. Since several PFs can
* run in parallel - a resource lock is needed.
* If either the resource lock or resource set value commands are not
* supported - skip the the max values setting, release the lock if
* supported - skip the max values setting, release the lock if
* needed, and proceed to the queries. Other failures, including a
* failure to acquire the lock, will cause this function to fail.
*/
@ -4775,7 +4833,7 @@ int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
u16 min, max;
min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
min = (u16)RESC_START(p_hwfn, QED_L2_QUEUE);
max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
DP_NOTICE(p_hwfn,
"l2_queue id [%d] is not valid, available indices [%d - %d]\n",
@ -4909,7 +4967,7 @@ int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
goto out;
address = BAR0_MAP_REG_USDM_RAM +
USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
USTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id);
rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
sizeof(struct ustorm_eth_queue_zone), timeset);
@ -4948,7 +5006,7 @@ int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
goto out;
address = BAR0_MAP_REG_XSDM_RAM +
XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
XSTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id);
rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
sizeof(struct xstorm_eth_queue_zone), timeset);

347
drivers/net/ethernet/qlogic/qed/qed_dev_api.h
View File

@ -15,44 +15,52 @@
#include "qed_int.h"
/**
* @brief qed_init_dp - initialize the debug level
* qed_init_dp(): Initialize the debug level.
*
* @param cdev
* @param dp_module
* @param dp_level
* @cdev: Qed dev pointer.
* @dp_module: Module debug parameter.
* @dp_level: Module debug level.
*
* Return: Void.
*/
void qed_init_dp(struct qed_dev *cdev,
u32 dp_module,
u8 dp_level);
/**
* @brief qed_init_struct - initialize the device structure to
* its defaults
* qed_init_struct(): Initialize the device structure to
* its defaults.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* Return: Void.
*/
void qed_init_struct(struct qed_dev *cdev);
/**
* @brief qed_resc_free -
* qed_resc_free: Free device resources.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* Return: Void.
*/
void qed_resc_free(struct qed_dev *cdev);
/**
* @brief qed_resc_alloc -
* qed_resc_alloc(): Alloc device resources.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return int
* Return: Int.
*/
int qed_resc_alloc(struct qed_dev *cdev);
/**
* @brief qed_resc_setup -
* qed_resc_setup(): Setup device resources.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* Return: Void.
*/
void qed_resc_setup(struct qed_dev *cdev);
@ -105,94 +113,96 @@ struct qed_hw_init_params {
};
/**
* @brief qed_hw_init -
* qed_hw_init(): Init Qed hardware.
*
* @param cdev
* @param p_params
* @cdev: Qed dev pointer.
* @p_params: Pointers to params.
*
* @return int
* Return: Int.
*/
int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params);
/**
* @brief qed_hw_timers_stop_all - stop the timers HW block
* qed_hw_timers_stop_all(): Stop the timers HW block.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return void
* Return: void.
*/
void qed_hw_timers_stop_all(struct qed_dev *cdev);
/**
* @brief qed_hw_stop -
* qed_hw_stop(): Stop Qed hardware.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return int
* Return: int.
*/
int qed_hw_stop(struct qed_dev *cdev);
/**
* @brief qed_hw_stop_fastpath -should be called incase
* slowpath is still required for the device,
* but fastpath is not.
* qed_hw_stop_fastpath(): Should be called incase
* slowpath is still required for the device,
* but fastpath is not.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return int
* Return: Int.
*/
int qed_hw_stop_fastpath(struct qed_dev *cdev);
/**
* @brief qed_hw_start_fastpath -restart fastpath traffic,
* only if hw_stop_fastpath was called
* qed_hw_start_fastpath(): Restart fastpath traffic,
* only if hw_stop_fastpath was called.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn);
/**
* @brief qed_hw_prepare -
* qed_hw_prepare(): Prepare Qed hardware.
*
* @param cdev
* @param personality - personality to initialize
* @cdev: Qed dev pointer.
* @personality: Personality to initialize.
*
* @return int
* Return: Int.
*/
int qed_hw_prepare(struct qed_dev *cdev,
int personality);
/**
* @brief qed_hw_remove -
* qed_hw_remove(): Remove Qed hardware.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* Return: Void.
*/
void qed_hw_remove(struct qed_dev *cdev);
/**
* @brief qed_ptt_acquire - Allocate a PTT window
* qed_ptt_acquire(): Allocate a PTT window.
*
* @p_hwfn: HW device data.
*
* Return: struct qed_ptt.
*
* Should be called at the entry point to the driver (at the beginning of an
* exported function)
*
* @param p_hwfn
*
* @return struct qed_ptt
* exported function).
*/
struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn);
/**
* @brief qed_ptt_release - Release PTT Window
* qed_ptt_release(): Release PTT Window.
*
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* Return: Void.
*
* Should be called at the end of a flow - at the end of the function that
* acquired the PTT.
*
*
* @param p_hwfn
* @param p_ptt
*/
void qed_ptt_release(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
@ -205,15 +215,17 @@ enum qed_dmae_address_type_t {
};
/**
* @brief qed_dmae_host2grc - copy data from source addr to
* dmae registers using the given ptt
* qed_dmae_host2grc(): Copy data from source addr to
* dmae registers using the given ptt.
*
* @param p_hwfn
* @param p_ptt
* @param source_addr
* @param grc_addr (dmae_data_offset)
* @param size_in_dwords
* @param p_params (default parameters will be used in case of NULL)
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @source_addr: Source address.
* @grc_addr: GRC address (dmae_data_offset).
* @size_in_dwords: Size.
* @p_params: (default parameters will be used in case of NULL).
*
* Return: Int.
*/
int
qed_dmae_host2grc(struct qed_hwfn *p_hwfn,
@ -224,29 +236,34 @@ qed_dmae_host2grc(struct qed_hwfn *p_hwfn,
struct qed_dmae_params *p_params);
/**
* @brief qed_dmae_grc2host - Read data from dmae data offset
* to source address using the given ptt
* qed_dmae_grc2host(): Read data from dmae data offset
* to source address using the given ptt.
*
* @param p_ptt
* @param grc_addr (dmae_data_offset)
* @param dest_addr
* @param size_in_dwords
* @param p_params (default parameters will be used in case of NULL)
* @p_ptt: P_ptt.
* @grc_addr: GRC address (dmae_data_offset).
* @dest_addr: Destination Address.
* @size_in_dwords: Size.
* @p_params: (default parameters will be used in case of NULL).
*
* Return: Int.
*/
int qed_dmae_grc2host(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u32 grc_addr, dma_addr_t dest_addr, u32 size_in_dwords,
struct qed_dmae_params *p_params);
/**
* @brief qed_dmae_host2host - copy data from to source address
* to a destination adress (for SRIOV) using the given ptt
* qed_dmae_host2host(): Copy data from to source address
* to a destination adrress (for SRIOV) using the given
* ptt.
*
* @param p_hwfn
* @param p_ptt
* @param source_addr
* @param dest_addr
* @param size_in_dwords
* @param p_params (default parameters will be used in case of NULL)
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @source_addr: Source address.
* @dest_addr: Destination address.
* @size_in_dwords: size.
* @p_params: (default parameters will be used in case of NULL).
*
* Return: Int.
*/
int qed_dmae_host2host(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@ -259,51 +276,51 @@ int qed_chain_alloc(struct qed_dev *cdev, struct qed_chain *chain,
void qed_chain_free(struct qed_dev *cdev, struct qed_chain *chain);
/**
* @@brief qed_fw_l2_queue - Get absolute L2 queue ID
* qed_fw_l2_queue(): Get absolute L2 queue ID.
*
* @param p_hwfn
* @param src_id - relative to p_hwfn
* @param dst_id - absolute per engine
* @p_hwfn: HW device data.
* @src_id: Relative to p_hwfn.
* @dst_id: Absolute per engine.
*
* @return int
* Return: Int.
*/
int qed_fw_l2_queue(struct qed_hwfn *p_hwfn,
u16 src_id,
u16 *dst_id);
/**
* @@brief qed_fw_vport - Get absolute vport ID
* qed_fw_vport(): Get absolute vport ID.
*
* @param p_hwfn
* @param src_id - relative to p_hwfn
* @param dst_id - absolute per engine
* @p_hwfn: HW device data.
* @src_id: Relative to p_hwfn.
* @dst_id: Absolute per engine.
*
* @return int
* Return: Int.
*/
int qed_fw_vport(struct qed_hwfn *p_hwfn,
u8 src_id,
u8 *dst_id);
/**
* @@brief qed_fw_rss_eng - Get absolute RSS engine ID
* qed_fw_rss_eng(): Get absolute RSS engine ID.
*
* @param p_hwfn
* @param src_id - relative to p_hwfn
* @param dst_id - absolute per engine
* @p_hwfn: HW device data.
* @src_id: Relative to p_hwfn.
* @dst_id: Absolute per engine.
*
* @return int
* Return: Int.
*/
int qed_fw_rss_eng(struct qed_hwfn *p_hwfn,
u8 src_id,
u8 *dst_id);
/**
* @brief qed_llh_get_num_ppfid - Return the allocated number of LLH filter
* banks that are allocated to the PF.
* qed_llh_get_num_ppfid(): Return the allocated number of LLH filter
* banks that are allocated to the PF.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return u8 - Number of LLH filter banks
* Return: u8 Number of LLH filter banks.
*/
u8 qed_llh_get_num_ppfid(struct qed_dev *cdev);
@ -314,45 +331,50 @@ enum qed_eng {
};
/**
* @brief qed_llh_set_ppfid_affinity - Set the engine affinity for the given
* LLH filter bank.
* qed_llh_set_ppfid_affinity(): Set the engine affinity for the given
* LLH filter bank.
*
* @param cdev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param eng
* @cdev: Qed dev pointer.
* @ppfid: Relative within the allocated ppfids ('0' is the default one).
* @eng: Engine.
*
* @return int
* Return: Int.
*/
int qed_llh_set_ppfid_affinity(struct qed_dev *cdev,
u8 ppfid, enum qed_eng eng);
/**
* @brief qed_llh_set_roce_affinity - Set the RoCE engine affinity
* qed_llh_set_roce_affinity(): Set the RoCE engine affinity.
*
* @param cdev
* @param eng
* @cdev: Qed dev pointer.
* @eng: Engine.
*
* @return int
* Return: Int.
*/
int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng);
/**
* @brief qed_llh_add_mac_filter - Add a LLH MAC filter into the given filter
* bank.
* qed_llh_add_mac_filter(): Add a LLH MAC filter into the given filter
* bank.
*
* @param cdev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param mac_addr - MAC to add
* @cdev: Qed dev pointer.
* @ppfid: Relative within the allocated ppfids ('0' is the default one).
* @mac_addr: MAC to add.
*
* Return: Int.
*/
int qed_llh_add_mac_filter(struct qed_dev *cdev,
u8 ppfid, u8 mac_addr[ETH_ALEN]);
/**
* @brief qed_llh_remove_mac_filter - Remove a LLH MAC filter from the given
* filter bank.
* qed_llh_remove_mac_filter(): Remove a LLH MAC filter from the given
* filter bank.
*
* @param p_ptt
* @param p_filter - MAC to remove
* @cdev: Qed dev pointer.
* @ppfid: Ppfid.
* @mac_addr: MAC to remove
*
* Return: Void.
*/
void qed_llh_remove_mac_filter(struct qed_dev *cdev,
u8 ppfid, u8 mac_addr[ETH_ALEN]);
@ -368,15 +390,16 @@ enum qed_llh_prot_filter_type_t {
};
/**
* @brief qed_llh_add_protocol_filter - Add a LLH protocol filter into the
* given filter bank.
* qed_llh_add_protocol_filter(): Add a LLH protocol filter into the
* given filter bank.
*
* @param cdev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param type - type of filters and comparing
* @param source_port_or_eth_type - source port or ethertype to add
* @param dest_port - destination port to add
* @param type - type of filters and comparing
* @cdev: Qed dev pointer.
* @ppfid: Relative within the allocated ppfids ('0' is the default one).
* @type: Type of filters and comparing.
* @source_port_or_eth_type: Source port or ethertype to add.
* @dest_port: Destination port to add.
*
* Return: Int.
*/
int
qed_llh_add_protocol_filter(struct qed_dev *cdev,
@ -385,14 +408,14 @@ qed_llh_add_protocol_filter(struct qed_dev *cdev,
u16 source_port_or_eth_type, u16 dest_port);
/**
* @brief qed_llh_remove_protocol_filter - Remove a LLH protocol filter from
* the given filter bank.
* qed_llh_remove_protocol_filter(): Remove a LLH protocol filter from
* the given filter bank.
*
* @param cdev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param type - type of filters and comparing
* @param source_port_or_eth_type - source port or ethertype to add
* @param dest_port - destination port to add
* @cdev: Qed dev pointer.
* @ppfid: Relative within the allocated ppfids ('0' is the default one).
* @type: Type of filters and comparing.
* @source_port_or_eth_type: Source port or ethertype to add.
* @dest_port: Destination port to add.
*/
void
qed_llh_remove_protocol_filter(struct qed_dev *cdev,
@ -401,31 +424,31 @@ qed_llh_remove_protocol_filter(struct qed_dev *cdev,
u16 source_port_or_eth_type, u16 dest_port);
/**
* *@brief Cleanup of previous driver remains prior to load
* qed_final_cleanup(): Cleanup of previous driver remains prior to load.
*
* @param p_hwfn
* @param p_ptt
* @param id - For PF, engine-relative. For VF, PF-relative.
* @param is_vf - true iff cleanup is made for a VF.
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @id: For PF, engine-relative. For VF, PF-relative.
* @is_vf: True iff cleanup is made for a VF.
*
* @return int
* Return: Int.
*/
int qed_final_cleanup(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u16 id, bool is_vf);
/**
* @brief qed_get_queue_coalesce - Retrieve coalesce value for a given queue.
* qed_get_queue_coalesce(): Retrieve coalesce value for a given queue.
*
* @param p_hwfn
* @param p_coal - store coalesce value read from the hardware.
* @param p_handle
* @p_hwfn: HW device data.
* @coal: Store coalesce value read from the hardware.
* @handle: P_handle.
*
* @return int
* Return: Int.
**/
int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *coal, void *handle);
/**
* @brief qed_set_queue_coalesce - Configure coalesce parameters for Rx and
* qed_set_queue_coalesce(): Configure coalesce parameters for Rx and
* Tx queue. The fact that we can configure coalescing to up to 511, but on
* varying accuracy [the bigger the value the less accurate] up to a mistake
* of 3usec for the highest values.
@ -433,37 +456,38 @@ int qed_get_queue_coalesce(struct qed_hwfn *p_hwfn, u16 *coal, void *handle);
* should be in same range [i.e., either 0-0x7f, 0x80-0xff or 0x100-0x1ff]
* otherwise configuration would break.
*
* @rx_coal: Rx Coalesce value in micro seconds.
* @tx_coal: TX Coalesce value in micro seconds.
* @p_handle: P_handle.
*
* @param rx_coal - Rx Coalesce value in micro seconds.
* @param tx_coal - TX Coalesce value in micro seconds.
* @param p_handle
*
* @return int
* Return: Int.
**/
int
qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle);
/**
* @brief qed_pglueb_set_pfid_enable - Enable or disable PCI BUS MASTER
* qed_pglueb_set_pfid_enable(): Enable or disable PCI BUS MASTER.
*
* @param p_hwfn
* @param p_ptt
* @param b_enable - true/false
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @b_enable: True/False.
*
* @return int
* Return: Int.
*/
int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, bool b_enable);
/**
* @brief db_recovery_add - add doorbell information to the doorbell
* recovery mechanism.
* qed_db_recovery_add(): add doorbell information to the doorbell
* recovery mechanism.
*
* @param cdev
* @param db_addr - doorbell address
* @param db_data - address of where db_data is stored
* @param db_width - doorbell is 32b pr 64b
* @param db_space - doorbell recovery addresses are user or kernel space
* @cdev: Qed dev pointer.
* @db_addr: Doorbell address.
* @db_data: Address of where db_data is stored.
* @db_width: Doorbell is 32b pr 64b.
* @db_space: Doorbell recovery addresses are user or kernel space.
*
* Return: Int.
*/
int qed_db_recovery_add(struct qed_dev *cdev,
void __iomem *db_addr,
@ -472,17 +496,18 @@ int qed_db_recovery_add(struct qed_dev *cdev,
enum qed_db_rec_space db_space);
/**
* @brief db_recovery_del - remove doorbell information from the doorbell
* qed_db_recovery_del() - remove doorbell information from the doorbell
* recovery mechanism. db_data serves as key (db_addr is not unique).
*
* @param cdev
* @param db_addr - doorbell address
* @param db_data - address where db_data is stored. Serves as key for the
* @cdev: Qed dev pointer.
* @db_addr: doorbell address.
* @db_data: address where db_data is stored. Serves as key for the
* entry to delete.
*
* Return: Int.
*/
int qed_db_recovery_del(struct qed_dev *cdev,
void __iomem *db_addr, void *db_data);
const char *qed_hw_get_resc_name(enum qed_resources res_id);
#endif

25
drivers/net/ethernet/qlogic/qed/qed_fcoe.c
View File

@ -30,6 +30,7 @@
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_int.h"
#include "qed_iro_hsi.h"
#include "qed_ll2.h"
#include "qed_mcp.h"
#include "qed_reg_addr.h"
@ -89,7 +90,7 @@ qed_sp_fcoe_func_start(struct qed_hwfn *p_hwfn,
struct qed_fcoe_pf_params *fcoe_pf_params = NULL;
struct fcoe_init_ramrod_params *p_ramrod = NULL;
struct fcoe_init_func_ramrod_data *p_data;
struct e4_fcoe_conn_context *p_cxt = NULL;
struct fcoe_conn_context *p_cxt = NULL;
struct qed_spq_entry *p_ent = NULL;
struct qed_sp_init_data init_data;
struct qed_cxt_info cxt_info;
@ -144,7 +145,7 @@ qed_sp_fcoe_func_start(struct qed_hwfn *p_hwfn,
memset(p_cxt, 0, sizeof(*p_cxt));
SET_FIELD(p_cxt->tstorm_ag_context.flags3,
E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);
TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN, 1);
fcoe_pf_params->dummy_icid = (u16)dummy_cid;
@ -506,10 +507,9 @@ static void __iomem *qed_fcoe_get_primary_bdq_prod(struct qed_hwfn *p_hwfn,
{
if (RESC_NUM(p_hwfn, QED_BDQ)) {
return (u8 __iomem *)p_hwfn->regview +
GTT_BAR0_MAP_REG_MSDM_RAM +
MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(RESC_START(p_hwfn,
QED_BDQ),
bdq_id);
GET_GTT_BDQ_REG_ADDR(GTT_BAR0_MAP_REG_MSDM_RAM,
MSTORM_SCSI_BDQ_EXT_PROD,
RESC_START(p_hwfn, QED_BDQ), bdq_id);
} else {
DP_NOTICE(p_hwfn, "BDQ is not allocated!\n");
return NULL;
@ -521,10 +521,9 @@ static void __iomem *qed_fcoe_get_secondary_bdq_prod(struct qed_hwfn *p_hwfn,
{
if (RESC_NUM(p_hwfn, QED_BDQ)) {
return (u8 __iomem *)p_hwfn->regview +
GTT_BAR0_MAP_REG_TSDM_RAM +
TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(RESC_START(p_hwfn,
QED_BDQ),
bdq_id);
GET_GTT_BDQ_REG_ADDR(GTT_BAR0_MAP_REG_TSDM_RAM,
TSTORM_SCSI_BDQ_EXT_PROD,
RESC_START(p_hwfn, QED_BDQ), bdq_id);
} else {
DP_NOTICE(p_hwfn, "BDQ is not allocated!\n");
return NULL;
@ -549,7 +548,7 @@ int qed_fcoe_alloc(struct qed_hwfn *p_hwfn)
void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
{
struct e4_fcoe_task_context *p_task_ctx = NULL;
struct fcoe_task_context *p_task_ctx = NULL;
u32 i, lc;
int rc;
@ -561,7 +560,7 @@ void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
if (rc)
continue;
memset(p_task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(p_task_ctx, 0, sizeof(struct fcoe_task_context));
lc = 0;
SET_FIELD(lc, TIMERS_CONTEXT_VALIDLC0, 1);
@ -572,7 +571,7 @@ void qed_fcoe_setup(struct qed_hwfn *p_hwfn)
p_task_ctx->timer_context.logical_client_1 = cpu_to_le32(lc);
SET_FIELD(p_task_ctx->tstorm_ag_context.flags0,
E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE, 1);
}
}

12335
drivers/net/ethernet/qlogic/qed/qed_hsi.h
View File

File diff suppressed because it is too large Load Diff

214
drivers/net/ethernet/qlogic/qed/qed_hw.h
View File

@ -53,85 +53,94 @@ enum _dmae_cmd_crc_mask {
#define DMAE_MAX_CLIENTS 32
/**
* @brief qed_gtt_init - Initialize GTT windows
* qed_gtt_init(): Initialize GTT windows.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_gtt_init(struct qed_hwfn *p_hwfn);
/**
* @brief qed_ptt_invalidate - Forces all ptt entries to be re-configured
* qed_ptt_invalidate(): Forces all ptt entries to be re-configured
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_ptt_invalidate(struct qed_hwfn *p_hwfn);
/**
* @brief qed_ptt_pool_alloc - Allocate and initialize PTT pool
* qed_ptt_pool_alloc(): Allocate and initialize PTT pool.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return struct _qed_status - success (0), negative - error.
* Return: struct _qed_status - success (0), negative - error.
*/
int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_ptt_pool_free -
* qed_ptt_pool_free(): Free PTT pool.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_ptt_pool_free(struct qed_hwfn *p_hwfn);
/**
* @brief qed_ptt_get_hw_addr - Get PTT's GRC/HW address
* qed_ptt_get_hw_addr(): Get PTT's GRC/HW address.
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt
*
* @return u32
* Return: u32.
*/
u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
/**
* @brief qed_ptt_get_bar_addr - Get PPT's external BAR address
* qed_ptt_get_bar_addr(): Get PPT's external BAR address.
*
* @param p_hwfn
* @param p_ptt
* @p_ptt: P_ptt
*
* @return u32
* Return: u32.
*/
u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt);
/**
* @brief qed_ptt_set_win - Set PTT Window's GRC BAR address
* qed_ptt_set_win(): Set PTT Window's GRC BAR address
*
* @param p_hwfn
* @param new_hw_addr
* @param p_ptt
* @p_hwfn: HW device data.
* @new_hw_addr: New HW address.
* @p_ptt: P_Ptt
*
* Return: Void.
*/
void qed_ptt_set_win(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u32 new_hw_addr);
/**
* @brief qed_get_reserved_ptt - Get a specific reserved PTT
* qed_get_reserved_ptt(): Get a specific reserved PTT.
*
* @param p_hwfn
* @param ptt_idx
* @p_hwfn: HW device data.
* @ptt_idx: Ptt Index.
*
* @return struct qed_ptt *
* Return: struct qed_ptt *.
*/
struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn,
enum reserved_ptts ptt_idx);
/**
* @brief qed_wr - Write value to BAR using the given ptt
* qed_wr(): Write value to BAR using the given ptt.
*
* @param p_hwfn
* @param p_ptt
* @param val
* @param hw_addr
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @val: Val.
* @hw_addr: HW address
*
* Return: Void.
*/
void qed_wr(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@ -139,26 +148,28 @@ void qed_wr(struct qed_hwfn *p_hwfn,
u32 val);
/**
* @brief qed_rd - Read value from BAR using the given ptt
* qed_rd(): Read value from BAR using the given ptt.
*
* @param p_hwfn
* @param p_ptt
* @param val
* @param hw_addr
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @hw_addr: HW address
*
* Return: Void.
*/
u32 qed_rd(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u32 hw_addr);
/**
* @brief qed_memcpy_from - copy n bytes from BAR using the given
* ptt
* qed_memcpy_from(): Copy n bytes from BAR using the given ptt.
*
* @param p_hwfn
* @param p_ptt
* @param dest
* @param hw_addr
* @param n
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @dest: Destination.
* @hw_addr: HW address.
* @n: N
*
* Return: Void.
*/
void qed_memcpy_from(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@ -167,14 +178,15 @@ void qed_memcpy_from(struct qed_hwfn *p_hwfn,
size_t n);
/**
* @brief qed_memcpy_to - copy n bytes to BAR using the given
* ptt
* qed_memcpy_to(): Copy n bytes to BAR using the given ptt
*
* @param p_hwfn
* @param p_ptt
* @param hw_addr
* @param src
* @param n
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @hw_addr: HW address.
* @src: Source.
* @n: N
*
* Return: Void.
*/
void qed_memcpy_to(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@ -182,83 +194,97 @@ void qed_memcpy_to(struct qed_hwfn *p_hwfn,
void *src,
size_t n);
/**
* @brief qed_fid_pretend - pretend to another function when
* accessing the ptt window. There is no way to unpretend
* a function. The only way to cancel a pretend is to
* pretend back to the original function.
* qed_fid_pretend(): pretend to another function when
* accessing the ptt window. There is no way to unpretend
* a function. The only way to cancel a pretend is to
* pretend back to the original function.
*
* @param p_hwfn
* @param p_ptt
* @param fid - fid field of pxp_pretend structure. Can contain
* either pf / vf, port/path fields are don't care.
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @fid: fid field of pxp_pretend structure. Can contain
* either pf / vf, port/path fields are don't care.
*
* Return: Void.
*/
void qed_fid_pretend(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u16 fid);
/**
* @brief qed_port_pretend - pretend to another port when
* accessing the ptt window
* qed_port_pretend(): Pretend to another port when accessing the ptt window
*
* @param p_hwfn
* @param p_ptt
* @param port_id - the port to pretend to
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @port_id: The port to pretend to
*
* Return: Void.
*/
void qed_port_pretend(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u8 port_id);
/**
* @brief qed_port_unpretend - cancel any previously set port
* pretend
* qed_port_unpretend(): Cancel any previously set port pretend
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* Return: Void.
*/
void qed_port_unpretend(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
/**
* @brief qed_port_fid_pretend - pretend to another port and another function
* when accessing the ptt window
* qed_port_fid_pretend(): Pretend to another port and another function
* when accessing the ptt window
*
* @param p_hwfn
* @param p_ptt
* @param port_id - the port to pretend to
* @param fid - fid field of pxp_pretend structure. Can contain either pf / vf.
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @port_id: The port to pretend to
* @fid: fid field of pxp_pretend structure. Can contain either pf / vf.
*
* Return: Void.
*/
void qed_port_fid_pretend(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 port_id, u16 fid);
/**
* @brief qed_vfid_to_concrete - build a concrete FID for a
* given VF ID
* qed_vfid_to_concrete(): Build a concrete FID for a given VF ID
*
* @param p_hwfn
* @param p_ptt
* @param vfid
* @p_hwfn: HW device data.
* @vfid: VFID.
*
* Return: Void.
*/
u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid);
/**
* @brief qed_dmae_idx_to_go_cmd - map the idx to dmae cmd
* this is declared here since other files will require it.
* @param idx
* qed_dmae_idx_to_go_cmd(): Map the idx to dmae cmd
* this is declared here since other files will require it.
*
* @idx: Index
*
* Return: Void.
*/
u32 qed_dmae_idx_to_go_cmd(u8 idx);
/**
* @brief qed_dmae_info_alloc - Init the dmae_info structure
* which is part of p_hwfn.
* @param p_hwfn
* qed_dmae_info_alloc(): Init the dmae_info structure
* which is part of p_hwfn.
*
* @p_hwfn: HW device data.
*
* Return: Int.
*/
int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_dmae_info_free - Free the dmae_info structure
* which is part of p_hwfn
* qed_dmae_info_free(): Free the dmae_info structure
* which is part of p_hwfn.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_dmae_info_free(struct qed_hwfn *p_hwfn);
@ -292,14 +318,16 @@ int qed_dmae_sanity(struct qed_hwfn *p_hwfn,
#define QED_HW_ERR_MAX_STR_SIZE 256
/**
* @brief qed_hw_err_notify - Notify upper layer driver and management FW
* about a HW error.
* qed_hw_err_notify(): Notify upper layer driver and management FW
* about a HW error.
*
* @param p_hwfn
* @param p_ptt
* @param err_type
* @param fmt - debug data buffer to send to the MFW
* @param ... - buffer format args
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @err_type: Err Type.
* @fmt: Debug data buffer to send to the MFW
* @...: buffer format args
*
* Return void.
*/
void __printf(4, 5) __cold qed_hw_err_notify(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,

405
drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/* QLogic qed NIC Driver
* Copyright (c) 2015-2017 QLogic Corporation
* Copyright (c) 2019-2020 Marvell International Ltd.
* Copyright (c) 2019-2021 Marvell International Ltd.
*/
#include <linux/types.h>
@ -13,17 +13,18 @@
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_init_ops.h"
#include "qed_iro_hsi.h"
#include "qed_reg_addr.h"
#define CDU_VALIDATION_DEFAULT_CFG 61
#define CDU_VALIDATION_DEFAULT_CFG CDU_CONTEXT_VALIDATION_DEFAULT_CFG
static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES_E4] = {
static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES] = {
{400, 336, 352, 368, 304, 384, 416, 352}, /* region 3 offsets */
{528, 496, 416, 512, 448, 512, 544, 480}, /* region 4 offsets */
{608, 544, 496, 576, 576, 592, 624, 560} /* region 5 offsets */
};
static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES] = {
{240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
};
@ -42,25 +43,49 @@ static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
#define QM_BYPASS_EN 1
#define QM_BYTE_CRD_EN 1
/* Initial VOQ byte credit */
#define QM_INITIAL_VOQ_BYTE_CRD 98304
/* Other PQ constants */
#define QM_OTHER_PQS_PER_PF 4
/* VOQ constants */
#define MAX_NUM_VOQS (MAX_NUM_PORTS_K2 * NUM_TCS_4PORT_K2)
#define VOQS_BIT_MASK (BIT(MAX_NUM_VOQS) - 1)
/* WFQ constants */
/* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
#define QM_WFQ_UPPER_BOUND 62500000
/* PF WFQ increment value, 0x9000 = 4*9*1024 */
#define QM_PF_WFQ_INC_VAL(weight) ((weight) * 0x9000)
/* Bit of VOQ in WFQ VP PQ map */
#define QM_WFQ_VP_PQ_VOQ_SHIFT 0
/* PF WFQ Upper bound, in MB, 10 * burst size of 1ms in 50Gbps */
#define QM_PF_WFQ_UPPER_BOUND 62500000
/* Bit of PF in WFQ VP PQ map */
#define QM_WFQ_VP_PQ_PF_E4_SHIFT 5
/* PF WFQ max increment value, 0.7 * upper bound */
#define QM_PF_WFQ_MAX_INC_VAL ((QM_PF_WFQ_UPPER_BOUND * 7) / 10)
/* 0x9000 = 4*9*1024 */
#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
/* Number of VOQs in E5 PF WFQ credit register (QmWfqCrd) */
#define QM_PF_WFQ_CRD_E5_NUM_VOQS 16
/* Max WFQ increment value is 0.7 * upper bound */
#define QM_WFQ_MAX_INC_VAL ((QM_WFQ_UPPER_BOUND * 7) / 10)
/* VP WFQ increment value */
#define QM_VP_WFQ_INC_VAL(weight) ((weight) * QM_VP_WFQ_MIN_INC_VAL)
/* VP WFQ min increment value */
#define QM_VP_WFQ_MIN_INC_VAL 10800
/* VP WFQ max increment value, 2^30 */
#define QM_VP_WFQ_MAX_INC_VAL 0x40000000
/* VP WFQ bypass threshold */
#define QM_VP_WFQ_BYPASS_THRESH (QM_VP_WFQ_MIN_INC_VAL - 100)
/* VP RL credit task cost */
#define QM_VP_RL_CRD_TASK_COST 9700
/* Bit of VOQ in VP WFQ PQ map */
#define QM_VP_WFQ_PQ_VOQ_SHIFT 0
/* Bit of PF in VP WFQ PQ map */
#define QM_VP_WFQ_PQ_PF_SHIFT 5
/* RL constants */
@ -71,12 +96,13 @@ static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
#define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
/* RL increment value - rate is specified in mbps */
#define QM_RL_INC_VAL(rate) ({ \
typeof(rate) __rate = (rate); \
max_t(u32, \
(u32)(((__rate ? __rate : 1000000) * QM_RL_PERIOD * 101) / \
(8 * 100)), \
1); })
#define QM_RL_INC_VAL(rate) ({ \
typeof(rate) __rate = (rate); \
max_t(u32, \
(u32)(((__rate ? __rate : \
100000) * \
QM_RL_PERIOD * \
101) / (8 * 100)), 1); })
/* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
#define QM_PF_RL_UPPER_BOUND 62500000
@ -84,16 +110,13 @@ static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
/* Max PF RL increment value is 0.7 * upper bound */
#define QM_PF_RL_MAX_INC_VAL ((QM_PF_RL_UPPER_BOUND * 7) / 10)
/* Vport RL Upper bound, link speed is in Mpbs */
#define QM_VP_RL_UPPER_BOUND(speed) ((u32)max_t(u32, \
QM_RL_INC_VAL(speed), \
9700 + 1000))
/* Max Vport RL increment value is the Vport RL upper bound */
#define QM_VP_RL_MAX_INC_VAL(speed) QM_VP_RL_UPPER_BOUND(speed)
/* Vport RL credit threshold in case of QM bypass */
#define QM_VP_RL_BYPASS_THRESH_SPEED (QM_VP_RL_UPPER_BOUND(10000) - 1)
/* QCN RL Upper bound, speed is in Mpbs */
#define QM_GLOBAL_RL_UPPER_BOUND(speed) ((u32)max_t( \
u32, \
(u32)(((speed) * \
QM_RL_PERIOD * 101) / (8 * 100)), \
QM_VP_RL_CRD_TASK_COST \
+ 1000))
/* AFullOprtnstcCrdMask constants */
#define QM_OPPOR_LINE_VOQ_DEF 1
@ -156,20 +179,20 @@ static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
cmd ## _ ## field, \
value)
#define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, vp_pq_id, rl_valid, \
#define QM_INIT_TX_PQ_MAP(p_hwfn, map, pq_id, vp_pq_id, rl_valid, \
rl_id, ext_voq, wrr) \
do { \
u32 __reg = 0; \
\
BUILD_BUG_ON(sizeof((map).reg) != sizeof(__reg)); \
\
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_PQ_VALID, 1); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_RL_VALID, \
memset(&(map), 0, sizeof(map)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_PQ_VALID, 1); \
SET_FIELD(__reg, QM_RF_PQ_MAP_RL_VALID, \
!!(rl_valid)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_VP_PQ_ID, (vp_pq_id)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_RL_ID, (rl_id)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_VOQ, (ext_voq)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_##chip##_WRR_WEIGHT_GROUP, \
SET_FIELD(__reg, QM_RF_PQ_MAP_VP_PQ_ID, (vp_pq_id)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_RL_ID, (rl_id)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_VOQ, (ext_voq)); \
SET_FIELD(__reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, \
(wrr)); \
\
STORE_RT_REG((p_hwfn), QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \
@ -184,8 +207,8 @@ static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
(((rl) >> 8) << 9))
#define PQ_INFO_RAM_GRC_ADDRESS(pq_id) \
XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + \
XSTORM_PQ_INFO_OFFSET(pq_id)
(XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + \
XSTORM_PQ_INFO_OFFSET(pq_id))
/******************** INTERNAL IMPLEMENTATION *********************/
@ -204,7 +227,7 @@ static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
{
STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
if (pf_rl_en) {
u8 num_ext_voqs = MAX_NUM_VOQS_E4;
u8 num_ext_voqs = MAX_NUM_VOQS;
u64 voq_bit_mask = ((u64)1 << num_ext_voqs) - 1;
/* Enable RLs for all VOQs */
@ -236,7 +259,7 @@ static void qed_enable_pf_wfq(struct qed_hwfn *p_hwfn, bool pf_wfq_en)
if (pf_wfq_en && QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET,
QM_WFQ_UPPER_BOUND);
QM_PF_WFQ_UPPER_BOUND);
}
/* Prepare global RL enable/disable runtime init values */
@ -257,7 +280,7 @@ static void qed_enable_global_rl(struct qed_hwfn *p_hwfn, bool global_rl_en)
if (QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
QM_VP_RL_BYPASS_THRESH_SPEED);
QM_GLOBAL_RL_UPPER_BOUND(10000) - 1);
}
}
@ -271,7 +294,7 @@ static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en)
if (vport_wfq_en && QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET,
QM_WFQ_UPPER_BOUND);
QM_VP_WFQ_BYPASS_THRESH);
}
/* Prepare runtime init values to allocate PBF command queue lines for
@ -291,14 +314,14 @@ static void qed_cmdq_lines_voq_rt_init(struct qed_hwfn *p_hwfn,
}
/* Prepare runtime init values to allocate PBF command queue lines. */
static void qed_cmdq_lines_rt_init(
struct qed_hwfn *p_hwfn,
u8 max_ports_per_engine,
u8 max_phys_tcs_per_port,
struct init_qm_port_params port_params[MAX_NUM_PORTS])
static void
qed_cmdq_lines_rt_init(struct qed_hwfn *p_hwfn,
u8 max_ports_per_engine,
u8 max_phys_tcs_per_port,
struct init_qm_port_params port_params[MAX_NUM_PORTS])
{
u8 tc, ext_voq, port_id, num_tcs_in_port;
u8 num_ext_voqs = MAX_NUM_VOQS_E4;
u8 num_ext_voqs = MAX_NUM_VOQS;
/* Clear PBF lines of all VOQs */
for (ext_voq = 0; ext_voq < num_ext_voqs; ext_voq++)
@ -364,11 +387,11 @@ static void qed_cmdq_lines_rt_init(
* - No optimization for lossy TC (all are considered lossless). Shared space
* is not enabled and allocated for each TC.
*/
static void qed_btb_blocks_rt_init(
struct qed_hwfn *p_hwfn,
u8 max_ports_per_engine,
u8 max_phys_tcs_per_port,
struct init_qm_port_params port_params[MAX_NUM_PORTS])
static void
qed_btb_blocks_rt_init(struct qed_hwfn *p_hwfn,
u8 max_ports_per_engine,
u8 max_phys_tcs_per_port,
struct init_qm_port_params port_params[MAX_NUM_PORTS])
{
u32 usable_blocks, pure_lb_blocks, phys_blocks;
u8 tc, ext_voq, port_id, num_tcs_in_port;
@ -428,7 +451,7 @@ static void qed_btb_blocks_rt_init(
*/
static int qed_global_rl_rt_init(struct qed_hwfn *p_hwfn)
{
u32 upper_bound = QM_VP_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) |
u32 upper_bound = QM_GLOBAL_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) |
(u32)QM_RL_CRD_REG_SIGN_BIT;
u32 inc_val;
u16 rl_id;
@ -450,11 +473,73 @@ static int qed_global_rl_rt_init(struct qed_hwfn *p_hwfn)
return 0;
}
/* Returns the upper bound for the specified Vport RL parameters.
* link_speed is in Mbps.
* Returns 0 in case of error.
*/
static u32 qed_get_vport_rl_upper_bound(enum init_qm_rl_type vport_rl_type,
u32 link_speed)
{
switch (vport_rl_type) {
case QM_RL_TYPE_NORMAL:
return QM_INITIAL_VOQ_BYTE_CRD;
case QM_RL_TYPE_QCN:
return QM_GLOBAL_RL_UPPER_BOUND(link_speed);
default:
return 0;
}
}
/* Prepare VPORT RL runtime init values.
* Return -1 on error.
*/
static int qed_vport_rl_rt_init(struct qed_hwfn *p_hwfn,
u16 start_rl,
u16 num_rls,
u32 link_speed,
struct init_qm_rl_params *rl_params)
{
u16 i, rl_id;
if (num_rls && start_rl + num_rls >= MAX_QM_GLOBAL_RLS) {
DP_NOTICE(p_hwfn, "Invalid rate limiter configuration\n");
return -1;
}
/* Go over all PF VPORTs */
for (i = 0, rl_id = start_rl; i < num_rls; i++, rl_id++) {
u32 upper_bound, inc_val;
upper_bound =
qed_get_vport_rl_upper_bound((enum init_qm_rl_type)
rl_params[i].vport_rl_type,
link_speed);
inc_val =
QM_RL_INC_VAL(rl_params[i].vport_rl ?
rl_params[i].vport_rl : link_speed);
if (inc_val > upper_bound) {
DP_NOTICE(p_hwfn,
"Invalid RL rate - limit configuration\n");
return -1;
}
STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + rl_id,
(u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + rl_id,
upper_bound | (u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + rl_id,
inc_val);
}
return 0;
}
/* Prepare Tx PQ mapping runtime init values for the specified PF */
static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
struct qed_qm_pf_rt_init_params *p_params,
u32 base_mem_addr_4kb)
static int qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
struct qed_qm_pf_rt_init_params *p_params,
u32 base_mem_addr_4kb)
{
u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
struct init_qm_vport_params *vport_params = p_params->vport_params;
@ -487,7 +572,7 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
/* Go over all Tx PQs */
for (i = 0, pq_id = p_params->start_pq; i < num_pqs; i++, pq_id++) {
u16 *p_first_tx_pq_id, vport_id_in_pf;
struct qm_rf_pq_map_e4 tx_pq_map;
struct qm_rf_pq_map tx_pq_map;
u8 tc_id = pq_params[i].tc_id;
bool is_vf_pq;
u8 ext_voq;
@ -504,8 +589,8 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
&vport_params[vport_id_in_pf].first_tx_pq_id[tc_id];
if (*p_first_tx_pq_id == QM_INVALID_PQ_ID) {
u32 map_val =
(ext_voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
(p_params->pf_id << QM_WFQ_VP_PQ_PF_E4_SHIFT);
(ext_voq << QM_VP_WFQ_PQ_VOQ_SHIFT) |
(p_params->pf_id << QM_VP_WFQ_PQ_PF_SHIFT);
/* Create new VP PQ */
*p_first_tx_pq_id = pq_id;
@ -520,7 +605,6 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
/* Prepare PQ map entry */
QM_INIT_TX_PQ_MAP(p_hwfn,
tx_pq_map,
E4,
pq_id,
*p_first_tx_pq_id,
pq_params[i].rl_valid,
@ -570,6 +654,8 @@ static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
STORE_RT_REG(p_hwfn,
QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i,
tx_pq_vf_mask[i]);
return 0;
}
/* Prepare Other PQ mapping runtime init values for the specified PF */
@ -620,7 +706,6 @@ static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn,
* Return -1 on error.
*/
static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
struct qed_qm_pf_rt_init_params *p_params)
{
u16 num_tx_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
@ -629,8 +714,8 @@ static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
u8 ext_voq;
u16 i;
inc_val = QM_WFQ_INC_VAL(p_params->pf_wfq);
if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
inc_val = QM_PF_WFQ_INC_VAL(p_params->pf_wfq);
if (!inc_val || inc_val > QM_PF_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
return -1;
}
@ -652,7 +737,7 @@ static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
STORE_RT_REG(p_hwfn,
QM_REG_WFQPFUPPERBOUND_RT_OFFSET + p_params->pf_id,
QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
QM_PF_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + p_params->pf_id,
inc_val);
@ -689,34 +774,38 @@ static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
u16 num_vports,
struct init_qm_vport_params *vport_params)
{
u16 vport_pq_id, i;
u16 vport_pq_id, wfq, i;
u32 inc_val;
u8 tc;
/* Go over all PF VPORTs */
for (i = 0; i < num_vports; i++) {
if (!vport_params[i].wfq)
continue;
inc_val = QM_WFQ_INC_VAL(vport_params[i].wfq);
if (inc_val > QM_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn,
"Invalid VPORT WFQ weight configuration\n");
return -1;
}
/* Each VPORT can have several VPORT PQ IDs for various TCs */
for (tc = 0; tc < NUM_OF_TCS; tc++) {
/* Check if VPORT/TC is valid */
vport_pq_id = vport_params[i].first_tx_pq_id[tc];
if (vport_pq_id != QM_INVALID_PQ_ID) {
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPCRD_RT_OFFSET +
vport_pq_id,
(u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPWEIGHT_RT_OFFSET +
vport_pq_id, inc_val);
if (vport_pq_id == QM_INVALID_PQ_ID)
continue;
/* Find WFQ weight (per VPORT or per VPORT+TC) */
wfq = vport_params[i].wfq;
wfq = wfq ? wfq : vport_params[i].tc_wfq[tc];
inc_val = QM_VP_WFQ_INC_VAL(wfq);
if (inc_val > QM_VP_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn,
"Invalid VPORT WFQ weight configuration\n");
return -1;
}
/* Config registers */
STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET +
vport_pq_id,
(u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQVPUPPERBOUND_RT_OFFSET +
vport_pq_id,
inc_val | QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQVPWEIGHT_RT_OFFSET +
vport_pq_id, inc_val);
}
}
@ -780,11 +869,14 @@ int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_LINEVOQ,
QM_OPPOR_LINE_VOQ_DEF);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ, QM_BYTE_CRD_EN);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFWFQ, p_params->pf_wfq_en);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPWFQ, p_params->vport_wfq_en);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFRL, p_params->pf_rl_en);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFWFQ,
p_params->pf_wfq_en ? 1 : 0);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPWFQ,
p_params->vport_wfq_en ? 1 : 0);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFRL,
p_params->pf_rl_en ? 1 : 0);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPQCNRL,
p_params->global_rl_en);
p_params->global_rl_en ? 1 : 0);
SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_FWPAUSE, QM_OPPOR_FW_STOP_DEF);
SET_FIELD(mask,
QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY, QM_OPPOR_PQ_EMPTY_DEF);
@ -830,7 +922,6 @@ int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
u16 i;
u8 tc;
/* Clear first Tx PQ ID array for each VPORT */
for (i = 0; i < p_params->num_vports; i++)
for (tc = 0; tc < NUM_OF_TCS; tc++)
@ -843,7 +934,8 @@ int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
p_params->num_tids, 0);
/* Map Tx PQs */
qed_tx_pq_map_rt_init(p_hwfn, p_ptt, p_params, other_mem_size_4kb);
if (qed_tx_pq_map_rt_init(p_hwfn, p_ptt, p_params, other_mem_size_4kb))
return -1;
/* Init PF WFQ */
if (p_params->pf_wfq)
@ -858,15 +950,21 @@ int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
if (qed_vp_wfq_rt_init(p_hwfn, p_params->num_vports, vport_params))
return -1;
/* Set VPORT RL */
if (qed_vport_rl_rt_init(p_hwfn, p_params->start_rl,
p_params->num_rls, p_params->link_speed,
p_params->rl_params))
return -1;
return 0;
}
int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq)
{
u32 inc_val = QM_WFQ_INC_VAL(pf_wfq);
u32 inc_val = QM_PF_WFQ_INC_VAL(pf_wfq);
if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
if (!inc_val || inc_val > QM_PF_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
return -1;
}
@ -897,41 +995,66 @@ int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq)
{
int result = 0;
u16 vport_pq_id;
u32 inc_val;
u8 tc;
inc_val = QM_WFQ_INC_VAL(wfq);
if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
for (tc = 0; tc < NUM_OF_TCS && !result; tc++) {
vport_pq_id = first_tx_pq_id[tc];
if (vport_pq_id != QM_INVALID_PQ_ID)
result = qed_init_vport_tc_wfq(p_hwfn, p_ptt,
vport_pq_id, wfq);
}
return result;
}
int qed_init_vport_tc_wfq(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
u16 first_tx_pq_id, u16 wfq)
{
u32 inc_val;
if (first_tx_pq_id == QM_INVALID_PQ_ID)
return -1;
inc_val = QM_VP_WFQ_INC_VAL(wfq);
if (!inc_val || inc_val > QM_VP_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, "Invalid VPORT WFQ configuration.\n");
return -1;
}
/* A VPORT can have several VPORT PQ IDs for various TCs */
for (tc = 0; tc < NUM_OF_TCS; tc++) {
vport_pq_id = first_tx_pq_id[tc];
if (vport_pq_id != QM_INVALID_PQ_ID)
qed_wr(p_hwfn,
p_ptt,
QM_REG_WFQVPWEIGHT + vport_pq_id * 4, inc_val);
}
qed_wr(p_hwfn, p_ptt, QM_REG_WFQVPCRD + first_tx_pq_id * 4,
(u32)QM_WFQ_CRD_REG_SIGN_BIT);
qed_wr(p_hwfn, p_ptt, QM_REG_WFQVPUPPERBOUND + first_tx_pq_id * 4,
inc_val | QM_WFQ_CRD_REG_SIGN_BIT);
qed_wr(p_hwfn, p_ptt, QM_REG_WFQVPWEIGHT + first_tx_pq_id * 4,
inc_val);
return 0;
}
int qed_init_global_rl(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u16 rl_id, u32 rate_limit)
struct qed_ptt *p_ptt, u16 rl_id, u32 rate_limit,
enum init_qm_rl_type vport_rl_type)
{
u32 inc_val;
u32 inc_val, upper_bound;
upper_bound =
(vport_rl_type ==
QM_RL_TYPE_QCN) ? QM_GLOBAL_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) :
QM_INITIAL_VOQ_BYTE_CRD;
inc_val = QM_RL_INC_VAL(rate_limit);
if (inc_val > QM_VP_RL_MAX_INC_VAL(rate_limit)) {
DP_NOTICE(p_hwfn, "Invalid rate limit configuration.\n");
if (inc_val > upper_bound) {
DP_NOTICE(p_hwfn, "Invalid VPORT rate limit configuration.\n");
return -1;
}
qed_wr(p_hwfn, p_ptt,
QM_REG_RLGLBLCRD + rl_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
qed_wr(p_hwfn,
p_ptt,
QM_REG_RLGLBLUPPERBOUND + rl_id * 4,
upper_bound | (u32)QM_RL_CRD_REG_SIGN_BIT);
qed_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + rl_id * 4, inc_val);
return 0;
@ -1013,7 +1136,7 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
static int qed_dmae_to_grc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
__le32 *p_data, u32 addr, u32 len_in_dwords)
{
struct qed_dmae_params params = {};
struct qed_dmae_params params = { 0 };
u32 *data_cpu;
int rc;
@ -1066,16 +1189,16 @@ void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
/* Update PRS register */
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT;
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
SET_FIELD(reg_val,
PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE, vxlan_enable);
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val) {
reg_val =
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
/* Update output only if tunnel blocks not included. */
if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
(u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
}
@ -1099,18 +1222,20 @@ void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
/* Update PRS register */
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT;
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT;
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
SET_FIELD(reg_val,
PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE,
eth_gre_enable);
SET_FIELD(reg_val,
PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE,
ip_gre_enable);
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val) {
reg_val =
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
/* Update output only if tunnel blocks not included. */
if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
(u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
}
@ -1148,22 +1273,23 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
bool eth_geneve_enable, bool ip_geneve_enable)
{
u32 reg_val;
u8 shift;
/* Update PRS register */
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT;
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_geneve_enable);
shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT;
SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_geneve_enable);
SET_FIELD(reg_val,
PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE,
eth_geneve_enable);
SET_FIELD(reg_val,
PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE,
ip_geneve_enable);
qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val) {
reg_val =
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
/* Update output only if tunnel blocks not included. */
if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
(u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
}
@ -1179,16 +1305,16 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
/* Update DORQ registers */
qed_wr(p_hwfn,
p_ptt,
DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5,
DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2,
eth_geneve_enable ? 1 : 0);
qed_wr(p_hwfn,
p_ptt,
DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5,
DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2,
ip_geneve_enable ? 1 : 0);
}
#define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET 3
#define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT -925189872
#define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT 0xC8DAB910
void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, bool enable)
@ -1208,7 +1334,7 @@ void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
/* update PRS FIC register */
qed_wr(p_hwfn,
p_ptt,
PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
PRS_REG_OUTPUT_FORMAT_4_0,
(u32)PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT);
} else {
/* clear VXLAN_NO_L2_ENABLE flag */
@ -1229,7 +1355,7 @@ void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id)
{
struct regpair ram_line = { };
struct regpair ram_line = { 0 };
/* Disable gft search for PF */
qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
@ -1621,6 +1747,8 @@ struct phys_mem_desc *qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
storm_buf_size = GET_FIELD(hdr->data,
FW_OVERLAY_BUF_HDR_BUF_SIZE);
storm_id = GET_FIELD(hdr->data, FW_OVERLAY_BUF_HDR_STORM_ID);
if (storm_id >= NUM_STORMS)
break;
storm_mem_desc = allocated_mem + storm_id;
storm_mem_desc->size = storm_buf_size * sizeof(u32);
@ -1645,7 +1773,7 @@ struct phys_mem_desc *qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
/* If memory allocation has failed, free all allocated memory */
if (buf_offset < buf_size) {
qed_fw_overlay_mem_free(p_hwfn, allocated_mem);
qed_fw_overlay_mem_free(p_hwfn, &allocated_mem);
return NULL;
}
@ -1679,16 +1807,16 @@ void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
}
void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
struct phys_mem_desc *fw_overlay_mem)
struct phys_mem_desc **fw_overlay_mem)
{
u8 storm_id;
if (!fw_overlay_mem)
if (!fw_overlay_mem || !(*fw_overlay_mem))
return;
for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
struct phys_mem_desc *storm_mem_desc =
(struct phys_mem_desc *)fw_overlay_mem + storm_id;
(struct phys_mem_desc *)*fw_overlay_mem + storm_id;
/* Free Storm's physical memory */
if (storm_mem_desc->virt_addr)
@ -1699,5 +1827,6 @@ void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
}
/* Free allocated virtual memory */
kfree(fw_overlay_mem);
kfree(*fw_overlay_mem);
*fw_overlay_mem = NULL;
}

98
drivers/net/ethernet/qlogic/qed/qed_init_ops.c
View File

@ -15,6 +15,7 @@
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_init_ops.h"
#include "qed_iro_hsi.h"
#include "qed_reg_addr.h"
#include "qed_sriov.h"
@ -46,30 +47,32 @@ static u32 pxp_global_win[] = {
/* IRO Array */
static const u32 iro_arr[] = {
0x00000000, 0x00000000, 0x00080000,
0x00004478, 0x00000008, 0x00080000,
0x00003288, 0x00000088, 0x00880000,
0x000058e8, 0x00000020, 0x00200000,
0x000058a8, 0x00000020, 0x00200000,
0x00003188, 0x00000008, 0x00080000,
0x00000b00, 0x00000008, 0x00040000,
0x00000a80, 0x00000008, 0x00040000,
0x00000000, 0x00000008, 0x00020000,
0x00000080, 0x00000008, 0x00040000,
0x00000084, 0x00000008, 0x00020000,
0x00005718, 0x00000004, 0x00040000,
0x00004dd0, 0x00000000, 0x00780000,
0x00005798, 0x00000004, 0x00040000,
0x00004e50, 0x00000000, 0x00780000,
0x00003e40, 0x00000000, 0x00780000,
0x00004480, 0x00000000, 0x00780000,
0x00004500, 0x00000000, 0x00780000,
0x00003210, 0x00000000, 0x00780000,
0x00003b50, 0x00000000, 0x00780000,
0x00007f58, 0x00000000, 0x00780000,
0x00005f58, 0x00000000, 0x00080000,
0x00005fd8, 0x00000000, 0x00080000,
0x00007100, 0x00000000, 0x00080000,
0x0000aea0, 0x00000000, 0x00080000,
0x0000af20, 0x00000000, 0x00080000,
0x00004398, 0x00000000, 0x00080000,
0x0000a5a0, 0x00000000, 0x00080000,
0x0000bde8, 0x00000000, 0x00080000,
0x00000020, 0x00000004, 0x00040000,
0x000056c8, 0x00000010, 0x00100000,
0x00005688, 0x00000010, 0x00100000,
0x0000c210, 0x00000030, 0x00300000,
0x0000b088, 0x00000038, 0x00380000,
0x0000b108, 0x00000038, 0x00380000,
0x00003d20, 0x00000080, 0x00400000,
0x0000bf60, 0x00000000, 0x00040000,
0x00004560, 0x00040080, 0x00040000,
@ -77,11 +80,11 @@ static const u32 iro_arr[] = {
0x00003d60, 0x00000080, 0x00200000,
0x00008960, 0x00000040, 0x00300000,
0x0000e840, 0x00000060, 0x00600000,
0x00004618, 0x00000080, 0x00380000,
0x00010738, 0x000000c0, 0x00c00000,
0x00004698, 0x00000080, 0x00380000,
0x000107b8, 0x000000c0, 0x00c00000,
0x000001f8, 0x00000002, 0x00020000,
0x0000a2a0, 0x00000000, 0x01080000,
0x0000a3a8, 0x00000008, 0x00080000,
0x0000a260, 0x00000000, 0x01080000,
0x0000a368, 0x00000008, 0x00080000,
0x000001c0, 0x00000008, 0x00080000,
0x000001f8, 0x00000008, 0x00080000,
0x00000ac0, 0x00000008, 0x00080000,
@ -90,39 +93,46 @@ static const u32 iro_arr[] = {
0x00000280, 0x00000008, 0x00080000,
0x00000680, 0x00080018, 0x00080000,
0x00000b78, 0x00080018, 0x00020000,
0x0000c640, 0x00000050, 0x003c0000,
0x00012038, 0x00000018, 0x00100000,
0x00011b00, 0x00000040, 0x00180000,
0x000095d0, 0x00000050, 0x00200000,
0x0000c600, 0x00000058, 0x003c0000,
0x00012038, 0x00000020, 0x00100000,
0x00011b00, 0x00000048, 0x00180000,
0x00009650, 0x00000050, 0x00200000,
0x00008b10, 0x00000040, 0x00280000,
0x00011640, 0x00000018, 0x00100000,
0x0000c828, 0x00000048, 0x00380000,
0x00011710, 0x00000020, 0x00200000,
0x00004650, 0x00000080, 0x00100000,
0x000116c0, 0x00000018, 0x00100000,
0x0000c808, 0x00000048, 0x00380000,
0x00011790, 0x00000020, 0x00200000,
0x000046d0, 0x00000080, 0x00100000,
0x00003618, 0x00000010, 0x00100000,
0x0000a968, 0x00000008, 0x00010000,
0x0000a9e8, 0x00000008, 0x00010000,
0x000097a0, 0x00000008, 0x00010000,
0x00011990, 0x00000008, 0x00010000,
0x0000f018, 0x00000008, 0x00010000,
0x00012628, 0x00000008, 0x00010000,
0x00011da8, 0x00000008, 0x00010000,
0x0000aa78, 0x00000030, 0x00100000,
0x0000d768, 0x00000028, 0x00280000,
0x00009a58, 0x00000018, 0x00180000,
0x00009bd8, 0x00000008, 0x00080000,
0x00013a18, 0x00000008, 0x00080000,
0x000126e8, 0x00000018, 0x00180000,
0x0000e608, 0x00500288, 0x00100000,
0x00012970, 0x00000138, 0x00280000,
0x00011a10, 0x00000008, 0x00010000,
0x0000e9f8, 0x00000008, 0x00010000,
0x00012648, 0x00000008, 0x00010000,
0x000121c8, 0x00000008, 0x00010000,
0x0000af08, 0x00000030, 0x00100000,
0x0000d748, 0x00000028, 0x00280000,
0x00009e68, 0x00000018, 0x00180000,
0x00009fe8, 0x00000008, 0x00080000,
0x00013ea8, 0x00000008, 0x00080000,
0x00012f18, 0x00000018, 0x00180000,
0x0000dfe8, 0x00500288, 0x00100000,
0x000131a0, 0x00000138, 0x00280000,
};
void qed_init_iro_array(struct qed_dev *cdev)
{
cdev->iro_arr = iro_arr;
cdev->iro_arr = iro_arr + E4_IRO_ARR_OFFSET;
}
void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, u32 rt_offset, u32 val)
{
if (rt_offset >= RUNTIME_ARRAY_SIZE) {
DP_ERR(p_hwfn,
"Avoid storing %u in rt_data at index %u!\n",
val, rt_offset);
return;
}
p_hwfn->rt_data.init_val[rt_offset] = val;
p_hwfn->rt_data.b_valid[rt_offset] = true;
}
@ -132,6 +142,14 @@ void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn,
{
size_t i;
if ((rt_offset + size - 1) >= RUNTIME_ARRAY_SIZE) {
DP_ERR(p_hwfn,
"Avoid storing values in rt_data at indices %u-%u!\n",
rt_offset,
(u32)(rt_offset + size - 1));
return;
}
for (i = 0; i < size / sizeof(u32); i++) {
p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
p_hwfn->rt_data.b_valid[rt_offset + i] = true;
@ -175,7 +193,7 @@ static int qed_init_rt(struct qed_hwfn *p_hwfn,
return rc;
/* invalidate after writing */
for (j = i; j < i + segment; j++)
for (j = i; j < (u32)(i + segment); j++)
p_valid[j] = false;
/* Jump over the entire segment, including invalid entry */
@ -245,7 +263,7 @@ static int qed_init_array_dmae(struct qed_hwfn *p_hwfn,
static int qed_init_fill_dmae(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u32 addr, u32 fill, u32 fill_count)
u32 addr, u32 fill_count)
{
static u32 zero_buffer[DMAE_MAX_RW_SIZE];
struct qed_dmae_params params = {};
@ -372,7 +390,7 @@ static int qed_init_cmd_wr(struct qed_hwfn *p_hwfn,
case INIT_SRC_ZEROS:
data = le32_to_cpu(p_cmd->args.zeros_count);
if (b_must_dmae || (b_can_dmae && (data >= 64)))
rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, data);
else
qed_init_fill(p_hwfn, p_ptt, addr, 0, data);
break;
@ -419,7 +437,6 @@ static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn,
addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);
val = qed_rd(p_hwfn, p_ptt, addr);
if (poll == INIT_POLL_NONE)
@ -515,8 +532,7 @@ static u32 qed_init_cmd_mode(struct qed_hwfn *p_hwfn,
INIT_IF_MODE_OP_CMD_OFFSET);
}
static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn,
struct init_if_phase_op *p_cmd,
static u32 qed_init_cmd_phase(struct init_if_phase_op *p_cmd,
u32 phase, u32 phase_id)
{
u32 data = le32_to_cpu(p_cmd->phase_data);
@ -563,7 +579,7 @@ int qed_init_run(struct qed_hwfn *p_hwfn,
modes);
break;
case INIT_OP_IF_PHASE:
cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase,
cmd_num += qed_init_cmd_phase(&cmd->if_phase,
phase, phase_id);
break;
case INIT_OP_DELAY:

60
drivers/net/ethernet/qlogic/qed/qed_init_ops.h
View File

@ -12,23 +12,24 @@
#include "qed.h"
/**
* @brief qed_init_iro_array - init iro_arr.
* qed_init_iro_array(): init iro_arr.
*
* @cdev: Qed dev pointer.
*
* @param cdev
* Return: Void.
*/
void qed_init_iro_array(struct qed_dev *cdev);
/**
* @brief qed_init_run - Run the init-sequence.
* qed_init_run(): Run the init-sequence.
*
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @phase: Phase.
* @phase_id: Phase ID.
* @modes: Mode.
*
* @param p_hwfn
* @param p_ptt
* @param phase
* @param phase_id
* @param modes
* @return _qed_status_t
* Return: _qed_status_t
*/
int qed_init_run(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@ -37,30 +38,31 @@ int qed_init_run(struct qed_hwfn *p_hwfn,
int modes);
/**
* @brief qed_init_hwfn_allocate - Allocate RT array, Store 'values' ptrs.
* qed_init_alloc(): Allocate RT array, Store 'values' ptrs.
*
* @p_hwfn: HW device data.
*
* @param p_hwfn
*
* @return _qed_status_t
* Return: _qed_status_t.
*/
int qed_init_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_init_hwfn_deallocate
* qed_init_free(): Init HW function deallocate.
*
* @p_hwfn: HW device data.
*
* @param p_hwfn
* Return: Void.
*/
void qed_init_free(struct qed_hwfn *p_hwfn);
/**
* @brief qed_init_store_rt_reg - Store a configuration value in the RT array.
* qed_init_store_rt_reg(): Store a configuration value in the RT array.
*
* @p_hwfn: HW device data.
* @rt_offset: RT offset.
* @val: Val.
*
* @param p_hwfn
* @param rt_offset
* @param val
* Return: Void.
*/
void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn,
u32 rt_offset,
@ -72,29 +74,21 @@ void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn,
#define OVERWRITE_RT_REG(hwfn, offset, val) \
qed_init_store_rt_reg(hwfn, offset, val)
/**
* @brief
*
*
* @param p_hwfn
* @param rt_offset
* @param val
* @param size
*/
void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn,
u32 rt_offset,
u32 *val,
size_t size);
#define STORE_RT_REG_AGG(hwfn, offset, val) \
qed_init_store_rt_agg(hwfn, offset, (u32 *)&val, sizeof(val))
qed_init_store_rt_agg(hwfn, offset, (u32 *)&(val), sizeof(val))
/**
* @brief
* Initialize GTT global windows and set admin window
* related params of GTT/PTT to default values.
* qed_gtt_init(): Initialize GTT global windows and set admin window
* related params of GTT/PTT to default values.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return Void.
*/
void qed_gtt_init(struct qed_hwfn *p_hwfn);
#endif

4
drivers/net/ethernet/qlogic/qed/qed_int.c
View File

@ -36,7 +36,7 @@ struct qed_sb_sp_info {
struct qed_sb_info sb_info;
/* per protocol index data */
struct qed_pi_info pi_info_arr[PIS_PER_SB_E4];
struct qed_pi_info pi_info_arr[PIS_PER_SB];
};
enum qed_attention_type {
@ -1507,7 +1507,7 @@ static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
else
SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 1);
sb_offset = igu_sb_id * PIS_PER_SB_E4;
sb_offset = igu_sb_id * PIS_PER_SB;
pi_offset = sb_offset + pi_index;
if (p_hwfn->hw_init_done)

276
drivers/net/ethernet/qlogic/qed/qed_int.h
View File

@ -53,51 +53,54 @@ enum qed_coalescing_fsm {
};
/**
* @brief qed_int_igu_enable_int - enable device interrupts
* qed_int_igu_enable_int(): Enable device interrupts.
*
* @param p_hwfn
* @param p_ptt
* @param int_mode - interrupt mode to use
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @int_mode: Interrupt mode to use.
*
* Return: Void.
*/
void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
enum qed_int_mode int_mode);
/**
* @brief qed_int_igu_disable_int - disable device interrupts
* qed_int_igu_disable_int(): Disable device interrupts.
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* Return: Void.
*/
void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
/**
* @brief qed_int_igu_read_sisr_reg - Reads the single isr multiple dpc
* register from igu.
* qed_int_igu_read_sisr_reg(): Reads the single isr multiple dpc
* register from igu.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return u64
* Return: u64.
*/
u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn);
#define QED_SP_SB_ID 0xffff
/**
* @brief qed_int_sb_init - Initializes the sb_info structure.
* qed_int_sb_init(): Initializes the sb_info structure.
*
* once the structure is initialized it can be passed to sb related functions.
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @sb_info: points to an uninitialized (but allocated) sb_info structure
* @sb_virt_addr: SB Virtual address.
* @sb_phy_addr: SB Physial address.
* @sb_id: the sb_id to be used (zero based in driver)
* should use QED_SP_SB_ID for SP Status block
*
* @param p_hwfn
* @param p_ptt
* @param sb_info points to an uninitialized (but
* allocated) sb_info structure
* @param sb_virt_addr
* @param sb_phy_addr
* @param sb_id the sb_id to be used (zero based in driver)
* should use QED_SP_SB_ID for SP Status block
* Return: int.
*
* @return int
* Once the structure is initialized it can be passed to sb related functions.
*/
int qed_int_sb_init(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@ -106,82 +109,91 @@ int qed_int_sb_init(struct qed_hwfn *p_hwfn,
dma_addr_t sb_phy_addr,
u16 sb_id);
/**
* @brief qed_int_sb_setup - Setup the sb.
* qed_int_sb_setup(): Setup the sb.
*
* @param p_hwfn
* @param p_ptt
* @param sb_info initialized sb_info structure
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @sb_info: Initialized sb_info structure.
*
* Return: Void.
*/
void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
struct qed_sb_info *sb_info);
/**
* @brief qed_int_sb_release - releases the sb_info structure.
* qed_int_sb_release(): Releases the sb_info structure.
*
* once the structure is released, it's memory can be freed
* @p_hwfn: HW device data.
* @sb_info: Points to an allocated sb_info structure.
* @sb_id: The sb_id to be used (zero based in driver)
* should never be equal to QED_SP_SB_ID
* (SP Status block).
*
* @param p_hwfn
* @param sb_info points to an allocated sb_info structure
* @param sb_id the sb_id to be used (zero based in driver)
* should never be equal to QED_SP_SB_ID
* (SP Status block)
* Return: int.
*
* @return int
* Once the structure is released, it's memory can be freed.
*/
int qed_int_sb_release(struct qed_hwfn *p_hwfn,
struct qed_sb_info *sb_info,
u16 sb_id);
/**
* @brief qed_int_sp_dpc - To be called when an interrupt is received on the
* default status block.
* qed_int_sp_dpc(): To be called when an interrupt is received on the
* default status block.
*
* @param p_hwfn - pointer to hwfn
* @t: Tasklet.
*
* Return: Void.
*
*/
void qed_int_sp_dpc(struct tasklet_struct *t);
/**
* @brief qed_int_get_num_sbs - get the number of status
* blocks configured for this funciton in the igu.
* qed_int_get_num_sbs(): Get the number of status blocks configured
* for this funciton in the igu.
*
* @param p_hwfn
* @param p_sb_cnt_info
* @p_hwfn: HW device data.
* @p_sb_cnt_info: Pointer to SB count info.
*
* @return int - number of status blocks configured
* Return: Void.
*/
void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
struct qed_sb_cnt_info *p_sb_cnt_info);
/**
* @brief qed_int_disable_post_isr_release - performs the cleanup post ISR
* qed_int_disable_post_isr_release(): Performs the cleanup post ISR
* release. The API need to be called after releasing all slowpath IRQs
* of the device.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* Return: Void.
*/
void qed_int_disable_post_isr_release(struct qed_dev *cdev);
/**
* @brief qed_int_attn_clr_enable - sets whether the general behavior is
* qed_int_attn_clr_enable: Sets whether the general behavior is
* preventing attentions from being reasserted, or following the
* attributes of the specific attention.
*
* @param cdev
* @param clr_enable
* @cdev: Qed dev pointer.
* @clr_enable: Clear enable
*
* Return: Void.
*
*/
void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable);
/**
* @brief - Doorbell Recovery handler.
* qed_db_rec_handler(): Doorbell Recovery handler.
* Run doorbell recovery in case of PF overflow (and flush DORQ if
* needed).
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* Return: Int.
*/
int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
@ -192,7 +204,7 @@ int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
#define QED_SB_EVENT_MASK 0x0003
#define SB_ALIGNED_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)
ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
#define QED_SB_INVALID_IDX 0xffff
@ -223,30 +235,34 @@ struct qed_igu_info {
};
/**
* @brief - Make sure the IGU CAM reflects the resources provided by MFW
* qed_int_igu_reset_cam(): Make sure the IGU CAM reflects the resources
* provided by MFW.
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* Return: Void.
*/
int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
/**
* @brief Translate the weakly-defined client sb-id into an IGU sb-id
* qed_get_igu_sb_id(): Translate the weakly-defined client sb-id into
* an IGU sb-id
*
* @param p_hwfn
* @param sb_id - user provided sb_id
* @p_hwfn: HW device data.
* @sb_id: user provided sb_id.
*
* @return an index inside IGU CAM where the SB resides
* Return: An index inside IGU CAM where the SB resides.
*/
u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
/**
* @brief return a pointer to an unused valid SB
* qed_get_igu_free_sb(): Return a pointer to an unused valid SB
*
* @param p_hwfn
* @param b_is_pf - true iff we want a SB belonging to a PF
* @p_hwfn: HW device data.
* @b_is_pf: True iff we want a SB belonging to a PF.
*
* @return point to an igu_block, NULL if none is available
* Return: Point to an igu_block, NULL if none is available.
*/
struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn,
bool b_is_pf);
@ -259,15 +275,15 @@ void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn);
/**
* @brief qed_int_igu_read_cam - Reads the IGU CAM.
* qed_int_igu_read_cam(): Reads the IGU CAM.
* This function needs to be called during hardware
* prepare. It reads the info from igu cam to know which
* status block is the default / base status block etc.
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* @return int
* Return: Int.
*/
int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
@ -275,24 +291,22 @@ int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn,
typedef int (*qed_int_comp_cb_t)(struct qed_hwfn *p_hwfn,
void *cookie);
/**
* @brief qed_int_register_cb - Register callback func for
* slowhwfn statusblock.
* qed_int_register_cb(): Register callback func for slowhwfn statusblock.
*
* Every protocol that uses the slowhwfn status block
* should register a callback function that will be called
* once there is an update of the sp status block.
* @p_hwfn: HW device data.
* @comp_cb: Function to be called when there is an
* interrupt on the sp sb
* @cookie: Passed to the callback function
* @sb_idx: (OUT) parameter which gives the chosen index
* for this protocol.
* @p_fw_cons: Pointer to the actual address of the
* consumer for this protocol.
*
* @param p_hwfn
* @param comp_cb - function to be called when there is an
* interrupt on the sp sb
* Return: Int.
*
* @param cookie - passed to the callback function
* @param sb_idx - OUT parameter which gives the chosen index
* for this protocol.
* @param p_fw_cons - pointer to the actual address of the
* consumer for this protocol.
*
* @return int
* Every protocol that uses the slowhwfn status block
* should register a callback function that will be called
* once there is an update of the sp status block.
*/
int qed_int_register_cb(struct qed_hwfn *p_hwfn,
qed_int_comp_cb_t comp_cb,
@ -301,37 +315,40 @@ int qed_int_register_cb(struct qed_hwfn *p_hwfn,
__le16 **p_fw_cons);
/**
* @brief qed_int_unregister_cb - Unregisters callback
* function from sp sb.
* Partner of qed_int_register_cb -> should be called
* when no longer required.
* qed_int_unregister_cb(): Unregisters callback function from sp sb.
*
* @param p_hwfn
* @param pi
* @p_hwfn: HW device data.
* @pi: Producer Index.
*
* @return int
* Return: Int.
*
* Partner of qed_int_register_cb -> should be called
* when no longer required.
*/
int qed_int_unregister_cb(struct qed_hwfn *p_hwfn,
u8 pi);
/**
* @brief qed_int_get_sp_sb_id - Get the slowhwfn sb id.
* qed_int_get_sp_sb_id(): Get the slowhwfn sb id.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return u16
* Return: u16.
*/
u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn);
/**
* @brief Status block cleanup. Should be called for each status
* block that will be used -> both PF / VF
* qed_int_igu_init_pure_rt_single(): Status block cleanup.
* Should be called for each status
* block that will be used -> both PF / VF.
*
* @param p_hwfn
* @param p_ptt
* @param igu_sb_id - igu status block id
* @param opaque - opaque fid of the sb owner.
* @param b_set - set(1) / clear(0)
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @igu_sb_id: IGU status block id.
* @opaque: Opaque fid of the sb owner.
* @b_set: Set(1) / Clear(0).
*
* Return: Void.
*/
void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@ -340,15 +357,16 @@ void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
bool b_set);
/**
* @brief qed_int_cau_conf - configure cau for a given status
* block
* qed_int_cau_conf_sb(): Configure cau for a given status block.
*
* @param p_hwfn
* @param ptt
* @param sb_phys
* @param igu_sb_id
* @param vf_number
* @param vf_valid
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @sb_phys: SB Physical.
* @igu_sb_id: IGU status block id.
* @vf_number: VF number
* @vf_valid: VF valid or not.
*
* Return: Void.
*/
void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
@ -358,52 +376,58 @@ void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
u8 vf_valid);
/**
* @brief qed_int_alloc
* qed_int_alloc(): QED interrupt alloc.
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* @return int
* Return: Int.
*/
int qed_int_alloc(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
/**
* @brief qed_int_free
* qed_int_free(): QED interrupt free.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_int_free(struct qed_hwfn *p_hwfn);
/**
* @brief qed_int_setup
* qed_int_setup(): QED interrupt setup.
*
* @param p_hwfn
* @param p_ptt
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
*
* Return: Void.
*/
void qed_int_setup(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
/**
* @brief - Enable Interrupt & Attention for hw function
* qed_int_igu_enable(): Enable Interrupt & Attention for hw function.
*
* @param p_hwfn
* @param p_ptt
* @param int_mode
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @int_mode: Interrut mode
*
* @return int
* Return: Int.
*/
int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
enum qed_int_mode int_mode);
/**
* @brief - Initialize CAU status block entry
* qed_init_cau_sb_entry(): Initialize CAU status block entry.
*
* @param p_hwfn
* @param p_sb_entry
* @param pf_id
* @param vf_number
* @param vf_valid
* @p_hwfn: HW device data.
* @p_sb_entry: Pointer SB entry.
* @pf_id: PF number
* @vf_number: VF number
* @vf_valid: VF valid or not.
*
* Return: Void.
*/
void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
struct cau_sb_entry *p_sb_entry,

500
drivers/net/ethernet/qlogic/qed/qed_iro_hsi.h Normal file
View File

@ -0,0 +1,500 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/* QLogic qed NIC Driver
* Copyright (c) 2019-2021 Marvell International Ltd.
*/
#ifndef _QED_IRO_HSI_H
#define _QED_IRO_HSI_H
#include <linux/types.h>
enum {
IRO_YSTORM_FLOW_CONTROL_MODE_GTT,
IRO_PSTORM_PKT_DUPLICATION_CFG,
IRO_TSTORM_PORT_STAT,
IRO_TSTORM_LL2_PORT_STAT,
IRO_TSTORM_PKT_DUPLICATION_CFG,
IRO_USTORM_VF_PF_CHANNEL_READY_GTT,
IRO_USTORM_FLR_FINAL_ACK_GTT,
IRO_USTORM_EQE_CONS_GTT,
IRO_USTORM_ETH_QUEUE_ZONE_GTT,
IRO_USTORM_COMMON_QUEUE_CONS_GTT,
IRO_XSTORM_PQ_INFO,
IRO_XSTORM_INTEG_TEST_DATA,
IRO_YSTORM_INTEG_TEST_DATA,
IRO_PSTORM_INTEG_TEST_DATA,
IRO_TSTORM_INTEG_TEST_DATA,
IRO_MSTORM_INTEG_TEST_DATA,
IRO_USTORM_INTEG_TEST_DATA,
IRO_XSTORM_OVERLAY_BUF_ADDR,
IRO_YSTORM_OVERLAY_BUF_ADDR,
IRO_PSTORM_OVERLAY_BUF_ADDR,
IRO_TSTORM_OVERLAY_BUF_ADDR,
IRO_MSTORM_OVERLAY_BUF_ADDR,
IRO_USTORM_OVERLAY_BUF_ADDR,
IRO_TSTORM_LL2_RX_PRODS_GTT,
IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT,
IRO_CORE_LL2_USTORM_PER_QUEUE_STAT,
IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT,
IRO_MSTORM_QUEUE_STAT,
IRO_MSTORM_TPA_TIMEOUT_US,
IRO_MSTORM_ETH_VF_PRODS,
IRO_MSTORM_ETH_PF_PRODS_GTT,
IRO_MSTORM_ETH_PF_STAT,
IRO_USTORM_QUEUE_STAT,
IRO_USTORM_ETH_PF_STAT,
IRO_PSTORM_QUEUE_STAT,
IRO_PSTORM_ETH_PF_STAT,
IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT,
IRO_TSTORM_ETH_PRS_INPUT,
IRO_ETH_RX_RATE_LIMIT,
IRO_TSTORM_ETH_RSS_UPDATE_GTT,
IRO_XSTORM_ETH_QUEUE_ZONE_GTT,
IRO_YSTORM_TOE_CQ_PROD,
IRO_USTORM_TOE_CQ_PROD,
IRO_USTORM_TOE_GRQ_PROD,
IRO_TSTORM_SCSI_CMDQ_CONS_GTT,
IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT,
IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT,
IRO_TSTORM_ISCSI_RX_STATS,
IRO_MSTORM_ISCSI_RX_STATS,
IRO_USTORM_ISCSI_RX_STATS,
IRO_XSTORM_ISCSI_TX_STATS,
IRO_YSTORM_ISCSI_TX_STATS,
IRO_PSTORM_ISCSI_TX_STATS,
IRO_TSTORM_FCOE_RX_STATS,
IRO_PSTORM_FCOE_TX_STATS,
IRO_PSTORM_RDMA_QUEUE_STAT,
IRO_TSTORM_RDMA_QUEUE_STAT,
IRO_XSTORM_RDMA_ASSERT_LEVEL,
IRO_YSTORM_RDMA_ASSERT_LEVEL,
IRO_PSTORM_RDMA_ASSERT_LEVEL,
IRO_TSTORM_RDMA_ASSERT_LEVEL,
IRO_MSTORM_RDMA_ASSERT_LEVEL,
IRO_USTORM_RDMA_ASSERT_LEVEL,
IRO_XSTORM_IWARP_RXMIT_STATS,
IRO_TSTORM_ROCE_EVENTS_STAT,
IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS,
IRO_YSTORM_ROCE_ERROR_STATS,
IRO_PSTORM_ROCE_DCQCN_SENT_STATS,
IRO_USTORM_ROCE_CQE_STATS,
};
/* Pstorm LiteL2 queue statistics */
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
(IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].base \
+ ((core_tx_stats_id) * IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].m1))
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE \
(IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].size)
/* Tstorm LightL2 queue statistics */
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
(IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].base \
+ ((core_rx_queue_id) * IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].m1))
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE \
(IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].size)
/* Ustorm LiteL2 queue statistics */
#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
(IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].base \
+ ((core_rx_queue_id) * IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].m1))
#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE \
(IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].size)
/* Tstorm Eth limit Rx rate */
#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
(IRO[IRO_ETH_RX_RATE_LIMIT].base \
+ ((pf_id) * IRO[IRO_ETH_RX_RATE_LIMIT].m1))
#define ETH_RX_RATE_LIMIT_SIZE (IRO[IRO_ETH_RX_RATE_LIMIT].size)
/* Mstorm ETH PF queues producers */
#define MSTORM_ETH_PF_PRODS_GTT_OFFSET(queue_id) \
(IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].base \
+ ((queue_id) * IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].m1))
#define MSTORM_ETH_PF_PRODS_GTT_SIZE (IRO[IRO_MSTORM_ETH_PF_PRODS_GTT].size)
/* Mstorm pf statistics */
#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
(IRO[IRO_MSTORM_ETH_PF_STAT].base \
+ ((pf_id) * IRO[IRO_MSTORM_ETH_PF_STAT].m1))
#define MSTORM_ETH_PF_STAT_SIZE (IRO[IRO_MSTORM_ETH_PF_STAT].size)
/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone
* size mode.
*/
#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
(IRO[IRO_MSTORM_ETH_VF_PRODS].base \
+ ((vf_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m1) \
+ ((vf_queue_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m2))
#define MSTORM_ETH_VF_PRODS_SIZE (IRO[IRO_MSTORM_ETH_VF_PRODS].size)
/* Mstorm Integration Test Data */
#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_MSTORM_INTEG_TEST_DATA].base)
#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_MSTORM_INTEG_TEST_DATA].size)
/* Mstorm iSCSI RX stats */
#define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
(IRO[IRO_MSTORM_ISCSI_RX_STATS].base \
+ ((storage_func_id) * IRO[IRO_MSTORM_ISCSI_RX_STATS].m1))
#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_MSTORM_ISCSI_RX_STATS].size)
/* Mstorm overlay buffer host address */
#define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].base)
#define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].size)
/* Mstorm queue statistics */
#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[IRO_MSTORM_QUEUE_STAT].base \
+ ((stat_counter_id) * IRO[IRO_MSTORM_QUEUE_STAT].m1))
#define MSTORM_QUEUE_STAT_SIZ (IRO[IRO_MSTORM_QUEUE_STAT].size)
/* Mstorm error level for assert */
#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
(IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].m1))
#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].size)
/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
#define MSTORM_SCSI_BDQ_EXT_PROD_GTT_OFFSET(storage_func_id, bdq_id) \
(IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].base \
+ ((storage_func_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \
+ ((bdq_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))
#define MSTORM_SCSI_BDQ_EXT_PROD_GTT_SIZE \
(IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD_GTT].size)
/* TPA agregation timeout in us resolution (on ASIC) */
#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[IRO_MSTORM_TPA_TIMEOUT_US].base)
#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[IRO_MSTORM_TPA_TIMEOUT_US].size)
/* Control frame's EthType configuration for TX control frame security */
#define PSTORM_CTL_FRAME_ETHTYPE_GTT_OFFSET(ethtype_id) \
(IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].base \
+ ((ethtype_id) * IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].m1))
#define PSTORM_CTL_FRAME_ETHTYPE_GTT_SIZE \
(IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE_GTT].size)
/* Pstorm pf statistics */
#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
(IRO[IRO_PSTORM_ETH_PF_STAT].base \
+ ((pf_id) * IRO[IRO_PSTORM_ETH_PF_STAT].m1))
#define PSTORM_ETH_PF_STAT_SIZE (IRO[IRO_PSTORM_ETH_PF_STAT].size)
/* Pstorm FCoE TX stats */
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
(IRO[IRO_PSTORM_FCOE_TX_STATS].base \
+ ((pf_id) * IRO[IRO_PSTORM_FCOE_TX_STATS].m1))
#define PSTORM_FCOE_TX_STATS_SIZE (IRO[IRO_PSTORM_FCOE_TX_STATS].size)
/* Pstorm Integration Test Data */
#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_PSTORM_INTEG_TEST_DATA].base)
#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_PSTORM_INTEG_TEST_DATA].size)
/* Pstorm iSCSI TX stats */
#define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
(IRO[IRO_PSTORM_ISCSI_TX_STATS].base \
+ ((storage_func_id) * IRO[IRO_PSTORM_ISCSI_TX_STATS].m1))
#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_PSTORM_ISCSI_TX_STATS].size)
/* Pstorm overlay buffer host address */
#define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].base)
#define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].size)
/* Pstorm LL2 packet duplication configuration. Use pstorm_pkt_dup_cfg
* data type.
*/
#define PSTORM_PKT_DUPLICATION_CFG_OFFSET(pf_id) \
(IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].base \
+ ((pf_id) * IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].m1))
#define PSTORM_PKT_DUPLICATION_CFG_SIZE \
(IRO[IRO_PSTORM_PKT_DUPLICATION_CFG].size)
/* Pstorm queue statistics */
#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[IRO_PSTORM_QUEUE_STAT].base \
+ ((stat_counter_id) * IRO[IRO_PSTORM_QUEUE_STAT].m1))
#define PSTORM_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_QUEUE_STAT].size)
/* Pstorm error level for assert */
#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
(IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].m1))
#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].size)
/* Pstorm RDMA queue statistics */
#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
(IRO[IRO_PSTORM_RDMA_QUEUE_STAT].base \
+ ((rdma_stat_counter_id) * IRO[IRO_PSTORM_RDMA_QUEUE_STAT].m1))
#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].size)
/* DCQCN Sent Statistics */
#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
(IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].base \
+ ((roce_pf_id) * IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].m1))
#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE \
(IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].size)
/* Tstorm last parser message */
#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[IRO_TSTORM_ETH_PRS_INPUT].base)
#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[IRO_TSTORM_ETH_PRS_INPUT].size)
/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
* Use eth_tstorm_rss_update_data for update.
*/
#define TSTORM_ETH_RSS_UPDATE_GTT_OFFSET(pf_id) \
(IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].base \
+ ((pf_id) * IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].m1))
#define TSTORM_ETH_RSS_UPDATE_GTT_SIZE\
(IRO[IRO_TSTORM_ETH_RSS_UPDATE_GTT].size)
/* Tstorm FCoE RX stats */
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
(IRO[IRO_TSTORM_FCOE_RX_STATS].base \
+ ((pf_id) * IRO[IRO_TSTORM_FCOE_RX_STATS].m1))
#define TSTORM_FCOE_RX_STATS_SIZE (IRO[IRO_TSTORM_FCOE_RX_STATS].size)
/* Tstorm Integration Test Data */
#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_TSTORM_INTEG_TEST_DATA].base)
#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_TSTORM_INTEG_TEST_DATA].size)
/* Tstorm iSCSI RX stats */
#define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
(IRO[IRO_TSTORM_ISCSI_RX_STATS].base \
+ ((storage_func_id) * IRO[IRO_TSTORM_ISCSI_RX_STATS].m1))
#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_TSTORM_ISCSI_RX_STATS].size)
/* Tstorm ll2 port statistics */
#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
(IRO[IRO_TSTORM_LL2_PORT_STAT].base \
+ ((port_id) * IRO[IRO_TSTORM_LL2_PORT_STAT].m1))
#define TSTORM_LL2_PORT_STAT_SIZE (IRO[IRO_TSTORM_LL2_PORT_STAT].size)
/* Tstorm producers */
#define TSTORM_LL2_RX_PRODS_GTT_OFFSET(core_rx_queue_id) \
(IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].base \
+ ((core_rx_queue_id) * IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].m1))
#define TSTORM_LL2_RX_PRODS_GTT_SIZE (IRO[IRO_TSTORM_LL2_RX_PRODS_GTT].size)
/* Tstorm overlay buffer host address */
#define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].base)
#define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].size)
/* Tstorm LL2 packet duplication configuration.
* Use tstorm_pkt_dup_cfg data type.
*/
#define TSTORM_PKT_DUPLICATION_CFG_OFFSET(pf_id) \
(IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].base \
+ ((pf_id) * IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].m1))
#define TSTORM_PKT_DUPLICATION_CFG_SIZE \
(IRO[IRO_TSTORM_PKT_DUPLICATION_CFG].size)
/* Tstorm port statistics */
#define TSTORM_PORT_STAT_OFFSET(port_id) \
(IRO[IRO_TSTORM_PORT_STAT].base \
+ ((port_id) * IRO[IRO_TSTORM_PORT_STAT].m1))
#define TSTORM_PORT_STAT_SIZE (IRO[IRO_TSTORM_PORT_STAT].size)
/* Tstorm error level for assert */
#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
(IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].m1))
#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].size)
/* Tstorm RDMA queue statistics */
#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
(IRO[IRO_TSTORM_RDMA_QUEUE_STAT].base \
+ ((rdma_stat_counter_id) * IRO[IRO_TSTORM_RDMA_QUEUE_STAT].m1))
#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].size)
/* Tstorm RoCE Event Statistics */
#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
(IRO[IRO_TSTORM_ROCE_EVENTS_STAT].base \
+ ((roce_pf_id) * IRO[IRO_TSTORM_ROCE_EVENTS_STAT].m1))
#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].size)
/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
* BDqueue-id.
*/
#define TSTORM_SCSI_BDQ_EXT_PROD_GTT_OFFSET(storage_func_id, bdq_id) \
(IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].base \
+ ((storage_func_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m1) \
+ ((bdq_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].m2))
#define TSTORM_SCSI_BDQ_EXT_PROD_GTT_SIZE \
(IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD_GTT].size)
/* Tstorm cmdq-cons of given command queue-id */
#define TSTORM_SCSI_CMDQ_CONS_GTT_OFFSET(cmdq_queue_id) \
(IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].base \
+ ((cmdq_queue_id) * IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].m1))
#define TSTORM_SCSI_CMDQ_CONS_GTT_SIZE \
(IRO[IRO_TSTORM_SCSI_CMDQ_CONS_GTT].size)
/* Ustorm Common Queue ring consumer */
#define USTORM_COMMON_QUEUE_CONS_GTT_OFFSET(queue_zone_id) \
(IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].base \
+ ((queue_zone_id) * IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].m1))
#define USTORM_COMMON_QUEUE_CONS_GTT_SIZE \
(IRO[IRO_USTORM_COMMON_QUEUE_CONS_GTT].size)
/* Ustorm Event ring consumer */
#define USTORM_EQE_CONS_GTT_OFFSET(pf_id) \
(IRO[IRO_USTORM_EQE_CONS_GTT].base \
+ ((pf_id) * IRO[IRO_USTORM_EQE_CONS_GTT].m1))
#define USTORM_EQE_CONS_GTT_SIZE (IRO[IRO_USTORM_EQE_CONS_GTT].size)
/* Ustorm pf statistics */
#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
(IRO[IRO_USTORM_ETH_PF_STAT].base \
+ ((pf_id) * IRO[IRO_USTORM_ETH_PF_STAT].m1))
#define USTORM_ETH_PF_STAT_SIZE (IRO[IRO_USTORM_ETH_PF_STAT].size)
/* Ustorm eth queue zone */
#define USTORM_ETH_QUEUE_ZONE_GTT_OFFSET(queue_zone_id) \
(IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].base \
+ ((queue_zone_id) * IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].m1))
#define USTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_USTORM_ETH_QUEUE_ZONE_GTT].size)
/* Ustorm Final flr cleanup ack */
#define USTORM_FLR_FINAL_ACK_GTT_OFFSET(pf_id) \
(IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].base \
+ ((pf_id) * IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].m1))
#define USTORM_FLR_FINAL_ACK_GTT_SIZE (IRO[IRO_USTORM_FLR_FINAL_ACK_GTT].size)
/* Ustorm Integration Test Data */
#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_USTORM_INTEG_TEST_DATA].base)
#define USTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_USTORM_INTEG_TEST_DATA].size)
/* Ustorm iSCSI RX stats */
#define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
(IRO[IRO_USTORM_ISCSI_RX_STATS].base \
+ ((storage_func_id) * IRO[IRO_USTORM_ISCSI_RX_STATS].m1))
#define USTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_USTORM_ISCSI_RX_STATS].size)
/* Ustorm overlay buffer host address */
#define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].base)
#define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].size)
/* Ustorm queue statistics */
#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[IRO_USTORM_QUEUE_STAT].base \
+ ((stat_counter_id) * IRO[IRO_USTORM_QUEUE_STAT].m1))
#define USTORM_QUEUE_STAT_SIZE (IRO[IRO_USTORM_QUEUE_STAT].size)
/* Ustorm error level for assert */
#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
(IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].m1))
#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].size)
/* RoCE CQEs Statistics */
#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
(IRO[IRO_USTORM_ROCE_CQE_STATS].base \
+ ((roce_pf_id) * IRO[IRO_USTORM_ROCE_CQE_STATS].m1))
#define USTORM_ROCE_CQE_STATS_SIZE (IRO[IRO_USTORM_ROCE_CQE_STATS].size)
/* Ustorm cqe producer */
#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
(IRO[IRO_USTORM_TOE_CQ_PROD].base \
+ ((rss_id) * IRO[IRO_USTORM_TOE_CQ_PROD].m1))
#define USTORM_TOE_CQ_PROD_SIZE (IRO[IRO_USTORM_TOE_CQ_PROD].size)
/* Ustorm grq producer */
#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
(IRO[IRO_USTORM_TOE_GRQ_PROD].base \
+ ((pf_id) * IRO[IRO_USTORM_TOE_GRQ_PROD].m1))
#define USTORM_TOE_GRQ_PROD_SIZE (IRO[IRO_USTORM_TOE_GRQ_PROD].size)
/* Ustorm VF-PF Channel ready flag */
#define USTORM_VF_PF_CHANNEL_READY_GTT_OFFSET(vf_id) \
(IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].base \
+ ((vf_id) * IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].m1))
#define USTORM_VF_PF_CHANNEL_READY_GTT_SIZE \
(IRO[IRO_USTORM_VF_PF_CHANNEL_READY_GTT].size)
/* Xstorm queue zone */
#define XSTORM_ETH_QUEUE_ZONE_GTT_OFFSET(queue_id) \
(IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].base \
+ ((queue_id) * IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].m1))
#define XSTORM_ETH_QUEUE_ZONE_GTT_SIZE (IRO[IRO_XSTORM_ETH_QUEUE_ZONE_GTT].size)
/* Xstorm Integration Test Data */
#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_XSTORM_INTEG_TEST_DATA].base)
#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_XSTORM_INTEG_TEST_DATA].size)
/* Xstorm iSCSI TX stats */
#define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
(IRO[IRO_XSTORM_ISCSI_TX_STATS].base \
+ ((storage_func_id) * IRO[IRO_XSTORM_ISCSI_TX_STATS].m1))
#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_XSTORM_ISCSI_TX_STATS].size)
/* Xstorm iWARP rxmit stats */
#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
(IRO[IRO_XSTORM_IWARP_RXMIT_STATS].base \
+ ((pf_id) * IRO[IRO_XSTORM_IWARP_RXMIT_STATS].m1))
#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].size)
/* Xstorm overlay buffer host address */
#define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].base)
#define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].size)
/* Xstorm common PQ info */
#define XSTORM_PQ_INFO_OFFSET(pq_id) \
(IRO[IRO_XSTORM_PQ_INFO].base \
+ ((pq_id) * IRO[IRO_XSTORM_PQ_INFO].m1))
#define XSTORM_PQ_INFO_SIZE (IRO[IRO_XSTORM_PQ_INFO].size)
/* Xstorm error level for assert */
#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
(IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].m1))
#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].size)
/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
#define YSTORM_FLOW_CONTROL_MODE_GTT_OFFSET \
(IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].base)
#define YSTORM_FLOW_CONTROL_MODE_GTT_SIZE \
(IRO[IRO_YSTORM_FLOW_CONTROL_MODE_GTT].size)
/* Ystorm Integration Test Data */
#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_YSTORM_INTEG_TEST_DATA].base)
#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_YSTORM_INTEG_TEST_DATA].size)
/* Ystorm iSCSI TX stats */
#define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
(IRO[IRO_YSTORM_ISCSI_TX_STATS].base \
+ ((storage_func_id) * IRO[IRO_YSTORM_ISCSI_TX_STATS].m1))
#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_YSTORM_ISCSI_TX_STATS].size)
/* Ystorm overlay buffer host address */
#define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].base)
#define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].size)
/* Ystorm error level for assert */
#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
(IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].base \
+ ((pf_id) * IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].m1))
#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].size)
/* DCQCN Received Statistics */
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \
(IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].base \
+ ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].m1))
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE \
(IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].size)
/* RoCE Error Statistics */
#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
(IRO[IRO_YSTORM_ROCE_ERROR_STATS].base \
+ ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_ERROR_STATS].m1))
#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[IRO_YSTORM_ROCE_ERROR_STATS].size)
/* Ystorm cqe producer */
#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
(IRO[IRO_YSTORM_TOE_CQ_PROD].base \
+ ((rss_id) * IRO[IRO_YSTORM_TOE_CQ_PROD].m1))
#define YSTORM_TOE_CQ_PROD_SIZE (IRO[IRO_YSTORM_TOE_CQ_PROD].size)
/* Per-chip offsets in iro_arr in dwords */
#define E4_IRO_ARR_OFFSET 0
#endif

15
drivers/net/ethernet/qlogic/qed/qed_iscsi.c
View File

@ -29,6 +29,7 @@
#include "qed_hsi.h"
#include "qed_hw.h"
#include "qed_int.h"
#include "qed_iro_hsi.h"
#include "qed_iscsi.h"
#include "qed_ll2.h"
#include "qed_mcp.h"
@ -627,10 +628,9 @@ static void __iomem *qed_iscsi_get_primary_bdq_prod(struct qed_hwfn *p_hwfn,
{
if (RESC_NUM(p_hwfn, QED_BDQ)) {
return (u8 __iomem *)p_hwfn->regview +
GTT_BAR0_MAP_REG_MSDM_RAM +
MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(RESC_START(p_hwfn,
QED_BDQ),
bdq_id);
GET_GTT_BDQ_REG_ADDR(GTT_BAR0_MAP_REG_MSDM_RAM,
MSTORM_SCSI_BDQ_EXT_PROD,
RESC_START(p_hwfn, QED_BDQ), bdq_id);
} else {
DP_NOTICE(p_hwfn, "BDQ is not allocated!\n");
return NULL;
@ -642,10 +642,9 @@ static void __iomem *qed_iscsi_get_secondary_bdq_prod(struct qed_hwfn *p_hwfn,
{
if (RESC_NUM(p_hwfn, QED_BDQ)) {
return (u8 __iomem *)p_hwfn->regview +
GTT_BAR0_MAP_REG_TSDM_RAM +
TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(RESC_START(p_hwfn,
QED_BDQ),
bdq_id);
GET_GTT_BDQ_REG_ADDR(GTT_BAR0_MAP_REG_TSDM_RAM,
TSTORM_SCSI_BDQ_EXT_PROD,
RESC_START(p_hwfn, QED_BDQ), bdq_id);
} else {
DP_NOTICE(p_hwfn, "BDQ is not allocated!\n");
return NULL;

9
drivers/net/ethernet/qlogic/qed/qed_iscsi.h
View File

@ -34,10 +34,13 @@ void qed_iscsi_setup(struct qed_hwfn *p_hwfn);
void qed_iscsi_free(struct qed_hwfn *p_hwfn);
/**
* @brief - Fills provided statistics struct with statistics.
* qed_get_protocol_stats_iscsi(): Fills provided statistics
* struct with statistics.
*
* @param cdev
* @param stats - points to struct that will be filled with statistics.
* @cdev: Qed dev pointer.
* @stats: Points to struct that will be filled with statistics.
*
* Return: Void.
*/
void qed_get_protocol_stats_iscsi(struct qed_dev *cdev,
struct qed_mcp_iscsi_stats *stats);

2
drivers/net/ethernet/qlogic/qed/qed_iwarp.c
View File

@ -114,6 +114,8 @@ qed_iwarp_init_fw_ramrod(struct qed_hwfn *p_hwfn,
RESC_START(p_hwfn, QED_LL2_RAM_QUEUE) +
p_hwfn->p_rdma_info->iwarp.ll2_ooo_handle;
p_ramrod->tcp.tx_sws_timer = cpu_to_le16(QED_TX_SWS_TIMER_DFLT);
p_ramrod->tcp.two_msl_timer = cpu_to_le32(QED_TWO_MSL_TIMER_DFLT);
p_ramrod->tcp.max_fin_rt = QED_IWARP_MAX_FIN_RT_DEFAULT;
return;

18
drivers/net/ethernet/qlogic/qed/qed_l2.c
View File

@ -28,6 +28,7 @@
#include "qed_dev_api.h"
#include <linux/qed/qed_eth_if.h>
#include "qed_hsi.h"
#include "qed_iro_hsi.h"
#include "qed_hw.h"
#include "qed_int.h"
#include "qed_l2.h"
@ -37,7 +38,6 @@
#include "qed_sp.h"
#include "qed_sriov.h"
#define QED_MAX_SGES_NUM 16
#define CRC32_POLY 0x1edc6f41
@ -904,9 +904,10 @@ qed_eth_pf_rx_queue_start(struct qed_hwfn *p_hwfn,
{
u32 init_prod_val = 0;
*pp_prod = p_hwfn->regview +
GTT_BAR0_MAP_REG_MSDM_RAM +
MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id);
*pp_prod = (u8 __iomem *)
p_hwfn->regview +
GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_MSDM_RAM,
MSTORM_ETH_PF_PRODS, p_cid->abs.queue_id);
/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
@ -1111,7 +1112,6 @@ qed_eth_pf_tx_queue_start(struct qed_hwfn *p_hwfn,
{
int rc;
rc = qed_eth_txq_start_ramrod(p_hwfn, p_cid,
pbl_addr, pbl_size,
qed_get_cm_pq_idx_mcos(p_hwfn, tc));
@ -2010,7 +2010,7 @@ qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn,
struct qed_spq_comp_cb *p_cb,
struct qed_ntuple_filter_params *p_params)
{
struct rx_update_gft_filter_data *p_ramrod = NULL;
struct rx_update_gft_filter_ramrod_data *p_ramrod = NULL;
struct qed_spq_entry *p_ent = NULL;
struct qed_sp_init_data init_data;
u16 abs_rx_q_id = 0;
@ -2031,7 +2031,7 @@ qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn,
}
rc = qed_sp_init_request(p_hwfn, &p_ent,
ETH_RAMROD_GFT_UPDATE_FILTER,
ETH_RAMROD_RX_UPDATE_GFT_FILTER,
PROTOCOLID_ETH, &init_data);
if (rc)
return rc;
@ -2100,7 +2100,7 @@ int qed_get_rxq_coalesce(struct qed_hwfn *p_hwfn,
CAU_SB_ENTRY_TIMER_RES0);
address = BAR0_MAP_REG_USDM_RAM +
USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
USTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id);
coalesce = qed_rd(p_hwfn, p_ptt, address);
is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);
@ -2134,7 +2134,7 @@ int qed_get_txq_coalesce(struct qed_hwfn *p_hwfn,
CAU_SB_ENTRY_TIMER_RES1);
address = BAR0_MAP_REG_XSDM_RAM +
XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
XSTORM_ETH_QUEUE_ZONE_GTT_OFFSET(p_cid->abs.queue_id);
coalesce = qed_rd(p_hwfn, p_ptt, address);
is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID);

135
drivers/net/ethernet/qlogic/qed/qed_l2.h
View File

@ -92,18 +92,18 @@ struct qed_filter_mcast {
};
/**
* @brief qed_eth_rx_queue_stop - This ramrod closes an Rx queue
* qed_eth_rx_queue_stop(): This ramrod closes an Rx queue.
*
* @param p_hwfn
* @param p_rxq Handler of queue to close
* @param eq_completion_only If True completion will be on
* EQe, if False completion will be
* on EQe if p_hwfn opaque
* different from the RXQ opaque
* otherwise on CQe.
* @param cqe_completion If True completion will be
* receive on CQe.
* @return int
* @p_hwfn: HW device data.
* @p_rxq: Handler of queue to close
* @eq_completion_only: If True completion will be on
* EQe, if False completion will be
* on EQe if p_hwfn opaque
* different from the RXQ opaque
* otherwise on CQe.
* @cqe_completion: If True completion will be receive on CQe.
*
* Return: Int.
*/
int
qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
@ -111,12 +111,12 @@ qed_eth_rx_queue_stop(struct qed_hwfn *p_hwfn,
bool eq_completion_only, bool cqe_completion);
/**
* @brief qed_eth_tx_queue_stop - closes a Tx queue
* qed_eth_tx_queue_stop(): Closes a Tx queue.
*
* @param p_hwfn
* @param p_txq - handle to Tx queue needed to be closed
* @p_hwfn: HW device data.
* @p_txq: handle to Tx queue needed to be closed.
*
* @return int
* Return: Int.
*/
int qed_eth_tx_queue_stop(struct qed_hwfn *p_hwfn, void *p_txq);
@ -146,7 +146,6 @@ struct qed_sp_vport_start_params {
int qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
struct qed_sp_vport_start_params *p_params);
struct qed_filter_accept_flags {
u8 update_rx_mode_config;
u8 update_tx_mode_config;
@ -205,16 +204,15 @@ int qed_sp_vport_update(struct qed_hwfn *p_hwfn,
struct qed_spq_comp_cb *p_comp_data);
/**
* @brief qed_sp_vport_stop -
* qed_sp_vport_stop: This ramrod closes a VPort after all its
* RX and TX queues are terminated.
* An Assert is generated if any queues are left open.
*
* This ramrod closes a VPort after all its RX and TX queues are terminated.
* An Assert is generated if any queues are left open.
* @p_hwfn: HW device data.
* @opaque_fid: Opaque FID
* @vport_id: VPort ID.
*
* @param p_hwfn
* @param opaque_fid
* @param vport_id VPort ID
*
* @return int
* Return: Int.
*/
int qed_sp_vport_stop(struct qed_hwfn *p_hwfn, u16 opaque_fid, u8 vport_id);
@ -225,22 +223,21 @@ int qed_sp_eth_filter_ucast(struct qed_hwfn *p_hwfn,
struct qed_spq_comp_cb *p_comp_data);
/**
* @brief qed_sp_rx_eth_queues_update -
* qed_sp_eth_rx_queues_update(): This ramrod updates an RX queue.
* It is used for setting the active state
* of the queue and updating the TPA and
* SGE parameters.
* @p_hwfn: HW device data.
* @pp_rxq_handlers: An array of queue handlers to be updated.
* @num_rxqs: number of queues to update.
* @complete_cqe_flg: Post completion to the CQE Ring if set.
* @complete_event_flg: Post completion to the Event Ring if set.
* @comp_mode: Comp mode.
* @p_comp_data: Pointer Comp data.
*
* This ramrod updates an RX queue. It is used for setting the active state
* of the queue and updating the TPA and SGE parameters.
* Return: Int.
*
* @note At the moment - only used by non-linux VFs.
*
* @param p_hwfn
* @param pp_rxq_handlers An array of queue handlers to be updated.
* @param num_rxqs number of queues to update.
* @param complete_cqe_flg Post completion to the CQE Ring if set
* @param complete_event_flg Post completion to the Event Ring if set
* @param comp_mode
* @param p_comp_data
*
* @return int
* Note At the moment - only used by non-linux VFs.
*/
int
@ -257,30 +254,32 @@ void qed_get_vport_stats(struct qed_dev *cdev, struct qed_eth_stats *stats);
void qed_reset_vport_stats(struct qed_dev *cdev);
/**
* *@brief qed_arfs_mode_configure -
* qed_arfs_mode_configure(): Enable or disable rfs mode.
* It must accept at least one of tcp or udp true
* and at least one of ipv4 or ipv6 true to enable
* rfs mode.
*
**Enable or disable rfs mode. It must accept atleast one of tcp or udp true
**and atleast one of ipv4 or ipv6 true to enable rfs mode.
*
**@param p_hwfn
**@param p_ptt
**@param p_cfg_params - arfs mode configuration parameters.
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @p_cfg_params: arfs mode configuration parameters.
*
* Return. Void.
*/
void qed_arfs_mode_configure(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
struct qed_arfs_config_params *p_cfg_params);
/**
* @brief - qed_configure_rfs_ntuple_filter
* qed_configure_rfs_ntuple_filter(): This ramrod should be used to add
* or remove arfs hw filter
*
* This ramrod should be used to add or remove arfs hw filter
* @p_hwfn: HW device data.
* @p_cb: Used for QED_SPQ_MODE_CB,where client would initialize
* it with cookie and callback function address, if not
* using this mode then client must pass NULL.
* @p_params: Pointer to params.
*
* @params p_hwfn
* @params p_cb - Used for QED_SPQ_MODE_CB,where client would initialize
* it with cookie and callback function address, if not
* using this mode then client must pass NULL.
* @params p_params
* Return: Void.
*/
int
qed_configure_rfs_ntuple_filter(struct qed_hwfn *p_hwfn,
@ -374,16 +373,17 @@ qed_sp_eth_vport_start(struct qed_hwfn *p_hwfn,
struct qed_sp_vport_start_params *p_params);
/**
* @brief - Starts an Rx queue, when queue_cid is already prepared
* qed_eth_rxq_start_ramrod(): Starts an Rx queue, when queue_cid is
* already prepared
*
* @param p_hwfn
* @param p_cid
* @param bd_max_bytes
* @param bd_chain_phys_addr
* @param cqe_pbl_addr
* @param cqe_pbl_size
* @p_hwfn: HW device data.
* @p_cid: Pointer CID.
* @bd_max_bytes: Max bytes.
* @bd_chain_phys_addr: Chain physcial address.
* @cqe_pbl_addr: PBL address.
* @cqe_pbl_size: PBL size.
*
* @return int
* Return: Int.
*/
int
qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
@ -393,15 +393,16 @@ qed_eth_rxq_start_ramrod(struct qed_hwfn *p_hwfn,
dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size);
/**
* @brief - Starts a Tx queue, where queue_cid is already prepared
* qed_eth_txq_start_ramrod(): Starts a Tx queue, where queue_cid is
* already prepared
*
* @param p_hwfn
* @param p_cid
* @param pbl_addr
* @param pbl_size
* @param p_pq_params - parameters for choosing the PQ for this Tx queue
* @p_hwfn: HW device data.
* @p_cid: Pointer CID.
* @pbl_addr: PBL address.
* @pbl_size: PBL size.
* @pq_id: Parameters for choosing the PQ for this Tx queue.
*
* @return int
* Return: Int.
*/
int
qed_eth_txq_start_ramrod(struct qed_hwfn *p_hwfn,

64
drivers/net/ethernet/qlogic/qed/qed_ll2.c
View File

@ -28,6 +28,7 @@
#include "qed_cxt.h"
#include "qed_dev_api.h"
#include "qed_hsi.h"
#include "qed_iro_hsi.h"
#include "qed_hw.h"
#include "qed_int.h"
#include "qed_ll2.h"
@ -43,6 +44,8 @@
#define QED_LL2_TX_SIZE (256)
#define QED_LL2_RX_SIZE (4096)
#define QED_LL2_INVALID_STATS_ID 0xff
struct qed_cb_ll2_info {
int rx_cnt;
u32 rx_size;
@ -62,6 +65,29 @@ struct qed_ll2_buffer {
dma_addr_t phys_addr;
};
static u8 qed_ll2_handle_to_stats_id(struct qed_hwfn *p_hwfn,
u8 ll2_queue_type, u8 qid)
{
u8 stats_id;
/* For legacy (RAM based) queues, the stats_id will be set as the
* queue_id. Otherwise (context based queue), it will be set to
* the "abs_pf_id" offset from the end of the RAM based queue IDs.
* If the final value exceeds the total counters amount, return
* INVALID value to indicate that the stats for this connection should
* be disabled.
*/
if (ll2_queue_type == QED_LL2_RX_TYPE_LEGACY)
stats_id = qid;
else
stats_id = MAX_NUM_LL2_RX_RAM_QUEUES + p_hwfn->abs_pf_id;
if (stats_id < MAX_NUM_LL2_TX_STATS_COUNTERS)
return stats_id;
else
return QED_LL2_INVALID_STATS_ID;
}
static void qed_ll2b_complete_tx_packet(void *cxt,
u8 connection_handle,
void *cookie,
@ -106,7 +132,7 @@ static int qed_ll2_alloc_buffer(struct qed_dev *cdev,
}
static int qed_ll2_dealloc_buffer(struct qed_dev *cdev,
struct qed_ll2_buffer *buffer)
struct qed_ll2_buffer *buffer)
{
spin_lock_bh(&cdev->ll2->lock);
@ -1124,6 +1150,7 @@ static int qed_sp_ll2_tx_queue_stop(struct qed_hwfn *p_hwfn,
struct qed_spq_entry *p_ent = NULL;
struct qed_sp_init_data init_data;
int rc = -EINVAL;
qed_db_recovery_del(p_hwfn->cdev, p_tx->doorbell_addr, &p_tx->db_msg);
/* Get SPQ entry */
@ -1533,7 +1560,7 @@ static inline u8 qed_ll2_handle_to_queue_id(struct qed_hwfn *p_hwfn,
int qed_ll2_establish_connection(void *cxt, u8 connection_handle)
{
struct e4_core_conn_context *p_cxt;
struct core_conn_context *p_cxt;
struct qed_ll2_tx_packet *p_pkt;
struct qed_ll2_info *p_ll2_conn;
struct qed_hwfn *p_hwfn = cxt;
@ -1544,7 +1571,7 @@ int qed_ll2_establish_connection(void *cxt, u8 connection_handle)
int rc = -EINVAL;
u32 i, capacity;
size_t desc_size;
u8 qid;
u8 qid, stats_id;
p_ptt = qed_ptt_acquire(p_hwfn);
if (!p_ptt)
@ -1610,16 +1637,32 @@ int qed_ll2_establish_connection(void *cxt, u8 connection_handle)
qid = qed_ll2_handle_to_queue_id(p_hwfn, connection_handle,
p_ll2_conn->input.rx_conn_type);
stats_id = qed_ll2_handle_to_stats_id(p_hwfn,
p_ll2_conn->input.rx_conn_type,
qid);
p_ll2_conn->queue_id = qid;
p_ll2_conn->tx_stats_id = qid;
p_ll2_conn->tx_stats_id = stats_id;
DP_VERBOSE(p_hwfn, QED_MSG_LL2,
"Establishing ll2 queue. PF %d ctx_based=%d abs qid=%d\n",
p_hwfn->rel_pf_id, p_ll2_conn->input.rx_conn_type, qid);
/* If there is no valid stats id for this connection, disable stats */
if (p_ll2_conn->tx_stats_id == QED_LL2_INVALID_STATS_ID) {
p_ll2_conn->tx_stats_en = 0;
DP_VERBOSE(p_hwfn,
QED_MSG_LL2,
"Disabling stats for queue %d - not enough counters\n",
qid);
}
DP_VERBOSE(p_hwfn,
QED_MSG_LL2,
"Establishing ll2 queue. PF %d ctx_bsaed=%d abs qid=%d stats_id=%d\n",
p_hwfn->rel_pf_id,
p_ll2_conn->input.rx_conn_type, qid, stats_id);
if (p_ll2_conn->input.rx_conn_type == QED_LL2_RX_TYPE_LEGACY) {
p_rx->set_prod_addr = p_hwfn->regview +
GTT_BAR0_MAP_REG_TSDM_RAM + TSTORM_LL2_RX_PRODS_OFFSET(qid);
p_rx->set_prod_addr =
(u8 __iomem *)p_hwfn->regview +
GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_TSDM_RAM,
TSTORM_LL2_RX_PRODS, qid);
} else {
/* QED_LL2_RX_TYPE_CTX - using doorbell */
p_rx->ctx_based = 1;
@ -1762,7 +1805,7 @@ int qed_ll2_post_rx_buffer(void *cxt,
}
}
/* If we're lacking entires, let's try to flush buffers to FW */
/* If we're lacking entries, let's try to flush buffers to FW */
if (!p_curp || !p_curb) {
rc = -EBUSY;
p_curp = NULL;
@ -2609,7 +2652,6 @@ static int qed_ll2_start(struct qed_dev *cdev, struct qed_ll2_params *params)
DP_NOTICE(cdev, "Failed to add an LLH filter\n");
goto err3;
}
}
ether_addr_copy(cdev->ll2_mac_address, params->ll2_mac_address);

131
drivers/net/ethernet/qlogic/qed/qed_ll2.h
View File

@ -32,7 +32,6 @@
#define QED_LL2_LEGACY_CONN_BASE_PF 0
#define QED_LL2_CTX_CONN_BASE_PF QED_MAX_NUM_OF_LEGACY_LL2_CONNS_PF
struct qed_ll2_rx_packet {
struct list_head list_entry;
struct core_rx_bd_with_buff_len *rxq_bd;
@ -119,41 +118,41 @@ struct qed_ll2_info {
extern const struct qed_ll2_ops qed_ll2_ops_pass;
/**
* @brief qed_ll2_acquire_connection - allocate resources,
* starts rx & tx (if relevant) queues pair. Provides
* connecion handler as output parameter.
* qed_ll2_acquire_connection(): Allocate resources,
* starts rx & tx (if relevant) queues pair.
* Provides connecion handler as output
* parameter.
*
* @cxt: Pointer to the hw-function [opaque to some].
* @data: Describes connection parameters.
*
* @param cxt - pointer to the hw-function [opaque to some]
* @param data - describes connection parameters
* @return int
* Return: Int.
*/
int qed_ll2_acquire_connection(void *cxt, struct qed_ll2_acquire_data *data);
/**
* @brief qed_ll2_establish_connection - start previously
* allocated LL2 queues pair
* qed_ll2_establish_connection(): start previously allocated LL2 queues pair
*
* @param cxt - pointer to the hw-function [opaque to some]
* @param p_ptt
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
* @cxt: Pointer to the hw-function [opaque to some].
* @connection_handle: LL2 connection's handle obtained from
* qed_ll2_require_connection.
*
* @return 0 on success, failure otherwise
* Return: 0 on success, failure otherwise.
*/
int qed_ll2_establish_connection(void *cxt, u8 connection_handle);
/**
* @brief qed_ll2_post_rx_buffers - submit buffers to LL2 Rx queue.
* qed_ll2_post_rx_buffer(): Submit buffers to LL2 Rx queue.
*
* @param cxt - pointer to the hw-function [opaque to some]
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
* @param addr rx (physical address) buffers to submit
* @param cookie
* @param notify_fw produce corresponding Rx BD immediately
* @cxt: Pointer to the hw-function [opaque to some].
* @connection_handle: LL2 connection's handle obtained from
* qed_ll2_require_connection.
* @addr: RX (physical address) buffers to submit.
* @buf_len: Buffer Len.
* @cookie: Cookie.
* @notify_fw: Produce corresponding Rx BD immediately.
*
* @return 0 on success, failure otherwise
* Return: 0 on success, failure otherwise.
*/
int qed_ll2_post_rx_buffer(void *cxt,
u8 connection_handle,
@ -161,15 +160,15 @@ int qed_ll2_post_rx_buffer(void *cxt,
u16 buf_len, void *cookie, u8 notify_fw);
/**
* @brief qed_ll2_prepare_tx_packet - request for start Tx BD
* to prepare Tx packet submission to FW.
* qed_ll2_prepare_tx_packet(): Request for start Tx BD
* to prepare Tx packet submission to FW.
*
* @param cxt - pointer to the hw-function [opaque to some]
* @param connection_handle
* @param pkt - info regarding the tx packet
* @param notify_fw - issue doorbell to fw for this packet
* @cxt: Pointer to the hw-function [opaque to some].
* @connection_handle: Connection handle.
* @pkt: Info regarding the tx packet.
* @notify_fw: Issue doorbell to fw for this packet.
*
* @return 0 on success, failure otherwise
* Return: 0 on success, failure otherwise.
*/
int qed_ll2_prepare_tx_packet(void *cxt,
u8 connection_handle,
@ -177,81 +176,83 @@ int qed_ll2_prepare_tx_packet(void *cxt,
bool notify_fw);
/**
* @brief qed_ll2_release_connection - releases resources
* allocated for LL2 connection
* qed_ll2_release_connection(): Releases resources allocated for LL2
* connection.
*
* @param cxt - pointer to the hw-function [opaque to some]
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
* @cxt: Pointer to the hw-function [opaque to some].
* @connection_handle: LL2 connection's handle obtained from
* qed_ll2_require_connection.
*
* Return: Void.
*/
void qed_ll2_release_connection(void *cxt, u8 connection_handle);
/**
* @brief qed_ll2_set_fragment_of_tx_packet - provides fragments to fill
* Tx BD of BDs requested by
* qed_ll2_prepare_tx_packet
* qed_ll2_set_fragment_of_tx_packet(): Provides fragments to fill
* Tx BD of BDs requested by
* qed_ll2_prepare_tx_packet
*
* @param cxt - pointer to the hw-function [opaque to some]
* @param connection_handle LL2 connection's handle
* obtained from
* qed_ll2_require_connection
* @param addr
* @param nbytes
* @cxt: Pointer to the hw-function [opaque to some].
* @connection_handle: LL2 connection's handle obtained from
* qed_ll2_require_connection.
* @addr: Address.
* @nbytes: Number of bytes.
*
* @return 0 on success, failure otherwise
* Return: 0 on success, failure otherwise.
*/
int qed_ll2_set_fragment_of_tx_packet(void *cxt,
u8 connection_handle,
dma_addr_t addr, u16 nbytes);
/**
* @brief qed_ll2_terminate_connection - stops Tx/Rx queues
* qed_ll2_terminate_connection(): Stops Tx/Rx queues
*
* @cxt: Pointer to the hw-function [opaque to some].
* @connection_handle: LL2 connection's handle obtained from
* qed_ll2_require_connection.
*
* @param cxt - pointer to the hw-function [opaque to some]
* @param connection_handle LL2 connection's handle
* obtained from
* qed_ll2_require_connection
*
* @return 0 on success, failure otherwise
* Return: 0 on success, failure otherwise.
*/
int qed_ll2_terminate_connection(void *cxt, u8 connection_handle);
/**
* @brief qed_ll2_get_stats - get LL2 queue's statistics
* qed_ll2_get_stats(): Get LL2 queue's statistics
*
* @cxt: Pointer to the hw-function [opaque to some].
* @connection_handle: LL2 connection's handle obtained from
* qed_ll2_require_connection.
* @p_stats: Pointer Status.
*
* @param cxt - pointer to the hw-function [opaque to some]
* @param connection_handle LL2 connection's handle obtained from
* qed_ll2_require_connection
* @param p_stats
*
* @return 0 on success, failure otherwise
* Return: 0 on success, failure otherwise.
*/
int qed_ll2_get_stats(void *cxt,
u8 connection_handle, struct qed_ll2_stats *p_stats);
/**
* @brief qed_ll2_alloc - Allocates LL2 connections set
* qed_ll2_alloc(): Allocates LL2 connections set.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_ll2_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_ll2_setup - Inits LL2 connections set
* qed_ll2_setup(): Inits LL2 connections set.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*
*/
void qed_ll2_setup(struct qed_hwfn *p_hwfn);
/**
* @brief qed_ll2_free - Releases LL2 connections set
* qed_ll2_free(): Releases LL2 connections set
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*
*/
void qed_ll2_free(struct qed_hwfn *p_hwfn);

21
drivers/net/ethernet/qlogic/qed/qed_main.c
View File

@ -99,10 +99,6 @@ static const u32 qed_mfw_ext_10g[] __initconst = {
ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
};
static const u32 qed_mfw_ext_20g[] __initconst = {
ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
};
static const u32 qed_mfw_ext_25g[] __initconst = {
ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
@ -148,7 +144,6 @@ static const u32 qed_mfw_ext_100g_base_r4[] __initconst = {
static struct qed_mfw_speed_map qed_mfw_ext_maps[] __ro_after_init = {
QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_1G, qed_mfw_ext_1g),
QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_10G, qed_mfw_ext_10g),
QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_20G, qed_mfw_ext_20g),
QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_25G, qed_mfw_ext_25g),
QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_40G, qed_mfw_ext_40g),
QED_MFW_SPEED_MAP(ETH_EXT_ADV_SPEED_50G_BASE_R,
@ -262,7 +257,7 @@ module_exit(qed_exit);
/* Check if the DMA controller on the machine can properly handle the DMA
* addressing required by the device.
*/
*/
static int qed_set_coherency_mask(struct qed_dev *cdev)
{
struct device *dev = &cdev->pdev->dev;
@ -547,7 +542,7 @@ static struct qed_dev *qed_probe(struct pci_dev *pdev,
goto err2;
}
DP_INFO(cdev, "qed_probe completed successfully\n");
DP_INFO(cdev, "%s completed successfully\n", __func__);
return cdev;
@ -980,7 +975,7 @@ static int qed_slowpath_setup_int(struct qed_dev *cdev,
rc = qed_set_int_mode(cdev, false);
if (rc) {
DP_ERR(cdev, "qed_slowpath_setup_int ERR\n");
DP_ERR(cdev, "%s ERR\n", __func__);
return rc;
}
@ -1161,6 +1156,7 @@ static int qed_slowpath_delayed_work(struct qed_hwfn *hwfn,
/* Memory barrier for setting atomic bit */
smp_mb__before_atomic();
set_bit(wq_flag, &hwfn->slowpath_task_flags);
/* Memory barrier after setting atomic bit */
smp_mb__after_atomic();
queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, delay);
@ -1381,7 +1377,7 @@ static int qed_slowpath_start(struct qed_dev *cdev,
(params->drv_minor << 16) |
(params->drv_rev << 8) |
(params->drv_eng);
strlcpy(drv_version.name, params->name,
strscpy(drv_version.name, params->name,
MCP_DRV_VER_STR_SIZE - 4);
rc = qed_mcp_send_drv_version(hwfn, hwfn->p_main_ptt,
&drv_version);
@ -3078,8 +3074,10 @@ int qed_mfw_tlv_req(struct qed_hwfn *hwfn)
DP_VERBOSE(hwfn->cdev, NETIF_MSG_DRV,
"Scheduling slowpath task [Flag: %d]\n",
QED_SLOWPATH_MFW_TLV_REQ);
/* Memory barrier for setting atomic bit */
smp_mb__before_atomic();
set_bit(QED_SLOWPATH_MFW_TLV_REQ, &hwfn->slowpath_task_flags);
/* Memory barrier after setting atomic bit */
smp_mb__after_atomic();
queue_delayed_work(hwfn->slowpath_wq, &hwfn->slowpath_task, 0);
@ -3158,3 +3156,8 @@ int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, enum qed_mfw_tlv_type type,
return 0;
}
unsigned long qed_get_epoch_time(void)
{
return ktime_get_real_seconds();
}

64
drivers/net/ethernet/qlogic/qed/qed_mcp.c
View File

@ -17,6 +17,7 @@
#include "qed_cxt.h"
#include "qed_dcbx.h"
#include "qed_hsi.h"
#include "qed_mfw_hsi.h"
#include "qed_hw.h"
#include "qed_mcp.h"
#include "qed_reg_addr.h"
@ -30,11 +31,11 @@
#define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
#define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset)), \
_val)
#define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset)))
#define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
@ -384,7 +385,7 @@ qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
/* Get the union data */
if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
if (p_mb_params->p_data_dst && p_mb_params->data_dst_size) {
u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
offsetof(struct public_drv_mb,
union_data);
@ -410,7 +411,7 @@ static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
offsetof(struct public_drv_mb, union_data);
memset(&union_data, 0, sizeof(union_data));
if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
if (p_mb_params->p_data_src && p_mb_params->data_src_size)
memcpy(&union_data, p_mb_params->p_data_src,
p_mb_params->data_src_size);
qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
@ -671,7 +672,8 @@ int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
u32 cmd,
u32 param,
u32 *o_mcp_resp,
u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
u32 *o_mcp_param,
u32 *o_txn_size, u32 *o_buf, bool b_can_sleep)
{
struct qed_mcp_mb_params mb_params;
u8 raw_data[MCP_DRV_NVM_BUF_LEN];
@ -684,6 +686,8 @@ int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
/* Use the maximal value since the actual one is part of the response */
mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
if (b_can_sleep)
mb_params.flags = QED_MB_FLAG_CAN_SLEEP;
rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
if (rc)
@ -916,7 +920,6 @@ enum qed_load_req_force {
};
static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
enum qed_load_req_force force_cmd,
u8 *p_mfw_force_cmd)
{
@ -1526,15 +1529,13 @@ int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
FW_MB_PARAM_FEATURE_SUPPORT_EXT_SPEED_FEC_CONTROL) {
ext_speed = 0;
if (params->ext_speed.autoneg)
ext_speed |= ETH_EXT_SPEED_AN;
ext_speed |= ETH_EXT_SPEED_NONE;
val = params->ext_speed.forced_speed;
if (val & QED_EXT_SPEED_1G)
ext_speed |= ETH_EXT_SPEED_1G;
if (val & QED_EXT_SPEED_10G)
ext_speed |= ETH_EXT_SPEED_10G;
if (val & QED_EXT_SPEED_20G)
ext_speed |= ETH_EXT_SPEED_20G;
if (val & QED_EXT_SPEED_25G)
ext_speed |= ETH_EXT_SPEED_25G;
if (val & QED_EXT_SPEED_40G)
@ -1560,8 +1561,6 @@ int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
ext_speed |= ETH_EXT_ADV_SPEED_1G;
if (val & QED_EXT_SPEED_MASK_10G)
ext_speed |= ETH_EXT_ADV_SPEED_10G;
if (val & QED_EXT_SPEED_MASK_20G)
ext_speed |= ETH_EXT_ADV_SPEED_20G;
if (val & QED_EXT_SPEED_MASK_25G)
ext_speed |= ETH_EXT_ADV_SPEED_25G;
if (val & QED_EXT_SPEED_MASK_40G)
@ -2081,7 +2080,7 @@ int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt,
u32 *p_mfw_ver, u32 *p_running_bundle_id)
{
u32 global_offsize;
u32 global_offsize, public_base;
if (IS_VF(p_hwfn->cdev)) {
if (p_hwfn->vf_iov_info) {
@ -2098,16 +2097,16 @@ int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
}
}
public_base = p_hwfn->mcp_info->public_base;
global_offsize = qed_rd(p_hwfn, p_ptt,
SECTION_OFFSIZE_ADDR(p_hwfn->
mcp_info->public_base,
SECTION_OFFSIZE_ADDR(public_base,
PUBLIC_GLOBAL));
*p_mfw_ver =
qed_rd(p_hwfn, p_ptt,
SECTION_ADDR(global_offsize,
0) + offsetof(struct public_global, mfw_ver));
if (p_running_bundle_id != NULL) {
if (p_running_bundle_id) {
*p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
SECTION_ADDR(global_offsize, 0) +
offsetof(struct public_global,
@ -2209,6 +2208,7 @@ int qed_mcp_get_transceiver_data(struct qed_hwfn *p_hwfn,
return 0;
}
static bool qed_is_transceiver_ready(u32 transceiver_state,
u32 transceiver_type)
{
@ -2378,7 +2378,7 @@ qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
"According to Legacy capabilities, L2 personality is %08x\n",
(u32) *p_proto);
(u32)*p_proto);
}
static int
@ -2423,7 +2423,7 @@ qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
DP_VERBOSE(p_hwfn,
NETIF_MSG_IFUP,
"According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
(u32) *p_proto, resp, param);
(u32)*p_proto, resp, param);
return 0;
}
@ -2445,9 +2445,6 @@ qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
case FUNC_MF_CFG_PROTOCOL_ISCSI:
*p_proto = QED_PCI_ISCSI;
break;
case FUNC_MF_CFG_PROTOCOL_NVMETCP:
*p_proto = QED_PCI_NVMETCP;
break;
case FUNC_MF_CFG_PROTOCOL_FCOE:
*p_proto = QED_PCI_FCOE;
break;
@ -3026,7 +3023,7 @@ int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
DRV_MB_PARAM_NVM_LEN_OFFSET),
&resp, &resp_param,
&read_len,
(u32 *)(p_buf + offset));
(u32 *)(p_buf + offset), false);
if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
@ -3034,7 +3031,7 @@ int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
}
/* This can be a lengthy process, and it's possible scheduler
* isn't preemptable. Sleep a bit to prevent CPU hogging.
* isn't preemptible. Sleep a bit to prevent CPU hogging.
*/
if (bytes_left % 0x1000 <
(bytes_left - read_len) % 0x1000)
@ -3129,10 +3126,12 @@ int qed_mcp_nvm_write(struct qed_dev *cdev,
* to be delivered to MFW.
*/
if (param && cmd == QED_PUT_FILE_DATA) {
buf_idx = QED_MFW_GET_FIELD(param,
FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET);
buf_size = QED_MFW_GET_FIELD(param,
FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE);
buf_idx =
QED_MFW_GET_FIELD(param,
FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET);
buf_size =
QED_MFW_GET_FIELD(param,
FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE);
} else {
buf_idx += buf_size;
buf_size = min_t(u32, (len - buf_idx),
@ -3176,7 +3175,7 @@ int qed_mcp_phy_sfp_read(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
DRV_MSG_CODE_TRANSCEIVER_READ,
nvm_offset, &resp, &param, &buf_size,
(u32 *)(p_buf + offset));
(u32 *)(p_buf + offset), true);
if (rc) {
DP_NOTICE(p_hwfn,
"Failed to send a transceiver read command to the MFW. rc = %d.\n",
@ -3275,7 +3274,7 @@ int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
DRV_MSG_CODE_BIST_TEST, param,
&resp, &resp_param,
&buf_size,
(u32 *)p_image_att);
(u32 *)p_image_att, false);
if (rc)
return rc;
@ -3388,7 +3387,7 @@ qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
type = NVM_TYPE_DEFAULT_CFG;
break;
case QED_NVM_IMAGE_NVM_META:
type = NVM_TYPE_META;
type = NVM_TYPE_NVM_META;
break;
default:
DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
@ -3905,10 +3904,6 @@ int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK |
DRV_MB_PARAM_FEATURE_SUPPORT_PORT_FEC_CONTROL;
if (QED_IS_E5(p_hwfn->cdev))
features |=
DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EXT_SPEED_FEC_CONTROL;
return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
features, &mcp_resp, &mcp_param);
}
@ -4002,7 +3997,8 @@ int qed_mcp_nvm_get_cfg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
DRV_MSG_CODE_GET_NVM_CFG_OPTION,
mb_param, &resp, &param, p_len, (u32 *)p_buf);
mb_param, &resp, &param, p_len,
(u32 *)p_buf, false);
return rc;
}

761
drivers/net/ethernet/qlogic/qed/qed_mcp.h
View File

File diff suppressed because it is too large Load Diff

2474
drivers/net/ethernet/qlogic/qed/qed_mfw_hsi.h Normal file
View File

File diff suppressed because it is too large Load Diff

7
drivers/net/ethernet/qlogic/qed/qed_rdma.c
View File

@ -22,6 +22,7 @@
#include "qed.h"
#include "qed_cxt.h"
#include "qed_hsi.h"
#include "qed_iro_hsi.h"
#include "qed_hw.h"
#include "qed_init_ops.h"
#include "qed_int.h"
@ -33,7 +34,6 @@
#include "qed_roce.h"
#include "qed_sp.h"
int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
struct qed_bmap *bmap, u32 max_count, char *name)
{
@ -865,8 +865,8 @@ static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod)
}
qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset;
addr = GTT_BAR0_MAP_REG_USDM_RAM +
USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num);
addr = GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_USDM_RAM,
USTORM_COMMON_QUEUE_CONS, qz_num);
REG_WR16(p_hwfn, addr, prod);
@ -1903,7 +1903,6 @@ void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm);
}
void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
p_hwfn->db_bar_no_edpm = true;

7
drivers/net/ethernet/qlogic/qed/qed_rdma.h
View File

@ -168,16 +168,19 @@ static inline bool qed_rdma_is_xrc_qp(struct qed_rdma_qp *qp)
return false;
}
#if IS_ENABLED(CONFIG_QED_RDMA)
void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn);
void qed_rdma_info_free(struct qed_hwfn *p_hwfn);
#else
static inline void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) {}
static inline void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt) {}
static inline void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt) {}
static inline int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn) {return -EINVAL;}
static inline int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn)
{return -EINVAL; }
static inline void qed_rdma_info_free(struct qed_hwfn *p_hwfn) {}
#endif

95
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
View File

@ -126,6 +126,8 @@
0x1009c4UL
#define QM_REG_PF_EN \
0x2f2ea4UL
#define QM_REG_RLGLBLUPPERBOUND \
0x2f3c00UL
#define TCFC_REG_WEAK_ENABLE_VF \
0x2d0704UL
#define TCFC_REG_STRONG_ENABLE_PF \
@ -576,7 +578,7 @@
#define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
#define PRS_REG_GRE_PROTOCOL 0x1f0734UL
#define PRS_REG_VXLAN_PORT 0x1f0738UL
#define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL
#define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
#define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
#define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
@ -595,8 +597,8 @@
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
#define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
#define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2 0x10092cUL
#define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2 0x100930UL
#define NIG_REG_NGE_IP_ENABLE 0x508b28UL
#define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
@ -606,7 +608,10 @@
#define QM_REG_WFQPFWEIGHT 0x2f4e80UL
#define QM_REG_WFQVPWEIGHT 0x2fa000UL
#define QM_REG_WFQVPUPPERBOUND \
0x2fb000UL
#define QM_REG_WFQVPCRD \
0x2fc000UL
#define PGLCS_REG_DBG_SELECT_K2_E5 \
0x001d14UL
#define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \
@ -1437,29 +1442,29 @@
0x1401140UL
#define XSEM_REG_SYNC_DBG_EMPTY \
0x1401160UL
#define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
#define XSEM_REG_SLOW_DBG_ACTIVE \
0x1401400UL
#define XSEM_REG_SLOW_DBG_MODE_BB_K2 \
#define XSEM_REG_SLOW_DBG_MODE \
0x1401404UL
#define XSEM_REG_DBG_FRAME_MODE_BB_K2 \
#define XSEM_REG_DBG_FRAME_MODE \
0x1401408UL
#define XSEM_REG_DBG_GPRE_VECT \
0x1401410UL
#define XSEM_REG_DBG_MODE1_CFG_BB_K2 \
#define XSEM_REG_DBG_MODE1_CFG \
0x1401420UL
#define XSEM_REG_FAST_MEMORY \
0x1440000UL
#define YSEM_REG_SYNC_DBG_EMPTY \
0x1501160UL
#define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
#define YSEM_REG_SLOW_DBG_ACTIVE \
0x1501400UL
#define YSEM_REG_SLOW_DBG_MODE_BB_K2 \
#define YSEM_REG_SLOW_DBG_MODE \
0x1501404UL
#define YSEM_REG_DBG_FRAME_MODE_BB_K2 \
#define YSEM_REG_DBG_FRAME_MODE \
0x1501408UL
#define YSEM_REG_DBG_GPRE_VECT \
0x1501410UL
#define YSEM_REG_DBG_MODE1_CFG_BB_K2 \
#define YSEM_REG_DBG_MODE1_CFG \
0x1501420UL
#define YSEM_REG_FAST_MEMORY \
0x1540000UL
@ -1467,15 +1472,15 @@
0x1601140UL
#define PSEM_REG_SYNC_DBG_EMPTY \
0x1601160UL
#define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
#define PSEM_REG_SLOW_DBG_ACTIVE \
0x1601400UL
#define PSEM_REG_SLOW_DBG_MODE_BB_K2 \
#define PSEM_REG_SLOW_DBG_MODE \
0x1601404UL
#define PSEM_REG_DBG_FRAME_MODE_BB_K2 \
#define PSEM_REG_DBG_FRAME_MODE \
0x1601408UL
#define PSEM_REG_DBG_GPRE_VECT \
0x1601410UL
#define PSEM_REG_DBG_MODE1_CFG_BB_K2 \
#define PSEM_REG_DBG_MODE1_CFG \
0x1601420UL
#define PSEM_REG_FAST_MEMORY \
0x1640000UL
@ -1483,15 +1488,15 @@
0x1701140UL
#define TSEM_REG_SYNC_DBG_EMPTY \
0x1701160UL
#define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
#define TSEM_REG_SLOW_DBG_ACTIVE \
0x1701400UL
#define TSEM_REG_SLOW_DBG_MODE_BB_K2 \
#define TSEM_REG_SLOW_DBG_MODE \
0x1701404UL
#define TSEM_REG_DBG_FRAME_MODE_BB_K2 \
#define TSEM_REG_DBG_FRAME_MODE \
0x1701408UL
#define TSEM_REG_DBG_GPRE_VECT \
0x1701410UL
#define TSEM_REG_DBG_MODE1_CFG_BB_K2 \
#define TSEM_REG_DBG_MODE1_CFG \
0x1701420UL
#define TSEM_REG_FAST_MEMORY \
0x1740000UL
@ -1499,15 +1504,15 @@
0x1801140UL
#define MSEM_REG_SYNC_DBG_EMPTY \
0x1801160UL
#define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
#define MSEM_REG_SLOW_DBG_ACTIVE \
0x1801400UL
#define MSEM_REG_SLOW_DBG_MODE_BB_K2 \
#define MSEM_REG_SLOW_DBG_MODE \
0x1801404UL
#define MSEM_REG_DBG_FRAME_MODE_BB_K2 \
#define MSEM_REG_DBG_FRAME_MODE \
0x1801408UL
#define MSEM_REG_DBG_GPRE_VECT \
0x1801410UL
#define MSEM_REG_DBG_MODE1_CFG_BB_K2 \
#define MSEM_REG_DBG_MODE1_CFG \
0x1801420UL
#define MSEM_REG_FAST_MEMORY \
0x1840000UL
@ -1517,21 +1522,21 @@
20480
#define USEM_REG_SYNC_DBG_EMPTY \
0x1901160UL
#define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
#define USEM_REG_SLOW_DBG_ACTIVE \
0x1901400UL
#define USEM_REG_SLOW_DBG_MODE_BB_K2 \
#define USEM_REG_SLOW_DBG_MODE \
0x1901404UL
#define USEM_REG_DBG_FRAME_MODE_BB_K2 \
#define USEM_REG_DBG_FRAME_MODE \
0x1901408UL
#define USEM_REG_DBG_GPRE_VECT \
0x1901410UL
#define USEM_REG_DBG_MODE1_CFG_BB_K2 \
#define USEM_REG_DBG_MODE1_CFG \
0x1901420UL
#define USEM_REG_FAST_MEMORY \
0x1940000UL
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \
0x000748UL
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE \
#define SEM_FAST_REG_DBG_MODSRC_DISABLE \
0x00074cUL
#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \
0x000750UL
@ -1561,7 +1566,7 @@
0x341500UL
#define BRB_REG_BIG_RAM_DATA_SIZE \
64
#define SEM_FAST_REG_STALL_0_BB_K2 \
#define SEM_FAST_REG_STALL_0 \
0x000488UL
#define SEM_FAST_REG_STALLED \
0x000494UL
@ -1619,35 +1624,35 @@
0x008c14UL
#define NWS_REG_NWS_CMU_K2 \
0x720000UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5 \
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 \
0x000680UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5 \
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 \
0x000684UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5 \
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 \
0x0006c0UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 \
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 \
0x0006c4UL
#define MS_REG_MS_CMU_K2_E5 \
#define MS_REG_MS_CMU_K2 \
0x6a4000UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 \
0x000208UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 \
0x00020cUL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 \
0x000210UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 \
0x000214UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 \
0x000208UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 \
0x00020cUL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 \
0x000210UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 \
0x000214UL
#define PHY_PCIE_REG_PHY0_K2_E5 \
#define PHY_PCIE_REG_PHY0_K2 \
0x620000UL
#define PHY_PCIE_REG_PHY1_K2_E5 \
#define PHY_PCIE_REG_PHY1_K2 \
0x624000UL
#define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL

1
drivers/net/ethernet/qlogic/qed/qed_roce.c
View File

@ -792,7 +792,6 @@ static int qed_roce_sp_destroy_qp_requester(struct qed_hwfn *p_hwfn,
if (rc)
goto err;
/* Free ORQ - only if ramrod succeeded, in case FW is still using it */
dma_free_coherent(&p_hwfn->cdev->pdev->dev,
qp->orq_num_pages * RDMA_RING_PAGE_SIZE,

30
drivers/net/ethernet/qlogic/qed/qed_selftest.h
View File

@ -6,47 +6,47 @@
#include <linux/types.h>
/**
* @brief qed_selftest_memory - Perform memory test
* qed_selftest_memory(): Perform memory test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return int
* Return: Int.
*/
int qed_selftest_memory(struct qed_dev *cdev);
/**
* @brief qed_selftest_interrupt - Perform interrupt test
* qed_selftest_interrupt(): Perform interrupt test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return int
* Return: Int.
*/
int qed_selftest_interrupt(struct qed_dev *cdev);
/**
* @brief qed_selftest_register - Perform register test
* qed_selftest_register(): Perform register test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return int
* Return: Int.
*/
int qed_selftest_register(struct qed_dev *cdev);
/**
* @brief qed_selftest_clock - Perform clock test
* qed_selftest_clock(): Perform clock test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return int
* Return: Int.
*/
int qed_selftest_clock(struct qed_dev *cdev);
/**
* @brief qed_selftest_nvram - Perform nvram test
* qed_selftest_nvram(): Perform nvram test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return int
* Return: Int.
*/
int qed_selftest_nvram(struct qed_dev *cdev);

223
drivers/net/ethernet/qlogic/qed/qed_sp.h
View File

@ -23,31 +23,26 @@ enum spq_mode {
};
struct qed_spq_comp_cb {
void (*function)(struct qed_hwfn *,
void *,
union event_ring_data *,
void (*function)(struct qed_hwfn *p_hwfn,
void *cookie,
union event_ring_data *data,
u8 fw_return_code);
void *cookie;
};
/**
* @brief qed_eth_cqe_completion - handles the completion of a
* ramrod on the cqe ring
* qed_eth_cqe_completion(): handles the completion of a
* ramrod on the cqe ring.
*
* @param p_hwfn
* @param cqe
* @p_hwfn: HW device data.
* @cqe: CQE.
*
* @return int
* Return: Int.
*/
int qed_eth_cqe_completion(struct qed_hwfn *p_hwfn,
struct eth_slow_path_rx_cqe *cqe);
/**
* @file
*
* QED Slow-hwfn queue interface
*/
/* QED Slow-hwfn queue interface */
union ramrod_data {
struct pf_start_ramrod_data pf_start;
struct pf_update_ramrod_data pf_update;
@ -58,7 +53,7 @@ union ramrod_data {
struct tx_queue_stop_ramrod_data tx_queue_stop;
struct vport_start_ramrod_data vport_start;
struct vport_stop_ramrod_data vport_stop;
struct rx_update_gft_filter_data rx_update_gft;
struct rx_update_gft_filter_ramrod_data rx_update_gft;
struct vport_update_ramrod_data vport_update;
struct core_rx_start_ramrod_data core_rx_queue_start;
struct core_rx_stop_ramrod_data core_rx_queue_stop;
@ -207,117 +202,128 @@ struct qed_spq {
};
/**
* @brief qed_spq_post - Posts a Slow hwfn request to FW, or lacking that
* Pends it to the future list.
* qed_spq_post(): Posts a Slow hwfn request to FW, or lacking that
* Pends it to the future list.
*
* @param p_hwfn
* @param p_req
* @p_hwfn: HW device data.
* @p_ent: Ent.
* @fw_return_code: Return code from firmware.
*
* @return int
* Return: Int.
*/
int qed_spq_post(struct qed_hwfn *p_hwfn,
struct qed_spq_entry *p_ent,
u8 *fw_return_code);
/**
* @brief qed_spq_allocate - Alloocates & initializes the SPQ and EQ.
* qed_spq_alloc(): Alloocates & initializes the SPQ and EQ.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_spq_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_spq_setup - Reset the SPQ to its start state.
* qed_spq_setup(): Reset the SPQ to its start state.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_spq_setup(struct qed_hwfn *p_hwfn);
/**
* @brief qed_spq_deallocate - Deallocates the given SPQ struct.
* qed_spq_free(): Deallocates the given SPQ struct.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_spq_free(struct qed_hwfn *p_hwfn);
/**
* @brief qed_spq_get_entry - Obtain an entrry from the spq
* free pool list.
* qed_spq_get_entry(): Obtain an entrry from the spq
* free pool list.
*
* @p_hwfn: HW device data.
* @pp_ent: PP ENT.
*
*
* @param p_hwfn
* @param pp_ent
*
* @return int
* Return: Int.
*/
int
qed_spq_get_entry(struct qed_hwfn *p_hwfn,
struct qed_spq_entry **pp_ent);
/**
* @brief qed_spq_return_entry - Return an entry to spq free
* pool list
* qed_spq_return_entry(): Return an entry to spq free pool list.
*
* @param p_hwfn
* @param p_ent
* @p_hwfn: HW device data.
* @p_ent: P ENT.
*
* Return: Void.
*/
void qed_spq_return_entry(struct qed_hwfn *p_hwfn,
struct qed_spq_entry *p_ent);
/**
* @brief qed_eq_allocate - Allocates & initializes an EQ struct
* qed_eq_alloc(): Allocates & initializes an EQ struct.
*
* @param p_hwfn
* @param num_elem number of elements in the eq
* @p_hwfn: HW device data.
* @num_elem: number of elements in the eq.
*
* @return int
* Return: Int.
*/
int qed_eq_alloc(struct qed_hwfn *p_hwfn, u16 num_elem);
/**
* @brief qed_eq_setup - Reset the EQ to its start state.
* qed_eq_setup(): Reset the EQ to its start state.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_eq_setup(struct qed_hwfn *p_hwfn);
/**
* @brief qed_eq_free - deallocates the given EQ struct.
* qed_eq_free(): deallocates the given EQ struct.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_eq_free(struct qed_hwfn *p_hwfn);
/**
* @brief qed_eq_prod_update - update the FW with default EQ producer
* qed_eq_prod_update(): update the FW with default EQ producer.
*
* @param p_hwfn
* @param prod
* @p_hwfn: HW device data.
* @prod: Prod.
*
* Return: Void.
*/
void qed_eq_prod_update(struct qed_hwfn *p_hwfn,
u16 prod);
/**
* @brief qed_eq_completion - Completes currently pending EQ elements
* qed_eq_completion(): Completes currently pending EQ elements.
*
* @param p_hwfn
* @param cookie
* @p_hwfn: HW device data.
* @cookie: Cookie.
*
* @return int
* Return: Int.
*/
int qed_eq_completion(struct qed_hwfn *p_hwfn,
void *cookie);
/**
* @brief qed_spq_completion - Completes a single event
* qed_spq_completion(): Completes a single event.
*
* @param p_hwfn
* @param echo - echo value from cookie (used for determining completion)
* @param p_data - data from cookie (used in callback function if applicable)
* @p_hwfn: HW device data.
* @echo: echo value from cookie (used for determining completion).
* @fw_return_code: FW return code.
* @p_data: data from cookie (used in callback function if applicable).
*
* @return int
* Return: Int.
*/
int qed_spq_completion(struct qed_hwfn *p_hwfn,
__le16 echo,
@ -325,44 +331,43 @@ int qed_spq_completion(struct qed_hwfn *p_hwfn,
union event_ring_data *p_data);
/**
* @brief qed_spq_get_cid - Given p_hwfn, return cid for the hwfn's SPQ
* qed_spq_get_cid(): Given p_hwfn, return cid for the hwfn's SPQ.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return u32 - SPQ CID
* Return: u32 - SPQ CID.
*/
u32 qed_spq_get_cid(struct qed_hwfn *p_hwfn);
/**
* @brief qed_consq_alloc - Allocates & initializes an ConsQ
* struct
* qed_consq_alloc(): Allocates & initializes an ConsQ struct.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_consq_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_consq_setup - Reset the ConsQ to its start state.
* qed_consq_setup(): Reset the ConsQ to its start state.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return Void.
*/
void qed_consq_setup(struct qed_hwfn *p_hwfn);
/**
* @brief qed_consq_free - deallocates the given ConsQ struct.
* qed_consq_free(): deallocates the given ConsQ struct.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return Void.
*/
void qed_consq_free(struct qed_hwfn *p_hwfn);
int qed_spq_pend_post(struct qed_hwfn *p_hwfn);
/**
* @file
*
* @brief Slow-hwfn low-level commands (Ramrods) function definitions.
*/
/* Slow-hwfn low-level commands (Ramrods) function definitions. */
#define QED_SP_EQ_COMPLETION 0x01
#define QED_SP_CQE_COMPLETION 0x02
@ -377,12 +382,15 @@ struct qed_sp_init_data {
};
/**
* @brief Returns a SPQ entry to the pool / frees the entry if allocated.
* Should be called on in error flows after initializing the SPQ entry
* and before posting it.
* qed_sp_destroy_request(): Returns a SPQ entry to the pool / frees the
* entry if allocated. Should be called on in error
* flows after initializing the SPQ entry
* and before posting it.
*
* @param p_hwfn
* @param p_ent
* @p_hwfn: HW device data.
* @p_ent: Ent.
*
* Return: Void.
*/
void qed_sp_destroy_request(struct qed_hwfn *p_hwfn,
struct qed_spq_entry *p_ent);
@ -394,7 +402,14 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn,
struct qed_sp_init_data *p_data);
/**
* @brief qed_sp_pf_start - PF Function Start Ramrod
* qed_sp_pf_start(): PF Function Start Ramrod.
*
* @p_hwfn: HW device data.
* @p_ptt: P_ptt.
* @p_tunn: P_tunn.
* @allow_npar_tx_switch: Allow NPAR TX Switch.
*
* Return: Int.
*
* This ramrod is sent to initialize a physical function (PF). It will
* configure the function related parameters and write its completion to the
@ -404,12 +419,6 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn,
* allocated by the driver on host memory and its parameters are written
* to the internal RAM of the UStorm by the Function Start Ramrod.
*
* @param p_hwfn
* @param p_ptt
* @param p_tunn
* @param allow_npar_tx_switch
*
* @return int
*/
int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
@ -418,47 +427,33 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
bool allow_npar_tx_switch);
/**
* @brief qed_sp_pf_update - PF Function Update Ramrod
* qed_sp_pf_update(): PF Function Update Ramrod.
*
* @p_hwfn: HW device data.
*
* Return: Int.
*
* This ramrod updates function-related parameters. Every parameter can be
* updated independently, according to configuration flags.
*
* @param p_hwfn
*
* @return int
*/
int qed_sp_pf_update(struct qed_hwfn *p_hwfn);
/**
* @brief qed_sp_pf_update_stag - Update firmware of new outer tag
* qed_sp_pf_update_stag(): Update firmware of new outer tag.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_sp_pf_update_stag(struct qed_hwfn *p_hwfn);
/**
* @brief qed_sp_pf_stop - PF Function Stop Ramrod
* qed_sp_pf_update_ufp(): PF ufp update Ramrod.
*
* This ramrod is sent to close a Physical Function (PF). It is the last ramrod
* sent and the last completion written to the PFs Event Ring. This ramrod also
* deletes the context for the Slowhwfn connection on this PF.
* @p_hwfn: HW device data.
*
* @note Not required for first packet.
*
* @param p_hwfn
*
* @return int
*/
/**
* @brief qed_sp_pf_update_ufp - PF ufp update Ramrod
*
* @param p_hwfn
*
* @return int
* Return: Int.
*/
int qed_sp_pf_update_ufp(struct qed_hwfn *p_hwfn);
@ -470,11 +465,11 @@ int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
enum spq_mode comp_mode,
struct qed_spq_comp_cb *p_comp_data);
/**
* @brief qed_sp_heartbeat_ramrod - Send empty Ramrod
* qed_sp_heartbeat_ramrod(): Send empty Ramrod.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn);

10
drivers/net/ethernet/qlogic/qed/qed_sp_commands.c
View File

@ -369,8 +369,12 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
qed_chain_get_pbl_phys(&p_hwfn->p_eq->chain));
page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_eq->chain);
p_ramrod->event_ring_num_pages = page_cnt;
DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_addr,
/* Place consolidation queue address in ramrod */
DMA_REGPAIR_LE(p_ramrod->consolid_q_pbl_base_addr,
qed_chain_get_pbl_phys(&p_hwfn->p_consq->chain));
page_cnt = (u8)qed_chain_get_page_cnt(&p_hwfn->p_consq->chain);
p_ramrod->consolid_q_num_pages = page_cnt;
qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);
@ -401,8 +405,8 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
if (p_hwfn->cdev->p_iov_info) {
struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
p_ramrod->base_vf_id = (u8) p_iov->first_vf_in_pf;
p_ramrod->num_vfs = (u8) p_iov->total_vfs;
p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf;
p_ramrod->num_vfs = (u8)p_iov->total_vfs;
}
p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;

63
drivers/net/ethernet/qlogic/qed/qed_spq.c
View File

@ -20,6 +20,7 @@
#include "qed_cxt.h"
#include "qed_dev_api.h"
#include "qed_hsi.h"
#include "qed_iro_hsi.h"
#include "qed_hw.h"
#include "qed_int.h"
#include "qed_iscsi.h"
@ -31,8 +32,8 @@
#include "qed_rdma.h"
/***************************************************************************
* Structures & Definitions
***************************************************************************/
* Structures & Definitions
***************************************************************************/
#define SPQ_HIGH_PRI_RESERVE_DEFAULT (1)
@ -42,8 +43,8 @@
#define SPQ_BLOCK_SLEEP_MS (5)
/***************************************************************************
* Blocking Imp. (BLOCK/EBLOCK mode)
***************************************************************************/
* Blocking Imp. (BLOCK/EBLOCK mode)
***************************************************************************/
static void qed_spq_blocking_cb(struct qed_hwfn *p_hwfn,
void *cookie,
union event_ring_data *data, u8 fw_return_code)
@ -149,8 +150,8 @@ static int qed_spq_block(struct qed_hwfn *p_hwfn,
}
/***************************************************************************
* SPQ entries inner API
***************************************************************************/
* SPQ entries inner API
***************************************************************************/
static int qed_spq_fill_entry(struct qed_hwfn *p_hwfn,
struct qed_spq_entry *p_ent)
{
@ -184,12 +185,12 @@ static int qed_spq_fill_entry(struct qed_hwfn *p_hwfn,
}
/***************************************************************************
* HSI access
***************************************************************************/
* HSI access
***************************************************************************/
static void qed_spq_hw_initialize(struct qed_hwfn *p_hwfn,
struct qed_spq *p_spq)
{
struct e4_core_conn_context *p_cxt;
struct core_conn_context *p_cxt;
struct qed_cxt_info cxt_info;
u16 physical_q;
int rc;
@ -207,23 +208,20 @@ static void qed_spq_hw_initialize(struct qed_hwfn *p_hwfn,
p_cxt = cxt_info.p_cxt;
SET_FIELD(p_cxt->xstorm_ag_context.flags10,
E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);
XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN, 1);
SET_FIELD(p_cxt->xstorm_ag_context.flags1,
E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);
XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE, 1);
SET_FIELD(p_cxt->xstorm_ag_context.flags9,
E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);
XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN, 1);
/* QM physical queue */
physical_q = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB);
p_cxt->xstorm_ag_context.physical_q0 = cpu_to_le16(physical_q);
p_cxt->xstorm_st_context.spq_base_lo =
p_cxt->xstorm_st_context.spq_base_addr.lo =
DMA_LO_LE(p_spq->chain.p_phys_addr);
p_cxt->xstorm_st_context.spq_base_hi =
p_cxt->xstorm_st_context.spq_base_addr.hi =
DMA_HI_LE(p_spq->chain.p_phys_addr);
DMA_REGPAIR_LE(p_cxt->xstorm_st_context.consolid_base_addr,
p_hwfn->p_consq->chain.p_phys_addr);
}
static int qed_spq_hw_post(struct qed_hwfn *p_hwfn,
@ -265,8 +263,8 @@ static int qed_spq_hw_post(struct qed_hwfn *p_hwfn,
}
/***************************************************************************
* Asynchronous events
***************************************************************************/
* Asynchronous events
***************************************************************************/
static int
qed_async_event_completion(struct qed_hwfn *p_hwfn,
struct event_ring_entry *p_eqe)
@ -311,12 +309,12 @@ qed_spq_unregister_async_cb(struct qed_hwfn *p_hwfn,
}
/***************************************************************************
* EQ API
***************************************************************************/
* EQ API
***************************************************************************/
void qed_eq_prod_update(struct qed_hwfn *p_hwfn, u16 prod)
{
u32 addr = GTT_BAR0_MAP_REG_USDM_RAM +
USTORM_EQE_CONS_OFFSET(p_hwfn->rel_pf_id);
u32 addr = GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_USDM_RAM,
USTORM_EQE_CONS, p_hwfn->rel_pf_id);
REG_WR16(p_hwfn, addr, prod);
}
@ -433,8 +431,8 @@ void qed_eq_free(struct qed_hwfn *p_hwfn)
}
/***************************************************************************
* CQE API - manipulate EQ functionality
***************************************************************************/
* CQE API - manipulate EQ functionality
***************************************************************************/
static int qed_cqe_completion(struct qed_hwfn *p_hwfn,
struct eth_slow_path_rx_cqe *cqe,
enum protocol_type protocol)
@ -464,8 +462,8 @@ int qed_eth_cqe_completion(struct qed_hwfn *p_hwfn,
}
/***************************************************************************
* Slow hwfn Queue (spq)
***************************************************************************/
* Slow hwfn Queue (spq)
***************************************************************************/
void qed_spq_setup(struct qed_hwfn *p_hwfn)
{
struct qed_spq *p_spq = p_hwfn->p_spq;
@ -548,7 +546,7 @@ int qed_spq_alloc(struct qed_hwfn *p_hwfn)
int ret;
/* SPQ struct */
p_spq = kzalloc(sizeof(struct qed_spq), GFP_KERNEL);
p_spq = kzalloc(sizeof(*p_spq), GFP_KERNEL);
if (!p_spq)
return -ENOMEM;
@ -676,7 +674,6 @@ static int qed_spq_add_entry(struct qed_hwfn *p_hwfn,
struct qed_spq *p_spq = p_hwfn->p_spq;
if (p_ent->queue == &p_spq->unlimited_pending) {
if (list_empty(&p_spq->free_pool)) {
list_add_tail(&p_ent->list, &p_spq->unlimited_pending);
p_spq->unlimited_pending_count++;
@ -725,8 +722,8 @@ static int qed_spq_add_entry(struct qed_hwfn *p_hwfn,
}
/***************************************************************************
* Accessor
***************************************************************************/
* Accessor
***************************************************************************/
u32 qed_spq_get_cid(struct qed_hwfn *p_hwfn)
{
if (!p_hwfn->p_spq)
@ -735,8 +732,8 @@ u32 qed_spq_get_cid(struct qed_hwfn *p_hwfn)
}
/***************************************************************************
* Posting new Ramrods
***************************************************************************/
* Posting new Ramrods
***************************************************************************/
static int qed_spq_post_list(struct qed_hwfn *p_hwfn,
struct list_head *head, u32 keep_reserve)
{

200
drivers/net/ethernet/qlogic/qed/qed_sriov.c
View File

@ -11,6 +11,7 @@
#include <linux/qed/qed_iov_if.h>
#include "qed_cxt.h"
#include "qed_hsi.h"
#include "qed_iro_hsi.h"
#include "qed_hw.h"
#include "qed_init_ops.h"
#include "qed_int.h"
@ -19,12 +20,13 @@
#include "qed_sp.h"
#include "qed_sriov.h"
#include "qed_vf.h"
static int qed_sriov_eqe_event(struct qed_hwfn *p_hwfn,
u8 opcode,
__le16 echo,
union event_ring_data *data, u8 fw_return_code);
static int qed_iov_bulletin_set_mac(struct qed_hwfn *p_hwfn, u8 *mac, int vfid);
static u16 qed_vf_from_entity_id(__le16 entity_id)
{
return le16_to_cpu(entity_id) - MAX_NUM_PFS;
}
static u8 qed_vf_calculate_legacy(struct qed_vf_info *p_vf)
{
u8 legacy = 0;
@ -169,8 +171,8 @@ static struct qed_vf_info *qed_iov_get_vf_info(struct qed_hwfn *p_hwfn,
b_enabled_only, false))
vf = &p_hwfn->pf_iov_info->vfs_array[relative_vf_id];
else
DP_ERR(p_hwfn, "qed_iov_get_vf_info: VF[%d] is not enabled\n",
relative_vf_id);
DP_ERR(p_hwfn, "%s: VF[%d] is not enabled\n",
__func__, relative_vf_id);
return vf;
}
@ -308,7 +310,7 @@ static int qed_iov_post_vf_bulletin(struct qed_hwfn *p_hwfn,
struct qed_dmae_params params;
struct qed_vf_info *p_vf;
p_vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
p_vf = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!p_vf)
return -EINVAL;
@ -420,7 +422,7 @@ static void qed_iov_setup_vfdb(struct qed_hwfn *p_hwfn)
bulletin_p = p_iov_info->bulletins_phys;
if (!p_req_virt_addr || !p_reply_virt_addr || !p_bulletin_virt) {
DP_ERR(p_hwfn,
"qed_iov_setup_vfdb called without allocating mem first\n");
"%s called without allocating mem first\n", __func__);
return;
}
@ -464,7 +466,7 @@ static int qed_iov_allocate_vfdb(struct qed_hwfn *p_hwfn)
num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;
DP_VERBOSE(p_hwfn, QED_MSG_IOV,
"qed_iov_allocate_vfdb for %d VFs\n", num_vfs);
"%s for %d VFs\n", __func__, num_vfs);
/* Allocate PF Mailbox buffer (per-VF) */
p_iov_info->mbx_msg_size = sizeof(union vfpf_tlvs) * num_vfs;
@ -500,10 +502,10 @@ static int qed_iov_allocate_vfdb(struct qed_hwfn *p_hwfn)
QED_MSG_IOV,
"PF's Requests mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys] Bulletins [%p virt 0x%llx phys]\n",
p_iov_info->mbx_msg_virt_addr,
(u64) p_iov_info->mbx_msg_phys_addr,
(u64)p_iov_info->mbx_msg_phys_addr,
p_iov_info->mbx_reply_virt_addr,
(u64) p_iov_info->mbx_reply_phys_addr,
p_iov_info->p_bulletins, (u64) p_iov_info->bulletins_phys);
(u64)p_iov_info->mbx_reply_phys_addr,
p_iov_info->p_bulletins, (u64)p_iov_info->bulletins_phys);
return 0;
}
@ -608,7 +610,7 @@ int qed_iov_hw_info(struct qed_hwfn *p_hwfn)
if (rc)
return rc;
/* We want PF IOV to be synonemous with the existance of p_iov_info;
/* We want PF IOV to be synonemous with the existence of p_iov_info;
* In case the capability is published but there are no VFs, simply
* de-allocate the struct.
*/
@ -714,12 +716,12 @@ static void qed_iov_vf_igu_reset(struct qed_hwfn *p_hwfn,
int i;
/* Set VF masks and configuration - pretend */
qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)vf->concrete_fid);
qed_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_VF_MSG_SENT, 0);
/* unpretend */
qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)p_hwfn->hw_info.concrete_fid);
/* iterate over all queues, clear sb consumer */
for (i = 0; i < vf->num_sbs; i++)
@ -734,7 +736,7 @@ static void qed_iov_vf_igu_set_int(struct qed_hwfn *p_hwfn,
{
u32 igu_vf_conf;
qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)vf->concrete_fid);
igu_vf_conf = qed_rd(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION);
@ -746,7 +748,7 @@ static void qed_iov_vf_igu_set_int(struct qed_hwfn *p_hwfn,
qed_wr(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION, igu_vf_conf);
/* unpretend */
qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)p_hwfn->hw_info.concrete_fid);
}
static int
@ -807,7 +809,7 @@ static int qed_iov_enable_vf_access(struct qed_hwfn *p_hwfn,
if (rc)
return rc;
qed_fid_pretend(p_hwfn, p_ptt, (u16) vf->concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)vf->concrete_fid);
SET_FIELD(igu_vf_conf, IGU_VF_CONF_PARENT, p_hwfn->rel_pf_id);
STORE_RT_REG(p_hwfn, IGU_REG_VF_CONFIGURATION_RT_OFFSET, igu_vf_conf);
@ -816,7 +818,7 @@ static int qed_iov_enable_vf_access(struct qed_hwfn *p_hwfn,
p_hwfn->hw_info.hw_mode);
/* unpretend */
qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)p_hwfn->hw_info.concrete_fid);
vf->state = VF_FREE;
@ -904,7 +906,7 @@ static u8 qed_iov_alloc_vf_igu_sbs(struct qed_hwfn *p_hwfn,
p_block->igu_sb_id * sizeof(u64), 2, NULL);
}
vf->num_sbs = (u8) num_rx_queues;
vf->num_sbs = (u8)num_rx_queues;
return vf->num_sbs;
}
@ -988,7 +990,7 @@ static int qed_iov_init_hw_for_vf(struct qed_hwfn *p_hwfn,
vf = qed_iov_get_vf_info(p_hwfn, p_params->rel_vf_id, false);
if (!vf) {
DP_ERR(p_hwfn, "qed_iov_init_hw_for_vf : vf is NULL\n");
DP_ERR(p_hwfn, "%s : vf is NULL\n", __func__);
return -EINVAL;
}
@ -1092,7 +1094,7 @@ static int qed_iov_release_hw_for_vf(struct qed_hwfn *p_hwfn,
vf = qed_iov_get_vf_info(p_hwfn, rel_vf_id, true);
if (!vf) {
DP_ERR(p_hwfn, "qed_iov_release_hw_for_vf : vf is NULL\n");
DP_ERR(p_hwfn, "%s : vf is NULL\n", __func__);
return -EINVAL;
}
@ -1220,8 +1222,8 @@ static void qed_iov_send_response(struct qed_hwfn *p_hwfn,
* channel would be re-set to ready prior to that.
*/
REG_WR(p_hwfn,
GTT_BAR0_MAP_REG_USDM_RAM +
USTORM_VF_PF_CHANNEL_READY_OFFSET(eng_vf_id), 1);
GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_USDM_RAM,
USTORM_VF_PF_CHANNEL_READY, eng_vf_id), 1);
qed_dmae_host2host(p_hwfn, p_ptt, mbx->reply_phys,
mbx->req_virt->first_tlv.reply_address,
@ -1545,7 +1547,7 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
memset(resp, 0, sizeof(*resp));
/* Write the PF version so that VF would know which version
* is supported - might be later overriden. This guarantees that
* is supported - might be later overridden. This guarantees that
* VF could recognize legacy PF based on lack of versions in reply.
*/
pfdev_info->major_fp_hsi = ETH_HSI_VER_MAJOR;
@ -1603,7 +1605,7 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
/* fill in pfdev info */
pfdev_info->chip_num = p_hwfn->cdev->chip_num;
pfdev_info->db_size = 0;
pfdev_info->indices_per_sb = PIS_PER_SB_E4;
pfdev_info->indices_per_sb = PIS_PER_SB;
pfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |
PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;
@ -1897,7 +1899,7 @@ static void qed_iov_vf_mbx_start_vport(struct qed_hwfn *p_hwfn,
int sb_id;
int rc;
vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vf->relative_vf_id, true);
vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vf->relative_vf_id, true);
if (!vf_info) {
DP_NOTICE(p_hwfn->cdev,
"Failed to get VF info, invalid vfid [%d]\n",
@ -1957,7 +1959,7 @@ static void qed_iov_vf_mbx_start_vport(struct qed_hwfn *p_hwfn,
rc = qed_sp_eth_vport_start(p_hwfn, &params);
if (rc) {
DP_ERR(p_hwfn,
"qed_iov_vf_mbx_start_vport returned error %d\n", rc);
"%s returned error %d\n", __func__, rc);
status = PFVF_STATUS_FAILURE;
} else {
vf->vport_instance++;
@ -1993,8 +1995,8 @@ static void qed_iov_vf_mbx_stop_vport(struct qed_hwfn *p_hwfn,
rc = qed_sp_vport_stop(p_hwfn, vf->opaque_fid, vf->vport_id);
if (rc) {
DP_ERR(p_hwfn, "qed_iov_vf_mbx_stop_vport returned error %d\n",
rc);
DP_ERR(p_hwfn, "%s returned error %d\n",
__func__, rc);
status = PFVF_STATUS_FAILURE;
}
@ -2138,10 +2140,10 @@ static void qed_iov_vf_mbx_start_rxq(struct qed_hwfn *p_hwfn,
* calculate on their own and clean the producer prior to this.
*/
if (!(vf_legacy & QED_QCID_LEGACY_VF_RX_PROD))
REG_WR(p_hwfn,
GTT_BAR0_MAP_REG_MSDM_RAM +
MSTORM_ETH_VF_PRODS_OFFSET(vf->abs_vf_id, req->rx_qid),
0);
qed_wr(p_hwfn, p_ptt, MSEM_REG_FAST_MEMORY +
SEM_FAST_REG_INT_RAM +
MSTORM_ETH_VF_PRODS_OFFSET(vf->abs_vf_id,
req->rx_qid), 0);
rc = qed_eth_rxq_start_ramrod(p_hwfn, p_cid,
req->bd_max_bytes,
@ -3030,7 +3032,7 @@ static void qed_iov_vf_mbx_vport_update(struct qed_hwfn *p_hwfn,
goto out;
}
p_rss_params = vzalloc(sizeof(*p_rss_params));
if (p_rss_params == NULL) {
if (!p_rss_params) {
status = PFVF_STATUS_FAILURE;
goto out;
}
@ -3550,6 +3552,7 @@ static void qed_iov_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
qed_iov_prepare_resp(p_hwfn, p_ptt, vf, CHANNEL_TLV_COALESCE_UPDATE,
sizeof(struct pfvf_def_resp_tlv), status);
}
static int
qed_iov_vf_flr_poll_dorq(struct qed_hwfn *p_hwfn,
struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
@ -3557,7 +3560,7 @@ qed_iov_vf_flr_poll_dorq(struct qed_hwfn *p_hwfn,
int cnt;
u32 val;
qed_fid_pretend(p_hwfn, p_ptt, (u16) p_vf->concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)p_vf->concrete_fid);
for (cnt = 0; cnt < 50; cnt++) {
val = qed_rd(p_hwfn, p_ptt, DORQ_REG_VF_USAGE_CNT);
@ -3565,7 +3568,7 @@ qed_iov_vf_flr_poll_dorq(struct qed_hwfn *p_hwfn,
break;
msleep(20);
}
qed_fid_pretend(p_hwfn, p_ptt, (u16) p_hwfn->hw_info.concrete_fid);
qed_fid_pretend(p_hwfn, p_ptt, (u16)p_hwfn->hw_info.concrete_fid);
if (cnt == 50) {
DP_ERR(p_hwfn,
@ -3577,48 +3580,73 @@ qed_iov_vf_flr_poll_dorq(struct qed_hwfn *p_hwfn,
return 0;
}
#define MAX_NUM_EXT_VOQS (MAX_NUM_PORTS * NUM_OF_TCS)
static int
qed_iov_vf_flr_poll_pbf(struct qed_hwfn *p_hwfn,
struct qed_vf_info *p_vf, struct qed_ptt *p_ptt)
{
u32 cons[MAX_NUM_VOQS_E4], distance[MAX_NUM_VOQS_E4];
int i, cnt;
u32 prod, cons[MAX_NUM_EXT_VOQS], distance[MAX_NUM_EXT_VOQS], tmp;
u8 max_phys_tcs_per_port = p_hwfn->qm_info.max_phys_tcs_per_port;
u8 max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
u32 prod_voq0_addr = PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0;
u32 cons_voq0_addr = PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0;
u8 port_id, tc, tc_id = 0, voq = 0;
int cnt;
memset(cons, 0, MAX_NUM_EXT_VOQS * sizeof(u32));
memset(distance, 0, MAX_NUM_EXT_VOQS * sizeof(u32));
/* Read initial consumers & producers */
for (i = 0; i < MAX_NUM_VOQS_E4; i++) {
u32 prod;
cons[i] = qed_rd(p_hwfn, p_ptt,
PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 +
i * 0x40);
prod = qed_rd(p_hwfn, p_ptt,
PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 +
i * 0x40);
distance[i] = prod - cons[i];
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
/* "max_phys_tcs_per_port" active TCs + 1 pure LB TC */
for (tc = 0; tc < max_phys_tcs_per_port + 1; tc++) {
tc_id = (tc < max_phys_tcs_per_port) ? tc : PURE_LB_TC;
voq = VOQ(port_id, tc_id, max_phys_tcs_per_port);
cons[voq] = qed_rd(p_hwfn, p_ptt,
cons_voq0_addr + voq * 0x40);
prod = qed_rd(p_hwfn, p_ptt,
prod_voq0_addr + voq * 0x40);
distance[voq] = prod - cons[voq];
}
}
/* Wait for consumers to pass the producers */
i = 0;
port_id = 0;
tc = 0;
for (cnt = 0; cnt < 50; cnt++) {
for (; i < MAX_NUM_VOQS_E4; i++) {
u32 tmp;
for (; port_id < max_ports_per_engine; port_id++) {
/* "max_phys_tcs_per_port" active TCs + 1 pure LB TC */
for (; tc < max_phys_tcs_per_port + 1; tc++) {
tc_id = (tc < max_phys_tcs_per_port) ?
tc : PURE_LB_TC;
voq = VOQ(port_id,
tc_id, max_phys_tcs_per_port);
tmp = qed_rd(p_hwfn, p_ptt,
cons_voq0_addr + voq * 0x40);
if (distance[voq] > tmp - cons[voq])
break;
}
tmp = qed_rd(p_hwfn, p_ptt,
PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 +
i * 0x40);
if (distance[i] > tmp - cons[i])
if (tc == max_phys_tcs_per_port + 1)
tc = 0;
else
break;
}
if (i == MAX_NUM_VOQS_E4)
if (port_id == max_ports_per_engine)
break;
msleep(20);
}
if (cnt == 50) {
DP_ERR(p_hwfn, "VF[%d] - pbf polling failed on VOQ %d\n",
p_vf->abs_vf_id, i);
DP_ERR(p_hwfn, "VF[%d]: pbf poll failed on VOQ%d\n",
p_vf->abs_vf_id, (int)voq);
DP_ERR(p_hwfn, "VOQ %d has port_id as %d and tc_id as %d]\n",
(int)voq, (int)port_id, (int)tc_id);
return -EBUSY;
}
@ -3680,8 +3708,8 @@ qed_iov_execute_vf_flr_cleanup(struct qed_hwfn *p_hwfn,
* doesn't do that as a part of FLR.
*/
REG_WR(p_hwfn,
GTT_BAR0_MAP_REG_USDM_RAM +
USTORM_VF_PF_CHANNEL_READY_OFFSET(vfid), 1);
GET_GTT_REG_ADDR(GTT_BAR0_MAP_REG_USDM_RAM,
USTORM_VF_PF_CHANNEL_READY, vfid), 1);
/* VF_STOPPED has to be set only after final cleanup
* but prior to re-enabling the VF.
@ -3842,7 +3870,7 @@ static void qed_iov_process_mbx_req(struct qed_hwfn *p_hwfn,
struct qed_iov_vf_mbx *mbx;
struct qed_vf_info *p_vf;
p_vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
p_vf = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!p_vf)
return;
@ -3979,7 +4007,7 @@ static void qed_iov_pf_get_pending_events(struct qed_hwfn *p_hwfn, u64 *events)
static struct qed_vf_info *qed_sriov_get_vf_from_absid(struct qed_hwfn *p_hwfn,
u16 abs_vfid)
{
u8 min = (u8) p_hwfn->cdev->p_iov_info->first_vf_in_pf;
u8 min = (u8)p_hwfn->cdev->p_iov_info->first_vf_in_pf;
if (!_qed_iov_pf_sanity_check(p_hwfn, (int)abs_vfid - min, false)) {
DP_VERBOSE(p_hwfn,
@ -3989,7 +4017,7 @@ static struct qed_vf_info *qed_sriov_get_vf_from_absid(struct qed_hwfn *p_hwfn,
return NULL;
}
return &p_hwfn->pf_iov_info->vfs_array[(u8) abs_vfid - min];
return &p_hwfn->pf_iov_info->vfs_array[(u8)abs_vfid - min];
}
static int qed_sriov_vfpf_msg(struct qed_hwfn *p_hwfn,
@ -4013,13 +4041,13 @@ static int qed_sriov_vfpf_msg(struct qed_hwfn *p_hwfn,
return 0;
}
static void qed_sriov_vfpf_malicious(struct qed_hwfn *p_hwfn,
struct malicious_vf_eqe_data *p_data)
void qed_sriov_vfpf_malicious(struct qed_hwfn *p_hwfn,
struct fw_err_data *p_data)
{
struct qed_vf_info *p_vf;
p_vf = qed_sriov_get_vf_from_absid(p_hwfn, p_data->vf_id);
p_vf = qed_sriov_get_vf_from_absid(p_hwfn, qed_vf_from_entity_id
(p_data->entity_id));
if (!p_vf)
return;
@ -4036,16 +4064,13 @@ static void qed_sriov_vfpf_malicious(struct qed_hwfn *p_hwfn,
}
}
static int qed_sriov_eqe_event(struct qed_hwfn *p_hwfn, u8 opcode, __le16 echo,
union event_ring_data *data, u8 fw_return_code)
int qed_sriov_eqe_event(struct qed_hwfn *p_hwfn, u8 opcode, __le16 echo,
union event_ring_data *data, u8 fw_return_code)
{
switch (opcode) {
case COMMON_EVENT_VF_PF_CHANNEL:
return qed_sriov_vfpf_msg(p_hwfn, le16_to_cpu(echo),
&data->vf_pf_channel.msg_addr);
case COMMON_EVENT_MALICIOUS_VF:
qed_sriov_vfpf_malicious(p_hwfn, &data->malicious_vf);
return 0;
default:
DP_INFO(p_hwfn->cdev, "Unknown sriov eqe event 0x%02x\n",
opcode);
@ -4075,7 +4100,7 @@ static int qed_iov_copy_vf_msg(struct qed_hwfn *p_hwfn, struct qed_ptt *ptt,
struct qed_dmae_params params;
struct qed_vf_info *vf_info;
vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!vf_info)
return -EINVAL;
@ -4176,7 +4201,7 @@ static void qed_iov_bulletin_set_forced_vlan(struct qed_hwfn *p_hwfn,
struct qed_vf_info *vf_info;
u64 feature;
vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!vf_info) {
DP_NOTICE(p_hwfn->cdev,
"Can not set forced MAC, invalid vfid [%d]\n", vfid);
@ -4226,7 +4251,7 @@ static bool qed_iov_vf_has_vport_instance(struct qed_hwfn *p_hwfn, int vfid)
{
struct qed_vf_info *p_vf_info;
p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!p_vf_info)
return false;
@ -4237,7 +4262,7 @@ static bool qed_iov_is_vf_stopped(struct qed_hwfn *p_hwfn, int vfid)
{
struct qed_vf_info *p_vf_info;
p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
p_vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!p_vf_info)
return true;
@ -4248,7 +4273,7 @@ static bool qed_iov_spoofchk_get(struct qed_hwfn *p_hwfn, int vfid)
{
struct qed_vf_info *vf_info;
vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!vf_info)
return false;
@ -4266,7 +4291,7 @@ static int qed_iov_spoofchk_set(struct qed_hwfn *p_hwfn, int vfid, bool val)
goto out;
}
vf = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
vf = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!vf)
goto out;
@ -4345,7 +4370,8 @@ static int qed_iov_configure_tx_rate(struct qed_hwfn *p_hwfn,
return rc;
rl_id = abs_vp_id; /* The "rl_id" is set as the "vport_id" */
return qed_init_global_rl(p_hwfn, p_ptt, rl_id, (u32)val);
return qed_init_global_rl(p_hwfn, p_ptt, rl_id, (u32)val,
QM_RL_TYPE_NORMAL);
}
static int
@ -4376,7 +4402,7 @@ static int qed_iov_get_vf_min_rate(struct qed_hwfn *p_hwfn, int vfid)
struct qed_wfq_data *vf_vp_wfq;
struct qed_vf_info *vf_info;
vf_info = qed_iov_get_vf_info(p_hwfn, (u16) vfid, true);
vf_info = qed_iov_get_vf_info(p_hwfn, (u16)vfid, true);
if (!vf_info)
return 0;
@ -4395,8 +4421,10 @@ static int qed_iov_get_vf_min_rate(struct qed_hwfn *p_hwfn, int vfid)
*/
void qed_schedule_iov(struct qed_hwfn *hwfn, enum qed_iov_wq_flag flag)
{
/* Memory barrier for setting atomic bit */
smp_mb__before_atomic();
set_bit(flag, &hwfn->iov_task_flags);
/* Memory barrier after setting atomic bit */
smp_mb__after_atomic();
DP_VERBOSE(hwfn, QED_MSG_IOV, "Scheduling iov task [Flag: %d]\n", flag);
queue_delayed_work(hwfn->iov_wq, &hwfn->iov_task, 0);
@ -4407,8 +4435,8 @@ void qed_vf_start_iov_wq(struct qed_dev *cdev)
int i;
for_each_hwfn(cdev, i)
queue_delayed_work(cdev->hwfns[i].iov_wq,
&cdev->hwfns[i].iov_task, 0);
queue_delayed_work(cdev->hwfns[i].iov_wq,
&cdev->hwfns[i].iov_task, 0);
}
int qed_sriov_disable(struct qed_dev *cdev, bool pci_enabled)
@ -4416,8 +4444,8 @@ int qed_sriov_disable(struct qed_dev *cdev, bool pci_enabled)
int i, j;
for_each_hwfn(cdev, i)
if (cdev->hwfns[i].iov_wq)
flush_workqueue(cdev->hwfns[i].iov_wq);
if (cdev->hwfns[i].iov_wq)
flush_workqueue(cdev->hwfns[i].iov_wq);
/* Mark VFs for disablement */
qed_iov_set_vfs_to_disable(cdev, true);
@ -5010,7 +5038,7 @@ static void qed_handle_bulletin_post(struct qed_hwfn *hwfn)
}
qed_for_each_vf(hwfn, i)
qed_iov_post_vf_bulletin(hwfn, i, ptt);
qed_iov_post_vf_bulletin(hwfn, i, ptt);
qed_ptt_release(hwfn, ptt);
}

126
drivers/net/ethernet/qlogic/qed/qed_sriov.h
View File

@ -142,7 +142,7 @@ struct qed_vf_queue {
enum vf_state {
VF_FREE = 0, /* VF ready to be acquired holds no resc */
VF_ACQUIRED, /* VF, acquired, but not initalized */
VF_ACQUIRED, /* VF, acquired, but not initialized */
VF_ENABLED, /* VF, Enabled */
VF_RESET, /* VF, FLR'd, pending cleanup */
VF_STOPPED /* VF, Stopped */
@ -250,29 +250,31 @@ extern const struct qed_iov_hv_ops qed_iov_ops_pass;
#ifdef CONFIG_QED_SRIOV
/**
* @brief Check if given VF ID @vfid is valid
* w.r.t. @b_enabled_only value
* if b_enabled_only = true - only enabled VF id is valid
* else any VF id less than max_vfs is valid
* qed_iov_is_valid_vfid(): Check if given VF ID @vfid is valid
* w.r.t. @b_enabled_only value
* if b_enabled_only = true - only enabled
* VF id is valid.
* else any VF id less than max_vfs is valid.
*
* @param p_hwfn
* @param rel_vf_id - Relative VF ID
* @param b_enabled_only - consider only enabled VF
* @param b_non_malicious - true iff we want to validate vf isn't malicious.
* @p_hwfn: HW device data.
* @rel_vf_id: Relative VF ID.
* @b_enabled_only: consider only enabled VF.
* @b_non_malicious: true iff we want to validate vf isn't malicious.
*
* @return bool - true for valid VF ID
* Return: bool - true for valid VF ID
*/
bool qed_iov_is_valid_vfid(struct qed_hwfn *p_hwfn,
int rel_vf_id,
bool b_enabled_only, bool b_non_malicious);
/**
* @brief - Given a VF index, return index of next [including that] active VF.
* qed_iov_get_next_active_vf(): Given a VF index, return index of
* next [including that] active VF.
*
* @param p_hwfn
* @param rel_vf_id
* @p_hwfn: HW device data.
* @rel_vf_id: VF ID.
*
* @return MAX_NUM_VFS in case no further active VFs, otherwise index.
* Return: MAX_NUM_VFS in case no further active VFs, otherwise index.
*/
u16 qed_iov_get_next_active_vf(struct qed_hwfn *p_hwfn, u16 rel_vf_id);
@ -280,83 +282,117 @@ void qed_iov_bulletin_set_udp_ports(struct qed_hwfn *p_hwfn,
int vfid, u16 vxlan_port, u16 geneve_port);
/**
* @brief Read sriov related information and allocated resources
* reads from configuration space, shmem, etc.
* qed_iov_hw_info(): Read sriov related information and allocated resources
* reads from configuration space, shmem, etc.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_iov_hw_info(struct qed_hwfn *p_hwfn);
/**
* @brief qed_add_tlv - place a given tlv on the tlv buffer at next offset
* qed_add_tlv(): place a given tlv on the tlv buffer at next offset
*
* @param p_hwfn
* @param p_iov
* @param type
* @param length
* @p_hwfn: HW device data.
* @offset: offset.
* @type: Type
* @length: Length.
*
* @return pointer to the newly placed tlv
* Return: pointer to the newly placed tlv
*/
void *qed_add_tlv(struct qed_hwfn *p_hwfn, u8 **offset, u16 type, u16 length);
/**
* @brief list the types and lengths of the tlvs on the buffer
* qed_dp_tlv_list(): list the types and lengths of the tlvs on the buffer
*
* @param p_hwfn
* @param tlvs_list
* @p_hwfn: HW device data.
* @tlvs_list: Tlvs_list.
*
* Return: Void.
*/
void qed_dp_tlv_list(struct qed_hwfn *p_hwfn, void *tlvs_list);
/**
* @brief qed_iov_alloc - allocate sriov related resources
* qed_sriov_vfpf_malicious(): Handle malicious VF/PF.
*
* @param p_hwfn
* @p_hwfn: HW device data.
* @p_data: Pointer to data.
*
* @return int
* Return: Void.
*/
void qed_sriov_vfpf_malicious(struct qed_hwfn *p_hwfn,
struct fw_err_data *p_data);
/**
* qed_sriov_eqe_event(): Callback for SRIOV events.
*
* @p_hwfn: HW device data.
* @opcode: Opcode.
* @echo: Echo.
* @data: data
* @fw_return_code: FW return code.
*
* Return: Int.
*/
int qed_sriov_eqe_event(struct qed_hwfn *p_hwfn, u8 opcode, __le16 echo,
union event_ring_data *data, u8 fw_return_code);
/**
* qed_iov_alloc(): allocate sriov related resources
*
* @p_hwfn: HW device data.
*
* Return: Int.
*/
int qed_iov_alloc(struct qed_hwfn *p_hwfn);
/**
* @brief qed_iov_setup - setup sriov related resources
* qed_iov_setup(): setup sriov related resources
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_iov_setup(struct qed_hwfn *p_hwfn);
/**
* @brief qed_iov_free - free sriov related resources
* qed_iov_free(): free sriov related resources
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* Return: Void.
*/
void qed_iov_free(struct qed_hwfn *p_hwfn);
/**
* @brief free sriov related memory that was allocated during hw_prepare
* qed_iov_free_hw_info(): free sriov related memory that was
* allocated during hw_prepare
*
* @param cdev
* @cdev: Qed dev pointer.
*
* Return: Void.
*/
void qed_iov_free_hw_info(struct qed_dev *cdev);
/**
* @brief Mark structs of vfs that have been FLR-ed.
* qed_iov_mark_vf_flr(): Mark structs of vfs that have been FLR-ed.
*
* @param p_hwfn
* @param disabled_vfs - bitmask of all VFs on path that were FLRed
* @p_hwfn: HW device data.
* @disabled_vfs: bitmask of all VFs on path that were FLRed
*
* @return true iff one of the PF's vfs got FLRed. false otherwise.
* Return: true iff one of the PF's vfs got FLRed. false otherwise.
*/
bool qed_iov_mark_vf_flr(struct qed_hwfn *p_hwfn, u32 *disabled_vfs);
/**
* @brief Search extended TLVs in request/reply buffer.
* qed_iov_search_list_tlvs(): Search extended TLVs in request/reply buffer.
*
* @param p_hwfn
* @param p_tlvs_list - Pointer to tlvs list
* @param req_type - Type of TLV
* @p_hwfn: HW device data.
* @p_tlvs_list: Pointer to tlvs list
* @req_type: Type of TLV
*
* @return pointer to tlv type if found, otherwise returns NULL.
* Return: pointer to tlv type if found, otherwise returns NULL.
*/
void *qed_iov_search_list_tlvs(struct qed_hwfn *p_hwfn,
void *p_tlvs_list, u16 req_type);

11
drivers/net/ethernet/qlogic/qed/qed_vf.c
View File

@ -27,7 +27,7 @@ static void *qed_vf_pf_prep(struct qed_hwfn *p_hwfn, u16 type, u16 length)
"preparing to send 0x%04x tlv over vf pf channel\n",
type);
/* Reset Requst offset */
/* Reset Request offset */
p_iov->offset = (u8 *)p_iov->vf2pf_request;
/* Clear mailbox - both request and reply */
@ -444,7 +444,7 @@ int qed_vf_hw_prepare(struct qed_hwfn *p_hwfn)
u32 reg;
int rc;
/* Set number of hwfns - might be overriden once leading hwfn learns
/* Set number of hwfns - might be overridden once leading hwfn learns
* actual configuration from PF.
*/
if (IS_LEAD_HWFN(p_hwfn))
@ -504,7 +504,7 @@ int qed_vf_hw_prepare(struct qed_hwfn *p_hwfn)
QED_MSG_IOV,
"VF's Request mailbox [%p virt 0x%llx phys], Response mailbox [%p virt 0x%llx phys]\n",
p_iov->vf2pf_request,
(u64) p_iov->vf2pf_request_phys,
(u64)p_iov->vf2pf_request_phys,
p_iov->pf2vf_reply, (u64)p_iov->pf2vf_reply_phys);
/* Allocate Bulletin board */
@ -561,6 +561,7 @@ int qed_vf_hw_prepare(struct qed_hwfn *p_hwfn)
return -ENOMEM;
}
#define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
#define MSTORM_QZONE_START(dev) (TSTORM_QZONE_START + \
(TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
@ -1285,8 +1286,8 @@ int qed_vf_pf_filter_ucast(struct qed_hwfn *p_hwfn,
/* clear mailbox and prep first tlv */
req = qed_vf_pf_prep(p_hwfn, CHANNEL_TLV_UCAST_FILTER, sizeof(*req));
req->opcode = (u8) p_ucast->opcode;
req->type = (u8) p_ucast->type;
req->opcode = (u8)p_ucast->opcode;
req->type = (u8)p_ucast->type;
memcpy(req->mac, p_ucast->mac, ETH_ALEN);
req->vlan = p_ucast->vlan;

307
drivers/net/ethernet/qlogic/qed/qed_vf.h
View File

@ -48,7 +48,7 @@ struct channel_tlv {
u16 length;
};
/* header of first vf->pf tlv carries the offset used to calculate reponse
/* header of first vf->pf tlv carries the offset used to calculate response
* buffer address
*/
struct vfpf_first_tlv {
@ -85,8 +85,8 @@ struct vfpf_acquire_tlv {
struct vfpf_first_tlv first_tlv;
struct vf_pf_vfdev_info {
#define VFPF_ACQUIRE_CAP_PRE_FP_HSI (1 << 0) /* VF pre-FP hsi version */
#define VFPF_ACQUIRE_CAP_100G (1 << 1) /* VF can support 100g */
#define VFPF_ACQUIRE_CAP_PRE_FP_HSI BIT(0) /* VF pre-FP hsi version */
#define VFPF_ACQUIRE_CAP_100G BIT(1) /* VF can support 100g */
/* A requirement for supporting multi-Tx queues on a single queue-zone,
* VF would pass qids as additional information whenever passing queue
* references.
@ -688,13 +688,16 @@ struct qed_vf_iov {
};
/**
* @brief VF - Set Rx/Tx coalesce per VF's relative queue.
* Coalesce value '0' will omit the configuration.
* qed_vf_pf_set_coalesce(): VF - Set Rx/Tx coalesce per VF's relative queue.
* Coalesce value '0' will omit the
* configuration.
*
* @param p_hwfn
* @param rx_coal - coalesce value in micro second for rx queue
* @param tx_coal - coalesce value in micro second for tx queue
* @param p_cid - queue cid
* @p_hwfn: HW device data.
* @rx_coal: coalesce value in micro second for rx queue.
* @tx_coal: coalesce value in micro second for tx queue.
* @p_cid: queue cid.
*
* Return: Int.
*
**/
int qed_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
@ -702,148 +705,172 @@ int qed_vf_pf_set_coalesce(struct qed_hwfn *p_hwfn,
u16 tx_coal, struct qed_queue_cid *p_cid);
/**
* @brief VF - Get coalesce per VF's relative queue.
* qed_vf_pf_get_coalesce(): VF - Get coalesce per VF's relative queue.
*
* @param p_hwfn
* @param p_coal - coalesce value in micro second for VF queues.
* @param p_cid - queue cid
* @p_hwfn: HW device data.
* @p_coal: coalesce value in micro second for VF queues.
* @p_cid: queue cid.
*
* Return: Int.
**/
int qed_vf_pf_get_coalesce(struct qed_hwfn *p_hwfn,
u16 *p_coal, struct qed_queue_cid *p_cid);
#ifdef CONFIG_QED_SRIOV
/**
* @brief Read the VF bulletin and act on it if needed
* qed_vf_read_bulletin(): Read the VF bulletin and act on it if needed.
*
* @param p_hwfn
* @param p_change - qed fills 1 iff bulletin board has changed, 0 otherwise.
* @p_hwfn: HW device data.
* @p_change: qed fills 1 iff bulletin board has changed, 0 otherwise.
*
* @return enum _qed_status
* Return: enum _qed_status.
*/
int qed_vf_read_bulletin(struct qed_hwfn *p_hwfn, u8 *p_change);
/**
* @brief Get link paramters for VF from qed
* qed_vf_get_link_params(): Get link parameters for VF from qed
*
* @param p_hwfn
* @param params - the link params structure to be filled for the VF
* @p_hwfn: HW device data.
* @params: the link params structure to be filled for the VF.
*
* Return: Void.
*/
void qed_vf_get_link_params(struct qed_hwfn *p_hwfn,
struct qed_mcp_link_params *params);
/**
* @brief Get link state for VF from qed
* qed_vf_get_link_state(): Get link state for VF from qed.
*
* @param p_hwfn
* @param link - the link state structure to be filled for the VF
* @p_hwfn: HW device data.
* @link: the link state structure to be filled for the VF
*
* Return: Void.
*/
void qed_vf_get_link_state(struct qed_hwfn *p_hwfn,
struct qed_mcp_link_state *link);
/**
* @brief Get link capabilities for VF from qed
* qed_vf_get_link_caps(): Get link capabilities for VF from qed.
*
* @param p_hwfn
* @param p_link_caps - the link capabilities structure to be filled for the VF
* @p_hwfn: HW device data.
* @p_link_caps: the link capabilities structure to be filled for the VF
*
* Return: Void.
*/
void qed_vf_get_link_caps(struct qed_hwfn *p_hwfn,
struct qed_mcp_link_capabilities *p_link_caps);
/**
* @brief Get number of Rx queues allocated for VF by qed
* qed_vf_get_num_rxqs(): Get number of Rx queues allocated for VF by qed
*
* @param p_hwfn
* @param num_rxqs - allocated RX queues
* @p_hwfn: HW device data.
* @num_rxqs: allocated RX queues
*
* Return: Void.
*/
void qed_vf_get_num_rxqs(struct qed_hwfn *p_hwfn, u8 *num_rxqs);
/**
* @brief Get number of Rx queues allocated for VF by qed
* qed_vf_get_num_txqs(): Get number of Rx queues allocated for VF by qed
*
* @param p_hwfn
* @param num_txqs - allocated RX queues
* @p_hwfn: HW device data.
* @num_txqs: allocated RX queues
*
* Return: Void.
*/
void qed_vf_get_num_txqs(struct qed_hwfn *p_hwfn, u8 *num_txqs);
/**
* @brief Get number of available connections [both Rx and Tx] for VF
* qed_vf_get_num_cids(): Get number of available connections
* [both Rx and Tx] for VF
*
* @param p_hwfn
* @param num_cids - allocated number of connections
* @p_hwfn: HW device data.
* @num_cids: allocated number of connections
*
* Return: Void.
*/
void qed_vf_get_num_cids(struct qed_hwfn *p_hwfn, u8 *num_cids);
/**
* @brief Get port mac address for VF
* qed_vf_get_port_mac(): Get port mac address for VF.
*
* @param p_hwfn
* @param port_mac - destination location for port mac
* @p_hwfn: HW device data.
* @port_mac: destination location for port mac
*
* Return: Void.
*/
void qed_vf_get_port_mac(struct qed_hwfn *p_hwfn, u8 *port_mac);
/**
* @brief Get number of VLAN filters allocated for VF by qed
* qed_vf_get_num_vlan_filters(): Get number of VLAN filters allocated
* for VF by qed.
*
* @param p_hwfn
* @param num_rxqs - allocated VLAN filters
* @p_hwfn: HW device data.
* @num_vlan_filters: allocated VLAN filters
*
* Return: Void.
*/
void qed_vf_get_num_vlan_filters(struct qed_hwfn *p_hwfn,
u8 *num_vlan_filters);
/**
* @brief Get number of MAC filters allocated for VF by qed
* qed_vf_get_num_mac_filters(): Get number of MAC filters allocated
* for VF by qed
*
* @param p_hwfn
* @param num_rxqs - allocated MAC filters
* @p_hwfn: HW device data.
* @num_mac_filters: allocated MAC filters
*
* Return: Void.
*/
void qed_vf_get_num_mac_filters(struct qed_hwfn *p_hwfn, u8 *num_mac_filters);
/**
* @brief Check if VF can set a MAC address
* qed_vf_check_mac(): Check if VF can set a MAC address
*
* @param p_hwfn
* @param mac
* @p_hwfn: HW device data.
* @mac: Mac.
*
* @return bool
* Return: bool.
*/
bool qed_vf_check_mac(struct qed_hwfn *p_hwfn, u8 *mac);
/**
* @brief Set firmware version information in dev_info from VFs acquire response tlv
* qed_vf_get_fw_version(): Set firmware version information
* in dev_info from VFs acquire response tlv
*
* @param p_hwfn
* @param fw_major
* @param fw_minor
* @param fw_rev
* @param fw_eng
* @p_hwfn: HW device data.
* @fw_major: FW major.
* @fw_minor: FW minor.
* @fw_rev: FW rev.
* @fw_eng: FW eng.
*
* Return: Void.
*/
void qed_vf_get_fw_version(struct qed_hwfn *p_hwfn,
u16 *fw_major, u16 *fw_minor,
u16 *fw_rev, u16 *fw_eng);
/**
* @brief hw preparation for VF
* sends ACQUIRE message
* qed_vf_hw_prepare(): hw preparation for VF sends ACQUIRE message
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return int
* Return: Int.
*/
int qed_vf_hw_prepare(struct qed_hwfn *p_hwfn);
/**
* @brief VF - start the RX Queue by sending a message to the PF
* @param p_hwfn
* @param p_cid - Only relative fields are relevant
* @param bd_max_bytes - maximum number of bytes per bd
* @param bd_chain_phys_addr - physical address of bd chain
* @param cqe_pbl_addr - physical address of pbl
* @param cqe_pbl_size - pbl size
* @param pp_prod - pointer to the producer to be
* used in fastpath
* qed_vf_pf_rxq_start(): start the RX Queue by sending a message to the PF
*
* @return int
* @p_hwfn: HW device data.
* @p_cid: Only relative fields are relevant
* @bd_max_bytes: maximum number of bytes per bd
* @bd_chain_phys_addr: physical address of bd chain
* @cqe_pbl_addr: physical address of pbl
* @cqe_pbl_size: pbl size
* @pp_prod: pointer to the producer to be used in fastpath
*
* Return: Int.
*/
int qed_vf_pf_rxq_start(struct qed_hwfn *p_hwfn,
struct qed_queue_cid *p_cid,
@ -853,18 +880,16 @@ int qed_vf_pf_rxq_start(struct qed_hwfn *p_hwfn,
u16 cqe_pbl_size, void __iomem **pp_prod);
/**
* @brief VF - start the TX queue by sending a message to the
* PF.
* qed_vf_pf_txq_start(): VF - start the TX queue by sending a message to the
* PF.
*
* @param p_hwfn
* @param tx_queue_id - zero based within the VF
* @param sb - status block for this queue
* @param sb_index - index within the status block
* @param bd_chain_phys_addr - physical address of tx chain
* @param pp_doorbell - pointer to address to which to
* write the doorbell too..
* @p_hwfn: HW device data.
* @p_cid: CID.
* @pbl_addr: PBL address.
* @pbl_size: PBL Size.
* @pp_doorbell: pointer to address to which to write the doorbell too.
*
* @return int
* Return: Int.
*/
int
qed_vf_pf_txq_start(struct qed_hwfn *p_hwfn,
@ -873,90 +898,91 @@ qed_vf_pf_txq_start(struct qed_hwfn *p_hwfn,
u16 pbl_size, void __iomem **pp_doorbell);
/**
* @brief VF - stop the RX queue by sending a message to the PF
* qed_vf_pf_rxq_stop(): VF - stop the RX queue by sending a message to the PF.
*
* @param p_hwfn
* @param p_cid
* @param cqe_completion
* @p_hwfn: HW device data.
* @p_cid: CID.
* @cqe_completion: CQE Completion.
*
* @return int
* Return: Int.
*/
int qed_vf_pf_rxq_stop(struct qed_hwfn *p_hwfn,
struct qed_queue_cid *p_cid, bool cqe_completion);
/**
* @brief VF - stop the TX queue by sending a message to the PF
* qed_vf_pf_txq_stop(): VF - stop the TX queue by sending a message to the PF.
*
* @param p_hwfn
* @param tx_qid
* @p_hwfn: HW device data.
* @p_cid: CID.
*
* @return int
* Return: Int.
*/
int qed_vf_pf_txq_stop(struct qed_hwfn *p_hwfn, struct qed_queue_cid *p_cid);
/**
* @brief VF - send a vport update command
* qed_vf_pf_vport_update(): VF - send a vport update command.
*
* @param p_hwfn
* @param params
* @p_hwfn: HW device data.
* @p_params: Params
*
* @return int
* Return: Int.
*/
int qed_vf_pf_vport_update(struct qed_hwfn *p_hwfn,
struct qed_sp_vport_update_params *p_params);
/**
* qed_vf_pf_reset(): VF - send a close message to PF.
*
* @brief VF - send a close message to PF
* @p_hwfn: HW device data.
*
* @param p_hwfn
*
* @return enum _qed_status
* Return: enum _qed_status
*/
int qed_vf_pf_reset(struct qed_hwfn *p_hwfn);
/**
* @brief VF - free vf`s memories
* qed_vf_pf_release(): VF - free vf`s memories.
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return enum _qed_status
* Return: enum _qed_status
*/
int qed_vf_pf_release(struct qed_hwfn *p_hwfn);
/**
* @brief qed_vf_get_igu_sb_id - Get the IGU SB ID for a given
* qed_vf_get_igu_sb_id(): Get the IGU SB ID for a given
* sb_id. For VFs igu sbs don't have to be contiguous
*
* @param p_hwfn
* @param sb_id
* @p_hwfn: HW device data.
* @sb_id: SB ID.
*
* @return INLINE u16
* Return: INLINE u16
*/
u16 qed_vf_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id);
/**
* @brief Stores [or removes] a configured sb_info.
* qed_vf_set_sb_info(): Stores [or removes] a configured sb_info.
*
* @param p_hwfn
* @param sb_id - zero-based SB index [for fastpath]
* @param sb_info - may be NULL [during removal].
* @p_hwfn: HW device data.
* @sb_id: zero-based SB index [for fastpath]
* @p_sb: may be NULL [during removal].
*
* Return: Void.
*/
void qed_vf_set_sb_info(struct qed_hwfn *p_hwfn,
u16 sb_id, struct qed_sb_info *p_sb);
/**
* @brief qed_vf_pf_vport_start - perform vport start for VF.
* qed_vf_pf_vport_start(): perform vport start for VF.
*
* @param p_hwfn
* @param vport_id
* @param mtu
* @param inner_vlan_removal
* @param tpa_mode
* @param max_buffers_per_cqe,
* @param only_untagged - default behavior regarding vlan acceptance
* @p_hwfn: HW device data.
* @vport_id: Vport ID.
* @mtu: MTU.
* @inner_vlan_removal: Innter VLAN removal.
* @tpa_mode: TPA mode
* @max_buffers_per_cqe: Max buffer pre CQE.
* @only_untagged: default behavior regarding vlan acceptance
*
* @return enum _qed_status
* Return: enum _qed_status
*/
int qed_vf_pf_vport_start(struct qed_hwfn *p_hwfn,
u8 vport_id,
@ -966,11 +992,11 @@ int qed_vf_pf_vport_start(struct qed_hwfn *p_hwfn,
u8 max_buffers_per_cqe, u8 only_untagged);
/**
* @brief qed_vf_pf_vport_stop - stop the VF's vport
* qed_vf_pf_vport_stop(): stop the VF's vport
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return enum _qed_status
* Return: enum _qed_status
*/
int qed_vf_pf_vport_stop(struct qed_hwfn *p_hwfn);
@ -981,42 +1007,49 @@ void qed_vf_pf_filter_mcast(struct qed_hwfn *p_hwfn,
struct qed_filter_mcast *p_filter_cmd);
/**
* @brief qed_vf_pf_int_cleanup - clean the SB of the VF
* qed_vf_pf_int_cleanup(): clean the SB of the VF
*
* @param p_hwfn
* @p_hwfn: HW device data.
*
* @return enum _qed_status
* Return: enum _qed_status
*/
int qed_vf_pf_int_cleanup(struct qed_hwfn *p_hwfn);
/**
* @brief - return the link params in a given bulletin board
* __qed_vf_get_link_params(): return the link params in a given bulletin board
*
* @param p_hwfn
* @param p_params - pointer to a struct to fill with link params
* @param p_bulletin
* @p_hwfn: HW device data.
* @p_params: pointer to a struct to fill with link params
* @p_bulletin: Bulletin.
*
* Return: Void.
*/
void __qed_vf_get_link_params(struct qed_hwfn *p_hwfn,
struct qed_mcp_link_params *p_params,
struct qed_bulletin_content *p_bulletin);
/**
* @brief - return the link state in a given bulletin board
* __qed_vf_get_link_state(): return the link state in a given bulletin board
*
* @param p_hwfn
* @param p_link - pointer to a struct to fill with link state
* @param p_bulletin
* @p_hwfn: HW device data.
* @p_link: pointer to a struct to fill with link state
* @p_bulletin: Bulletin.
*
* Return: Void.
*/
void __qed_vf_get_link_state(struct qed_hwfn *p_hwfn,
struct qed_mcp_link_state *p_link,
struct qed_bulletin_content *p_bulletin);
/**
* @brief - return the link capabilities in a given bulletin board
* __qed_vf_get_link_caps(): return the link capabilities in a given
* bulletin board
*
* @param p_hwfn
* @param p_link - pointer to a struct to fill with link capabilities
* @param p_bulletin
* @p_hwfn: HW device data.
* @p_link_caps: pointer to a struct to fill with link capabilities
* @p_bulletin: Bulletin.
*
* Return: Void.
*/
void __qed_vf_get_link_caps(struct qed_hwfn *p_hwfn,
struct qed_mcp_link_capabilities *p_link_caps,
@ -1029,9 +1062,13 @@ int qed_vf_pf_tunnel_param_update(struct qed_hwfn *p_hwfn,
u32 qed_vf_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id);
/**
* @brief - Ask PF to update the MAC address in it's bulletin board
* qed_vf_pf_bulletin_update_mac(): Ask PF to update the MAC address in
* it's bulletin board
*
* @param p_mac - mac address to be updated in bulletin board
* @p_hwfn: HW device data.
* @p_mac: mac address to be updated in bulletin board
*
* Return: Int.
*/
int qed_vf_pf_bulletin_update_mac(struct qed_hwfn *p_hwfn, u8 *p_mac);

7
drivers/net/ethernet/qlogic/qede/qede_main.c
View File

@ -1395,7 +1395,7 @@ static void qede_free_mem_sb(struct qede_dev *edev, struct qed_sb_info *sb_info,
static int qede_alloc_mem_sb(struct qede_dev *edev,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
int rc;
@ -2800,10 +2800,13 @@ static void qede_get_eth_tlv_data(void *dev, void *data)
}
/**
* qede_io_error_detected - called when PCI error is detected
* qede_io_error_detected(): Called when PCI error is detected
*
* @pdev: Pointer to PCI device
* @state: The current pci connection state
*
*Return: pci_ers_result_t.
*
* This function is called after a PCI bus error affecting
* this device has been detected.
*/

8
drivers/scsi/qedf/drv_fcoe_fw_funcs.c
View File

@ -22,9 +22,9 @@ int init_initiator_rw_fcoe_task(struct fcoe_task_params *task_params,
u32 task_retry_id,
u8 fcp_cmd_payload[32])
{
struct e4_fcoe_task_context *ctx = task_params->context;
struct fcoe_task_context *ctx = task_params->context;
const u8 val_byte = ctx->ystorm_ag_context.byte0;
struct e4_ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ystorm_fcoe_task_st_ctx *y_st_ctx;
struct tstorm_fcoe_task_st_ctx *t_st_ctx;
struct mstorm_fcoe_task_st_ctx *m_st_ctx;
@ -115,9 +115,9 @@ int init_initiator_midpath_unsolicited_fcoe_task(
struct scsi_sgl_task_params *rx_sgl_task_params,
u8 fw_to_place_fc_header)
{
struct e4_fcoe_task_context *ctx = task_params->context;
struct fcoe_task_context *ctx = task_params->context;
const u8 val_byte = ctx->ystorm_ag_context.byte0;
struct e4_ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ustorm_fcoe_task_ag_ctx *u_ag_ctx;
struct ystorm_fcoe_task_st_ctx *y_st_ctx;
struct tstorm_fcoe_task_st_ctx *t_st_ctx;
struct mstorm_fcoe_task_st_ctx *m_st_ctx;

2
drivers/scsi/qedf/drv_fcoe_fw_funcs.h
View File

@ -10,7 +10,7 @@
struct fcoe_task_params {
/* Output parameter [set/filled by the HSI function] */
struct e4_fcoe_task_context *context;
struct fcoe_task_context *context;
/* Output parameter [set/filled by the HSI function] */
struct fcoe_wqe *sqe;

4
drivers/scsi/qedf/qedf.h
View File

@ -141,7 +141,7 @@ struct qedf_ioreq {
struct completion tm_done;
struct completion abts_done;
struct completion cleanup_done;
struct e4_fcoe_task_context *task;
struct fcoe_task_context *task;
struct fcoe_task_params *task_params;
struct scsi_sgl_task_params *sgl_task_params;
int idx;
@ -503,7 +503,7 @@ extern void qedf_cmd_timer_set(struct qedf_ctx *qedf, struct qedf_ioreq *io_req,
unsigned int timer_msec);
extern int qedf_init_mp_req(struct qedf_ioreq *io_req);
extern void qedf_init_mp_task(struct qedf_ioreq *io_req,
struct e4_fcoe_task_context *task_ctx, struct fcoe_wqe *sqe);
struct fcoe_task_context *task_ctx, struct fcoe_wqe *sqe);
extern u16 qedf_get_sqe_idx(struct qedf_rport *fcport);
extern void qedf_ring_doorbell(struct qedf_rport *fcport);
extern void qedf_process_els_compl(struct qedf_ctx *qedf, struct fcoe_cqe *cqe,

2
drivers/scsi/qedf/qedf_els.c
View File

@ -16,7 +16,7 @@ static int qedf_initiate_els(struct qedf_rport *fcport, unsigned int op,
struct qedf_ioreq *els_req;
struct qedf_mp_req *mp_req;
struct fc_frame_header *fc_hdr;
struct e4_fcoe_task_context *task;
struct fcoe_task_context *task;
int rc = 0;
uint32_t did, sid;
uint16_t xid;

12
drivers/scsi/qedf/qedf_io.c
View File

@ -584,7 +584,7 @@ static void qedf_build_fcp_cmnd(struct qedf_ioreq *io_req,
}
static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
struct qedf_ioreq *io_req, struct e4_fcoe_task_context *task_ctx,
struct qedf_ioreq *io_req, struct fcoe_task_context *task_ctx,
struct fcoe_wqe *sqe)
{
enum fcoe_task_type task_type;
@ -602,7 +602,7 @@ static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
/* Note init_initiator_rw_fcoe_task memsets the task context */
io_req->task = task_ctx;
memset(task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(task_ctx, 0, sizeof(struct fcoe_task_context));
memset(io_req->task_params, 0, sizeof(struct fcoe_task_params));
memset(io_req->sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
@ -674,7 +674,7 @@ static void qedf_init_task(struct qedf_rport *fcport, struct fc_lport *lport,
}
void qedf_init_mp_task(struct qedf_ioreq *io_req,
struct e4_fcoe_task_context *task_ctx, struct fcoe_wqe *sqe)
struct fcoe_task_context *task_ctx, struct fcoe_wqe *sqe)
{
struct qedf_mp_req *mp_req = &(io_req->mp_req);
struct qedf_rport *fcport = io_req->fcport;
@ -692,7 +692,7 @@ void qedf_init_mp_task(struct qedf_ioreq *io_req,
memset(&tx_sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
memset(&rx_sgl_task_params, 0, sizeof(struct scsi_sgl_task_params));
memset(task_ctx, 0, sizeof(struct e4_fcoe_task_context));
memset(task_ctx, 0, sizeof(struct fcoe_task_context));
memset(&task_fc_hdr, 0, sizeof(struct fcoe_tx_mid_path_params));
/* Setup the task from io_req for easy reference */
@ -850,7 +850,7 @@ int qedf_post_io_req(struct qedf_rport *fcport, struct qedf_ioreq *io_req)
struct Scsi_Host *host = sc_cmd->device->host;
struct fc_lport *lport = shost_priv(host);
struct qedf_ctx *qedf = lport_priv(lport);
struct e4_fcoe_task_context *task_ctx;
struct fcoe_task_context *task_ctx;
u16 xid;
struct fcoe_wqe *sqe;
u16 sqe_idx;
@ -2293,7 +2293,7 @@ static int qedf_execute_tmf(struct qedf_rport *fcport, struct scsi_cmnd *sc_cmd,
uint8_t tm_flags)
{
struct qedf_ioreq *io_req;
struct e4_fcoe_task_context *task;
struct fcoe_task_context *task;
struct qedf_ctx *qedf = fcport->qedf;
struct fc_lport *lport = qedf->lport;
int rc = 0;

8
drivers/scsi/qedf/qedf_main.c
View File

@ -2170,7 +2170,7 @@ static bool qedf_fp_has_work(struct qedf_fastpath *fp)
struct qedf_ctx *qedf = fp->qedf;
struct global_queue *que;
struct qed_sb_info *sb_info = fp->sb_info;
struct status_block_e4 *sb = sb_info->sb_virt;
struct status_block *sb = sb_info->sb_virt;
u16 prod_idx;
/* Get the pointer to the global CQ this completion is on */
@ -2197,7 +2197,7 @@ static bool qedf_process_completions(struct qedf_fastpath *fp)
{
struct qedf_ctx *qedf = fp->qedf;
struct qed_sb_info *sb_info = fp->sb_info;
struct status_block_e4 *sb = sb_info->sb_virt;
struct status_block *sb = sb_info->sb_virt;
struct global_queue *que;
u16 prod_idx;
struct fcoe_cqe *cqe;
@ -2688,12 +2688,12 @@ void qedf_fp_io_handler(struct work_struct *work)
static int qedf_alloc_and_init_sb(struct qedf_ctx *qedf,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
int ret;
sb_virt = dma_alloc_coherent(&qedf->pdev->dev,
sizeof(struct status_block_e4), &sb_phys, GFP_KERNEL);
sizeof(struct status_block), &sb_phys, GFP_KERNEL);
if (!sb_virt) {
QEDF_ERR(&qedf->dbg_ctx,

4
drivers/scsi/qedi/qedi_debugfs.c
View File

@ -136,7 +136,7 @@ qedi_gbl_ctx_show(struct seq_file *s, void *unused)
{
struct qedi_fastpath *fp = NULL;
struct qed_sb_info *sb_info = NULL;
struct status_block_e4 *sb = NULL;
struct status_block *sb = NULL;
struct global_queue *que = NULL;
int id;
u16 prod_idx;
@ -152,7 +152,7 @@ qedi_gbl_ctx_show(struct seq_file *s, void *unused)
sb_info = fp->sb_info;
sb = sb_info->sb_virt;
prod_idx = (sb->pi_array[QEDI_PROTO_CQ_PROD_IDX] &
STATUS_BLOCK_E4_PROD_INDEX_MASK);
STATUS_BLOCK_PROD_INDEX_MASK);
seq_printf(s, "SB PROD IDX: %d\n", prod_idx);
que = qedi->global_queues[fp->sb_id];
seq_printf(s, "DRV CONS IDX: %d\n", que->cq_cons_idx);

40
drivers/scsi/qedi/qedi_fw.c
View File

@ -85,7 +85,7 @@ static void qedi_process_text_resp(struct qedi_ctx *qedi,
{
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
struct e4_iscsi_task_context *task_ctx;
struct iscsi_task_context *task_ctx;
struct iscsi_text_rsp *resp_hdr_ptr;
struct iscsi_text_response_hdr *cqe_text_response;
struct qedi_cmd *cmd;
@ -261,7 +261,7 @@ static void qedi_process_login_resp(struct qedi_ctx *qedi,
{
struct iscsi_conn *conn = qedi_conn->cls_conn->dd_data;
struct iscsi_session *session = conn->session;
struct e4_iscsi_task_context *task_ctx;
struct iscsi_task_context *task_ctx;
struct iscsi_login_rsp *resp_hdr_ptr;
struct iscsi_login_response_hdr *cqe_login_response;
struct qedi_cmd *cmd;
@ -970,7 +970,7 @@ int qedi_send_iscsi_login(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct iscsi_login_req *login_hdr;
struct scsi_sge *resp_sge = NULL;
@ -990,9 +990,9 @@ int qedi_send_iscsi_login(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1073,7 +1073,7 @@ int qedi_send_iscsi_logout(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct iscsi_logout *logout_hdr = NULL;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct qedi_cmd *qedi_cmd;
@ -1091,9 +1091,9 @@ int qedi_send_iscsi_logout(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1434,7 +1434,7 @@ static int send_iscsi_tmf(struct qedi_conn *qedi_conn, struct iscsi_task *mtask,
struct iscsi_tmf_request_hdr tmf_pdu_header;
struct iscsi_task_params task_params;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct iscsi_tm *tmf_hdr;
struct qedi_cmd *qedi_cmd;
struct qedi_cmd *cmd;
@ -1454,9 +1454,9 @@ static int send_iscsi_tmf(struct qedi_conn *qedi_conn, struct iscsi_task *mtask,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1548,7 +1548,7 @@ int qedi_send_iscsi_text(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params tx_sgl_task_params;
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct iscsi_text *text_hdr;
struct scsi_sge *req_sge = NULL;
@ -1570,9 +1570,9 @@ int qedi_send_iscsi_text(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1649,7 +1649,7 @@ int qedi_send_iscsi_nopout(struct qedi_conn *qedi_conn,
struct scsi_sgl_task_params rx_sgl_task_params;
struct iscsi_task_params task_params;
struct qedi_ctx *qedi = qedi_conn->qedi;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct iscsi_nopout *nopout_hdr;
struct scsi_sge *resp_sge = NULL;
struct qedi_cmd *qedi_cmd;
@ -1669,9 +1669,9 @@ int qedi_send_iscsi_nopout(struct qedi_conn *qedi_conn,
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
qedi_cmd->task_id = tid;
@ -1991,7 +1991,7 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
struct iscsi_task_params task_params;
struct iscsi_conn_params conn_params;
struct scsi_initiator_cmd_params cmd_params;
struct e4_iscsi_task_context *fw_task_ctx;
struct iscsi_task_context *fw_task_ctx;
struct iscsi_cls_conn *cls_conn;
struct iscsi_scsi_req *hdr = (struct iscsi_scsi_req *)task->hdr;
enum iscsi_task_type task_type = MAX_ISCSI_TASK_TYPE;
@ -2014,9 +2014,9 @@ int qedi_iscsi_send_ioreq(struct iscsi_task *task)
return -ENOMEM;
fw_task_ctx =
(struct e4_iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
(struct iscsi_task_context *)qedi_get_task_mem(&qedi->tasks,
tid);
memset(fw_task_ctx, 0, sizeof(struct e4_iscsi_task_context));
memset(fw_task_ctx, 0, sizeof(struct iscsi_task_context));
cmd->task_id = tid;

22
drivers/scsi/qedi/qedi_fw_api.c
View File

@ -202,7 +202,7 @@ static void init_default_iscsi_task(struct iscsi_task_params *task_params,
struct data_hdr *pdu_header,
enum iscsi_task_type task_type)
{
struct e4_iscsi_task_context *context;
struct iscsi_task_context *context;
u32 val;
u16 index;
u8 val_byte;
@ -224,7 +224,7 @@ static void init_default_iscsi_task(struct iscsi_task_params *task_params,
cpu_to_le16(task_params->conn_icid);
SET_FIELD(context->ustorm_ag_context.flags1,
E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV, 1);
USTORM_ISCSI_TASK_AG_CTX_R2T2RECV, 1);
context->ustorm_st_context.task_type = task_type;
context->ustorm_st_context.cq_rss_number = task_params->cq_rss_number;
@ -254,7 +254,7 @@ void init_initiator_rw_cdb_ystorm_context(struct ystorm_iscsi_task_st_ctx *ystc,
static
void init_ustorm_task_contexts(struct ustorm_iscsi_task_st_ctx *ustorm_st_cxt,
struct e4_ustorm_iscsi_task_ag_ctx *ustorm_ag_cxt,
struct ustorm_iscsi_task_ag_ctx *ustorm_ag_cxt,
u32 remaining_recv_len, u32 expected_data_transfer_len,
u8 num_sges, bool tx_dif_conn_err_en)
{
@ -266,12 +266,12 @@ void init_ustorm_task_contexts(struct ustorm_iscsi_task_st_ctx *ustorm_st_cxt,
ustorm_st_cxt->exp_data_transfer_len = val;
SET_FIELD(ustorm_st_cxt->reg1.reg1_map, ISCSI_REG1_NUM_SGES, num_sges);
SET_FIELD(ustorm_ag_cxt->flags2,
E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN,
USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN,
tx_dif_conn_err_en ? 1 : 0);
}
static
void set_rw_exp_data_acked_and_cont_len(struct e4_iscsi_task_context *context,
void set_rw_exp_data_acked_and_cont_len(struct iscsi_task_context *context,
struct iscsi_conn_params *conn_params,
enum iscsi_task_type task_type,
u32 task_size,
@ -470,7 +470,7 @@ void init_rtdif_task_context(struct rdif_task_context *rdif_context,
}
}
static void set_local_completion_context(struct e4_iscsi_task_context *context)
static void set_local_completion_context(struct iscsi_task_context *context)
{
SET_FIELD(context->ystorm_st_context.state.flags,
YSTORM_ISCSI_TASK_STATE_LOCAL_COMP, 1);
@ -487,7 +487,7 @@ static int init_rw_iscsi_task(struct iscsi_task_params *task_params,
struct scsi_dif_task_params *dif_task_params)
{
u32 exp_data_transfer_len = conn_params->max_burst_length;
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
bool slow_io = false;
u32 task_size, val;
u8 num_sges = 0;
@ -615,7 +615,7 @@ int init_initiator_login_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
cxt = task_params->context;
@ -657,7 +657,7 @@ int init_initiator_nop_out_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_sgl_task_params,
struct scsi_sgl_task_params *rx_sgl_task_params)
{
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
cxt = task_params->context;
@ -703,7 +703,7 @@ int init_initiator_logout_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
cxt = task_params->context;
@ -758,7 +758,7 @@ int init_initiator_text_request_task(struct iscsi_task_params *task_params,
struct scsi_sgl_task_params *tx_params,
struct scsi_sgl_task_params *rx_params)
{
struct e4_iscsi_task_context *cxt;
struct iscsi_task_context *cxt;
cxt = task_params->context;

2
drivers/scsi/qedi/qedi_fw_iscsi.h
View File

@ -10,7 +10,7 @@
#include "qedi_fw_scsi.h"
struct iscsi_task_params {
struct e4_iscsi_task_context *context;
struct iscsi_task_context *context;
struct iscsi_wqe *sqe;
u32 tx_io_size;
u32 rx_io_size;

2
drivers/scsi/qedi/qedi_iscsi.h
View File

@ -182,7 +182,7 @@ struct qedi_cmd {
struct scsi_cmnd *scsi_cmd;
struct scatterlist *sg;
struct qedi_io_bdt io_tbl;
struct e4_iscsi_task_context request;
struct iscsi_task_context request;
unsigned char *sense_buffer;
dma_addr_t sense_buffer_dma;
u16 task_id;

11
drivers/scsi/qedi/qedi_main.c
View File

@ -351,12 +351,12 @@ static int qedi_init_uio(struct qedi_ctx *qedi)
static int qedi_alloc_and_init_sb(struct qedi_ctx *qedi,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
int ret;
sb_virt = dma_alloc_coherent(&qedi->pdev->dev,
sizeof(struct status_block_e4), &sb_phys,
sizeof(struct status_block), &sb_phys,
GFP_KERNEL);
if (!sb_virt) {
QEDI_ERR(&qedi->dbg_ctx,
@ -865,7 +865,8 @@ static int qedi_set_iscsi_pf_param(struct qedi_ctx *qedi)
qedi->pf_params.iscsi_pf_params.num_uhq_pages_in_ring = num_sq_pages;
qedi->pf_params.iscsi_pf_params.num_queues = qedi->num_queues;
qedi->pf_params.iscsi_pf_params.debug_mode = qedi_fw_debug;
qedi->pf_params.iscsi_pf_params.two_msl_timer = 4000;
qedi->pf_params.iscsi_pf_params.two_msl_timer = QED_TWO_MSL_TIMER_DFLT;
qedi->pf_params.iscsi_pf_params.tx_sws_timer = QED_TX_SWS_TIMER_DFLT;
qedi->pf_params.iscsi_pf_params.max_fin_rt = 2;
for (log_page_size = 0 ; log_page_size < 32 ; log_page_size++) {
@ -1259,7 +1260,7 @@ static bool qedi_process_completions(struct qedi_fastpath *fp)
{
struct qedi_ctx *qedi = fp->qedi;
struct qed_sb_info *sb_info = fp->sb_info;
struct status_block_e4 *sb = sb_info->sb_virt;
struct status_block *sb = sb_info->sb_virt;
struct qedi_percpu_s *p = NULL;
struct global_queue *que;
u16 prod_idx;
@ -1315,7 +1316,7 @@ static bool qedi_fp_has_work(struct qedi_fastpath *fp)
struct qedi_ctx *qedi = fp->qedi;
struct global_queue *que;
struct qed_sb_info *sb_info = fp->sb_info;
struct status_block_e4 *sb = sb_info->sb_virt;
struct status_block *sb = sb_info->sb_virt;
u16 prod_idx;
barrier();

141
include/linux/qed/common_hsi.h
View File

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/* QLogic qed NIC Driver
* Copyright (c) 2015-2016 QLogic Corporation
* Copyright (c) 2019-2020 Marvell International Ltd.
* Copyright (c) 2019-2021 Marvell International Ltd.
*/
#ifndef _COMMON_HSI_H
@ -47,10 +47,10 @@
#define ISCSI_CDU_TASK_SEG_TYPE 0
#define FCOE_CDU_TASK_SEG_TYPE 0
#define RDMA_CDU_TASK_SEG_TYPE 1
#define ETH_CDU_TASK_SEG_TYPE 2
#define FW_ASSERT_GENERAL_ATTN_IDX 32
/* Queue Zone sizes in bytes */
#define TSTORM_QZONE_SIZE 8
#define MSTORM_QZONE_SIZE 16
@ -60,9 +60,12 @@
#define PSTORM_QZONE_SIZE 0
#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
#define ETH_MAX_RXQ_VF_DEFAULT 16
#define ETH_MAX_RXQ_VF_DOUBLE 48
#define ETH_MAX_RXQ_VF_QUAD 112
#define ETH_RGSRC_CTX_SIZE 6
#define ETH_TGSRC_CTX_SIZE 6
/********************************/
/* CORE (LIGHT L2) FW CONSTANTS */
@ -89,8 +92,8 @@
#define MAX_NUM_LL2_TX_STATS_COUNTERS 48
#define FW_MAJOR_VERSION 8
#define FW_MINOR_VERSION 42
#define FW_REVISION_VERSION 2
#define FW_MINOR_VERSION 59
#define FW_REVISION_VERSION 1
#define FW_ENGINEERING_VERSION 0
/***********************/
@ -112,6 +115,7 @@
#define MAX_NUM_VFS (MAX_NUM_VFS_K2)
#define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
#define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
#define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
#define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)
@ -133,7 +137,7 @@
#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
/* CIDs */
#define NUM_OF_CONNECTION_TYPES_E4 (8)
#define NUM_OF_CONNECTION_TYPES (8)
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
@ -144,7 +148,7 @@
#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
/* Tools Version */
#define TOOLS_VERSION 10
#define TOOLS_VERSION 11
/*****************/
/* CDU CONSTANTS */
@ -162,6 +166,7 @@
#define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3)
#define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4)
#define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5)
#define CDU_CONTEXT_VALIDATION_DEFAULT_CFG (0x3d)
/*****************/
/* DQ CONSTANTS */
@ -302,6 +307,9 @@
/* PWM address mapping */
#define DQ_PWM_OFFSET_DPM_BASE 0x0
#define DQ_PWM_OFFSET_DPM_END 0x27
#define DQ_PWM_OFFSET_XCM32_24ICID_BASE 0x28
#define DQ_PWM_OFFSET_UCM32_24ICID_BASE 0x30
#define DQ_PWM_OFFSET_TCM32_24ICID_BASE 0x38
#define DQ_PWM_OFFSET_XCM16_BASE 0x40
#define DQ_PWM_OFFSET_XCM32_BASE 0x44
#define DQ_PWM_OFFSET_UCM16_BASE 0x48
@ -325,6 +333,13 @@
#define DQ_PWM_OFFSET_TCM_LL2_PROD_UPDATE \
(DQ_PWM_OFFSET_TCM32_BASE + DQ_TCM_AGG_VAL_SEL_REG9 - 4)
#define DQ_PWM_OFFSET_XCM_RDMA_24B_ICID_SQ_PROD \
(DQ_PWM_OFFSET_XCM32_24ICID_BASE + 2)
#define DQ_PWM_OFFSET_UCM_RDMA_24B_ICID_CQ_CONS_32BIT \
(DQ_PWM_OFFSET_UCM32_24ICID_BASE + 4)
#define DQ_PWM_OFFSET_TCM_ROCE_24B_ICID_RQ_PROD \
(DQ_PWM_OFFSET_TCM32_24ICID_BASE + 1)
#define DQ_REGION_SHIFT (12)
/* DPM */
@ -360,6 +375,7 @@
/* Number of global Vport/QCN rate limiters */
#define MAX_QM_GLOBAL_RLS 256
#define COMMON_MAX_QM_GLOBAL_RLS MAX_QM_GLOBAL_RLS
/* QM registers data */
#define QM_LINE_CRD_REG_WIDTH 16
@ -379,7 +395,7 @@
#define CAU_FSM_ETH_TX 1
/* Number of Protocol Indices per Status Block */
#define PIS_PER_SB_E4 12
#define PIS_PER_SB 12
#define MAX_PIS_PER_SB PIS_PER_SB
#define CAU_HC_STOPPED_STATE 3
@ -700,6 +716,13 @@ enum mf_mode {
MAX_MF_MODE
};
/* Per protocol packet duplication enable bit vector. If set, duplicate
* offloaded traffic to LL2 debug queueu.
*/
struct offload_pkt_dup_enable {
__le16 enable_vector;
};
/* Per-protocol connection types */
enum protocol_type {
PROTOCOLID_TCP_ULP,
@ -717,6 +740,12 @@ enum protocol_type {
MAX_PROTOCOL_TYPE
};
/* Pstorm packet duplication config */
struct pstorm_pkt_dup_cfg {
struct offload_pkt_dup_enable enable;
__le16 reserved[3];
};
struct regpair {
__le32 lo;
__le32 hi;
@ -728,10 +757,24 @@ struct rdma_eqe_destroy_qp {
u8 reserved[4];
};
/* RoCE Suspend Event Data */
struct rdma_eqe_suspend_qp {
__le32 cid;
u8 reserved[4];
};
/* RDMA Event Data Union */
union rdma_eqe_data {
struct regpair async_handle;
struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
struct rdma_eqe_suspend_qp rdma_suspend_qp_data;
};
/* Tstorm packet duplication config */
struct tstorm_pkt_dup_cfg {
struct offload_pkt_dup_enable enable;
__le16 reserved;
__le32 cid;
};
struct tstorm_queue_zone {
@ -891,6 +934,15 @@ struct db_legacy_addr {
#define DB_LEGACY_ADDR_ICID_SHIFT 5
};
/* Structure for doorbell address, in legacy mode, without DEMS */
struct db_legacy_wo_dems_addr {
__le32 addr;
#define DB_LEGACY_WO_DEMS_ADDR_RESERVED0_MASK 0x3
#define DB_LEGACY_WO_DEMS_ADDR_RESERVED0_SHIFT 0
#define DB_LEGACY_WO_DEMS_ADDR_ICID_MASK 0x3FFFFFFF
#define DB_LEGACY_WO_DEMS_ADDR_ICID_SHIFT 2
};
/* Structure for doorbell address, in PWM mode */
struct db_pwm_addr {
__le32 addr;
@ -906,6 +958,31 @@ struct db_pwm_addr {
#define DB_PWM_ADDR_RESERVED1_SHIFT 28
};
/* Parameters to RDMA firmware, passed in EDPM doorbell */
struct db_rdma_24b_icid_dpm_params {
__le32 params;
#define DB_RDMA_24B_ICID_DPM_PARAMS_SIZE_MASK 0x3F
#define DB_RDMA_24B_ICID_DPM_PARAMS_SIZE_SHIFT 0
#define DB_RDMA_24B_ICID_DPM_PARAMS_DPM_TYPE_MASK 0x3
#define DB_RDMA_24B_ICID_DPM_PARAMS_DPM_TYPE_SHIFT 6
#define DB_RDMA_24B_ICID_DPM_PARAMS_OPCODE_MASK 0xFF
#define DB_RDMA_24B_ICID_DPM_PARAMS_OPCODE_SHIFT 8
#define DB_RDMA_24B_ICID_DPM_PARAMS_ICID_EXT_MASK 0xFF
#define DB_RDMA_24B_ICID_DPM_PARAMS_ICID_EXT_SHIFT 16
#define DB_RDMA_24B_ICID_DPM_PARAMS_INV_BYTE_CNT_MASK 0x7
#define DB_RDMA_24B_ICID_DPM_PARAMS_INV_BYTE_CNT_SHIFT 24
#define DB_RDMA_24B_ICID_DPM_PARAMS_EXT_ICID_MODE_EN_MASK 0x1
#define DB_RDMA_24B_ICID_DPM_PARAMS_EXT_ICID_MODE_EN_SHIFT 27
#define DB_RDMA_24B_ICID_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
#define DB_RDMA_24B_ICID_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
#define DB_RDMA_24B_ICID_DPM_PARAMS_S_FLG_MASK 0x1
#define DB_RDMA_24B_ICID_DPM_PARAMS_S_FLG_SHIFT 29
#define DB_RDMA_24B_ICID_DPM_PARAMS_RESERVED1_MASK 0x1
#define DB_RDMA_24B_ICID_DPM_PARAMS_RESERVED1_SHIFT 30
#define DB_RDMA_24B_ICID_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
#define DB_RDMA_24B_ICID_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
};
/* Parameters to RDMA firmware, passed in EDPM doorbell */
struct db_rdma_dpm_params {
__le32 params;
@ -1220,21 +1297,41 @@ struct rdif_task_context {
__le32 reserved2;
};
/* Searcher Table struct */
struct src_entry_header {
__le32 flags;
#define SRC_ENTRY_HEADER_NEXT_PTR_TYPE_MASK 0x1
#define SRC_ENTRY_HEADER_NEXT_PTR_TYPE_SHIFT 0
#define SRC_ENTRY_HEADER_EMPTY_MASK 0x1
#define SRC_ENTRY_HEADER_EMPTY_SHIFT 1
#define SRC_ENTRY_HEADER_RESERVED_MASK 0x3FFFFFFF
#define SRC_ENTRY_HEADER_RESERVED_SHIFT 2
__le32 magic_number;
struct regpair next_ptr;
};
/* Enumeration for address type */
enum src_header_next_ptr_type_enum {
e_physical_addr,
e_logical_addr,
MAX_SRC_HEADER_NEXT_PTR_TYPE_ENUM
};
/* Status block structure */
struct status_block_e4 {
__le16 pi_array[PIS_PER_SB_E4];
struct status_block {
__le16 pi_array[PIS_PER_SB];
__le32 sb_num;
#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9
#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16
#define STATUS_BLOCK_SB_NUM_MASK 0x1FF
#define STATUS_BLOCK_SB_NUM_SHIFT 0
#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
#define STATUS_BLOCK_ZERO_PAD_SHIFT 9
#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
__le32 prod_index;
#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24
#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
#define STATUS_BLOCK_PROD_INDEX_SHIFT 0
#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
};
/* Tdif context */

1
include/linux/qed/eth_common.h
View File

@ -67,6 +67,7 @@
/* Ethernet vport update constants */
#define ETH_FILTER_RULES_COUNT 10
#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
#define ETH_RSS_IND_TABLE_MASK_SIZE_REGS (ETH_RSS_IND_TABLE_ENTRIES_NUM / 32)
#define ETH_RSS_KEY_SIZE_REGS 10
#define ETH_RSS_ENGINE_NUM_K2 207
#define ETH_RSS_ENGINE_NUM_BB 127

362
include/linux/qed/fcoe_common.h
View File

@ -150,49 +150,49 @@ struct ystorm_fcoe_task_st_ctx {
u8 reserved2[8];
};
struct e4_ystorm_fcoe_task_ag_ctx {
struct ystorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
@ -206,73 +206,73 @@ struct e4_ystorm_fcoe_task_ag_ctx {
__le32 reg2;
};
struct e4_tstorm_fcoe_task_ag_ctx {
struct tstorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
u8 flags1;
#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
u8 flags3;
#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
u8 flags4;
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 cleanup_state;
__le16 last_sent_tid;
__le32 rec_rr_tov_exp_timeout;
@ -352,49 +352,49 @@ struct tstorm_fcoe_task_st_ctx {
struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
};
struct e4_mstorm_fcoe_task_ag_ctx {
struct mstorm_fcoe_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 icid;
u8 flags0;
#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 cleanup_state;
__le32 received_bytes;
u8 byte3;
@ -440,56 +440,56 @@ struct mstorm_fcoe_task_st_ctx {
struct scsi_cached_sges data_desc;
};
struct e4_ustorm_fcoe_task_ag_ctx {
struct ustorm_fcoe_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 icid;
u8 flags0;
#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
u8 flags1;
#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
u8 flags3;
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 global_cq_num;
@ -499,18 +499,18 @@ struct e4_ustorm_fcoe_task_ag_ctx {
};
/* FCoE task context */
struct e4_fcoe_task_context {
struct fcoe_task_context {
struct ystorm_fcoe_task_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct tdif_task_context tdif_context;
struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context;
struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context;
struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
struct timers_context timer_context;
struct tstorm_fcoe_task_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2];
struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_task_ag_ctx mstorm_ag_context;
struct mstorm_fcoe_task_st_ctx mstorm_st_context;
struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context;
struct ustorm_fcoe_task_ag_ctx ustorm_ag_context;
struct rdif_task_context rdif_context;
};

360
include/linux/qed/iscsi_common.h
View File

@ -714,49 +714,49 @@ struct ystorm_iscsi_task_st_ctx {
union iscsi_task_hdr pdu_hdr;
};
struct e4_ystorm_iscsi_task_ag_ctx {
struct ystorm_iscsi_task_ag_ctx {
u8 reserved;
u8 byte1;
__le16 word0;
u8 flags0;
#define E4_YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define E4_YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define E4_YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_MASK 0x1 /* bit3 */
#define E4_YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_SHIFT 7
#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_MASK 0x1 /* bit3 */
#define YSTORM_ISCSI_TASK_AG_CTX_TTT_VALID_SHIFT 7
u8 flags1;
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 TTT;
u8 byte3;
@ -764,49 +764,49 @@ struct e4_ystorm_iscsi_task_ag_ctx {
__le16 word1;
};
struct e4_mstorm_iscsi_task_ag_ctx {
struct mstorm_iscsi_task_ag_ctx {
u8 cdu_validation;
u8 byte1;
__le16 task_cid;
u8 flags0;
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
u8 flags1;
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
u8 flags2;
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
u8 byte2;
__le32 reg0;
u8 byte3;
@ -814,56 +814,56 @@ struct e4_mstorm_iscsi_task_ag_ctx {
__le16 word1;
};
struct e4_ustorm_iscsi_task_ag_ctx {
struct ustorm_iscsi_task_ag_ctx {
u8 reserved;
u8 state;
__le16 icid;
u8 flags0;
#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define E4_USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define E4_USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CONN_CLEAR_SQ_FLAG_SHIFT 5
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
u8 flags1;
#define E4_USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
u8 flags2;
#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
#define E4_USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
u8 flags3;
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define E4_USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define E4_USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 rcv_cont_len;
@ -952,14 +952,14 @@ struct ustorm_iscsi_task_st_ctx {
};
/* iscsi task context */
struct e4_iscsi_task_context {
struct iscsi_task_context {
struct ystorm_iscsi_task_st_ctx ystorm_st_context;
struct e4_ystorm_iscsi_task_ag_ctx ystorm_ag_context;
struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
struct regpair ystorm_ag_padding[2];
struct tdif_task_context tdif_context;
struct e4_mstorm_iscsi_task_ag_ctx mstorm_ag_context;
struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
struct regpair mstorm_ag_padding[2];
struct e4_ustorm_iscsi_task_ag_ctx ustorm_ag_context;
struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
struct mstorm_iscsi_task_st_ctx mstorm_st_context;
struct ustorm_iscsi_task_st_ctx ustorm_st_context;
struct rdif_task_context rdif_context;
@ -1431,73 +1431,73 @@ struct ystorm_iscsi_stats_drv {
struct regpair iscsi_tx_tcp_pkt_cnt;
};
struct e4_tstorm_iscsi_task_ag_ctx {
struct tstorm_iscsi_task_ag_ctx {
u8 byte0;
u8 byte1;
__le16 word0;
u8 flags0;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define E4_TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
u8 flags3;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
u8 flags4;
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define E4_TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 byte2;
__le16 word1;
__le32 reg0;

18
include/linux/qed/nvmetcp_common.h
View File

@ -410,7 +410,7 @@ struct e5_ystorm_nvmetcp_task_ag_ctx {
u8 byte2;
u8 byte3;
u8 byte4;
u8 e4_reserved7;
u8 reserved7;
};
struct e5_mstorm_nvmetcp_task_ag_ctx {
@ -445,7 +445,7 @@ struct e5_mstorm_nvmetcp_task_ag_ctx {
u8 byte2;
u8 byte3;
u8 byte4;
u8 e4_reserved7;
u8 reserved7;
};
struct e5_ustorm_nvmetcp_task_ag_ctx {
@ -489,17 +489,17 @@ struct e5_ustorm_nvmetcp_task_ag_ctx {
#define E5_USTORM_NVMETCP_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
u8 flags3;
u8 flags4;
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED5_MASK 0x3
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED5_SHIFT 0
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED6_MASK 0x1
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED6_SHIFT 2
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED7_MASK 0x1
#define E5_USTORM_NVMETCP_TASK_AG_CTX_E4_RESERVED7_SHIFT 3
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED5_MASK 0x3
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED5_SHIFT 0
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED6_MASK 0x1
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED6_SHIFT 2
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED7_MASK 0x1
#define E5_USTORM_NVMETCP_TASK_AG_CTX_RESERVED7_SHIFT 3
#define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
#define E5_USTORM_NVMETCP_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
u8 byte2;
u8 byte3;
u8 e4_reserved8;
u8 reserved8;
__le32 dif_err_intervals;
__le32 dif_error_1st_interval;
__le32 rcv_cont_len;

97
include/linux/qed/qed_chain.h
View File

@ -268,14 +268,15 @@ static inline dma_addr_t qed_chain_get_pbl_phys(const struct qed_chain *chain)
}
/**
* @brief qed_chain_advance_page -
* qed_chain_advance_page(): Advance the next element across pages for a
* linked chain.
*
* Advance the next element across pages for a linked chain
* @p_chain: P_chain.
* @p_next_elem: P_next_elem.
* @idx_to_inc: Idx_to_inc.
* @page_to_inc: page_to_inc.
*
* @param p_chain
* @param p_next_elem
* @param idx_to_inc
* @param page_to_inc
* Return: Void.
*/
static inline void
qed_chain_advance_page(struct qed_chain *p_chain,
@ -336,12 +337,14 @@ qed_chain_advance_page(struct qed_chain *p_chain,
} while (0)
/**
* @brief qed_chain_return_produced -
* qed_chain_return_produced(): A chain in which the driver "Produces"
* elements should use this API
* to indicate previous produced elements
* are now consumed.
*
* A chain in which the driver "Produces" elements should use this API
* to indicate previous produced elements are now consumed.
* @p_chain: Chain.
*
* @param p_chain
* Return: Void.
*/
static inline void qed_chain_return_produced(struct qed_chain *p_chain)
{
@ -353,15 +356,15 @@ static inline void qed_chain_return_produced(struct qed_chain *p_chain)
}
/**
* @brief qed_chain_produce -
* qed_chain_produce(): A chain in which the driver "Produces"
* elements should use this to get a pointer to
* the next element which can be "Produced". It's driver
* responsibility to validate that the chain has room for
* new element.
*
* A chain in which the driver "Produces" elements should use this to get
* a pointer to the next element which can be "Produced". It's driver
* responsibility to validate that the chain has room for new element.
* @p_chain: Chain.
*
* @param p_chain
*
* @return void*, a pointer to next element
* Return: void*, a pointer to next element.
*/
static inline void *qed_chain_produce(struct qed_chain *p_chain)
{
@ -395,14 +398,11 @@ static inline void *qed_chain_produce(struct qed_chain *p_chain)
}
/**
* @brief qed_chain_get_capacity -
* qed_chain_get_capacity(): Get the maximum number of BDs in chain
*
* Get the maximum number of BDs in chain
* @p_chain: Chain.
*
* @param p_chain
* @param num
*
* @return number of unusable BDs
* Return: number of unusable BDs.
*/
static inline u32 qed_chain_get_capacity(struct qed_chain *p_chain)
{
@ -410,12 +410,14 @@ static inline u32 qed_chain_get_capacity(struct qed_chain *p_chain)
}
/**
* @brief qed_chain_recycle_consumed -
* qed_chain_recycle_consumed(): Returns an element which was
* previously consumed;
* Increments producers so they could
* be written to FW.
*
* Returns an element which was previously consumed;
* Increments producers so they could be written to FW.
* @p_chain: Chain.
*
* @param p_chain
* Return: Void.
*/
static inline void qed_chain_recycle_consumed(struct qed_chain *p_chain)
{
@ -427,14 +429,13 @@ static inline void qed_chain_recycle_consumed(struct qed_chain *p_chain)
}
/**
* @brief qed_chain_consume -
* qed_chain_consume(): A Chain in which the driver utilizes data written
* by a different source (i.e., FW) should use this to
* access passed buffers.
*
* A Chain in which the driver utilizes data written by a different source
* (i.e., FW) should use this to access passed buffers.
* @p_chain: Chain.
*
* @param p_chain
*
* @return void*, a pointer to the next buffer written
* Return: void*, a pointer to the next buffer written.
*/
static inline void *qed_chain_consume(struct qed_chain *p_chain)
{
@ -468,9 +469,11 @@ static inline void *qed_chain_consume(struct qed_chain *p_chain)
}
/**
* @brief qed_chain_reset - Resets the chain to its start state
* qed_chain_reset(): Resets the chain to its start state.
*
* @param p_chain pointer to a previously allocated chain
* @p_chain: pointer to a previously allocated chain.
*
* Return Void.
*/
static inline void qed_chain_reset(struct qed_chain *p_chain)
{
@ -519,13 +522,12 @@ static inline void qed_chain_reset(struct qed_chain *p_chain)
}
/**
* @brief qed_chain_get_last_elem -
* qed_chain_get_last_elem(): Returns a pointer to the last element of the
* chain.
*
* Returns a pointer to the last element of the chain
* @p_chain: Chain.
*
* @param p_chain
*
* @return void*
* Return: void*.
*/
static inline void *qed_chain_get_last_elem(struct qed_chain *p_chain)
{
@ -563,10 +565,13 @@ static inline void *qed_chain_get_last_elem(struct qed_chain *p_chain)
}
/**
* @brief qed_chain_set_prod - sets the prod to the given value
* qed_chain_set_prod(): sets the prod to the given value.
*
* @param prod_idx
* @param p_prod_elem
* @p_chain: Chain.
* @prod_idx: Prod Idx.
* @p_prod_elem: Prod elem.
*
* Return Void.
*/
static inline void qed_chain_set_prod(struct qed_chain *p_chain,
u32 prod_idx, void *p_prod_elem)
@ -610,9 +615,11 @@ static inline void qed_chain_set_prod(struct qed_chain *p_chain,
}
/**
* @brief qed_chain_pbl_zero_mem - set chain memory to 0
* qed_chain_pbl_zero_mem(): set chain memory to 0.
*
* @param p_chain
* @p_chain: Chain.
*
* Return: Void.
*/
static inline void qed_chain_pbl_zero_mem(struct qed_chain *p_chain)
{

263
include/linux/qed/qed_if.h
View File

@ -24,6 +24,9 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include <net/devlink.h>
#define QED_TX_SWS_TIMER_DFLT 500
#define QED_TWO_MSL_TIMER_DFLT 4000
enum dcbx_protocol_type {
DCBX_PROTOCOL_ISCSI,
DCBX_PROTOCOL_FCOE,
@ -588,7 +591,7 @@ enum qed_int_mode {
};
struct qed_sb_info {
struct status_block_e4 *sb_virt;
struct status_block *sb_virt;
dma_addr_t sb_phys;
u32 sb_ack; /* Last given ack */
u16 igu_sb_id;
@ -613,7 +616,6 @@ enum qed_hw_err_type {
enum qed_dev_type {
QED_DEV_TYPE_BB,
QED_DEV_TYPE_AH,
QED_DEV_TYPE_E5,
};
struct qed_dev_info {
@ -819,47 +821,47 @@ struct qed_common_cb_ops {
struct qed_selftest_ops {
/**
* @brief selftest_interrupt - Perform interrupt test
* selftest_interrupt(): Perform interrupt test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*selftest_interrupt)(struct qed_dev *cdev);
/**
* @brief selftest_memory - Perform memory test
* selftest_memory(): Perform memory test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*selftest_memory)(struct qed_dev *cdev);
/**
* @brief selftest_register - Perform register test
* selftest_register(): Perform register test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*selftest_register)(struct qed_dev *cdev);
/**
* @brief selftest_clock - Perform clock test
* selftest_clock(): Perform clock test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*selftest_clock)(struct qed_dev *cdev);
/**
* @brief selftest_nvram - Perform nvram test
* selftest_nvram(): Perform nvram test.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*selftest_nvram) (struct qed_dev *cdev);
};
@ -927,47 +929,53 @@ struct qed_common_ops {
enum qed_hw_err_type err_type);
/**
* @brief can_link_change - can the instance change the link or not
* can_link_change(): can the instance change the link or not.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return true if link-change is allowed, false otherwise.
* Return: true if link-change is allowed, false otherwise.
*/
bool (*can_link_change)(struct qed_dev *cdev);
/**
* @brief set_link - set links according to params
* set_link(): set links according to params.
*
* @param cdev
* @param params - values used to override the default link configuration
* @cdev: Qed dev pointer.
* @params: values used to override the default link configuration.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*set_link)(struct qed_dev *cdev,
struct qed_link_params *params);
/**
* @brief get_link - returns the current link state.
* get_link(): returns the current link state.
*
* @param cdev
* @param if_link - structure to be filled with current link configuration.
* @cdev: Qed dev pointer.
* @if_link: structure to be filled with current link configuration.
*
* Return: Void.
*/
void (*get_link)(struct qed_dev *cdev,
struct qed_link_output *if_link);
/**
* @brief - drains chip in case Tx completions fail to arrive due to pause.
* drain(): drains chip in case Tx completions fail to arrive due to pause.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* Return: Int.
*/
int (*drain)(struct qed_dev *cdev);
/**
* @brief update_msglvl - update module debug level
* update_msglvl(): update module debug level.
*
* @param cdev
* @param dp_module
* @param dp_level
* @cdev: Qed dev pointer.
* @dp_module: Debug module.
* @dp_level: Debug level.
*
* Return: Void.
*/
void (*update_msglvl)(struct qed_dev *cdev,
u32 dp_module,
@ -981,70 +989,73 @@ struct qed_common_ops {
struct qed_chain *p_chain);
/**
* @brief nvm_flash - Flash nvm data.
* nvm_flash(): Flash nvm data.
*
* @param cdev
* @param name - file containing the data
* @cdev: Qed dev pointer.
* @name: file containing the data.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*nvm_flash)(struct qed_dev *cdev, const char *name);
/**
* @brief nvm_get_image - reads an entire image from nvram
* nvm_get_image(): reads an entire image from nvram.
*
* @param cdev
* @param type - type of the request nvram image
* @param buf - preallocated buffer to fill with the image
* @param len - length of the allocated buffer
* @cdev: Qed dev pointer.
* @type: type of the request nvram image.
* @buf: preallocated buffer to fill with the image.
* @len: length of the allocated buffer.
*
* @return 0 on success, error otherwise
* Return: 0 on success, error otherwise.
*/
int (*nvm_get_image)(struct qed_dev *cdev,
enum qed_nvm_images type, u8 *buf, u16 len);
/**
* @brief set_coalesce - Configure Rx coalesce value in usec
* set_coalesce(): Configure Rx coalesce value in usec.
*
* @param cdev
* @param rx_coal - Rx coalesce value in usec
* @param tx_coal - Tx coalesce value in usec
* @param qid - Queue index
* @param sb_id - Status Block Id
* @cdev: Qed dev pointer.
* @rx_coal: Rx coalesce value in usec.
* @tx_coal: Tx coalesce value in usec.
* @handle: Handle.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*set_coalesce)(struct qed_dev *cdev,
u16 rx_coal, u16 tx_coal, void *handle);
/**
* @brief set_led - Configure LED mode
* set_led() - Configure LED mode.
*
* @param cdev
* @param mode - LED mode
* @cdev: Qed dev pointer.
* @mode: LED mode.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*set_led)(struct qed_dev *cdev,
enum qed_led_mode mode);
/**
* @brief attn_clr_enable - Prevent attentions from being reasserted
* attn_clr_enable(): Prevent attentions from being reasserted.
*
* @param cdev
* @param clr_enable
* @cdev: Qed dev pointer.
* @clr_enable: Clear enable.
*
* Return: Void.
*/
void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
/**
* @brief db_recovery_add - add doorbell information to the doorbell
* recovery mechanism.
* db_recovery_add(): add doorbell information to the doorbell
* recovery mechanism.
*
* @param cdev
* @param db_addr - doorbell address
* @param db_data - address of where db_data is stored
* @param db_is_32b - doorbell is 32b pr 64b
* @param db_is_user - doorbell recovery addresses are user or kernel space
* @cdev: Qed dev pointer.
* @db_addr: Doorbell address.
* @db_data: Dddress of where db_data is stored.
* @db_width: Doorbell is 32b or 64b.
* @db_space: Doorbell recovery addresses are user or kernel space.
*
* Return: Int.
*/
int (*db_recovery_add)(struct qed_dev *cdev,
void __iomem *db_addr,
@ -1053,114 +1064,130 @@ struct qed_common_ops {
enum qed_db_rec_space db_space);
/**
* @brief db_recovery_del - remove doorbell information from the doorbell
* db_recovery_del(): remove doorbell information from the doorbell
* recovery mechanism. db_data serves as key (db_addr is not unique).
*
* @param cdev
* @param db_addr - doorbell address
* @param db_data - address where db_data is stored. Serves as key for the
* entry to delete.
* @cdev: Qed dev pointer.
* @db_addr: Doorbell address.
* @db_data: Address where db_data is stored. Serves as key for the
* entry to delete.
*
* Return: Int.
*/
int (*db_recovery_del)(struct qed_dev *cdev,
void __iomem *db_addr, void *db_data);
/**
* @brief recovery_process - Trigger a recovery process
* recovery_process(): Trigger a recovery process.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*recovery_process)(struct qed_dev *cdev);
/**
* @brief recovery_prolog - Execute the prolog operations of a recovery process
* recovery_prolog(): Execute the prolog operations of a recovery process.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*recovery_prolog)(struct qed_dev *cdev);
/**
* @brief update_drv_state - API to inform the change in the driver state.
* update_drv_state(): API to inform the change in the driver state.
*
* @param cdev
* @param active
* @cdev: Qed dev pointer.
* @active: Active
*
* Return: Int.
*/
int (*update_drv_state)(struct qed_dev *cdev, bool active);
/**
* @brief update_mac - API to inform the change in the mac address
* update_mac(): API to inform the change in the mac address.
*
* @param cdev
* @param mac
* @cdev: Qed dev pointer.
* @mac: MAC.
*
* Return: Int.
*/
int (*update_mac)(struct qed_dev *cdev, u8 *mac);
/**
* @brief update_mtu - API to inform the change in the mtu
* update_mtu(): API to inform the change in the mtu.
*
* @param cdev
* @param mtu
* @cdev: Qed dev pointer.
* @mtu: MTU.
*
* Return: Int.
*/
int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
/**
* @brief update_wol - update of changes in the WoL configuration
* update_wol(): Update of changes in the WoL configuration.
*
* @param cdev
* @param enabled - true iff WoL should be enabled.
* @cdev: Qed dev pointer.
* @enabled: true iff WoL should be enabled.
*
* Return: Int.
*/
int (*update_wol) (struct qed_dev *cdev, bool enabled);
/**
* @brief read_module_eeprom
* read_module_eeprom(): Read EEPROM.
*
* @param cdev
* @param buf - buffer
* @param dev_addr - PHY device memory region
* @param offset - offset into eeprom contents to be read
* @param len - buffer length, i.e., max bytes to be read
* @cdev: Qed dev pointer.
* @buf: buffer.
* @dev_addr: PHY device memory region.
* @offset: offset into eeprom contents to be read.
* @len: buffer length, i.e., max bytes to be read.
*
* Return: Int.
*/
int (*read_module_eeprom)(struct qed_dev *cdev,
char *buf, u8 dev_addr, u32 offset, u32 len);
/**
* @brief get_affin_hwfn_idx
* get_affin_hwfn_idx(): Get affine HW function.
*
* @param cdev
* @cdev: Qed dev pointer.
*
* Return: u8.
*/
u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
/**
* @brief read_nvm_cfg - Read NVM config attribute value.
* @param cdev
* @param buf - buffer
* @param cmd - NVM CFG command id
* @param entity_id - Entity id
* read_nvm_cfg(): Read NVM config attribute value.
*
* @cdev: Qed dev pointer.
* @buf: Buffer.
* @cmd: NVM CFG command id.
* @entity_id: Entity id.
*
* Return: Int.
*/
int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
u32 entity_id);
/**
* @brief read_nvm_cfg - Read NVM config attribute value.
* @param cdev
* @param cmd - NVM CFG command id
* read_nvm_cfg_len(): Read NVM config attribute value.
*
* @return config id length, 0 on error.
* @cdev: Qed dev pointer.
* @cmd: NVM CFG command id.
*
* Return: config id length, 0 on error.
*/
int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
/**
* @brief set_grc_config - Configure value for grc config id.
* @param cdev
* @param cfg_id - grc config id
* @param val - grc config value
* set_grc_config(): Configure value for grc config id.
*
* @cdev: Qed dev pointer.
* @cfg_id: grc config id
* @val: grc config value
*
* Return: Int.
*/
int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
@ -1386,7 +1413,7 @@ static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
u16 rc = 0;
prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
STATUS_BLOCK_E4_PROD_INDEX_MASK;
STATUS_BLOCK_PROD_INDEX_MASK;
if (sb_info->sb_ack != prod) {
sb_info->sb_ack = prod;
rc |= QED_SB_IDX;
@ -1397,18 +1424,16 @@ static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
}
/**
* qed_sb_ack(): This function creates an update command for interrupts
* that is written to the IGU.
*
* @brief This function creates an update command for interrupts that is
* written to the IGU.
* @sb_info: This is the structure allocated and
* initialized per status block. Assumption is
* that it was initialized using qed_sb_init
* @int_cmd: Enable/Disable/Nop
* @upd_flg: Whether igu consumer should be updated.
*
* @param sb_info - This is the structure allocated and
* initialized per status block. Assumption is
* that it was initialized using qed_sb_init
* @param int_cmd - Enable/Disable/Nop
* @param upd_flg - whether igu consumer should be
* updated.
*
* @return inline void
* Return: inline void.
*/
static inline void qed_sb_ack(struct qed_sb_info *sb_info,
enum igu_int_cmd int_cmd,

2
include/linux/qed/qed_iscsi_if.h
View File

@ -182,7 +182,7 @@ struct qed_iscsi_cb_ops {
* @param stats - pointer to struck that would be filled
* we stats
* @return 0 on success, error otherwise.
* @change_mac Change MAC of interface
* @change_mac: Change MAC of interface
* @param cdev
* @param handle - the connection handle.
* @param mac - new MAC to configure.

42
include/linux/qed/qed_ll2_if.h
View File

@ -208,57 +208,57 @@ enum qed_ll2_xmit_flags {
struct qed_ll2_ops {
/**
* @brief start - initializes ll2
* start(): Initializes ll2.
*
* @param cdev
* @param params - protocol driver configuration for the ll2.
* @cdev: Qed dev pointer.
* @params: Protocol driver configuration for the ll2.
*
* @return 0 on success, otherwise error value.
* Return: 0 on success, otherwise error value.
*/
int (*start)(struct qed_dev *cdev, struct qed_ll2_params *params);
/**
* @brief stop - stops the ll2
* stop(): Stops the ll2
*
* @param cdev
* @cdev: Qed dev pointer.
*
* @return 0 on success, otherwise error value.
* Return: 0 on success, otherwise error value.
*/
int (*stop)(struct qed_dev *cdev);
/**
* @brief start_xmit - transmits an skb over the ll2 interface
* start_xmit(): Transmits an skb over the ll2 interface
*
* @param cdev
* @param skb
* @param xmit_flags - Transmit options defined by the enum qed_ll2_xmit_flags.
* @cdev: Qed dev pointer.
* @skb: SKB.
* @xmit_flags: Transmit options defined by the enum qed_ll2_xmit_flags.
*
* @return 0 on success, otherwise error value.
* Return: 0 on success, otherwise error value.
*/
int (*start_xmit)(struct qed_dev *cdev, struct sk_buff *skb,
unsigned long xmit_flags);
/**
* @brief register_cb_ops - protocol driver register the callback for Rx/Tx
* register_cb_ops(): Protocol driver register the callback for Rx/Tx
* packets. Should be called before `start'.
*
* @param cdev
* @param cookie - to be passed to the callback functions.
* @param ops - the callback functions to register for Rx / Tx.
* @cdev: Qed dev pointer.
* @cookie: to be passed to the callback functions.
* @ops: the callback functions to register for Rx / Tx.
*
* @return 0 on success, otherwise error value.
* Return: 0 on success, otherwise error value.
*/
void (*register_cb_ops)(struct qed_dev *cdev,
const struct qed_ll2_cb_ops *ops,
void *cookie);
/**
* @brief get LL2 related statistics
* get_stats(): Get LL2 related statistics.
*
* @param cdev
* @param stats - pointer to struct that would be filled with stats
* @cdev: Qed dev pointer.
* @stats: Pointer to struct that would be filled with stats.
*
* @return 0 on success, error otherwise.
* Return: 0 on success, error otherwise.
*/
int (*get_stats)(struct qed_dev *cdev, struct qed_ll2_stats *stats);
};

17
include/linux/qed/qed_nvmetcp_if.h
View File

@ -171,6 +171,23 @@ struct nvmetcp_task_params {
* @param dest_port
* @clear_all_filters: Clear all filters.
* @param cdev
* @init_read_io: Init read IO.
* @task_params
* @cmd_pdu_header
* @nvme_cmd
* @sgl_task_params
* @init_write_io: Init write IO.
* @task_params
* @cmd_pdu_header
* @nvme_cmd
* @sgl_task_params
* @init_icreq_exchange: Exchange ICReq.
* @task_params
* @init_conn_req_pdu_hdr
* @tx_sgl_task_params
* @rx_sgl_task_params
* @init_task_cleanup: Init task cleanup.
* @task_params
*/
struct qed_nvmetcp_ops {
const struct qed_common_ops *common;

1
include/linux/qed/rdma_common.h
View File

@ -27,6 +27,7 @@
#define RDMA_MAX_PDS (64 * 1024)
#define RDMA_MAX_XRC_SRQS (1024)
#define RDMA_MAX_SRQS (32 * 1024)
#define RDMA_MAX_IRQ_ELEMS_IN_PAGE (128)
#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
#define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2