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drm/i915/dsb: Introduce intel_dsb_align_tail()
Move the DSB tail cacheline alignment to a helper. No need to pollute the caller with mundane details like this. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221216003810.13338-10-ville.syrjala@linux.intel.com Reviewed-by: Animesh Manna <animesh.manna@intel.com>
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@ -187,6 +187,22 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
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}
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}
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static u32 intel_dsb_align_tail(struct intel_dsb *dsb)
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{
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u32 aligned_tail, tail;
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tail = dsb->free_pos * 4;
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aligned_tail = ALIGN(tail, CACHELINE_BYTES);
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if (aligned_tail > tail)
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memset(&dsb->cmd_buf[dsb->free_pos], 0,
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aligned_tail - tail);
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dsb->free_pos = aligned_tail / 4;
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return aligned_tail;
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}
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/**
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* intel_dsb_commit() - Trigger workload execution of DSB.
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* @dsb: DSB context
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@ -200,14 +216,10 @@ void intel_dsb_commit(struct intel_dsb *dsb)
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enum pipe pipe = crtc->pipe;
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u32 tail;
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if (!(dsb && dsb->free_pos))
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tail = intel_dsb_align_tail(dsb);
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if (tail == 0)
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return;
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tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
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if (tail > dsb->free_pos * 4)
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memset(&dsb->cmd_buf[dsb->free_pos], 0,
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(tail - dsb->free_pos * 4));
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if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
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drm_err(&dev_priv->drm, "DSB engine is busy.\n");
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goto reset;
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