mirror of
https://github.com/torvalds/linux.git
synced 2026-05-24 07:03:03 +02:00
Merge drm/drm-next into drm-intel-next
Bring drm-intel-next closer to drm-next and drm-intel-gt-next for a more feasible baseline for topic branches. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula
commit
e42c6c1bc8
|
|
@ -109,8 +109,8 @@ ForEachMacros:
|
|||
- 'css_for_each_child'
|
||||
- 'css_for_each_descendant_post'
|
||||
- 'css_for_each_descendant_pre'
|
||||
- 'cxl_for_each_cmd'
|
||||
- 'device_for_each_child_node'
|
||||
- 'displayid_iter_for_each'
|
||||
- 'dma_fence_chain_for_each'
|
||||
- 'do_for_each_ftrace_op'
|
||||
- 'drm_atomic_crtc_for_each_plane'
|
||||
|
|
@ -136,6 +136,7 @@ ForEachMacros:
|
|||
- 'drm_mm_for_each_node_in_range'
|
||||
- 'drm_mm_for_each_node_safe'
|
||||
- 'flow_action_for_each'
|
||||
- 'for_each_acpi_dev_match'
|
||||
- 'for_each_active_dev_scope'
|
||||
- 'for_each_active_drhd_unit'
|
||||
- 'for_each_active_iommu'
|
||||
|
|
@ -171,7 +172,6 @@ ForEachMacros:
|
|||
- 'for_each_dapm_widgets'
|
||||
- 'for_each_dev_addr'
|
||||
- 'for_each_dev_scope'
|
||||
- 'for_each_displayid_db'
|
||||
- 'for_each_dma_cap_mask'
|
||||
- 'for_each_dpcm_be'
|
||||
- 'for_each_dpcm_be_rollback'
|
||||
|
|
@ -179,6 +179,7 @@ ForEachMacros:
|
|||
- 'for_each_dpcm_fe'
|
||||
- 'for_each_drhd_unit'
|
||||
- 'for_each_dss_dev'
|
||||
- 'for_each_dtpm_table'
|
||||
- 'for_each_efi_memory_desc'
|
||||
- 'for_each_efi_memory_desc_in_map'
|
||||
- 'for_each_element'
|
||||
|
|
@ -215,6 +216,7 @@ ForEachMacros:
|
|||
- 'for_each_migratetype_order'
|
||||
- 'for_each_msi_entry'
|
||||
- 'for_each_msi_entry_safe'
|
||||
- 'for_each_msi_vector'
|
||||
- 'for_each_net'
|
||||
- 'for_each_net_continue_reverse'
|
||||
- 'for_each_netdev'
|
||||
|
|
@ -270,6 +272,12 @@ ForEachMacros:
|
|||
- 'for_each_prime_number_from'
|
||||
- 'for_each_process'
|
||||
- 'for_each_process_thread'
|
||||
- 'for_each_prop_codec_conf'
|
||||
- 'for_each_prop_dai_codec'
|
||||
- 'for_each_prop_dai_cpu'
|
||||
- 'for_each_prop_dlc_codecs'
|
||||
- 'for_each_prop_dlc_cpus'
|
||||
- 'for_each_prop_dlc_platforms'
|
||||
- 'for_each_property_of_node'
|
||||
- 'for_each_registered_fb'
|
||||
- 'for_each_requested_gpio'
|
||||
|
|
@ -430,6 +438,7 @@ ForEachMacros:
|
|||
- 'queue_for_each_hw_ctx'
|
||||
- 'radix_tree_for_each_slot'
|
||||
- 'radix_tree_for_each_tagged'
|
||||
- 'rb_for_each'
|
||||
- 'rbtree_postorder_for_each_entry_safe'
|
||||
- 'rdma_for_each_block'
|
||||
- 'rdma_for_each_port'
|
||||
|
|
|
|||
3
.mailmap
3
.mailmap
|
|
@ -243,6 +243,9 @@ Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
|
|||
Mayuresh Janorkar <mayur@ti.com>
|
||||
Michael Buesch <m@bues.ch>
|
||||
Michel Dänzer <michel@tungstengraphics.com>
|
||||
Michel Lespinasse <michel@lespinasse.org>
|
||||
Michel Lespinasse <michel@lespinasse.org> <walken@google.com>
|
||||
Michel Lespinasse <michel@lespinasse.org> <walken@zoy.org>
|
||||
Miguel Ojeda <ojeda@kernel.org> <miguel.ojeda.sandonis@gmail.com>
|
||||
Mike Rapoport <rppt@kernel.org> <mike@compulab.co.il>
|
||||
Mike Rapoport <rppt@kernel.org> <mike.rapoport@gmail.com>
|
||||
|
|
|
|||
|
|
@ -1458,11 +1458,22 @@ unprivileged_bpf_disabled
|
|||
=========================
|
||||
|
||||
Writing 1 to this entry will disable unprivileged calls to ``bpf()``;
|
||||
once disabled, calling ``bpf()`` without ``CAP_SYS_ADMIN`` will return
|
||||
``-EPERM``.
|
||||
once disabled, calling ``bpf()`` without ``CAP_SYS_ADMIN`` or ``CAP_BPF``
|
||||
will return ``-EPERM``. Once set to 1, this can't be cleared from the
|
||||
running kernel anymore.
|
||||
|
||||
Once set, this can't be cleared.
|
||||
Writing 2 to this entry will also disable unprivileged calls to ``bpf()``,
|
||||
however, an admin can still change this setting later on, if needed, by
|
||||
writing 0 or 1 to this entry.
|
||||
|
||||
If ``BPF_UNPRIV_DEFAULT_OFF`` is enabled in the kernel config, then this
|
||||
entry will default to 2 instead of 0.
|
||||
|
||||
= =============================================================
|
||||
0 Unprivileged calls to ``bpf()`` are enabled
|
||||
1 Unprivileged calls to ``bpf()`` are disabled without recovery
|
||||
2 Unprivileged calls to ``bpf()`` are disabled
|
||||
= =============================================================
|
||||
|
||||
watchdog
|
||||
========
|
||||
|
|
|
|||
|
|
@ -60,7 +60,6 @@ properties:
|
|||
maxItems: 2
|
||||
|
||||
idt,xtal-load-femtofarads:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 9000
|
||||
maximum: 22760
|
||||
description: Optional load capacitor for XTAL1 and XTAL2
|
||||
|
|
@ -84,7 +83,6 @@ patternProperties:
|
|||
enum: [ 1800000, 2500000, 3300000 ]
|
||||
idt,slew-percent:
|
||||
description: The Slew rate control for CMOS single-ended.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 80, 85, 90, 100 ]
|
||||
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -149,6 +149,17 @@ properties:
|
|||
maxItems: 6
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
sink-vdos-v1:
|
||||
description: An array of u32 with each entry, a Vendor Defined Message Object (VDO),
|
||||
providing additional information corresponding to the product, the detailed bit
|
||||
definitions and the order of each VDO can be found in
|
||||
"USB Power Delivery Specification Revision 2.0, Version 1.3" chapter 6.4.4.3.1 Discover
|
||||
Identity. User can specify the VDO array via VDO_IDH/_CERT/_PRODUCT/_CABLE/_AMA defined in
|
||||
dt-bindings/usb/pd.h.
|
||||
minItems: 3
|
||||
maxItems: 6
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
op-sink-microwatt:
|
||||
description: Sink required operating power in microwatt, if source can't
|
||||
offer the power, Capability Mismatch is set. Required for power sink and
|
||||
|
|
@ -207,6 +218,10 @@ properties:
|
|||
SNK_READY for non-pd link.
|
||||
type: boolean
|
||||
|
||||
dependencies:
|
||||
sink-vdos-v1: [ 'sink-vdos' ]
|
||||
sink-vdos: [ 'sink-vdos-v1' ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,9 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,bcm2835-vec
|
||||
enum:
|
||||
- brcm,bcm2711-vec
|
||||
- brcm,bcm2835-vec
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,82 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
|
||||
|
||||
maintainers:
|
||||
- Nicolas Boichat <drinkcat@chromium.org>
|
||||
- Enric Balletbo i Serra <enric.balletbo@collabora.com>
|
||||
|
||||
description: |
|
||||
ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
|
||||
DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
|
||||
which is connected to and operated by the ChromeOS Embedded Controller
|
||||
(See google,cros-ec.yaml). It is accessed using I2C tunneling through
|
||||
the EC and therefore its node should be a child of an EC I2C tunnel node
|
||||
(See google,cros-ec-i2c-tunnel.yaml).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: google,cros-ec-anx7688
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: I2C address of the device.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for HDMI input.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: USB Type-c connector.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c_tunnel_b: i2c-tunnel1 {
|
||||
compatible = "google,cros-ec-i2c-tunnel";
|
||||
google,remote-bus = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
anx7688: anx7688@2c {
|
||||
compatible = "google,cros-ec-anx7688";
|
||||
reg = <0x2c>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
anx7688_in: endpoint {
|
||||
remote-endpoint = <&hdmi0_out>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
anx7688_out: endpoint {
|
||||
remote-endpoint = <&typec_connector>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi83.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
description: |
|
||||
Texas Instruments SN65DSI83 1x Single-link MIPI DSI
|
||||
to 1x Single-link LVDS
|
||||
https://www.ti.com/lit/gpn/sn65dsi83
|
||||
Texas Instruments SN65DSI84 1x Single-link MIPI DSI
|
||||
to 1x Dual-link or 2x Single-link LVDS
|
||||
https://www.ti.com/lit/gpn/sn65dsi84
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,sn65dsi83
|
||||
- ti,sn65dsi84
|
||||
|
||||
reg:
|
||||
enum:
|
||||
- 0x2c
|
||||
- 0x2d
|
||||
|
||||
enable-gpios:
|
||||
maxItems: 1
|
||||
description: GPIO specifier for bridge_en pin (active high).
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for MIPI DSI Channel-A input
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
description: array of physical DSI data lane indexes.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: 1
|
||||
- const: 2
|
||||
- const: 3
|
||||
- const: 4
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for MIPI DSI Channel-B input
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
data-lanes:
|
||||
description: array of physical DSI data lane indexes.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
- const: 1
|
||||
- const: 2
|
||||
- const: 3
|
||||
- const: 4
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for LVDS Channel-A output (panel or bridge).
|
||||
|
||||
port@3:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Video port for LVDS Channel-B output (panel or bridge).
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- enable-gpios
|
||||
- ports
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,sn65dsi83
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
properties:
|
||||
port@1: false
|
||||
port@3: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,sn65dsi84
|
||||
then:
|
||||
properties:
|
||||
ports:
|
||||
properties:
|
||||
port@1: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
bridge@2d {
|
||||
compatible = "ti,sn65dsi83";
|
||||
reg = <0x2d>;
|
||||
|
||||
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&panel_in_lvds>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
* Faraday TV Encoder TVE200
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be one of:
|
||||
"faraday,tve200"
|
||||
"cortina,gemini-tvc", "faraday,tve200"
|
||||
|
||||
- reg: base address and size of the control registers block
|
||||
|
||||
- interrupts: contains an interrupt specifier for the interrupt
|
||||
line from the TVE200
|
||||
|
||||
- clock-names: should contain "PCLK" for the clock line clocking the
|
||||
silicon and "TVE" for the 27MHz clock to the video driver
|
||||
|
||||
- clocks: contains phandle and clock specifier pairs for the entries
|
||||
in the clock-names property. See
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Optional properties:
|
||||
|
||||
- resets: contains the reset line phandle for the block
|
||||
|
||||
Required sub-nodes:
|
||||
|
||||
- port: describes LCD panel signals, following the common binding
|
||||
for video transmitter interfaces; see
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
This port should have the properties:
|
||||
reg = <0>;
|
||||
It should have one endpoint connected to a remote endpoint where
|
||||
the display is connected.
|
||||
|
||||
Example:
|
||||
|
||||
display-controller@6a000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "faraday,tve200";
|
||||
reg = <0x6a000000 0x1000>;
|
||||
interrupts = <13 IRQ_TYPE_EDGE_RISING>;
|
||||
resets = <&syscon GEMINI_RESET_TVC>;
|
||||
clocks = <&syscon GEMINI_CLK_GATE_TVC>,
|
||||
<&syscon GEMINI_CLK_TVC>;
|
||||
clock-names = "PCLK", "TVE";
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
display_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/faraday,tve200.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Faraday TV Encoder TVE200
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linus.walleij@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: faraday,tve200
|
||||
- items:
|
||||
- const: cortina,gemini-tvc
|
||||
- const: faraday,tve200
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: PCLK
|
||||
- const: TVE
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clock-names
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/cortina,gemini-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/reset/cortina,gemini-reset.h>
|
||||
display-controller@6a000000 {
|
||||
compatible = "faraday,tve200";
|
||||
reg = <0x6a000000 0x1000>;
|
||||
interrupts = <13 IRQ_TYPE_EDGE_RISING>;
|
||||
resets = <&syscon GEMINI_RESET_TVC>;
|
||||
clocks = <&syscon GEMINI_CLK_GATE_TVC>,
|
||||
<&syscon GEMINI_CLK_TVC>;
|
||||
clock-names = "PCLK", "TVE";
|
||||
|
||||
port {
|
||||
display_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek HDMI CEC Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- CK Hu <ck.hu@mediatek.com>
|
||||
- Jitao shi <jitao.shi@mediatek.com>
|
||||
|
||||
description: |
|
||||
The HDMI CEC controller handles hotplug detection and CEC communication.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7623-cec
|
||||
- mediatek,mt8167-cec
|
||||
- mediatek,mt8173-cec
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
cec: cec@10013000 {
|
||||
compatible = "mediatek,mt8173-cec";
|
||||
reg = <0x10013000 0xbc>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_CEC>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek HDMI DDC Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- CK Hu <ck.hu@mediatek.com>
|
||||
- Jitao shi <jitao.shi@mediatek.com>
|
||||
|
||||
description: |
|
||||
The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7623-hdmi-ddc
|
||||
- mediatek,mt8167-hdmi-ddc
|
||||
- mediatek,mt8173-hdmi-ddc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ddc-i2c
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
hdmi_ddc0: i2c@11012000 {
|
||||
compatible = "mediatek,mt8173-hdmi-ddc";
|
||||
reg = <0x11012000 0x1c>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_I2C5>;
|
||||
clock-names = "ddc-i2c";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,136 +0,0 @@
|
|||
Mediatek HDMI Encoder
|
||||
=====================
|
||||
|
||||
The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
|
||||
its parallel input.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-hdmi".
|
||||
- the supported chips are mt2701, mt7623 and mt8173
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
|
||||
- phys: phandle link to the HDMI PHY node.
|
||||
See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
|
||||
- phy-names: must contain "hdmi"
|
||||
- mediatek,syscon-hdmi: phandle link and register offset to the system
|
||||
configuration registers. For mt8173 this must be offset 0x900 into the
|
||||
MMSYS_CONFIG region: <&mmsys 0x900>.
|
||||
- ports: A node containing input and output port nodes with endpoint
|
||||
definitions as documented in Documentation/devicetree/bindings/graph.txt.
|
||||
- port@0: The input port in the ports node should be connected to a DPI output
|
||||
port.
|
||||
- port@1: The output port in the ports node should be connected to the input
|
||||
port of a connector node that contains a ddc-i2c-bus property, or to the
|
||||
input port of an attached bridge chip, such as a SlimPort transmitter.
|
||||
|
||||
HDMI CEC
|
||||
========
|
||||
|
||||
The HDMI CEC controller handles hotplug detection and CEC communication.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-cec"
|
||||
- the supported chips are mt7623 and mt8173
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clock
|
||||
|
||||
HDMI DDC
|
||||
========
|
||||
|
||||
The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
|
||||
The Mediatek's I2C controller is used to interface with I2C devices.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
|
||||
- the supported chips are mt7623 and mt8173
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: device clock
|
||||
- clock-names: Should be "ddc-i2c".
|
||||
|
||||
HDMI PHY
|
||||
========
|
||||
See phy/mediatek,hdmi-phy.yaml
|
||||
|
||||
Example:
|
||||
|
||||
cec: cec@10013000 {
|
||||
compatible = "mediatek,mt8173-cec";
|
||||
reg = <0 0x10013000 0 0xbc>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&infracfg CLK_INFRA_CEC>;
|
||||
};
|
||||
|
||||
hdmi_phy: hdmi-phy@10209100 {
|
||||
compatible = "mediatek,mt8173-hdmi-phy";
|
||||
reg = <0 0x10209100 0 0x24>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
|
||||
clock-names = "pll_ref";
|
||||
clock-output-names = "hdmitx_dig_cts";
|
||||
mediatek,ibias = <0xa>;
|
||||
mediatek,ibias_up = <0x1c>;
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
hdmi_ddc0: i2c@11012000 {
|
||||
compatible = "mediatek,mt8173-hdmi-ddc";
|
||||
reg = <0 0x11012000 0 0x1c>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_I2C5>;
|
||||
clock-names = "ddc-i2c";
|
||||
};
|
||||
|
||||
hdmi0: hdmi@14025000 {
|
||||
compatible = "mediatek,mt8173-hdmi";
|
||||
reg = <0 0x14025000 0 0x400>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
|
||||
<&mmsys CLK_MM_HDMI_PLLCK>,
|
||||
<&mmsys CLK_MM_HDMI_AUDIO>,
|
||||
<&mmsys CLK_MM_HDMI_SPDIF>;
|
||||
clock-names = "pixel", "pll", "bclk", "spdif";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pin>;
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi";
|
||||
mediatek,syscon-hdmi = <&mmsys 0x900>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
|
||||
assigned-clock-parents = <&hdmi_phy>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
connector {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
ddc-i2c-bus = <&hdmiddc0>;
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek HDMI Encoder Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- CK Hu <ck.hu@mediatek.com>
|
||||
- Jitao shi <jitao.shi@mediatek.com>
|
||||
|
||||
description: |
|
||||
The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
|
||||
its parallel input.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt2701-hdmi
|
||||
- mediatek,mt7623-hdmi
|
||||
- mediatek,mt8167-hdmi
|
||||
- mediatek,mt8173-hdmi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Pixel Clock
|
||||
- description: HDMI PLL
|
||||
- description: Bit Clock
|
||||
- description: S/PDIF Clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pixel
|
||||
- const: pll
|
||||
- const: bclk
|
||||
- const: spdif
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: hdmi
|
||||
|
||||
mediatek,syscon-hdmi:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle-array'
|
||||
maxItems: 1
|
||||
description: |
|
||||
phandle link and register offset to the system configuration registers.
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: |
|
||||
Input port node. This port should be connected to a DPI output port.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: |
|
||||
Output port node. This port should be connected to the input port of a connector
|
||||
node that contains a ddc-i2c-bus property, or to the input port of an attached
|
||||
bridge chip, such as a SlimPort transmitter.
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- mediatek,syscon-hdmi
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8173-clk.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
hdmi0: hdmi@14025000 {
|
||||
compatible = "mediatek,mt8173-hdmi";
|
||||
reg = <0x14025000 0x400>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
|
||||
<&mmsys CLK_MM_HDMI_PLLCK>,
|
||||
<&mmsys CLK_MM_HDMI_AUDIO>,
|
||||
<&mmsys CLK_MM_HDMI_SPDIF>;
|
||||
clock-names = "pixel", "pll", "bclk", "spdif";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pin>;
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi";
|
||||
mediatek,syscon-hdmi = <&mmsys 0x900>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi0_in: endpoint {
|
||||
remote-endpoint = <&dpi0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
hdmi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
146
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
Normal file
146
Documentation/devicetree/bindings/display/msm/dp-controller.yaml
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MSM Display Port Controller
|
||||
|
||||
maintainers:
|
||||
- Kuogee Hsieh <khsieh@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Device tree bindings for DisplayPort host controller for MSM targets
|
||||
that are compatible with VESA DisplayPort interface specification.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-dp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB clock to enable register access
|
||||
- description: Display Port AUX clock
|
||||
- description: Display Port Link clock
|
||||
- description: Link interface clock between DP and PHY
|
||||
- description: Display Port Pixel clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core_iface
|
||||
- const: core_aux
|
||||
- const: ctrl_link
|
||||
- const: ctrl_link_iface
|
||||
- const: stream_pixel
|
||||
|
||||
assigned-clocks:
|
||||
items:
|
||||
- description: link clock source
|
||||
- description: pixel clock source
|
||||
|
||||
assigned-clock-parents:
|
||||
items:
|
||||
- description: phy 0 parent
|
||||
- description: phy 1 parent
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: dp
|
||||
|
||||
operating-points-v2:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
"#sound-dai-cells":
|
||||
const: 0
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Input endpoint of the controller
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Output endpoint of the controller
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- "#sound-dai-cells"
|
||||
- power-domains
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
|
||||
#include <dt-bindings/power/qcom-aoss-qmp.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
displayport-controller@ae90000 {
|
||||
compatible = "qcom,sc7180-dp";
|
||||
reg = <0xae90000 0x1400>;
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <12>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
|
||||
clock-names = "core_iface", "core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface", "stream_pixel";
|
||||
|
||||
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
|
||||
|
||||
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
|
||||
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
endpoint {
|
||||
remote-endpoint = <&typec>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
228
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
Normal file
228
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
Normal file
|
|
@ -0,0 +1,228 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SC7180 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for SC7180 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AHB clock from dispcc
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ahb
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
|
||||
ranges: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: Interconnect path specifying the port ids for data bus
|
||||
|
||||
interconnect-names:
|
||||
const: mdp0-mem
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sc7180-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display hf axi clock
|
||||
- description: Display ahb clock
|
||||
- description: Display rotator clock
|
||||
- description: Display lut clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: iface
|
||||
- const: rot
|
||||
- const: lut
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF0 (DP)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interconnect/qcom,sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sc7180-mdss";
|
||||
reg = <0xae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "ahb", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sc7180-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ROT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "bus", "iface", "rot", "lut", "core",
|
||||
"vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
212
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
Normal file
212
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
Normal file
|
|
@ -0,0 +1,212 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DPU dt properties for SDM845 target
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
|
||||
bindings of MDSS and DPU are mentioned for SDM845 target.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-mdss
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: mdss
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock from gcc
|
||||
- description: Display AXI clock
|
||||
- description: Display core clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
iommus:
|
||||
items:
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
|
||||
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
|
||||
|
||||
ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Node containing the properties of DPU.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,sdm845-dpu
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Address offset and size for mdp register set
|
||||
- description: Address offset and size for vbif register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: mdp
|
||||
- const: vbif
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display ahb clock
|
||||
- description: Display axi clock
|
||||
- description: Display core clock
|
||||
- description: Display vsync clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
description: |
|
||||
Contains the list of output ports from DPU device. These ports
|
||||
connect to interfaces that are external to the DPU hardware,
|
||||
such as DSI, DP etc. Each output port contains an endpoint that
|
||||
describes how it is connected to an external interface.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF1 (DSI1)
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: DPU_INTF2 (DSI2)
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- interrupts
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- power-domains
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- iommus
|
||||
- ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "qcom,sdm845-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&gcc GCC_DISP_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
iommus = <&apps_smmu 0x880 0x8>,
|
||||
<&apps_smmu 0xc80 0x8>;
|
||||
ranges;
|
||||
|
||||
display-controller@ae01000 {
|
||||
compatible = "qcom,sdm845-dpu";
|
||||
reg = <0x0ae01000 0x8f000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <0>;
|
||||
power-domains = <&rpmhpd SDM845_CX>;
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,141 +0,0 @@
|
|||
Qualcomm Technologies, Inc. DPU KMS
|
||||
|
||||
Description:
|
||||
|
||||
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
|
||||
sub-blocks like DPU display controller, DSI and DP interfaces etc.
|
||||
The DPU display controller is found in SDM845 SoC.
|
||||
|
||||
MDSS:
|
||||
Required properties:
|
||||
- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
|
||||
- reg: physical base address and length of controller's registers.
|
||||
- reg-names: register region names. The following region is required:
|
||||
* "mdss"
|
||||
- power-domains: a power domain consumer specifier according to
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
- clocks: list of clock specifiers for clocks needed by the device.
|
||||
- clock-names: device clock names, must be in same order as clocks property.
|
||||
The following clocks are required:
|
||||
* "iface"
|
||||
* "bus"
|
||||
* "core"
|
||||
- interrupts: interrupt signal from MDSS.
|
||||
- interrupt-controller: identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
|
||||
source, should be 1.
|
||||
- iommus: phandle of iommu device node.
|
||||
- #address-cells: number of address cells for the MDSS children. Should be 1.
|
||||
- #size-cells: Should be 1.
|
||||
- ranges: parent bus address space is the same as the child bus address space.
|
||||
- interconnects : interconnect path specifier for MDSS according to
|
||||
Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
|
||||
2 paths corresponding to 2 AXI ports.
|
||||
- interconnect-names : MDSS will have 2 port names to differentiate between the
|
||||
2 interconnect paths defined with interconnect specifier.
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
|
||||
- assigned-clock-rates: list of clock frequencies sorted in the same order as
|
||||
the assigned-clocks property.
|
||||
|
||||
MDP:
|
||||
Required properties:
|
||||
- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
|
||||
- reg: physical base address and length of controller's registers.
|
||||
- reg-names : register region names. The following region is required:
|
||||
* "mdp"
|
||||
* "vbif"
|
||||
- clocks: list of clock specifiers for clocks needed by the device.
|
||||
- clock-names: device clock names, must be in same order as clocks property.
|
||||
The following clocks are required.
|
||||
* "bus"
|
||||
* "iface"
|
||||
* "core"
|
||||
* "vsync"
|
||||
- interrupts: interrupt line from DPU to MDSS.
|
||||
- ports: contains the list of output ports from DPU device. These ports connect
|
||||
to interfaces that are external to the DPU hardware, such as DSI, DP etc.
|
||||
|
||||
Each output port contains an endpoint that describes how it is connected to an
|
||||
external interface. These are described by the standard properties documented
|
||||
here:
|
||||
Documentation/devicetree/bindings/graph.txt
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Port 0 -> DPU_INTF1 (DSI1)
|
||||
Port 1 -> DPU_INTF2 (DSI2)
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
|
||||
- assigned-clock-rates: list of clock frequencies sorted in the same order as
|
||||
the assigned-clocks property.
|
||||
|
||||
Example:
|
||||
|
||||
mdss: mdss@ae00000 {
|
||||
compatible = "qcom,sdm845-mdss";
|
||||
reg = <0xae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
|
||||
power-domains = <&clock_dispcc 0>;
|
||||
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "iface", "bus", "core";
|
||||
|
||||
assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
assigned-clock-rates = <300000000>;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
|
||||
<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
|
||||
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
iommus = <&apps_iommu 0>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xae00000 0xb2008>;
|
||||
|
||||
mdss_mdp: mdp@ae01000 {
|
||||
compatible = "qcom,sdm845-dpu";
|
||||
reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
|
||||
reg-names = "mdp", "vbif";
|
||||
|
||||
clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
clock-names = "iface", "bus", "core", "vsync";
|
||||
|
||||
assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
|
||||
assigned-clock-rates = <0 0 300000000 19200000>;
|
||||
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&dsi1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI controller
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "../dsi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
const: dsi_ctrl
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display byte clock
|
||||
- description: Display byte interface clock
|
||||
- description: Display pixel clock
|
||||
- description: Display escape clock
|
||||
- description: Display AHB clock
|
||||
- description: Display AXI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: byte
|
||||
- const: byte_intf
|
||||
- const: pixel
|
||||
- const: core
|
||||
- const: iface
|
||||
- const: bus
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
phy-names:
|
||||
const: dsi
|
||||
|
||||
"#address-cells": true
|
||||
|
||||
"#size-cells": true
|
||||
|
||||
syscon-sfpb:
|
||||
description: A phandle to mmss_sfpb syscon node (only for DSIv2).
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
qcom,dual-dsi-mode:
|
||||
type: boolean
|
||||
description: |
|
||||
Indicates if the DSI controller is driving a panel which needs
|
||||
2 DSI links.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
ports:
|
||||
$ref: "/schemas/graph.yaml#/properties/ports"
|
||||
description: |
|
||||
Contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
properties:
|
||||
port@0:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
description: |
|
||||
Input endpoints of the controller.
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
port@1:
|
||||
$ref: "/schemas/graph.yaml#/properties/port"
|
||||
description: |
|
||||
Output endpoints of the controller.
|
||||
properties:
|
||||
endpoint:
|
||||
$ref: /schemas/media/video-interfaces.yaml#
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
data-lanes:
|
||||
maxItems: 4
|
||||
minItems: 4
|
||||
items:
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
required:
|
||||
- port@0
|
||||
- port@1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- phys
|
||||
- phy-names
|
||||
- power-domains
|
||||
- operating-points-v2
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&mdss>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AXI_CLK>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus";
|
||||
|
||||
phys = <&dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
power-domains = <&rpmhpd SC7180_CX>;
|
||||
operating-points-v2 = <&dsi_opp_table>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&sn65dsi86_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 10nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-10nm
|
||||
- const: qcom,dsi-phy-10nm-8998
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy lane register set
|
||||
- description: dsi pll register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_lane
|
||||
- const: dsi_pll
|
||||
|
||||
vdds-supply:
|
||||
description: |
|
||||
Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
|
||||
connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vdds-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-10nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdds-supply = <&vdda_mipi_dsi0_pll>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 14nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-14nm
|
||||
- const: qcom,dsi-phy-14nm-660
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy lane register set
|
||||
- description: dsi pll register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_lane
|
||||
- const: dsi_pll
|
||||
|
||||
vcca-supply:
|
||||
description: Phandle to vcca regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vcca-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@ae94400 {
|
||||
compatible = "qcom,dsi-phy-14nm";
|
||||
reg = <0x0ae94400 0x200>,
|
||||
<0x0ae94600 0x280>,
|
||||
<0x0ae94a00 0x1e0>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vcca-supply = <&vcca_reg>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 20nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-20nm
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi pll register set
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy regulator register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_pll
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_regulator
|
||||
|
||||
vcca-supply:
|
||||
description: Phandle to vcca regulator device node.
|
||||
|
||||
vddio-supply:
|
||||
description: Phandle to vdd-io regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vddio-supply
|
||||
- vcca-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-20nm";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vcca-supply = <&vcca_reg>;
|
||||
vddio-supply = <&vddio_reg>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 28nm PHY
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: qcom,dsi-phy-28nm-hpm
|
||||
- const: qcom,dsi-phy-28nm-lp
|
||||
- const: qcom,dsi-phy-28nm-8960
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: dsi pll register set
|
||||
- description: dsi phy register set
|
||||
- description: dsi phy regulator register set
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dsi_pll
|
||||
- const: dsi_phy
|
||||
- const: dsi_phy_regulator
|
||||
|
||||
vddio-supply:
|
||||
description: Phandle to vdd-io regulator device node.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- vddio-supply
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-lp";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
reg-names = "dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vddio-supply = <&vddio_reg>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface", "ref";
|
||||
};
|
||||
...
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Description of Qualcomm Display DSI PHY common dt properties
|
||||
|
||||
maintainers:
|
||||
- Krishna Manikandan <mkrishn@codeaurora.org>
|
||||
|
||||
description: |
|
||||
This defines the DSI PHY dt properties which are common for all
|
||||
dsi phy versions.
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB clock
|
||||
- description: Board XO source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: iface
|
||||
- const: ref
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: true
|
||||
...
|
||||
|
|
@ -1,249 +0,0 @@
|
|||
Qualcomm Technologies Inc. adreno/snapdragon DSI output
|
||||
|
||||
DSI Controller:
|
||||
Required properties:
|
||||
- compatible:
|
||||
* "qcom,mdss-dsi-ctrl"
|
||||
- reg: Physical base address and length of the registers of controller
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
* "dsi_ctrl"
|
||||
- interrupts: The interrupt signal from the DSI block.
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: Phandles to device clocks.
|
||||
- clock-names: the following clocks are required:
|
||||
* "mdp_core"
|
||||
* "iface"
|
||||
* "bus"
|
||||
* "core_mmss"
|
||||
* "byte"
|
||||
* "pixel"
|
||||
* "core"
|
||||
For DSIv2, we need an additional clock:
|
||||
* "src"
|
||||
For DSI6G v2.0 onwards, we need also need the clock:
|
||||
* "byte_intf"
|
||||
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
|
||||
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
|
||||
by a DSI PHY block. See [1] for details on clock bindings.
|
||||
- vdd-supply: phandle to vdd regulator device node
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
- vdda-supply: phandle to vdda regulator device node
|
||||
- phys: phandle to DSI PHY device node
|
||||
- phy-names: the name of the corresponding PHY device
|
||||
- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
|
||||
- ports: Contains 2 DSI controller ports as child nodes. Each port contains
|
||||
an endpoint subnode as defined in [2] and [3].
|
||||
|
||||
Optional properties:
|
||||
- panel@0: Node of panel connected to this DSI controller.
|
||||
See files in [4] for each supported panel.
|
||||
- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
|
||||
driving a panel which needs 2 DSI links.
|
||||
- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
|
||||
the master link of the 2-DSI panel.
|
||||
- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
|
||||
driving a 2-DSI panel whose 2 links need receive command simultaneously.
|
||||
- pinctrl-names: the pin control state names; should contain "default"
|
||||
- pinctrl-0: the default pinctrl state (active)
|
||||
- pinctrl-n: the "sleep" pinctrl state
|
||||
- ports: contains DSI controller input and output ports as children, each
|
||||
containing one endpoint subnode.
|
||||
|
||||
DSI Endpoint properties:
|
||||
- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
|
||||
input endpoint. For port@1, set to the MDP interface output. See [2] for
|
||||
device graph info.
|
||||
|
||||
- data-lanes: this describes how the physical DSI data lanes are mapped
|
||||
to the logical lanes on the given platform. The value contained in
|
||||
index n describes what physical lane is mapped to the logical lane n
|
||||
(DATAn, where n lies between 0 and 3). The clock lane position is fixed
|
||||
and can't be changed. Hence, they aren't a part of the DT bindings. See
|
||||
[3] for more info on the data-lanes property.
|
||||
|
||||
For example:
|
||||
|
||||
data-lanes = <3 0 1 2>;
|
||||
|
||||
The above mapping describes that the logical data lane DATA0 is mapped to
|
||||
the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
|
||||
to phys DATA1 and logic DATA3 to phys DATA2.
|
||||
|
||||
There are only a limited number of physical to logical mappings possible:
|
||||
<0 1 2 3>
|
||||
<1 2 3 0>
|
||||
<2 3 0 1>
|
||||
<3 0 1 2>
|
||||
<0 3 2 1>
|
||||
<1 0 3 2>
|
||||
<2 1 0 3>
|
||||
<3 2 1 0>
|
||||
|
||||
DSI PHY:
|
||||
Required properties:
|
||||
- compatible: Could be the following
|
||||
* "qcom,dsi-phy-28nm-hpm"
|
||||
* "qcom,dsi-phy-28nm-lp"
|
||||
* "qcom,dsi-phy-20nm"
|
||||
* "qcom,dsi-phy-28nm-8960"
|
||||
* "qcom,dsi-phy-14nm"
|
||||
* "qcom,dsi-phy-14nm-660"
|
||||
* "qcom,dsi-phy-10nm"
|
||||
* "qcom,dsi-phy-10nm-8998"
|
||||
* "qcom,dsi-phy-7nm"
|
||||
* "qcom,dsi-phy-7nm-8150"
|
||||
- reg: Physical base address and length of the registers of PLL, PHY. Some
|
||||
revisions require the PHY regulator base address, whereas others require the
|
||||
PHY lane base address. See below for each PHY revision.
|
||||
- reg-names: The names of register regions. The following regions are required:
|
||||
For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
|
||||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_regulator"
|
||||
For DSI 14nm, 10nm and 7nm PHYs:
|
||||
* "dsi_pll"
|
||||
* "dsi_phy"
|
||||
* "dsi_phy_lane"
|
||||
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
|
||||
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
|
||||
- power-domains: Should be <&mmcc MDSS_GDSC>.
|
||||
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
|
||||
- clock-names: the following clocks are required:
|
||||
* "iface"
|
||||
* "ref" (only required for new DTS files/entries)
|
||||
For 28nm HPM/LP, 28nm 8960 PHYs:
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
For 20nm PHY:
|
||||
- vddio-supply: phandle to vdd-io regulator device node
|
||||
- vcca-supply: phandle to vcca regulator device node
|
||||
For 14nm PHY:
|
||||
- vcca-supply: phandle to vcca regulator device node
|
||||
For 10nm and 7nm PHY:
|
||||
- vdds-supply: phandle to vdds regulator device node
|
||||
|
||||
Optional properties:
|
||||
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
|
||||
regulator is wanted.
|
||||
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
|
||||
panels in microseconds. Driver uses this number to adjust
|
||||
the clock rate according to the expected transfer time.
|
||||
Increasing this value would slow down the mdp processing
|
||||
and can result in slower performance.
|
||||
Decreasing this value can speed up the mdp processing,
|
||||
but this can also impact power consumption.
|
||||
As a rule this time should not be higher than the time
|
||||
that would be expected with the processing at the
|
||||
dsi link rate since anyways this would be the maximum
|
||||
transfer time that could be achieved.
|
||||
If ping pong split is enabled, this time should not be higher
|
||||
than two times the dsi link rate time.
|
||||
If the property is not specified, then the default value is 14000 us.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/graph.txt
|
||||
[3] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
[4] Documentation/devicetree/bindings/display/panel/
|
||||
|
||||
Example:
|
||||
dsi0: dsi@fd922800 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
qcom,dsi-host-index = <0>;
|
||||
interrupt-parent = <&mdp>;
|
||||
interrupts = <4 0>;
|
||||
reg-names = "dsi_ctrl";
|
||||
reg = <0xfd922800 0x200>;
|
||||
power-domains = <&mmcc MDSS_GDSC>;
|
||||
clock-names =
|
||||
"bus",
|
||||
"byte",
|
||||
"core",
|
||||
"core_mmss",
|
||||
"iface",
|
||||
"mdp_core",
|
||||
"pixel";
|
||||
clocks =
|
||||
<&mmcc MDSS_AXI_CLK>,
|
||||
<&mmcc MDSS_BYTE0_CLK>,
|
||||
<&mmcc MDSS_ESC0_CLK>,
|
||||
<&mmcc MMSS_MISC_AHB_CLK>,
|
||||
<&mmcc MDSS_AHB_CLK>,
|
||||
<&mmcc MDSS_MDP_CLK>,
|
||||
<&mmcc MDSS_PCLK0_CLK>;
|
||||
|
||||
assigned-clocks =
|
||||
<&mmcc BYTE0_CLK_SRC>,
|
||||
<&mmcc PCLK0_CLK_SRC>;
|
||||
assigned-clock-parents =
|
||||
<&dsi_phy0 0>,
|
||||
<&dsi_phy0 1>;
|
||||
|
||||
vdda-supply = <&pma8084_l2>;
|
||||
vdd-supply = <&pma8084_l22>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
phys = <&dsi_phy0>;
|
||||
phy-names ="dsi-phy";
|
||||
|
||||
qcom,dual-dsi-mode;
|
||||
qcom,master-dsi;
|
||||
qcom,sync-dual-dsi;
|
||||
|
||||
qcom,mdss-mdp-transfer-time-us = <12000>;
|
||||
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&dsi_active>;
|
||||
pinctrl-1 = <&dsi_suspend>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
remote-endpoint = <&mdp_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel: panel@0 {
|
||||
compatible = "sharp,lq101r1sx01";
|
||||
reg = <0>;
|
||||
link2 = <&secondary>;
|
||||
|
||||
power-supply = <...>;
|
||||
backlight = <...>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_phy0: dsi-phy@fd922a00 {
|
||||
compatible = "qcom,dsi-phy-28nm-hpm";
|
||||
qcom,dsi-phy-index = <0>;
|
||||
reg-names =
|
||||
"dsi_pll",
|
||||
"dsi_phy",
|
||||
"dsi_phy_regulator";
|
||||
reg = <0xfd922a00 0xd4>,
|
||||
<0xfd922b00 0x2b0>,
|
||||
<0xfd922d80 0x7b>;
|
||||
clock-names = "iface";
|
||||
clocks = <&mmcc MDSS_AHB_CLK>;
|
||||
#clock-cells = <1>;
|
||||
vddio-supply = <&pma8084_l12>;
|
||||
|
||||
qcom,dsi-phy-regulator-ldo-mode;
|
||||
};
|
||||
|
|
@ -49,7 +49,7 @@ examples:
|
|||
#size-cells = <0>;
|
||||
|
||||
adc@48 {
|
||||
comatible = "ti,ads7828";
|
||||
compatible = "ti,ads7828";
|
||||
reg = <0x48>;
|
||||
vref-supply = <&vref>;
|
||||
ti,differential-input;
|
||||
|
|
|
|||
|
|
@ -46,6 +46,13 @@ properties:
|
|||
description: |
|
||||
I2C bus timeout in microseconds
|
||||
|
||||
fsl,i2c-erratum-a004447:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: |
|
||||
Indicates the presence of QorIQ erratum A-004447, which
|
||||
says that the standard i2c recovery scheme mechanism does
|
||||
not work and an alternate implementation is needed.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -102,7 +102,6 @@ patternProperties:
|
|||
|
||||
st,adc-channel-names:
|
||||
description: List of single-ended channel names.
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
|
||||
st,filter-order:
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -38,6 +38,5 @@ properties:
|
|||
Duration in seconds which the key should be kept pressed for device to
|
||||
reset automatically. Device with key pressed reset feature can specify
|
||||
this property.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
additionalProperties: true
|
||||
|
|
|
|||
|
|
@ -92,7 +92,6 @@ properties:
|
|||
this interconnect to send RPMh commands.
|
||||
|
||||
qcom,bcm-voter-names:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description: |
|
||||
Names for each of the qcom,bcm-voters specified.
|
||||
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ This controller is present on BCM6318, BCM6328, BCM6362 and BCM63268.
|
|||
In these SoCs it's possible to control LEDs both as GPIOs or by hardware.
|
||||
However, on some devices there are Serial LEDs (LEDs connected to a 74x164
|
||||
controller), which can either be controlled by software (exporting the 74x164
|
||||
as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
|
||||
by hardware using this driver.
|
||||
as spi-gpio. See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml),
|
||||
or by hardware using this driver.
|
||||
Some of these Serial LEDs are hardware controlled (e.g. ethernet LEDs) and
|
||||
exporting the 74x164 as spi-gpio prevents those LEDs to be hardware
|
||||
controlled, so the only chance to keep them working is by using this driver.
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ LEDs connected to Broadcom BCM6358 controller
|
|||
This controller is present on BCM6358 and BCM6368.
|
||||
In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller),
|
||||
which can either be controlled by software (exporting the 74x164 as spi-gpio.
|
||||
See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
|
||||
See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), or
|
||||
by hardware using this driver.
|
||||
|
||||
Required properties:
|
||||
|
|
|
|||
|
|
@ -67,9 +67,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
items:
|
||||
- const: fck
|
||||
const: fck
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
|
@ -99,32 +97,26 @@ properties:
|
|||
Indicates that the channel acts as primary among the bonded channels.
|
||||
|
||||
port:
|
||||
type: object
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
unevaluatedProperties: false
|
||||
description:
|
||||
Child port node corresponding to the data input, in accordance with the
|
||||
video interface bindings defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
The port node must contain at least one endpoint.
|
||||
Child port node corresponding to the data input. The port node must
|
||||
contain at least one endpoint.
|
||||
|
||||
properties:
|
||||
endpoint:
|
||||
type: object
|
||||
$ref: /schemas/graph.yaml#/$defs/endpoint-base
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
remote-endpoint:
|
||||
description:
|
||||
A phandle to the remote tuner endpoint subnode in remote node
|
||||
port.
|
||||
|
||||
sync-active:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
description:
|
||||
Indicates sync signal polarity, 0/1 for low/high respectively.
|
||||
This property maps to SYNCAC bit in the hardware manual. The
|
||||
default is 1 (active high).
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -105,7 +105,6 @@ properties:
|
|||
- description: Whether the IPA clock is enabled (if valid)
|
||||
|
||||
qcom,smem-state-names:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description: The names of the state bits used for SMP2P output
|
||||
items:
|
||||
- const: ipa-clock-enabled-valid
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ allOf:
|
|||
- $ref: ethernet-controller.yaml#
|
||||
|
||||
maintainers:
|
||||
- Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
|
||||
- Sergei Shtylyov <sergei.shtylyov@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@ Required properties:
|
|||
"mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
|
||||
"mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
|
||||
"mediatek,mt8516-efuse", "mediatek,efuse": for MT8516
|
||||
"mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
= Data cells =
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@ patternProperties:
|
|||
description:
|
||||
Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
|
||||
EXTERNAL_SSC or INTERNAL_SSC.
|
||||
Refer include/dt-bindings/phy/phy-cadence-torrent.h for the constants to be used.
|
||||
Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
default: 0
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
phys:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
maxItems: 1
|
||||
description: phandle to the USB phy
|
||||
|
||||
monitored-battery:
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ patternProperties:
|
|||
rate
|
||||
|
||||
sound-dai:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: phandle of the CPU DAI
|
||||
|
||||
patternProperties:
|
||||
|
|
@ -71,7 +71,7 @@ patternProperties:
|
|||
|
||||
properties:
|
||||
sound-dai:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description: phandle of the codec DAI
|
||||
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
memory-region:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
maxItems: 1
|
||||
description:
|
||||
phandle to a node describing reserved memory (System RAM memory)
|
||||
The M core can't access all the DDR memory space on some platform,
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ examples:
|
|||
|
||||
mux-controls = <&mux>;
|
||||
|
||||
spi-flash@0 {
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
|
|
|
|||
|
|
@ -178,6 +178,15 @@ DMA Fence Array
|
|||
.. kernel-doc:: include/linux/dma-fence-array.h
|
||||
:internal:
|
||||
|
||||
DMA Fence Chain
|
||||
~~~~~~~~~~~~~~~
|
||||
|
||||
.. kernel-doc:: drivers/dma-buf/dma-fence-chain.c
|
||||
:export:
|
||||
|
||||
.. kernel-doc:: include/linux/dma-fence-chain.h
|
||||
:internal:
|
||||
|
||||
DMA Fence uABI/Sync File
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
|
|
|||
|
|
@ -123,6 +123,8 @@ are in ``drivers/usb/common/common.c``.
|
|||
In addition, some functions useful for creating debugging output are
|
||||
defined in ``drivers/usb/common/debug.c``.
|
||||
|
||||
.. _usb_header:
|
||||
|
||||
Host-Side Data Types and Macros
|
||||
===============================
|
||||
|
||||
|
|
|
|||
|
|
@ -66,3 +66,9 @@ Display Core
|
|||
============
|
||||
|
||||
**WIP**
|
||||
|
||||
FreeSync Video
|
||||
--------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
|
||||
:doc: FreeSync Video
|
||||
|
|
|
|||
|
|
@ -300,4 +300,25 @@ pcie_replay_count
|
|||
.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
|
||||
:doc: pcie_replay_count
|
||||
|
||||
+GPU SmartShift Information
|
||||
============================
|
||||
|
||||
GPU SmartShift information via sysfs
|
||||
|
||||
smartshift_apu_power
|
||||
--------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
|
||||
:doc: smartshift_apu_power
|
||||
|
||||
smartshift_dgpu_power
|
||||
---------------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
|
||||
:doc: smartshift_dgpu_power
|
||||
|
||||
smartshift_bias
|
||||
---------------
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
|
||||
:doc: smartshift_bias
|
||||
|
|
|
|||
8
Documentation/gpu/driver-uapi.rst
Normal file
8
Documentation/gpu/driver-uapi.rst
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
===============
|
||||
DRM Driver uAPI
|
||||
===============
|
||||
|
||||
drm/i915 uAPI
|
||||
=============
|
||||
|
||||
.. kernel-doc:: include/uapi/drm/i915_drm.h
|
||||
|
|
@ -469,8 +469,8 @@ DRM MM Range Allocator Function References
|
|||
.. kernel-doc:: drivers/gpu/drm/drm_mm.c
|
||||
:export:
|
||||
|
||||
DRM Cache Handling
|
||||
==================
|
||||
DRM Cache Handling and Fast WC memcpy()
|
||||
=======================================
|
||||
|
||||
.. kernel-doc:: drivers/gpu/drm/drm_cache.c
|
||||
:export:
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ Linux GPU Driver Developer's Guide
|
|||
drm-kms
|
||||
drm-kms-helpers
|
||||
drm-uapi
|
||||
driver-uapi
|
||||
drm-client
|
||||
drivers
|
||||
backlight
|
||||
|
|
|
|||
131
Documentation/gpu/rfc/i915_gem_lmem.rst
Normal file
131
Documentation/gpu/rfc/i915_gem_lmem.rst
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
=========================
|
||||
I915 DG1/LMEM RFC Section
|
||||
=========================
|
||||
|
||||
Upstream plan
|
||||
=============
|
||||
For upstream the overall plan for landing all the DG1 stuff and turning it for
|
||||
real, with all the uAPI bits is:
|
||||
|
||||
* Merge basic HW enabling of DG1(still without pciid)
|
||||
* Merge the uAPI bits behind special CONFIG_BROKEN(or so) flag
|
||||
* At this point we can still make changes, but importantly this lets us
|
||||
start running IGTs which can utilize local-memory in CI
|
||||
* Convert over to TTM, make sure it all keeps working. Some of the work items:
|
||||
* TTM shrinker for discrete
|
||||
* dma_resv_lockitem for full dma_resv_lock, i.e not just trylock
|
||||
* Use TTM CPU pagefault handler
|
||||
* Route shmem backend over to TTM SYSTEM for discrete
|
||||
* TTM purgeable object support
|
||||
* Move i915 buddy allocator over to TTM
|
||||
* MMAP ioctl mode(see `I915 MMAP`_)
|
||||
* SET/GET ioctl caching(see `I915 SET/GET CACHING`_)
|
||||
* Send RFC(with mesa-dev on cc) for final sign off on the uAPI
|
||||
* Add pciid for DG1 and turn on uAPI for real
|
||||
|
||||
New object placement and region query uAPI
|
||||
==========================================
|
||||
Starting from DG1 we need to give userspace the ability to allocate buffers from
|
||||
device local-memory. Currently the driver supports gem_create, which can place
|
||||
buffers in system memory via shmem, and the usual assortment of other
|
||||
interfaces, like dumb buffers and userptr.
|
||||
|
||||
To support this new capability, while also providing a uAPI which will work
|
||||
beyond just DG1, we propose to offer three new bits of uAPI:
|
||||
|
||||
DRM_I915_QUERY_MEMORY_REGIONS
|
||||
-----------------------------
|
||||
New query ID which allows userspace to discover the list of supported memory
|
||||
regions(like system-memory and local-memory) for a given device. We identify
|
||||
each region with a class and instance pair, which should be unique. The class
|
||||
here would be DEVICE or SYSTEM, and the instance would be zero, on platforms
|
||||
like DG1.
|
||||
|
||||
Side note: The class/instance design is borrowed from our existing engine uAPI,
|
||||
where we describe every physical engine in terms of its class, and the
|
||||
particular instance, since we can have more than one per class.
|
||||
|
||||
In the future we also want to expose more information which can further
|
||||
describe the capabilities of a region.
|
||||
|
||||
.. kernel-doc:: include/uapi/drm/i915_drm.h
|
||||
:functions: drm_i915_gem_memory_class drm_i915_gem_memory_class_instance drm_i915_memory_region_info drm_i915_query_memory_regions
|
||||
|
||||
GEM_CREATE_EXT
|
||||
--------------
|
||||
New ioctl which is basically just gem_create but now allows userspace to provide
|
||||
a chain of possible extensions. Note that if we don't provide any extensions and
|
||||
set flags=0 then we get the exact same behaviour as gem_create.
|
||||
|
||||
Side note: We also need to support PXP[1] in the near future, which is also
|
||||
applicable to integrated platforms, and adds its own gem_create_ext extension,
|
||||
which basically lets userspace mark a buffer as "protected".
|
||||
|
||||
.. kernel-doc:: include/uapi/drm/i915_drm.h
|
||||
:functions: drm_i915_gem_create_ext
|
||||
|
||||
I915_GEM_CREATE_EXT_MEMORY_REGIONS
|
||||
----------------------------------
|
||||
Implemented as an extension for gem_create_ext, we would now allow userspace to
|
||||
optionally provide an immutable list of preferred placements at creation time,
|
||||
in priority order, for a given buffer object. For the placements we expect
|
||||
them each to use the class/instance encoding, as per the output of the regions
|
||||
query. Having the list in priority order will be useful in the future when
|
||||
placing an object, say during eviction.
|
||||
|
||||
.. kernel-doc:: include/uapi/drm/i915_drm.h
|
||||
:functions: drm_i915_gem_create_ext_memory_regions
|
||||
|
||||
One fair criticism here is that this seems a little over-engineered[2]. If we
|
||||
just consider DG1 then yes, a simple gem_create.flags or something is totally
|
||||
all that's needed to tell the kernel to allocate the buffer in local-memory or
|
||||
whatever. However looking to the future we need uAPI which can also support
|
||||
upcoming Xe HP multi-tile architecture in a sane way, where there can be
|
||||
multiple local-memory instances for a given device, and so using both class and
|
||||
instance in our uAPI to describe regions is desirable, although specifically
|
||||
for DG1 it's uninteresting, since we only have a single local-memory instance.
|
||||
|
||||
Existing uAPI issues
|
||||
====================
|
||||
Some potential issues we still need to resolve.
|
||||
|
||||
I915 MMAP
|
||||
---------
|
||||
In i915 there are multiple ways to MMAP GEM object, including mapping the same
|
||||
object using different mapping types(WC vs WB), i.e multiple active mmaps per
|
||||
object. TTM expects one MMAP at most for the lifetime of the object. If it
|
||||
turns out that we have to backpedal here, there might be some potential
|
||||
userspace fallout.
|
||||
|
||||
I915 SET/GET CACHING
|
||||
--------------------
|
||||
In i915 we have set/get_caching ioctl. TTM doesn't let us to change this, but
|
||||
DG1 doesn't support non-snooped pcie transactions, so we can just always
|
||||
allocate as WB for smem-only buffers. If/when our hw gains support for
|
||||
non-snooped pcie transactions then we must fix this mode at allocation time as
|
||||
a new GEM extension.
|
||||
|
||||
This is related to the mmap problem, because in general (meaning, when we're
|
||||
not running on intel cpus) the cpu mmap must not, ever, be inconsistent with
|
||||
allocation mode.
|
||||
|
||||
Possible idea is to let the kernel picks the mmap mode for userspace from the
|
||||
following table:
|
||||
|
||||
smem-only: WB. Userspace does not need to call clflush.
|
||||
|
||||
smem+lmem: We only ever allow a single mode, so simply allocate this as uncached
|
||||
memory, and always give userspace a WC mapping. GPU still does snooped access
|
||||
here(assuming we can't turn it off like on DG1), which is a bit inefficient.
|
||||
|
||||
lmem only: always WC
|
||||
|
||||
This means on discrete you only get a single mmap mode, all others must be
|
||||
rejected. That's probably going to be a new default mode or something like
|
||||
that.
|
||||
|
||||
Links
|
||||
=====
|
||||
[1] https://patchwork.freedesktop.org/series/86798/
|
||||
|
||||
[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5599#note_553791
|
||||
|
|
@ -15,3 +15,7 @@ host such documentation:
|
|||
|
||||
* Once the code has landed move all the documentation to the right places in
|
||||
the main core, helper or driver sections.
|
||||
|
||||
.. toctree::
|
||||
|
||||
i915_gem_lmem.rst
|
||||
|
|
|
|||
|
|
@ -109,6 +109,16 @@ auxiliary vector.
|
|||
|
||||
scv 0 syscalls will always behave as PPC_FEATURE2_HTM_NOSC.
|
||||
|
||||
ptrace
|
||||
------
|
||||
When ptracing system calls (PTRACE_SYSCALL), the pt_regs.trap value contains
|
||||
the system call type that can be used to distinguish between sc and scv 0
|
||||
system calls, and the different register conventions can be accounted for.
|
||||
|
||||
If the value of (pt_regs.trap & 0xfff0) is 0xc00 then the system call was
|
||||
performed with the sc instruction, if it is 0x3000 then the system call was
|
||||
performed with the scv 0 instruction.
|
||||
|
||||
vsyscall
|
||||
========
|
||||
|
||||
|
|
|
|||
|
|
@ -58,6 +58,6 @@ RISC-V Linux Kernel SV39
|
|||
|
|
||||
____________________________________________________________|____________________________________________________________
|
||||
| | | |
|
||||
ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules
|
||||
ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel, BPF
|
||||
ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
|
||||
ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
|
||||
__________________|____________|__________________|_________|____________________________________________________________
|
||||
|
|
|
|||
|
|
@ -250,14 +250,14 @@ Users can read via ``ioctl(SECCOMP_IOCTL_NOTIF_RECV)`` (or ``poll()``) on a
|
|||
seccomp notification fd to receive a ``struct seccomp_notif``, which contains
|
||||
five members: the input length of the structure, a unique-per-filter ``id``,
|
||||
the ``pid`` of the task which triggered this request (which may be 0 if the
|
||||
task is in a pid ns not visible from the listener's pid namespace), a ``flags``
|
||||
member which for now only has ``SECCOMP_NOTIF_FLAG_SIGNALED``, representing
|
||||
whether or not the notification is a result of a non-fatal signal, and the
|
||||
``data`` passed to seccomp. Userspace can then make a decision based on this
|
||||
information about what to do, and ``ioctl(SECCOMP_IOCTL_NOTIF_SEND)`` a
|
||||
response, indicating what should be returned to userspace. The ``id`` member of
|
||||
``struct seccomp_notif_resp`` should be the same ``id`` as in ``struct
|
||||
seccomp_notif``.
|
||||
task is in a pid ns not visible from the listener's pid namespace). The
|
||||
notification also contains the ``data`` passed to seccomp, and a filters flag.
|
||||
The structure should be zeroed out prior to calling the ioctl.
|
||||
|
||||
Userspace can then make a decision based on this information about what to do,
|
||||
and ``ioctl(SECCOMP_IOCTL_NOTIF_SEND)`` a response, indicating what should be
|
||||
returned to userspace. The ``id`` member of ``struct seccomp_notif_resp`` should
|
||||
be the same ``id`` as in ``struct seccomp_notif``.
|
||||
|
||||
It is worth noting that ``struct seccomp_data`` contains the values of register
|
||||
arguments to the syscall, but does not contain pointers to memory. The task's
|
||||
|
|
|
|||
|
|
@ -171,8 +171,8 @@ Shadow pages contain the following information:
|
|||
shadow pages) so role.quadrant takes values in the range 0..3. Each
|
||||
quadrant maps 1GB virtual address space.
|
||||
role.access:
|
||||
Inherited guest access permissions in the form uwx. Note execute
|
||||
permission is positive, not negative.
|
||||
Inherited guest access permissions from the parent ptes in the form uwx.
|
||||
Note execute permission is positive, not negative.
|
||||
role.invalid:
|
||||
The page is invalid and should not be used. It is a root page that is
|
||||
currently pinned (by a cpu hardware register pointing to it); once it is
|
||||
|
|
|
|||
|
|
@ -118,10 +118,12 @@ KVM_REQ_MMU_RELOAD
|
|||
necessary to inform each VCPU to completely refresh the tables. This
|
||||
request is used for that.
|
||||
|
||||
KVM_REQ_PENDING_TIMER
|
||||
KVM_REQ_UNBLOCK
|
||||
|
||||
This request may be made from a timer handler run on the host on behalf
|
||||
of a VCPU. It informs the VCPU thread to inject a timer interrupt.
|
||||
This request informs the vCPU to exit kvm_vcpu_block. It is used for
|
||||
example from timer handlers that run on the host on behalf of a vCPU,
|
||||
or in order to update the interrupt routing and ensure that assigned
|
||||
devices will wake up the vCPU.
|
||||
|
||||
KVM_REQ_UNHALT
|
||||
|
||||
|
|
|
|||
|
|
@ -181,7 +181,7 @@ SLUB Debug output
|
|||
Here is a sample of slub debug output::
|
||||
|
||||
====================================================================
|
||||
BUG kmalloc-8: Redzone overwritten
|
||||
BUG kmalloc-8: Right Redzone overwritten
|
||||
--------------------------------------------------------------------
|
||||
|
||||
INFO: 0xc90f6d28-0xc90f6d2b. First byte 0x00 instead of 0xcc
|
||||
|
|
@ -189,10 +189,10 @@ Here is a sample of slub debug output::
|
|||
INFO: Object 0xc90f6d20 @offset=3360 fp=0xc90f6d58
|
||||
INFO: Allocated in get_modalias+0x61/0xf5 age=53 cpu=1 pid=554
|
||||
|
||||
Bytes b4 0xc90f6d10: 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ
|
||||
Object 0xc90f6d20: 31 30 31 39 2e 30 30 35 1019.005
|
||||
Redzone 0xc90f6d28: 00 cc cc cc .
|
||||
Padding 0xc90f6d50: 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZ
|
||||
Bytes b4 (0xc90f6d10): 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ
|
||||
Object (0xc90f6d20): 31 30 31 39 2e 30 30 35 1019.005
|
||||
Redzone (0xc90f6d28): 00 cc cc cc .
|
||||
Padding (0xc90f6d50): 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZ
|
||||
|
||||
[<c010523d>] dump_trace+0x63/0x1eb
|
||||
[<c01053df>] show_trace_log_lvl+0x1a/0x2f
|
||||
|
|
|
|||
64
MAINTAINERS
64
MAINTAINERS
|
|
@ -1618,8 +1618,8 @@ F: Documentation/devicetree/bindings/sound/amlogic*
|
|||
F: sound/soc/meson/
|
||||
|
||||
ARM/Amlogic Meson SoC support
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Kevin Hilman <khilman@baylibre.com>
|
||||
R: Neil Armstrong <narmstrong@baylibre.com>
|
||||
R: Jerome Brunet <jbrunet@baylibre.com>
|
||||
R: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
|
|
@ -3877,6 +3877,7 @@ L: linux-btrfs@vger.kernel.org
|
|||
S: Maintained
|
||||
W: http://btrfs.wiki.kernel.org/
|
||||
Q: http://patchwork.kernel.org/project/linux-btrfs/list/
|
||||
C: irc://irc.libera.chat/btrfs
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git
|
||||
F: Documentation/filesystems/btrfs.rst
|
||||
F: fs/btrfs/
|
||||
|
|
@ -4138,6 +4139,14 @@ S: Odd Fixes
|
|||
F: Documentation/devicetree/bindings/arm/cavium-thunder2.txt
|
||||
F: arch/arm64/boot/dts/cavium/thunder2-99xx*
|
||||
|
||||
CBS/ETF/TAPRIO QDISCS
|
||||
M: Vinicius Costa Gomes <vinicius.gomes@intel.com>
|
||||
S: Maintained
|
||||
L: netdev@vger.kernel.org
|
||||
F: net/sched/sch_cbs.c
|
||||
F: net/sched/sch_etf.c
|
||||
F: net/sched/sch_taprio.c
|
||||
|
||||
CC2520 IEEE-802.15.4 RADIO DRIVER
|
||||
M: Varka Bhadram <varkabhadram@gmail.com>
|
||||
L: linux-wpan@vger.kernel.org
|
||||
|
|
@ -5569,7 +5578,6 @@ F: drivers/soc/fsl/dpio
|
|||
|
||||
DPAA2 ETHERNET DRIVER
|
||||
M: Ioana Ciornei <ioana.ciornei@nxp.com>
|
||||
M: Ioana Radulescu <ruxandra.radulescu@nxp.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ethernet-driver.rst
|
||||
|
|
@ -6084,6 +6092,14 @@ T: git git://anongit.freedesktop.org/drm/drm-misc
|
|||
F: Documentation/devicetree/bindings/display/hisilicon/
|
||||
F: drivers/gpu/drm/hisilicon/
|
||||
|
||||
DRM DRIVER FOR HYPERV SYNTHETIC VIDEO DEVICE
|
||||
M: Deepak Rawat <drawat.floss@gmail.com>
|
||||
L: linux-hyperv@vger.kernel.org
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: drivers/gpu/drm/hyperv
|
||||
|
||||
DRM DRIVERS FOR LIMA
|
||||
M: Qiang Yu <yuq825@gmail.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
|
|
@ -6945,6 +6961,7 @@ F: net/core/failover.c
|
|||
FANOTIFY
|
||||
M: Jan Kara <jack@suse.cz>
|
||||
R: Amir Goldstein <amir73il@gmail.com>
|
||||
R: Matthew Bobrowski <repnop@google.com>
|
||||
L: linux-fsdevel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: fs/notify/fanotify/
|
||||
|
|
@ -12195,6 +12212,7 @@ F: drivers/platform/surface/surfacepro3_button.c
|
|||
|
||||
MICROSOFT SURFACE SYSTEM AGGREGATOR SUBSYSTEM
|
||||
M: Maximilian Luz <luzmaximilian@gmail.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
S: Maintained
|
||||
W: https://github.com/linux-surface/surface-aggregator-module
|
||||
C: irc://chat.freenode.net/##linux-surface
|
||||
|
|
@ -12695,9 +12713,9 @@ F: drivers/rtc/rtc-ntxec.c
|
|||
F: include/linux/mfd/ntxec.h
|
||||
|
||||
NETRONOME ETHERNET DRIVERS
|
||||
M: Simon Horman <simon.horman@netronome.com>
|
||||
M: Simon Horman <simon.horman@corigine.com>
|
||||
R: Jakub Kicinski <kuba@kernel.org>
|
||||
L: oss-drivers@netronome.com
|
||||
L: oss-drivers@corigine.com
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/netronome/
|
||||
|
||||
|
|
@ -12724,7 +12742,6 @@ M: "David S. Miller" <davem@davemloft.net>
|
|||
M: Jakub Kicinski <kuba@kernel.org>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
W: http://www.linuxfoundation.org/en/Net
|
||||
Q: https://patchwork.kernel.org/project/netdevbpf/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
|
||||
|
|
@ -12769,7 +12786,6 @@ M: "David S. Miller" <davem@davemloft.net>
|
|||
M: Jakub Kicinski <kuba@kernel.org>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
W: http://www.linuxfoundation.org/en/Net
|
||||
Q: https://patchwork.kernel.org/project/netdevbpf/list/
|
||||
B: mailto:netdev@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
|
||||
|
|
@ -12911,8 +12927,10 @@ F: include/uapi/linux/nexthop.h
|
|||
F: net/ipv4/nexthop.c
|
||||
|
||||
NFC SUBSYSTEM
|
||||
M: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
L: linux-nfc@lists.01.org (subscribers-only)
|
||||
L: netdev@vger.kernel.org
|
||||
S: Orphan
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/net/nfc/
|
||||
F: drivers/nfc/
|
||||
F: include/linux/platform_data/nfcmrvl.h
|
||||
|
|
@ -12923,7 +12941,7 @@ F: net/nfc/
|
|||
NFC VIRTUAL NCI DEVICE DRIVER
|
||||
M: Bongsu Jeon <bongsu.jeon@samsung.com>
|
||||
L: netdev@vger.kernel.org
|
||||
L: linux-nfc@lists.01.org (moderated for non-subscribers)
|
||||
L: linux-nfc@lists.01.org (subscribers-only)
|
||||
S: Supported
|
||||
F: drivers/nfc/virtual_ncidev.c
|
||||
F: tools/testing/selftests/nci/
|
||||
|
|
@ -13220,9 +13238,8 @@ F: Documentation/devicetree/bindings/sound/tfa9879.txt
|
|||
F: sound/soc/codecs/tfa9879*
|
||||
|
||||
NXP-NCI NFC DRIVER
|
||||
M: Clément Perrochaud <clement.perrochaud@effinnov.com>
|
||||
R: Charles Gorand <charles.gorand@effinnov.com>
|
||||
L: linux-nfc@lists.01.org (moderated for non-subscribers)
|
||||
L: linux-nfc@lists.01.org (subscribers-only)
|
||||
S: Supported
|
||||
F: drivers/nfc/nxp-nci
|
||||
|
||||
|
|
@ -14125,6 +14142,7 @@ F: drivers/pci/controller/pci-v3-semi.c
|
|||
PCI ENDPOINT SUBSYSTEM
|
||||
M: Kishon Vijay Abraham I <kishon@ti.com>
|
||||
M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
R: Krzysztof Wilczyński <kw@linux.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/PCI/endpoint/*
|
||||
|
|
@ -14173,6 +14191,7 @@ F: drivers/pci/controller/pci-xgene-msi.c
|
|||
PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS
|
||||
M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
R: Rob Herring <robh@kernel.org>
|
||||
R: Krzysztof Wilczyński <kw@linux.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
Q: http://patchwork.ozlabs.org/project/linux-pci/list/
|
||||
|
|
@ -14332,10 +14351,12 @@ PER-CPU MEMORY ALLOCATOR
|
|||
M: Dennis Zhou <dennis@kernel.org>
|
||||
M: Tejun Heo <tj@kernel.org>
|
||||
M: Christoph Lameter <cl@linux.com>
|
||||
L: linux-mm@kvack.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/dennis/percpu.git
|
||||
F: arch/*/include/asm/percpu.h
|
||||
F: include/linux/percpu*.h
|
||||
F: lib/percpu*.c
|
||||
F: mm/percpu*.c
|
||||
|
||||
PER-TASK DELAY ACCOUNTING
|
||||
|
|
@ -14749,7 +14770,6 @@ W: https://wireless.wiki.kernel.org/en/users/Drivers/p54
|
|||
F: drivers/net/wireless/intersil/prism54/
|
||||
|
||||
PROC FILESYSTEM
|
||||
R: Alexey Dobriyan <adobriyan@gmail.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
L: linux-fsdevel@vger.kernel.org
|
||||
S: Maintained
|
||||
|
|
@ -15961,6 +15981,7 @@ S390 IUCV NETWORK LAYER
|
|||
M: Julian Wiedmann <jwi@linux.ibm.com>
|
||||
M: Karsten Graul <kgraul@linux.ibm.com>
|
||||
L: linux-s390@vger.kernel.org
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.ibm.com/developerworks/linux/linux390/
|
||||
F: drivers/s390/net/*iucv*
|
||||
|
|
@ -15971,6 +15992,7 @@ S390 NETWORK DRIVERS
|
|||
M: Julian Wiedmann <jwi@linux.ibm.com>
|
||||
M: Karsten Graul <kgraul@linux.ibm.com>
|
||||
L: linux-s390@vger.kernel.org
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.ibm.com/developerworks/linux/linux390/
|
||||
F: drivers/s390/net/
|
||||
|
|
@ -16149,7 +16171,7 @@ F: include/media/drv-intf/s3c_camif.h
|
|||
SAMSUNG S3FWRN5 NFC DRIVER
|
||||
M: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
M: Krzysztof Opasiak <k.opasiak@samsung.com>
|
||||
L: linux-nfc@lists.01.org (moderated for non-subscribers)
|
||||
L: linux-nfc@lists.01.org (subscribers-only)
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/net/nfc/samsung,s3fwrn5.yaml
|
||||
F: drivers/nfc/s3fwrn5
|
||||
|
|
@ -16562,6 +16584,7 @@ F: drivers/misc/sgi-xp/
|
|||
|
||||
SHARED MEMORY COMMUNICATIONS (SMC) SOCKETS
|
||||
M: Karsten Graul <kgraul@linux.ibm.com>
|
||||
M: Guvenc Gulce <guvenc@linux.ibm.com>
|
||||
L: linux-s390@vger.kernel.org
|
||||
S: Supported
|
||||
W: http://www.ibm.com/developerworks/linux/linux390/
|
||||
|
|
@ -17320,6 +17343,12 @@ L: linux-i2c@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/i2c/busses/i2c-stm32*
|
||||
|
||||
ST STM32 SPI DRIVER
|
||||
M: Alain Volmat <alain.volmat@foss.st.com>
|
||||
L: linux-spi@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/spi/spi-stm32.c
|
||||
|
||||
ST STPDDC60 DRIVER
|
||||
M: Daniel Nilsson <daniel.nilsson@flex.com>
|
||||
L: linux-hwmon@vger.kernel.org
|
||||
|
|
@ -17678,7 +17707,6 @@ R: Mika Westerberg <mika.westerberg@linux.intel.com>
|
|||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/i2c/busses/i2c-designware-*
|
||||
F: include/linux/platform_data/i2c-designware.h
|
||||
|
||||
SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER
|
||||
M: Jaehoon Chung <jh80.chung@samsung.com>
|
||||
|
|
@ -18334,7 +18362,7 @@ F: sound/soc/codecs/tas571x*
|
|||
TI TRF7970A NFC DRIVER
|
||||
M: Mark Greer <mgreer@animalcreek.com>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
L: linux-nfc@lists.01.org (moderated for non-subscribers)
|
||||
L: linux-nfc@lists.01.org (subscribers-only)
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/net/nfc/trf7970a.txt
|
||||
F: drivers/nfc/trf7970a.c
|
||||
|
|
@ -18870,6 +18898,13 @@ S: Maintained
|
|||
F: drivers/usb/host/isp116x*
|
||||
F: include/linux/usb/isp116x.h
|
||||
|
||||
USB ISP1760 DRIVER
|
||||
M: Rui Miguel Silva <rui.silva@linaro.org>
|
||||
L: linux-usb@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/usb/isp1760/*
|
||||
F: Documentation/devicetree/bindings/usb/nxp,isp1760.yaml
|
||||
|
||||
USB LAN78XX ETHERNET DRIVER
|
||||
M: Woojung Huh <woojung.huh@microchip.com>
|
||||
M: UNGLinuxDriver@microchip.com
|
||||
|
|
@ -20014,6 +20049,7 @@ F: arch/x86/xen/*swiotlb*
|
|||
F: drivers/xen/*swiotlb*
|
||||
|
||||
XFS FILESYSTEM
|
||||
C: irc://irc.oftc.net/xfs
|
||||
M: Darrick J. Wong <djwong@kernel.org>
|
||||
M: linux-xfs@vger.kernel.org
|
||||
L: linux-xfs@vger.kernel.org
|
||||
|
|
|
|||
12
Makefile
12
Makefile
|
|
@ -2,8 +2,8 @@
|
|||
VERSION = 5
|
||||
PATCHLEVEL = 13
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
NAME = Frozen Wasteland
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Opossums on Parade
|
||||
|
||||
# *DOCUMENTATION*
|
||||
# To see a list of typical targets execute "make help"
|
||||
|
|
@ -928,6 +928,14 @@ CC_FLAGS_LTO += -fvisibility=hidden
|
|||
|
||||
# Limit inlining across translation units to reduce binary size
|
||||
KBUILD_LDFLAGS += -mllvm -import-instr-limit=5
|
||||
|
||||
# Check for frame size exceeding threshold during prolog/epilog insertion
|
||||
# when using lld < 13.0.0.
|
||||
ifneq ($(CONFIG_FRAME_WARN),0)
|
||||
ifeq ($(shell test $(CONFIG_LLD_VERSION) -lt 130000; echo $$?),0)
|
||||
KBUILD_LDFLAGS += -plugin-opt=-warn-stack-size=$(CONFIG_FRAME_WARN)
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef CONFIG_LTO
|
||||
|
|
|
|||
|
|
@ -482,7 +482,7 @@
|
|||
550 common process_madvise sys_process_madvise
|
||||
551 common epoll_pwait2 sys_epoll_pwait2
|
||||
552 common mount_setattr sys_mount_setattr
|
||||
553 common quotactl_path sys_quotactl_path
|
||||
# 553 reserved for quotactl_path
|
||||
554 common landlock_create_ruleset sys_landlock_create_ruleset
|
||||
555 common landlock_add_rule sys_landlock_add_rule
|
||||
556 common landlock_restrict_self sys_landlock_restrict_self
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
*/
|
||||
struct sigcontext {
|
||||
struct user_regs_struct regs;
|
||||
struct user_regs_arcv2 v2abi;
|
||||
};
|
||||
|
||||
#endif /* _ASM_ARC_SIGCONTEXT_H */
|
||||
|
|
|
|||
|
|
@ -61,6 +61,41 @@ struct rt_sigframe {
|
|||
unsigned int sigret_magic;
|
||||
};
|
||||
|
||||
static int save_arcv2_regs(struct sigcontext *mctx, struct pt_regs *regs)
|
||||
{
|
||||
int err = 0;
|
||||
#ifndef CONFIG_ISA_ARCOMPACT
|
||||
struct user_regs_arcv2 v2abi;
|
||||
|
||||
v2abi.r30 = regs->r30;
|
||||
#ifdef CONFIG_ARC_HAS_ACCL_REGS
|
||||
v2abi.r58 = regs->r58;
|
||||
v2abi.r59 = regs->r59;
|
||||
#else
|
||||
v2abi.r58 = v2abi.r59 = 0;
|
||||
#endif
|
||||
err = __copy_to_user(&mctx->v2abi, &v2abi, sizeof(v2abi));
|
||||
#endif
|
||||
return err;
|
||||
}
|
||||
|
||||
static int restore_arcv2_regs(struct sigcontext *mctx, struct pt_regs *regs)
|
||||
{
|
||||
int err = 0;
|
||||
#ifndef CONFIG_ISA_ARCOMPACT
|
||||
struct user_regs_arcv2 v2abi;
|
||||
|
||||
err = __copy_from_user(&v2abi, &mctx->v2abi, sizeof(v2abi));
|
||||
|
||||
regs->r30 = v2abi.r30;
|
||||
#ifdef CONFIG_ARC_HAS_ACCL_REGS
|
||||
regs->r58 = v2abi.r58;
|
||||
regs->r59 = v2abi.r59;
|
||||
#endif
|
||||
#endif
|
||||
return err;
|
||||
}
|
||||
|
||||
static int
|
||||
stash_usr_regs(struct rt_sigframe __user *sf, struct pt_regs *regs,
|
||||
sigset_t *set)
|
||||
|
|
@ -94,6 +129,10 @@ stash_usr_regs(struct rt_sigframe __user *sf, struct pt_regs *regs,
|
|||
|
||||
err = __copy_to_user(&(sf->uc.uc_mcontext.regs.scratch), &uregs.scratch,
|
||||
sizeof(sf->uc.uc_mcontext.regs.scratch));
|
||||
|
||||
if (is_isa_arcv2())
|
||||
err |= save_arcv2_regs(&(sf->uc.uc_mcontext), regs);
|
||||
|
||||
err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(sigset_t));
|
||||
|
||||
return err ? -EFAULT : 0;
|
||||
|
|
@ -109,6 +148,10 @@ static int restore_usr_regs(struct pt_regs *regs, struct rt_sigframe __user *sf)
|
|||
err |= __copy_from_user(&uregs.scratch,
|
||||
&(sf->uc.uc_mcontext.regs.scratch),
|
||||
sizeof(sf->uc.uc_mcontext.regs.scratch));
|
||||
|
||||
if (is_isa_arcv2())
|
||||
err |= restore_arcv2_regs(&(sf->uc.uc_mcontext), regs);
|
||||
|
||||
if (err)
|
||||
return -EFAULT;
|
||||
|
||||
|
|
|
|||
|
|
@ -57,7 +57,6 @@ SECTIONS
|
|||
.init.ramfs : { INIT_RAM_FS }
|
||||
|
||||
. = ALIGN(PAGE_SIZE);
|
||||
_stext = .;
|
||||
|
||||
HEAD_TEXT_SECTION
|
||||
INIT_TEXT_SECTION(L1_CACHE_BYTES)
|
||||
|
|
@ -83,6 +82,7 @@ SECTIONS
|
|||
|
||||
.text : {
|
||||
_text = .;
|
||||
_stext = .;
|
||||
TEXT_TEXT
|
||||
SCHED_TEXT
|
||||
CPUIDLE_TEXT
|
||||
|
|
|
|||
|
|
@ -105,9 +105,13 @@ &fec {
|
|||
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
|
||||
phy-reset-duration = <20>;
|
||||
phy-supply = <&sw2_reg>;
|
||||
phy-handle = <ðphy0>;
|
||||
status = "okay";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -406,6 +406,18 @@ ®_soc {
|
|||
vin-supply = <&sw1_reg>;
|
||||
};
|
||||
|
||||
®_pu {
|
||||
vin-supply = <&sw1_reg>;
|
||||
};
|
||||
|
||||
®_vdd1p1 {
|
||||
vin-supply = <&sw2_reg>;
|
||||
};
|
||||
|
||||
®_vdd2p5 {
|
||||
vin-supply = <&sw2_reg>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@ boardid: gpio@3a {
|
|||
compatible = "nxp,pca8574";
|
||||
reg = <0x3a>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -193,7 +193,7 @@ &usdhc1 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
keep-power-in-suspend;
|
||||
tuning-step = <2>;
|
||||
fsl,tuning-step = <2>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
no-1-8-v;
|
||||
broken-cd;
|
||||
|
|
|
|||
|
|
@ -351,7 +351,7 @@ &usdhc1 {
|
|||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
tuning-step = <2>;
|
||||
fsl,tuning-step = <2>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
wakeup-source;
|
||||
no-1-8-v;
|
||||
|
|
|
|||
|
|
@ -7,9 +7,11 @@
|
|||
#ifdef CONFIG_CPU_IDLE
|
||||
extern int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv, int index);
|
||||
#define __cpuidle_method_section __used __section("__cpuidle_method_of_table")
|
||||
#else
|
||||
static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv, int index) { return -ENODEV; }
|
||||
#define __cpuidle_method_section __maybe_unused /* drop silently */
|
||||
#endif
|
||||
|
||||
/* Common ARM WFI state */
|
||||
|
|
@ -42,8 +44,7 @@ struct of_cpuidle_method {
|
|||
|
||||
#define CPUIDLE_METHOD_OF_DECLARE(name, _method, _ops) \
|
||||
static const struct of_cpuidle_method __cpuidle_method_of_table_##name \
|
||||
__used __section("__cpuidle_method_of_table") \
|
||||
= { .method = _method, .ops = _ops }
|
||||
__cpuidle_method_section = { .method = _method, .ops = _ops }
|
||||
|
||||
extern int arm_cpuidle_suspend(int index);
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/suspend.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
static int mx27_suspend_enter(suspend_state_t state)
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ config ARCH_WPCM450
|
|||
bool "Support for WPCM450 BMC (Hermon)"
|
||||
depends on ARCH_MULTI_V5
|
||||
select CPU_ARM926T
|
||||
select WPCM450_AIC
|
||||
select NPCM7XX_TIMER
|
||||
help
|
||||
General support for WPCM450 BMC (Hermon).
|
||||
|
|
|
|||
|
|
@ -458,20 +458,6 @@ static struct gpiod_lookup_table leds_gpio_table = {
|
|||
|
||||
#ifdef CONFIG_LEDS_TRIGGERS
|
||||
DEFINE_LED_TRIGGER(ams_delta_camera_led_trigger);
|
||||
|
||||
static int ams_delta_camera_power(struct device *dev, int power)
|
||||
{
|
||||
/*
|
||||
* turn on camera LED
|
||||
*/
|
||||
if (power)
|
||||
led_trigger_event(ams_delta_camera_led_trigger, LED_FULL);
|
||||
else
|
||||
led_trigger_event(ams_delta_camera_led_trigger, LED_OFF);
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define ams_delta_camera_power NULL
|
||||
#endif
|
||||
|
||||
static struct platform_device ams_delta_audio_device = {
|
||||
|
|
|
|||
|
|
@ -320,7 +320,7 @@ static int tps_setup(struct i2c_client *client, void *context)
|
|||
{
|
||||
if (!IS_BUILTIN(CONFIG_TPS65010))
|
||||
return -ENOSYS;
|
||||
|
||||
|
||||
tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V |
|
||||
TPS_LDO1_ENABLE | TPS_VLDO1_3_0V);
|
||||
|
||||
|
|
@ -394,6 +394,8 @@ static void __init h2_init(void)
|
|||
BUG_ON(gpio_request(H2_NAND_RB_GPIO_PIN, "NAND ready") < 0);
|
||||
gpio_direction_input(H2_NAND_RB_GPIO_PIN);
|
||||
|
||||
gpiod_add_lookup_table(&isp1301_gpiod_table);
|
||||
|
||||
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
|
||||
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
|
||||
|
||||
|
|
|
|||
|
|
@ -655,9 +655,13 @@ static int __init omap_pm_init(void)
|
|||
irq = INT_7XX_WAKE_UP_REQ;
|
||||
else if (cpu_is_omap16xx())
|
||||
irq = INT_1610_WAKE_UP_REQ;
|
||||
if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup",
|
||||
NULL))
|
||||
pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
|
||||
else
|
||||
irq = -1;
|
||||
|
||||
if (irq >= 0) {
|
||||
if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup", NULL))
|
||||
pr_err("Failed to request irq %d (peripheral wakeup)\n", irq);
|
||||
}
|
||||
|
||||
/* Program new power ramp-up time
|
||||
* (0 for most boards since we don't lower voltage when in deep sleep)
|
||||
|
|
|
|||
|
|
@ -322,6 +322,7 @@ static int n8x0_mmc_get_cover_state(struct device *dev, int slot)
|
|||
|
||||
static void n8x0_mmc_callback(void *data, u8 card_mask)
|
||||
{
|
||||
#ifdef CONFIG_MMC_OMAP
|
||||
int bit, *openp, index;
|
||||
|
||||
if (board_is_n800()) {
|
||||
|
|
@ -339,7 +340,6 @@ static void n8x0_mmc_callback(void *data, u8 card_mask)
|
|||
else
|
||||
*openp = 0;
|
||||
|
||||
#ifdef CONFIG_MMC_OMAP
|
||||
omap_mmc_notify_cover_event(mmc_device, index, *openp);
|
||||
#else
|
||||
pr_warn("MMC: notify cover event not available\n");
|
||||
|
|
|
|||
|
|
@ -121,8 +121,13 @@ static int cplds_probe(struct platform_device *pdev)
|
|||
return fpga->irq;
|
||||
|
||||
base_irq = platform_get_irq(pdev, 1);
|
||||
if (base_irq < 0)
|
||||
if (base_irq < 0) {
|
||||
base_irq = 0;
|
||||
} else {
|
||||
ret = devm_irq_alloc_descs(&pdev->dev, base_irq, base_irq, CPLDS_NB_IRQ, 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
fpga->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
|
|
|
|||
|
|
@ -456,7 +456,7 @@
|
|||
440 common process_madvise sys_process_madvise
|
||||
441 common epoll_pwait2 sys_epoll_pwait2
|
||||
442 common mount_setattr sys_mount_setattr
|
||||
443 common quotactl_path sys_quotactl_path
|
||||
# 443 reserved for quotactl_path
|
||||
444 common landlock_create_ruleset sys_landlock_create_ruleset
|
||||
445 common landlock_add_rule sys_landlock_add_rule
|
||||
446 common landlock_restrict_self sys_landlock_restrict_self
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-y += kernel/ mm/
|
||||
obj-$(CONFIG_NET) += net/
|
||||
obj-y += kernel/ mm/ net/
|
||||
obj-$(CONFIG_KVM) += kvm/
|
||||
obj-$(CONFIG_XEN) += xen/
|
||||
obj-$(CONFIG_CRYPTO) += crypto/
|
||||
|
|
|
|||
|
|
@ -165,6 +165,7 @@ config ARCH_MEDIATEK
|
|||
|
||||
config ARCH_MESON
|
||||
bool "Amlogic Platforms"
|
||||
select COMMON_CLK
|
||||
select MESON_IRQ_GPIO
|
||||
help
|
||||
This enables support for the arm64 based Amlogic SoCs
|
||||
|
|
|
|||
|
|
@ -46,7 +46,8 @@ phy0: ethernet-phy@4 {
|
|||
eee-broken-100tx;
|
||||
qca,clk-out-frequency = <125000000>;
|
||||
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
|
||||
vddio-supply = <&vddh>;
|
||||
qca,keep-pll-enabled;
|
||||
vddio-supply = <&vddio>;
|
||||
|
||||
vddio: vddio-regulator {
|
||||
regulator-name = "VDDIO";
|
||||
|
|
|
|||
|
|
@ -31,11 +31,10 @@ phy1: ethernet-phy@4 {
|
|||
reg = <0x4>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
|
||||
qca,clk-out-frequency = <125000000>;
|
||||
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
|
||||
|
||||
vddio-supply = <&vddh>;
|
||||
qca,keep-pll-enabled;
|
||||
vddio-supply = <&vddio>;
|
||||
|
||||
vddio: vddio-regulator {
|
||||
regulator-name = "VDDIO";
|
||||
|
|
|
|||
|
|
@ -197,8 +197,8 @@ soc: soc {
|
|||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
little-endian;
|
||||
};
|
||||
|
||||
dcfg: syscon@1e00000 {
|
||||
|
|
|
|||
|
|
@ -88,11 +88,11 @@ codec2: codec@18 {
|
|||
pinctrl-0 = <&pinctrl_codec2>;
|
||||
reg = <0x18>;
|
||||
#sound-dai-cells = <0>;
|
||||
HPVDD-supply = <®_3p3v>;
|
||||
SPRVDD-supply = <®_3p3v>;
|
||||
SPLVDD-supply = <®_3p3v>;
|
||||
AVDD-supply = <®_3p3v>;
|
||||
IOVDD-supply = <®_3p3v>;
|
||||
HPVDD-supply = <®_gen_3p3>;
|
||||
SPRVDD-supply = <®_gen_3p3>;
|
||||
SPLVDD-supply = <®_gen_3p3>;
|
||||
AVDD-supply = <®_gen_3p3>;
|
||||
IOVDD-supply = <®_gen_3p3>;
|
||||
DVDD-supply = <&vgen4_reg>;
|
||||
reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,8 +45,8 @@ pcie1_refclk: clock-pcie1-refclk {
|
|||
reg_12p0_main: regulator-12p0-main {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "12V_MAIN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -77,15 +77,6 @@ reg_gen_3p3: regulator-gen-3p3 {
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
vin-supply = <®_3p3_main>;
|
||||
regulator-name = "GEN_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-vsd-3v3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2>;
|
||||
|
|
@ -415,11 +406,11 @@ codec1: codec@18 {
|
|||
pinctrl-0 = <&pinctrl_codec1>;
|
||||
reg = <0x18>;
|
||||
#sound-dai-cells = <0>;
|
||||
HPVDD-supply = <®_3p3v>;
|
||||
SPRVDD-supply = <®_3p3v>;
|
||||
SPLVDD-supply = <®_3p3v>;
|
||||
AVDD-supply = <®_3p3v>;
|
||||
IOVDD-supply = <®_3p3v>;
|
||||
HPVDD-supply = <®_gen_3p3>;
|
||||
SPRVDD-supply = <®_gen_3p3>;
|
||||
SPLVDD-supply = <®_gen_3p3>;
|
||||
AVDD-supply = <®_gen_3p3>;
|
||||
IOVDD-supply = <®_gen_3p3>;
|
||||
DVDD-supply = <&vgen4_reg>;
|
||||
reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@ &csi20 {
|
|||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
csi20_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
|
|
@ -29,7 +28,6 @@ &csi40 {
|
|||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
|
|
|
|||
|
|
@ -2573,6 +2573,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2628,6 +2632,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -2419,6 +2419,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2474,6 +2478,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ &csi40 {
|
|||
status = "okay";
|
||||
|
||||
ports {
|
||||
port {
|
||||
port@0 {
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
|
|
|
|||
|
|
@ -1823,6 +1823,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -2709,6 +2709,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2764,6 +2768,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -192,6 +192,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -3097,6 +3097,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -3152,6 +3156,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -3191,6 +3199,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -2761,6 +2761,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2816,6 +2820,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -2499,6 +2499,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2554,6 +2558,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -2575,6 +2575,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -2630,6 +2634,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -1106,6 +1106,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -1439,6 +1439,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -1478,6 +1482,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -298,8 +298,6 @@ &csi40 {
|
|||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
|
|
|
|||
|
|
@ -1970,6 +1970,10 @@ ports {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
|
|||
|
|
@ -349,7 +349,6 @@ &csi20 {
|
|||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
csi20_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1>;
|
||||
|
|
@ -364,8 +363,6 @@ &csi40 {
|
|||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
|
|
|
|||
|
|
@ -42,12 +42,12 @@ gic_its: msi-controller@1820000 {
|
|||
};
|
||||
};
|
||||
|
||||
dmss: dmss {
|
||||
dmss: bus@48000000 {
|
||||
compatible = "simple-mfd";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
dma-ranges;
|
||||
ranges;
|
||||
ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
|
||||
|
||||
ti,sci-dev-id = <25>;
|
||||
|
||||
|
|
@ -134,7 +134,7 @@ main_pktdma: dma-controller@485c0000 {
|
|||
};
|
||||
};
|
||||
|
||||
dmsc: dmsc@44043000 {
|
||||
dmsc: system-controller@44043000 {
|
||||
compatible = "ti,k2g-sci";
|
||||
ti,host-id = <12>;
|
||||
mbox-names = "rx", "tx";
|
||||
|
|
@ -148,7 +148,7 @@ k3_pds: power-controller {
|
|||
#power-domain-cells = <2>;
|
||||
};
|
||||
|
||||
k3_clks: clocks {
|
||||
k3_clks: clock-controller {
|
||||
compatible = "ti,k2g-sci-clk";
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
|
@ -373,8 +373,9 @@ main_spi4: spi@20140000 {
|
|||
clocks = <&k3_clks 145 0>;
|
||||
};
|
||||
|
||||
main_gpio_intr: interrupt-controller0 {
|
||||
main_gpio_intr: interrupt-controller@a00000 {
|
||||
compatible = "ti,sci-intr";
|
||||
reg = <0x00 0x00a00000 0x00 0x800>;
|
||||
ti,intr-trigger-type = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user