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crypto: arm64/ghash - Move NEON GHASH assembly into its own file
arch/arm64/crypto/ghash-ce-core.S implements pmull_ghash_update_p8(), which is used only by a crypto_shash implementation of GHASH. It also implements other functions, including pmull_ghash_update_p64() and others, which are used only by a crypto_aead implementation of AES-GCM. While some code is shared between pmull_ghash_update_p8() and pmull_ghash_update_p64(), it's not very much. Since pmull_ghash_update_p8() will also need to be migrated into lib/crypto/ to achieve parity in the standalone GHASH support, let's move it into a separate file ghash-neon-core.S. Acked-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20260319061723.1140720-9-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
This commit is contained in:
Eric Biggers
parent
71e59795c9
commit
e3f473db02
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@ -27,7 +27,7 @@ obj-$(CONFIG_CRYPTO_SM4_ARM64_NEON_BLK) += sm4-neon.o
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sm4-neon-y := sm4-neon-glue.o sm4-neon-core.o
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obj-$(CONFIG_CRYPTO_GHASH_ARM64_CE) += ghash-ce.o
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ghash-ce-y := ghash-ce-glue.o ghash-ce-core.o
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ghash-ce-y := ghash-ce-glue.o ghash-ce-core.o ghash-neon-core.o
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obj-$(CONFIG_CRYPTO_AES_ARM64_CE_CCM) += aes-ce-ccm.o
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aes-ce-ccm-y := aes-ce-ccm-glue.o aes-ce-ccm-core.o
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Accelerated GHASH implementation with ARMv8 PMULL instructions.
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* Accelerated AES-GCM implementation with ARMv8 Crypto Extensions.
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*
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* Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*/
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@ -19,31 +19,6 @@
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XH .req v7
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IN1 .req v7
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k00_16 .req v8
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k32_48 .req v9
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t3 .req v10
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t4 .req v11
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t5 .req v12
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t6 .req v13
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t7 .req v14
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t8 .req v15
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t9 .req v16
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perm1 .req v17
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perm2 .req v18
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perm3 .req v19
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sh1 .req v20
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sh2 .req v21
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sh3 .req v22
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sh4 .req v23
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ss1 .req v24
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ss2 .req v25
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ss3 .req v26
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ss4 .req v27
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XL2 .req v8
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XM2 .req v9
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XH2 .req v10
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@ -60,90 +35,6 @@
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.text
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.arch armv8-a+crypto
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.macro __pmull_p64, rd, rn, rm
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pmull \rd\().1q, \rn\().1d, \rm\().1d
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.endm
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.macro __pmull2_p64, rd, rn, rm
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pmull2 \rd\().1q, \rn\().2d, \rm\().2d
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.endm
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.macro __pmull_p8, rq, ad, bd
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ext t3.8b, \ad\().8b, \ad\().8b, #1 // A1
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ext t5.8b, \ad\().8b, \ad\().8b, #2 // A2
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ext t7.8b, \ad\().8b, \ad\().8b, #3 // A3
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__pmull_p8_\bd \rq, \ad
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.endm
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.macro __pmull2_p8, rq, ad, bd
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tbl t3.16b, {\ad\().16b}, perm1.16b // A1
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tbl t5.16b, {\ad\().16b}, perm2.16b // A2
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tbl t7.16b, {\ad\().16b}, perm3.16b // A3
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__pmull2_p8_\bd \rq, \ad
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.endm
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.macro __pmull_p8_SHASH, rq, ad
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__pmull_p8_tail \rq, \ad\().8b, SHASH.8b, 8b,, sh1, sh2, sh3, sh4
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.endm
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.macro __pmull_p8_SHASH2, rq, ad
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__pmull_p8_tail \rq, \ad\().8b, SHASH2.8b, 8b,, ss1, ss2, ss3, ss4
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.endm
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.macro __pmull2_p8_SHASH, rq, ad
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__pmull_p8_tail \rq, \ad\().16b, SHASH.16b, 16b, 2, sh1, sh2, sh3, sh4
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.endm
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.macro __pmull_p8_tail, rq, ad, bd, nb, t, b1, b2, b3, b4
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pmull\t t3.8h, t3.\nb, \bd // F = A1*B
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pmull\t t4.8h, \ad, \b1\().\nb // E = A*B1
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pmull\t t5.8h, t5.\nb, \bd // H = A2*B
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pmull\t t6.8h, \ad, \b2\().\nb // G = A*B2
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pmull\t t7.8h, t7.\nb, \bd // J = A3*B
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pmull\t t8.8h, \ad, \b3\().\nb // I = A*B3
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pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
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pmull\t \rq\().8h, \ad, \bd // D = A*B
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eor t3.16b, t3.16b, t4.16b // L = E + F
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eor t5.16b, t5.16b, t6.16b // M = G + H
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eor t7.16b, t7.16b, t8.16b // N = I + J
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uzp1 t4.2d, t3.2d, t5.2d
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uzp2 t3.2d, t3.2d, t5.2d
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uzp1 t6.2d, t7.2d, t9.2d
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uzp2 t7.2d, t7.2d, t9.2d
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// t3 = (L) (P0 + P1) << 8
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// t5 = (M) (P2 + P3) << 16
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eor t4.16b, t4.16b, t3.16b
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and t3.16b, t3.16b, k32_48.16b
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// t7 = (N) (P4 + P5) << 24
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// t9 = (K) (P6 + P7) << 32
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eor t6.16b, t6.16b, t7.16b
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and t7.16b, t7.16b, k00_16.16b
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eor t4.16b, t4.16b, t3.16b
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eor t6.16b, t6.16b, t7.16b
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zip2 t5.2d, t4.2d, t3.2d
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zip1 t3.2d, t4.2d, t3.2d
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zip2 t9.2d, t6.2d, t7.2d
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zip1 t7.2d, t6.2d, t7.2d
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ext t3.16b, t3.16b, t3.16b, #15
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ext t5.16b, t5.16b, t5.16b, #14
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ext t7.16b, t7.16b, t7.16b, #13
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ext t9.16b, t9.16b, t9.16b, #12
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eor t3.16b, t3.16b, t5.16b
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eor t7.16b, t7.16b, t9.16b
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eor \rq\().16b, \rq\().16b, t3.16b
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eor \rq\().16b, \rq\().16b, t7.16b
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.endm
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.macro __pmull_pre_p64
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add x8, x3, #16
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ld1 {HH.2d-HH4.2d}, [x8]
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@ -160,43 +51,6 @@
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shl MASK.2d, MASK.2d, #57
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.endm
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.macro __pmull_pre_p8
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ext SHASH2.16b, SHASH.16b, SHASH.16b, #8
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eor SHASH2.16b, SHASH2.16b, SHASH.16b
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// k00_16 := 0x0000000000000000_000000000000ffff
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// k32_48 := 0x00000000ffffffff_0000ffffffffffff
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movi k32_48.2d, #0xffffffff
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mov k32_48.h[2], k32_48.h[0]
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ushr k00_16.2d, k32_48.2d, #32
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// prepare the permutation vectors
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mov_q x5, 0x080f0e0d0c0b0a09
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movi T1.8b, #8
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dup perm1.2d, x5
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eor perm1.16b, perm1.16b, T1.16b
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ushr perm2.2d, perm1.2d, #8
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ushr perm3.2d, perm1.2d, #16
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ushr T1.2d, perm1.2d, #24
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sli perm2.2d, perm1.2d, #56
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sli perm3.2d, perm1.2d, #48
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sli T1.2d, perm1.2d, #40
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// precompute loop invariants
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tbl sh1.16b, {SHASH.16b}, perm1.16b
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tbl sh2.16b, {SHASH.16b}, perm2.16b
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tbl sh3.16b, {SHASH.16b}, perm3.16b
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tbl sh4.16b, {SHASH.16b}, T1.16b
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ext ss1.8b, SHASH2.8b, SHASH2.8b, #1
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ext ss2.8b, SHASH2.8b, SHASH2.8b, #2
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ext ss3.8b, SHASH2.8b, SHASH2.8b, #3
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ext ss4.8b, SHASH2.8b, SHASH2.8b, #4
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.endm
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//
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// PMULL (64x64->128) based reduction for CPUs that can do
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// it in a single instruction.
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//
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.macro __pmull_reduce_p64
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pmull T2.1q, XL.1d, MASK.1d
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eor XM.16b, XM.16b, T1.16b
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@ -209,39 +63,15 @@
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pmull XL.1q, XL.1d, MASK.1d
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.endm
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//
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// Alternative reduction for CPUs that lack support for the
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// 64x64->128 PMULL instruction
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//
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.macro __pmull_reduce_p8
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eor XM.16b, XM.16b, T1.16b
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mov XL.d[1], XM.d[0]
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mov XH.d[0], XM.d[1]
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shl T1.2d, XL.2d, #57
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shl T2.2d, XL.2d, #62
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eor T2.16b, T2.16b, T1.16b
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shl T1.2d, XL.2d, #63
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eor T2.16b, T2.16b, T1.16b
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ext T1.16b, XL.16b, XH.16b, #8
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eor T2.16b, T2.16b, T1.16b
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mov XL.d[1], T2.d[0]
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mov XH.d[0], T2.d[1]
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ushr T2.2d, XL.2d, #1
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eor XH.16b, XH.16b, XL.16b
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eor XL.16b, XL.16b, T2.16b
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ushr T2.2d, T2.2d, #6
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ushr XL.2d, XL.2d, #1
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.endm
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.macro __pmull_ghash, pn
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/*
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* void pmull_ghash_update_p64(int blocks, u64 dg[], const char *src,
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* u64 const h[][2], const char *head)
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*/
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SYM_TYPED_FUNC_START(pmull_ghash_update_p64)
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ld1 {SHASH.2d}, [x3]
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ld1 {XL.2d}, [x1]
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__pmull_pre_\pn
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__pmull_pre_p64
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/* do the head block first, if supplied */
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cbz x4, 0f
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@ -249,7 +79,7 @@
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mov x4, xzr
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b 3f
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0: .ifc \pn, p64
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0:
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tbnz w0, #0, 2f // skip until #blocks is a
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tbnz w0, #1, 2f // round multiple of 4
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@ -314,7 +144,6 @@
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cbz w0, 5f
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b 1b
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.endif
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2: ld1 {T1.2d}, [x2], #16
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sub w0, w0, #1
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@ -327,16 +156,16 @@ CPU_LE( rev64 T1.16b, T1.16b )
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eor T1.16b, T1.16b, T2.16b
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eor XL.16b, XL.16b, IN1.16b
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__pmull2_\pn XH, XL, SHASH // a1 * b1
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pmull2 XH.1q, XL.2d, SHASH.2d // a1 * b1
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eor T1.16b, T1.16b, XL.16b
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__pmull_\pn XL, XL, SHASH // a0 * b0
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__pmull_\pn XM, T1, SHASH2 // (a1 + a0)(b1 + b0)
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pmull XL.1q, XL.1d, SHASH.1d // a0 * b0
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pmull XM.1q, T1.1d, SHASH2.1d // (a1 + a0)(b1 + b0)
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4: eor T2.16b, XL.16b, XH.16b
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ext T1.16b, XL.16b, XH.16b, #8
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eor XM.16b, XM.16b, T2.16b
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__pmull_reduce_\pn
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__pmull_reduce_p64
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eor T2.16b, T2.16b, XH.16b
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eor XL.16b, XL.16b, T2.16b
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@ -345,20 +174,8 @@ CPU_LE( rev64 T1.16b, T1.16b )
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5: st1 {XL.2d}, [x1]
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ret
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.endm
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/*
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* void pmull_ghash_update(int blocks, u64 dg[], const char *src,
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* struct ghash_key const *k, const char *head)
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*/
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SYM_TYPED_FUNC_START(pmull_ghash_update_p64)
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__pmull_ghash p64
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SYM_FUNC_END(pmull_ghash_update_p64)
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SYM_TYPED_FUNC_START(pmull_ghash_update_p8)
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__pmull_ghash p8
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SYM_FUNC_END(pmull_ghash_update_p8)
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KS0 .req v8
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KS1 .req v9
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KS2 .req v10
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226
arch/arm64/crypto/ghash-neon-core.S
Normal file
226
arch/arm64/crypto/ghash-neon-core.S
Normal file
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@ -0,0 +1,226 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Accelerated GHASH implementation with ARMv8 ASIMD instructions.
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*
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* Copyright (C) 2014 - 2018 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*/
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#include <linux/linkage.h>
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#include <linux/cfi_types.h>
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#include <asm/assembler.h>
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SHASH .req v0
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SHASH2 .req v1
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T1 .req v2
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T2 .req v3
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XM .req v5
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XL .req v6
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XH .req v7
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IN1 .req v7
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k00_16 .req v8
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k32_48 .req v9
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t3 .req v10
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t4 .req v11
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t5 .req v12
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t6 .req v13
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t7 .req v14
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t8 .req v15
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t9 .req v16
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perm1 .req v17
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perm2 .req v18
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perm3 .req v19
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sh1 .req v20
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sh2 .req v21
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sh3 .req v22
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sh4 .req v23
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ss1 .req v24
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ss2 .req v25
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ss3 .req v26
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ss4 .req v27
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.text
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.macro __pmull_p8, rq, ad, bd
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ext t3.8b, \ad\().8b, \ad\().8b, #1 // A1
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ext t5.8b, \ad\().8b, \ad\().8b, #2 // A2
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ext t7.8b, \ad\().8b, \ad\().8b, #3 // A3
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__pmull_p8_\bd \rq, \ad
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.endm
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.macro __pmull2_p8, rq, ad, bd
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tbl t3.16b, {\ad\().16b}, perm1.16b // A1
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tbl t5.16b, {\ad\().16b}, perm2.16b // A2
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tbl t7.16b, {\ad\().16b}, perm3.16b // A3
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__pmull2_p8_\bd \rq, \ad
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.endm
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.macro __pmull_p8_SHASH, rq, ad
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__pmull_p8_tail \rq, \ad\().8b, SHASH.8b, 8b,, sh1, sh2, sh3, sh4
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.endm
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.macro __pmull_p8_SHASH2, rq, ad
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__pmull_p8_tail \rq, \ad\().8b, SHASH2.8b, 8b,, ss1, ss2, ss3, ss4
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.endm
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.macro __pmull2_p8_SHASH, rq, ad
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__pmull_p8_tail \rq, \ad\().16b, SHASH.16b, 16b, 2, sh1, sh2, sh3, sh4
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.endm
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.macro __pmull_p8_tail, rq, ad, bd, nb, t, b1, b2, b3, b4
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pmull\t t3.8h, t3.\nb, \bd // F = A1*B
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pmull\t t4.8h, \ad, \b1\().\nb // E = A*B1
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pmull\t t5.8h, t5.\nb, \bd // H = A2*B
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pmull\t t6.8h, \ad, \b2\().\nb // G = A*B2
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pmull\t t7.8h, t7.\nb, \bd // J = A3*B
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pmull\t t8.8h, \ad, \b3\().\nb // I = A*B3
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pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
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pmull\t \rq\().8h, \ad, \bd // D = A*B
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eor t3.16b, t3.16b, t4.16b // L = E + F
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eor t5.16b, t5.16b, t6.16b // M = G + H
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eor t7.16b, t7.16b, t8.16b // N = I + J
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||||
|
||||
uzp1 t4.2d, t3.2d, t5.2d
|
||||
uzp2 t3.2d, t3.2d, t5.2d
|
||||
uzp1 t6.2d, t7.2d, t9.2d
|
||||
uzp2 t7.2d, t7.2d, t9.2d
|
||||
|
||||
// t3 = (L) (P0 + P1) << 8
|
||||
// t5 = (M) (P2 + P3) << 16
|
||||
eor t4.16b, t4.16b, t3.16b
|
||||
and t3.16b, t3.16b, k32_48.16b
|
||||
|
||||
// t7 = (N) (P4 + P5) << 24
|
||||
// t9 = (K) (P6 + P7) << 32
|
||||
eor t6.16b, t6.16b, t7.16b
|
||||
and t7.16b, t7.16b, k00_16.16b
|
||||
|
||||
eor t4.16b, t4.16b, t3.16b
|
||||
eor t6.16b, t6.16b, t7.16b
|
||||
|
||||
zip2 t5.2d, t4.2d, t3.2d
|
||||
zip1 t3.2d, t4.2d, t3.2d
|
||||
zip2 t9.2d, t6.2d, t7.2d
|
||||
zip1 t7.2d, t6.2d, t7.2d
|
||||
|
||||
ext t3.16b, t3.16b, t3.16b, #15
|
||||
ext t5.16b, t5.16b, t5.16b, #14
|
||||
ext t7.16b, t7.16b, t7.16b, #13
|
||||
ext t9.16b, t9.16b, t9.16b, #12
|
||||
|
||||
eor t3.16b, t3.16b, t5.16b
|
||||
eor t7.16b, t7.16b, t9.16b
|
||||
eor \rq\().16b, \rq\().16b, t3.16b
|
||||
eor \rq\().16b, \rq\().16b, t7.16b
|
||||
.endm
|
||||
|
||||
.macro __pmull_pre_p8
|
||||
ext SHASH2.16b, SHASH.16b, SHASH.16b, #8
|
||||
eor SHASH2.16b, SHASH2.16b, SHASH.16b
|
||||
|
||||
// k00_16 := 0x0000000000000000_000000000000ffff
|
||||
// k32_48 := 0x00000000ffffffff_0000ffffffffffff
|
||||
movi k32_48.2d, #0xffffffff
|
||||
mov k32_48.h[2], k32_48.h[0]
|
||||
ushr k00_16.2d, k32_48.2d, #32
|
||||
|
||||
// prepare the permutation vectors
|
||||
mov_q x5, 0x080f0e0d0c0b0a09
|
||||
movi T1.8b, #8
|
||||
dup perm1.2d, x5
|
||||
eor perm1.16b, perm1.16b, T1.16b
|
||||
ushr perm2.2d, perm1.2d, #8
|
||||
ushr perm3.2d, perm1.2d, #16
|
||||
ushr T1.2d, perm1.2d, #24
|
||||
sli perm2.2d, perm1.2d, #56
|
||||
sli perm3.2d, perm1.2d, #48
|
||||
sli T1.2d, perm1.2d, #40
|
||||
|
||||
// precompute loop invariants
|
||||
tbl sh1.16b, {SHASH.16b}, perm1.16b
|
||||
tbl sh2.16b, {SHASH.16b}, perm2.16b
|
||||
tbl sh3.16b, {SHASH.16b}, perm3.16b
|
||||
tbl sh4.16b, {SHASH.16b}, T1.16b
|
||||
ext ss1.8b, SHASH2.8b, SHASH2.8b, #1
|
||||
ext ss2.8b, SHASH2.8b, SHASH2.8b, #2
|
||||
ext ss3.8b, SHASH2.8b, SHASH2.8b, #3
|
||||
ext ss4.8b, SHASH2.8b, SHASH2.8b, #4
|
||||
.endm
|
||||
|
||||
.macro __pmull_reduce_p8
|
||||
eor XM.16b, XM.16b, T1.16b
|
||||
|
||||
mov XL.d[1], XM.d[0]
|
||||
mov XH.d[0], XM.d[1]
|
||||
|
||||
shl T1.2d, XL.2d, #57
|
||||
shl T2.2d, XL.2d, #62
|
||||
eor T2.16b, T2.16b, T1.16b
|
||||
shl T1.2d, XL.2d, #63
|
||||
eor T2.16b, T2.16b, T1.16b
|
||||
ext T1.16b, XL.16b, XH.16b, #8
|
||||
eor T2.16b, T2.16b, T1.16b
|
||||
|
||||
mov XL.d[1], T2.d[0]
|
||||
mov XH.d[0], T2.d[1]
|
||||
|
||||
ushr T2.2d, XL.2d, #1
|
||||
eor XH.16b, XH.16b, XL.16b
|
||||
eor XL.16b, XL.16b, T2.16b
|
||||
ushr T2.2d, T2.2d, #6
|
||||
ushr XL.2d, XL.2d, #1
|
||||
.endm
|
||||
|
||||
/*
|
||||
* void pmull_ghash_update_p8(int blocks, u64 dg[], const char *src,
|
||||
* u64 const h[][2], const char *head)
|
||||
*/
|
||||
SYM_TYPED_FUNC_START(pmull_ghash_update_p8)
|
||||
ld1 {SHASH.2d}, [x3]
|
||||
ld1 {XL.2d}, [x1]
|
||||
|
||||
__pmull_pre_p8
|
||||
|
||||
/* do the head block first, if supplied */
|
||||
cbz x4, 0f
|
||||
ld1 {T1.2d}, [x4]
|
||||
mov x4, xzr
|
||||
b 3f
|
||||
|
||||
0: ld1 {T1.2d}, [x2], #16
|
||||
sub w0, w0, #1
|
||||
|
||||
3: /* multiply XL by SHASH in GF(2^128) */
|
||||
CPU_LE( rev64 T1.16b, T1.16b )
|
||||
|
||||
ext T2.16b, XL.16b, XL.16b, #8
|
||||
ext IN1.16b, T1.16b, T1.16b, #8
|
||||
eor T1.16b, T1.16b, T2.16b
|
||||
eor XL.16b, XL.16b, IN1.16b
|
||||
|
||||
__pmull2_p8 XH, XL, SHASH // a1 * b1
|
||||
eor T1.16b, T1.16b, XL.16b
|
||||
__pmull_p8 XL, XL, SHASH // a0 * b0
|
||||
__pmull_p8 XM, T1, SHASH2 // (a1 + a0)(b1 + b0)
|
||||
|
||||
eor T2.16b, XL.16b, XH.16b
|
||||
ext T1.16b, XL.16b, XH.16b, #8
|
||||
eor XM.16b, XM.16b, T2.16b
|
||||
|
||||
__pmull_reduce_p8
|
||||
|
||||
eor T2.16b, T2.16b, XH.16b
|
||||
eor XL.16b, XL.16b, T2.16b
|
||||
|
||||
cbnz w0, 0b
|
||||
|
||||
st1 {XL.2d}, [x1]
|
||||
ret
|
||||
SYM_FUNC_END(pmull_ghash_update_p8)
|
||||
Loading…
Reference in New Issue
Block a user