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drm/amdgpu/vcn5.0.0: convert internal functions to use vcn_inst

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Pass the vcn instance structure to these functions rather
than adev and the instance number.

TODO: clean up the function internals to use the vinst state
directly rather than accessing it indirectly via adev->vcn.inst[].

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2024-11-22 18:07:03 -05:00
parent c07c0c0df9
commit e3eb71cd69
1 changed files with 55 additions and 44 deletions
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99
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
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@ -367,13 +367,14 @@ static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block)
/**
* vcn_v5_0_0_mc_resume - memory controller programming
*
* @adev: amdgpu_device pointer
* @inst: instance number
* @vinst: VCN instance
*
* Let the VCN memory controller know it's offsets
*/
static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst)
static void vcn_v5_0_0_mc_resume(struct amdgpu_vcn_inst *vinst)
{
struct amdgpu_device *adev = vinst->adev;
int inst = vinst->inst;
uint32_t offset, size;
const struct common_firmware_header *hdr;
@ -427,14 +428,16 @@ static void vcn_v5_0_0_mc_resume(struct amdgpu_device *adev, int inst)
/**
* vcn_v5_0_0_mc_resume_dpg_mode - memory controller programming for dpg mode
*
* @adev: amdgpu_device pointer
* @inst_idx: instance number index
* @vinst: VCN instance
* @indirect: indirectly write sram
*
* Let the VCN memory controller know it's offsets with dpg mode
*/
static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst,
bool indirect)
{
struct amdgpu_device *adev = vinst->adev;
int inst_idx = vinst->inst;
uint32_t offset, size;
const struct common_firmware_header *hdr;
@ -537,13 +540,14 @@ static void vcn_v5_0_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_i
/**
* vcn_v5_0_0_disable_static_power_gating - disable VCN static power gating
*
* @adev: amdgpu_device pointer
* @inst: instance number
* @vinst: VCN instance
*
* Disable static power gating for VCN block
*/
static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst)
{
struct amdgpu_device *adev = vinst->adev;
int inst = vinst->inst;
uint32_t data = 0;
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
@ -604,13 +608,14 @@ static void vcn_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev, i
/**
* vcn_v5_0_0_enable_static_power_gating - enable VCN static power gating
*
* @adev: amdgpu_device pointer
* @inst: instance number
* @vinst: VCN instance
*
* Enable static power gating for VCN block
*/
static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst)
{
struct amdgpu_device *adev = vinst->adev;
int inst = vinst->inst;
uint32_t data;
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
@ -650,12 +655,11 @@ static void vcn_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev, in
/**
* vcn_v5_0_0_disable_clock_gating - disable VCN clock gating
*
* @adev: amdgpu_device pointer
* @inst: instance number
* @vinst: VCN instance
*
* Disable clock gating for VCN block
*/
static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst)
{
return;
}
@ -664,15 +668,15 @@ static void vcn_v5_0_0_disable_clock_gating(struct amdgpu_device *adev, int inst
/**
* vcn_v5_0_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
*
* @adev: amdgpu_device pointer
* @vinst: VCN instance
* @sram_sel: sram select
* @inst_idx: instance number index
* @indirect: indirectly write sram
*
* Disable clock gating for VCN block with dpg mode
*/
static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
int inst_idx, uint8_t indirect)
static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst,
uint8_t sram_sel,
uint8_t indirect)
{
return;
}
@ -681,12 +685,11 @@ static void vcn_v5_0_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev,
/**
* vcn_v5_0_0_enable_clock_gating - enable VCN clock gating
*
* @adev: amdgpu_device pointer
* @inst: instance number
* @vinst: VCN instance
*
* Enable clock gating for VCN block
*/
static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst)
{
return;
}
@ -694,14 +697,16 @@ static void vcn_v5_0_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
/**
* vcn_v5_0_0_start_dpg_mode - VCN start with dpg mode
*
* @adev: amdgpu_device pointer
* @inst_idx: instance number index
* @vinst: VCN instance
* @indirect: indirectly write sram
*
* Start VCN block with dpg mode
*/
static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
bool indirect)
{
struct amdgpu_device *adev = vinst->adev;
int inst_idx = vinst->inst;
volatile struct amdgpu_vcn5_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
struct amdgpu_ring *ring;
uint32_t tmp;
@ -741,7 +746,7 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET(
VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
vcn_v5_0_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
vcn_v5_0_0_mc_resume_dpg_mode(vinst, indirect);
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
@ -793,13 +798,14 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
/**
* vcn_v5_0_0_start - VCN start
*
* @adev: amdgpu_device pointer
* @i: instance to start
* @vinst: VCN instance
*
* Start VCN block
*/
static int vcn_v5_0_0_start(struct amdgpu_device *adev, int i)
static int vcn_v5_0_0_start(struct amdgpu_vcn_inst *vinst)
{
struct amdgpu_device *adev = vinst->adev;
int i = vinst->inst;
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t tmp;
@ -814,10 +820,10 @@ static int vcn_v5_0_0_start(struct amdgpu_device *adev, int i)
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return vcn_v5_0_0_start_dpg_mode(adev, i, adev->vcn.inst[i].indirect_sram);
return vcn_v5_0_0_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram);
/* disable VCN power gating */
vcn_v5_0_0_disable_static_power_gating(adev, i);
vcn_v5_0_0_disable_static_power_gating(vinst);
/* set VCN status busy */
tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
@ -848,7 +854,7 @@ static int vcn_v5_0_0_start(struct amdgpu_device *adev, int i)
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
vcn_v5_0_0_mc_resume(adev, i);
vcn_v5_0_0_mc_resume(vinst);
/* VCN global tiling registers */
WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
@ -944,13 +950,14 @@ static int vcn_v5_0_0_start(struct amdgpu_device *adev, int i)
/**
* vcn_v5_0_0_stop_dpg_mode - VCN stop with dpg mode
*
* @adev: amdgpu_device pointer
* @inst_idx: instance number index
* @vinst: VCN instance
*
* Stop VCN block with dpg mode
*/
static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
{
struct amdgpu_device *adev = vinst->adev;
int inst_idx = vinst->inst;
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
uint32_t tmp;
@ -974,13 +981,14 @@ static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
/**
* vcn_v5_0_0_stop - VCN stop
*
* @adev: amdgpu_device pointer
* @i: instance to stop
* @vinst: VCN instance
*
* Stop VCN block
*/
static int vcn_v5_0_0_stop(struct amdgpu_device *adev, int i)
static int vcn_v5_0_0_stop(struct amdgpu_vcn_inst *vinst)
{
struct amdgpu_device *adev = vinst->adev;
int i = vinst->inst;
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
uint32_t tmp;
int r = 0;
@ -992,7 +1000,7 @@ static int vcn_v5_0_0_stop(struct amdgpu_device *adev, int i)
fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
vcn_v5_0_0_stop_dpg_mode(adev, i);
vcn_v5_0_0_stop_dpg_mode(vinst);
r = 0;
goto done;
}
@ -1046,7 +1054,7 @@ static int vcn_v5_0_0_stop(struct amdgpu_device *adev, int i)
WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
/* enable VCN power gating */
vcn_v5_0_0_enable_static_power_gating(adev, i);
vcn_v5_0_0_enable_static_power_gating(vinst);
done:
if (adev->pm.dpm_enabled)
@ -1273,15 +1281,17 @@ static int vcn_v5_0_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
int i;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
if (adev->vcn.harvest_config & (1 << i))
continue;
if (enable) {
if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
return -EBUSY;
vcn_v5_0_0_enable_clock_gating(adev, i);
vcn_v5_0_0_enable_clock_gating(vinst);
} else {
vcn_v5_0_0_disable_clock_gating(adev, i);
vcn_v5_0_0_disable_clock_gating(vinst);
}
}
@ -1293,15 +1303,16 @@ static int vcn_v5_0_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_bloc
int i)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i];
int ret = 0;
if (state == adev->vcn.inst[i].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
ret = vcn_v5_0_0_stop(adev, i);
ret = vcn_v5_0_0_stop(vinst);
else
ret = vcn_v5_0_0_start(adev, i);
ret = vcn_v5_0_0_start(vinst);
if (!ret)
adev->vcn.inst[i].cur_state = state;