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PCI: dwc: ep: Add comment explaining controller level PTM access in multi PF setup

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PCIe r6.0, section 7.9.15 requires PTM capability in exactly one
function to control all PTM-capable functions. This makes PTM registers
controller level rather than per-function.

Add a comment explaining why PTM capability registers are accessed
using the standard DBI accessors instead of func_no indexed
per-function accessors.

Suggested-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Aksh Garg <a-garg7@ti.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Link: https://patch.msgid.link/20260130115516.515082-4-a-garg7@ti.com
This commit is contained in:
Aksh Garg 2026-01-30 17:25:16 +05:30 committed by Bjorn Helgaas
parent 72cb5ed2a5
commit e3c3a5d25d
1 changed files with 12 additions and 0 deletions
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12
drivers/pci/controller/dwc/pcie-designware-ep.c
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@ -1187,6 +1187,18 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
if (ep->ops->init)
ep->ops->init(ep);
/*
* PCIe r6.0, section 7.9.15 states that for endpoints that support
* PTM, this capability structure is required in exactly one
* function, which controls the PTM behavior of all PTM capable
* functions. This indicates the PTM capability structure
* represents controller-level registers rather than per-function
* registers.
*
* Therefore, PTM capability registers are configured using the
* standard DBI accessors, instead of func_no indexed per-function
* accessors.
*/
ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM);
/*