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ARM: dts: imx6ul-var-som: Factor out common parts for all CPU variants
Factor out the parts on the Variscite VAR-SOM-6UL [1] that are common to all CPU variants (6UL, 6ULL, etc). This will simplify adding future dedicated device tree files for each CPU variant. Link https://dev.variscite.com/var-som-6ul [1] Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Hugo Villeneuve
Frank Li
parent
116f95fc84
commit
e3b21b3375
227
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
Normal file
227
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
Normal file
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@ -0,0 +1,227 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Support for the common parts shared by all the different CPU options on
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* Variscite VAR-SOM-6UL Module
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*
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* Copyright 2019 Variscite Ltd.
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* Copyright 2025 Bootlin
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*/
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#include <dt-bindings/clock/imx6ul-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Variscite VAR-SOM-6UL module";
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compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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reg_gpio_dvfs: reg-gpio-dvfs {
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compatible = "regulator-gpio";
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <1400000>;
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regulator-name = "gpio_dvfs";
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regulator-type = "voltage";
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gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
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states = <1300000 0x1
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1400000 0x0>;
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};
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rmii_ref_clk: rmii-ref-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "rmii-ref";
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};
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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clocks = <&rmii_ref_clk>;
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clock-names = "rmii-ref";
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reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <100000>;
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micrel,led-mode = <1>;
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micrel,rmii-reference-clock-select-25-mhz;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_enet1_gpio: enet1-gpiogrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
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>;
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};
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pinctrl_enet1_mdio: enet1-mdiogrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */
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MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
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MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
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MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
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MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
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MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
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>;
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};
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pinctrl_tsc: tscgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
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MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
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MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
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MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
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MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
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>;
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};
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};
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&pxp {
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status = "okay";
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};
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&sai2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
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<&clks IMX6UL_CLK_SAI2>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <0>, <12288000>;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&snvs_poweroff {
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status = "okay";
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};
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&tsc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc>;
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xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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measure-delay-time = <0xffff>;
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pre-charge-time = <0xfff>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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keep-power-in-suspend;
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wakeup-source;
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status = "okay";
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};
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@ -9,221 +9,9 @@
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/dts-v1/;
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#include "imx6ul.dtsi"
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#include <dt-bindings/clock/imx6ul-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "imx6ul-var-som-common.dtsi"
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/ {
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model = "Variscite VAR-SOM-6UL module";
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compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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reg_gpio_dvfs: reg-gpio-dvfs {
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compatible = "regulator-gpio";
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <1400000>;
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regulator-name = "gpio_dvfs";
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regulator-type = "voltage";
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gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
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states = <1300000 0x1
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1400000 0x0>;
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};
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rmii_ref_clk: rmii-ref-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "rmii-ref";
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};
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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clocks = <&rmii_ref_clk>;
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clock-names = "rmii-ref";
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reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <100000>;
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micrel,led-mode = <1>;
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micrel,rmii-reference-clock-select-25-mhz;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_enet1_gpio: enet1-gpiogrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
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>;
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};
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pinctrl_enet1_mdio: enet1-mdiogrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */
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MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
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MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
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MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
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MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
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MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
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>;
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};
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pinctrl_tsc: tscgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
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MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
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MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
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MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
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MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
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||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&pxp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai2>;
|
||||
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
|
||||
<&clks IMX6UL_CLK_SAI2>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <0>, <12288000>;
|
||||
fsl,sai-mclk-direction-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&snvs_poweroff {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc>;
|
||||
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
measure-delay-time = <0xffff>;
|
||||
pre-charge-time = <0xfff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
||||
bus-width = <8>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
keep-power-in-suspend;
|
||||
wakeup-source;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
15
arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
Normal file
15
arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Support for Variscite VAR-SOM-6UL module with imx6ull CPU
|
||||
*
|
||||
* Copyright 2019-2024 Variscite Ltd.
|
||||
* Copyright 2026 Dimonoff
|
||||
*/
|
||||
|
||||
#include "imx6ull.dtsi"
|
||||
#include "imx6ul-var-som-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Variscite VAR-SOM-6UL module";
|
||||
compatible = "variscite,var-som-imx6ull", "fsl,imx6ull";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user