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drm/i915/power-well: use generic poll_timeout_us() instead of wait_for() for VLV/CHV

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Prefer generic poll helpers over i915 custom helpers.

The functional change is losing the exponentially growing sleep of
wait_for(), which used to be 10, 20, 40, ..., 640, and 1280 us.

Use an arbitrary constant 500 us sleep instead. The timeout remains at
100 ms.

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/c644b7b5611a3c047ea5d3d52acd91830b2fa6b4.1756383233.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2025-08-28 15:20:53 +03:00
parent a8eb4cdced
commit e38e3c50a1
1 changed files with 15 additions and 14 deletions
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29
drivers/gpu/drm/i915/display/intel_display_power_well.c
View File

@ -8,7 +8,6 @@
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "i915_utils.h"
#include "intel_backlight_regs.h"
#include "intel_combo_phy.h"
#include "intel_combo_phy_regs.h"
@ -1127,6 +1126,8 @@ static void vlv_set_power_well(struct intel_display *display,
u32 mask;
u32 state;
u32 ctrl;
u32 val;
int ret;
mask = PUNIT_PWRGT_MASK(pw_idx);
state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
@ -1134,10 +1135,8 @@ static void vlv_set_power_well(struct intel_display *display,
vlv_punit_get(display->drm);
#define COND \
((vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS) & mask) == state)
if (COND)
val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS);
if ((val & mask) == state)
goto out;
ctrl = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL);
@ -1145,14 +1144,15 @@ static void vlv_set_power_well(struct intel_display *display,
ctrl |= state;
vlv_punit_write(display->drm, PUNIT_REG_PWRGT_CTRL, ctrl);
if (wait_for(COND, 100))
ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_PWRGT_STATUS),
(val & mask) == state,
500, 100 * 1000, false);
if (ret)
drm_err(display->drm,
"timeout setting power well state %08x (%08x)\n",
state,
vlv_punit_read(display->drm, PUNIT_REG_PWRGT_CTRL));
#undef COND
out:
vlv_punit_put(display->drm);
}
@ -1716,23 +1716,24 @@ static void chv_set_pipe_power_well(struct intel_display *display,
enum pipe pipe = PIPE_A;
u32 state;
u32 ctrl;
int ret;
state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
vlv_punit_get(display->drm);
#define COND \
((vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
if (COND)
ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
if ((ctrl & DP_SSS_MASK(pipe)) == state)
goto out;
ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM);
ctrl &= ~DP_SSC_MASK(pipe);
ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
vlv_punit_write(display->drm, PUNIT_REG_DSPSSPM, ctrl);
if (wait_for(COND, 100))
ret = poll_timeout_us(ctrl = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
(ctrl & DP_SSS_MASK(pipe)) == state,
500, 100 * 1000, false);
if (ret)
drm_err(display->drm,
"timeout setting power well state %08x (%08x)\n",
state,