From d5083527908a994496519f5b9098b33460f365d6 Mon Sep 17 00:00:00 2001 From: Denzeel Oliva Date: Sat, 13 Jun 2026 07:36:16 -0500 Subject: [PATCH 1/6] dt-bindings: clock: exynos990: Add CLK_GOUT_PERIS_TMU_SUB_PCLK Add the missing TMU_SUB_PCLK clock ID for the Exynos990 PERIS CMU. Signed-off-by: Denzeel Oliva Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260613-exynos990-peris-fix-v3-v3-1-2b230db78ae4@gmail.com Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/samsung,exynos990.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index 47540307cb52..c06f591d9d90 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -434,5 +434,6 @@ #define CLK_GOUT_PERIS_TMU_TOP_PCLK 17 #define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 #define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 +#define CLK_GOUT_PERIS_TMU_SUB_PCLK 20 #endif From b7d6221aa44fc523c3418ecd94c582eea6e6d53a Mon Sep 17 00:00:00 2001 From: Denzeel Oliva Date: Sat, 13 Jun 2026 07:36:17 -0500 Subject: [PATCH 2/6] clk: samsung: exynos990: Add PERIS TMU_SUB_PCLK gate Add the missing CLK_GOUT_PERIS_TMU_SUB_PCLK gate clock for the Thermal Management Unit sub-block and update CLKS_NR_PERIS accordingly. Signed-off-by: Denzeel Oliva Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260613-exynos990-peris-fix-v3-v3-2-2b230db78ae4@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos990.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c index 4385c3b76dd6..ee3566b8e57c 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -21,7 +21,7 @@ #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK + 1) #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PCLK + 1) #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_XIU_P_ACLK + 1) -#define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) +#define CLKS_NR_PERIS (CLK_GOUT_PERIS_TMU_SUB_PCLK + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ @@ -2619,6 +2619,10 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = { "gout_peris_d_tzpc_peris_pclk", "mout_peris_bus_user", CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_PERIS_TMU_SUB_PCLK, + "gout_peris_tmu_sub_pclk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK, + 21, 0, 0), GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK, "gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic", CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, From a016e89781478e4b756fbf104945d037d0cdc809 Mon Sep 17 00:00:00 2001 From: Denzeel Oliva Date: Sat, 13 Jun 2026 07:36:18 -0500 Subject: [PATCH 3/6] clk: samsung: exynos990: Fix PERIS gate clock parents Correct eight PERIS gate clock parents to match the hardware clock tree and reorder the GIC mux parents so mout_peris_bus_user is the default source. Signed-off-by: Denzeel Oliva Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260613-exynos990-peris-fix-v3-v3-3-2b230db78ae4@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos990.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c index ee3566b8e57c..df5928833b23 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -2551,7 +2551,7 @@ static const unsigned long peris_clk_regs[] __initconst = { /* Parent clock list for CMU_PERIS muxes */ PNAME(mout_peris_bus_user_p) = { "oscclk", "mout_cmu_peris_bus" }; -PNAME(mout_peris_clk_peris_gic_p) = { "oscclk", "mout_peris_bus_user" }; +PNAME(mout_peris_clk_peris_gic_p) = { "mout_peris_bus_user", "oscclk" }; static const struct samsung_mux_clock peris_mux_clks[] __initconst = { MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user", @@ -2584,15 +2584,15 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = { CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, 21, 0, 0), GATE(CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK, - "gout_peris_clk_peris_oscclk_clk", "mout_peris_bus_user", + "gout_peris_clk_peris_oscclk_clk", "oscclk", CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK, 21, 0, 0), GATE(CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK, - "gout_peris_clk_peris_gic_clk", "mout_peris_bus_user", + "gout_peris_clk_peris_gic_clk", "mout_peris_clk_peris_gic", CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, 21, 0, 0), GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM, - "gout_peris_ad_axi_p_peris_aclkm", "mout_peris_bus_user", + "gout_peris_ad_axi_p_peris_aclkm", "mout_peris_clk_peris_gic", CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK, @@ -2600,19 +2600,19 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = { CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_PERIS_GIC_CLK, - "gout_peris_gic_clk", "mout_peris_bus_user", + "gout_peris_gic_clk", "mout_peris_clk_peris_gic", CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK, 21, CLK_IS_CRITICAL, 0), GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK, - "gout_peris_lhm_axi_p_peris_clk", "oscclk", + "gout_peris_lhm_axi_p_peris_clk", "mout_peris_bus_user", CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_PERIS_MCT_PCLK, - "gout_peris_mct_pclk", "mout_peris_clk_peris_gic", + "gout_peris_mct_pclk", "mout_peris_bus_user", CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK, - "gout_peris_otp_con_top_pclk", "mout_peris_clk_peris_gic", + "gout_peris_otp_con_top_pclk", "mout_peris_bus_user", CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK, @@ -2624,7 +2624,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = { CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK, - "gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic", + "gout_peris_tmu_top_pclk", "mout_peris_bus_user", CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, 21, 0, 0), GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK, From 7b2a8eb5c7b5545793e18036c8b66106f2d9fbb8 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 28 Jun 2026 20:25:38 -0700 Subject: [PATCH 4/6] clk: samsung: use kzalloc_flex Simplify allocation by using kzalloc_flex with a flexible array member to combine allocations. samsung_clk_alloc_reg_dump is no longer needed for this struct but is needed elsewhere. Add __counted_by for extra runtime analysis. Move counting variable assignment after kzalloc_flex which does the same with GCC 15 and above. Signed-off-by: Rosen Penev Link: https://patch.msgid.link/20260629032540.2331559-2-rosenp@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk.c | 11 ++++++----- drivers/clk/samsung/clk.h | 4 ++-- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 91e5cdbc79d7..2895c77534ae 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -430,21 +430,22 @@ void samsung_clk_extended_sleep_init(void __iomem *reg_base, unsigned long nr_rsuspend) { struct samsung_clock_reg_cache *reg_cache; + int i; - reg_cache = kzalloc_obj(struct samsung_clock_reg_cache); + reg_cache = kzalloc_flex(*reg_cache, rdump, nr_rdump); if (!reg_cache) panic("could not allocate register reg_cache.\n"); - reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump); - if (!reg_cache->rdump) - panic("could not allocate register dump storage.\n"); + reg_cache->rd_num = nr_rdump; + + for (i = 0; i < nr_rdump; ++i) + reg_cache->rdump[i].offset = rdump[i]; if (list_empty(&clock_reg_cache_list)) register_syscore(&samsung_clk_syscore); reg_cache->reg_base = reg_base; reg_cache->sysreg = sysreg; - reg_cache->rd_num = nr_rdump; reg_cache->rsuspend = rsuspend; reg_cache->rsuspend_num = nr_rsuspend; list_add_tail(®_cache->node, &clock_reg_cache_list); diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index b1192ca03db5..be733eba08a2 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -324,10 +324,10 @@ struct samsung_clock_reg_cache { struct list_head node; void __iomem *reg_base; struct regmap *sysreg; - struct samsung_clk_reg_dump *rdump; - unsigned int rd_num; const struct samsung_clk_reg_dump *rsuspend; unsigned int rsuspend_num; + unsigned int rd_num; + struct samsung_clk_reg_dump rdump[] __counted_by(rd_num); }; /** From 421ccea8f872c0e7cf6fd754a4a3bef4f45cf2dc Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 28 Jun 2026 20:25:39 -0700 Subject: [PATCH 5/6] clk: samsung: cpu: use kzalloc_flex Use a flexible array member to combine allocations. As kmemdup_array is really kcalloc + memcpy and kzalloc_flex kzalloc + kcalloc, kzalloc and kcalloc combine leaving the memcpy. Add __counted_by for extra runtime analysis. Remove fake const num_cfgs. It needs to be assigned for __counted_by to work. Signed-off-by: Rosen Penev Link: https://patch.msgid.link/20260629032540.2331559-3-rosenp@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-cpu.c | 34 ++++++++++++++-------------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index ffc33e5decf5..37cf47533dc6 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -101,11 +101,11 @@ struct exynos_cpuclk { const struct clk_hw *alt_parent; void __iomem *base; spinlock_t *lock; - const struct exynos_cpuclk_cfg_data *cfg; - const unsigned long num_cfgs; + unsigned long num_cfgs; struct notifier_block clk_nb; unsigned long flags; const struct exynos_cpuclk_chip *chip; + struct exynos_cpuclk_cfg_data cfg[] __counted_by(num_cfgs); }; /* ---- Common code --------------------------------------------------------- */ @@ -660,10 +660,6 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, return -EINVAL; } - cpuclk = kzalloc_obj(*cpuclk); - if (!cpuclk) - return -ENOMEM; - parent_name = clk_hw_get_name(parent); init.name = clk_data->name; @@ -672,6 +668,17 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, init.num_parents = 1; init.ops = &exynos_cpuclk_clk_ops; + /* Find count of configuration rates in cfg */ + for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; ) + num_cfgs++; + + cpuclk = kzalloc_flex(*cpuclk, cfg, num_cfgs); + if (!cpuclk) + return -ENOMEM; + + cpuclk->num_cfgs = num_cfgs; + + memcpy(cpuclk->cfg, clk_data->cfg, num_cfgs * sizeof(*cpuclk->cfg)); cpuclk->alt_parent = alt_parent; cpuclk->hw.init = &init; cpuclk->base = ctx->reg_base + clk_data->offset; @@ -687,29 +694,16 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, goto free_cpuclk; } - /* Find count of configuration rates in cfg */ - for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; ) - num_cfgs++; - - cpuclk->cfg = kmemdup_array(clk_data->cfg, num_cfgs, sizeof(*cpuclk->cfg), - GFP_KERNEL); - if (!cpuclk->cfg) { - ret = -ENOMEM; - goto unregister_clk_nb; - } - ret = clk_hw_register(NULL, &cpuclk->hw); if (ret) { pr_err("%s: could not register cpuclk %s\n", __func__, clk_data->name); - goto free_cpuclk_data; + goto unregister_clk_nb; } samsung_clk_add_lookup(ctx, &cpuclk->hw, clk_data->id); return 0; -free_cpuclk_data: - kfree(cpuclk->cfg); unregister_clk_nb: clk_notifier_unregister(parent->clk, &cpuclk->clk_nb); free_cpuclk: From 6d32ae6403694035896cbf0436088fca4c6a35f1 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Sun, 28 Jun 2026 20:25:40 -0700 Subject: [PATCH 6/6] clk: samsung: pll: use kzalloc_flex Simplify allocation by using a flexible array member to combine allocations and remove a kfree. Use __counted_by for extra runtime analysis. Since rate_table is now a flexible array member, NULL checks don't work. So use the counting variable to check allocation. Signed-off-by: Rosen Penev Link: https://patch.msgid.link/20260629032540.2331559-4-rosenp@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-pll.c | 56 ++++++++++++++++------------------- 1 file changed, 26 insertions(+), 30 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index fdb84bcec912..e74552846ba3 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -28,7 +28,7 @@ struct samsung_clk_pll { unsigned short lock_offs; enum samsung_pll_type type; unsigned int rate_count; - const struct samsung_pll_rate_table *rate_table; + struct samsung_pll_rate_table rate_table[] __counted_by(rate_count); }; #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) @@ -1593,35 +1593,32 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, { struct samsung_clk_pll *pll; struct clk_init_data init; - int ret, len; + unsigned int len = 0; + int ret; - pll = kzalloc_obj(*pll); + if (pll_clk->rate_table) { + /* find count of rates in rate_table */ + while (pll_clk->rate_table[len].rate != 0) + len++; + } + + pll = kzalloc_flex(*pll, rate_table, len); if (!pll) { pr_err("%s: could not allocate pll clk %s\n", __func__, pll_clk->name); return; } + pll->rate_count = len; + if (len) + memcpy(pll->rate_table, pll_clk->rate_table, + len * sizeof(*pll->rate_table)); + init.name = pll_clk->name; init.flags = pll_clk->flags; init.parent_names = &pll_clk->parent_name; init.num_parents = 1; - if (pll_clk->rate_table) { - /* find count of rates in rate_table */ - for (len = 0; pll_clk->rate_table[len].rate != 0; ) - len++; - - pll->rate_count = len; - pll->rate_table = kmemdup_array(pll_clk->rate_table, - pll->rate_count, - sizeof(*pll->rate_table), - GFP_KERNEL); - WARN(!pll->rate_table, - "%s: could not allocate rate table for %s\n", - __func__, pll_clk->name); - } - switch (pll_clk->type) { case pll_2126: init.ops = &samsung_pll2126_clk_ops; @@ -1640,7 +1637,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_a9fracm: pll->enable_offs = PLL35XX_ENABLE_SHIFT; pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll35xx_clk_min_ops; else init.ops = &samsung_pll35xx_clk_ops; @@ -1659,7 +1656,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_0732x: pll->enable_offs = PLL0822X_ENABLE_SHIFT; pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll0822x_clk_min_ops; else init.ops = &samsung_pll0822x_clk_ops; @@ -1669,7 +1666,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, break; case pll_4502: case pll_4508: - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll45xx_clk_min_ops; else init.ops = &samsung_pll45xx_clk_ops; @@ -1679,7 +1676,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_2650: pll->enable_offs = PLL36XX_ENABLE_SHIFT; pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll36xx_clk_min_ops; else init.ops = &samsung_pll36xx_clk_ops; @@ -1687,7 +1684,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_0831x: pll->enable_offs = PLL0831X_ENABLE_SHIFT; pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll0831x_clk_min_ops; else init.ops = &samsung_pll0831x_clk_ops; @@ -1703,7 +1700,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_4650: case pll_4650c: case pll_1460x: - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll46xx_clk_min_ops; else init.ops = &samsung_pll46xx_clk_ops; @@ -1712,19 +1709,19 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll2550x_clk_ops; break; case pll_2550xx: - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll2550xx_clk_min_ops; else init.ops = &samsung_pll2550xx_clk_ops; break; case pll_2650x: - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll2650x_clk_min_ops; else init.ops = &samsung_pll2650x_clk_ops; break; case pll_2650xx: - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll2650xx_clk_min_ops; else init.ops = &samsung_pll2650xx_clk_ops; @@ -1734,7 +1731,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll531x_clk_ops; break; case pll_1031x: - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_pll1031x_clk_min_ops; else init.ops = &samsung_pll1031x_clk_ops; @@ -1742,7 +1739,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_a9fraco: pll->enable_offs = PLLA9FRACO_ENABLE_SHIFT; pll->lock_offs = PLLA9FRACO_LOCK_STAT_SHIFT; - if (!pll->rate_table) + if (!pll->rate_count) init.ops = &samsung_a9fraco_clk_min_ops; else init.ops = &samsung_a9fraco_clk_ops; @@ -1761,7 +1758,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, if (ret) { pr_err("%s: failed to register pll clock %s : %d\n", __func__, pll_clk->name, ret); - kfree(pll->rate_table); kfree(pll); return; }