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arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function

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First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com
This commit is contained in:
Kishon Vijay Abraham I 2020-09-30 15:20:31 +03:00 committed by Nishanth Menon
parent 6197d7139d
commit e38a45b019
1 changed files with 6 additions and 0 deletions
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6
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
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@ -7,6 +7,7 @@
#include "k3-j7200-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/mux/ti-serdes.h>
/ {
chosen {
@ -185,3 +186,8 @@ &main_sdhci1 {
ti,driver-strength-ohm = <50>;
disable-wp;
};
&serdes_ln_ctrl {
idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
};