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PCI: loongson: Override PCIe bridge supported speeds for Loongson-3C6000 series

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Older steppings of the Loongson-3C6000 series incorrectly report the
supported link speeds on their PCIe bridges (device IDs 0x3c19, 0x3c29)
as only 2.5 GT/s, despite the upstream bus supporting speeds from
2.5 GT/s up to 16 GT/s.

As a result, since commit 774c71c52a ("PCI/bwctrl: Enable only if more
than one speed is supported"), bwctrl will be disabled if there's only
one 2.5 GT/s value in vector 'supported_speeds'.

Manually override the 'supported_speeds' field for affected PCIe bridges
with those found on the upstream bus to correctly reflect the supported
link speeds.  Updating the speeds to reflect what the hardware actually
supports avoids quirks in drivers consuming the speed information.

This commit was originally found from AOSC OS[1].

Fixes: cd89edda40 ("PCI: loongson: Add ACPI init support")
Signed-off-by: Ayden Meng <aydenmeng@yeah.net>
Signed-off-by: Mingcong Bai <jeffbai@aosc.io>
[Ziyao Li: move from drivers/pci/quirks.c to drivers/pci/controller/pci-loongson.c]
Signed-off-by: Ziyao Li <liziyao@uniontech.com>
[Xi Ruoyao: Fixed falling through logic, added debug log, Fixes tag and rebased to 7.0-rc7]
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: commit log, https://lore.kernel.org/all/9d815df3b33a63223112b97440c01247935363c1.camel@xry111.site]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Lain Fearyncess Yang <fsf@live.com>
Tested-by: Ayden Meng <aydenmeng@yeah.net>
Tested-by: Mingcong Bai <jeffbai@aosc.io>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Cc: stable@vger.kernel.org
Link: 4392f44136
Link: https://github.com/AOSC-Tracking/linux/pull/2 #1
Link: https://patch.msgid.link/20260412101731.107059-1-xry111@xry111.site
This commit is contained in:
Ziyao Li 2026-04-12 18:17:31 +08:00 committed by Bjorn Helgaas
parent 1389ab9bf9
commit e373c789ba
1 changed files with 36 additions and 0 deletions
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36
drivers/pci/controller/pci-loongson.c
View File

@ -177,6 +177,42 @@ static void loongson_pci_msi_quirk(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, DEV_LS7A_PCIE_PORT5, loongson_pci_msi_quirk);
/*
* Older steppings of the Loongson-3C6000 series incorrectly report the
* supported link speeds on their PCIe bridges (device IDs 0x3c19,
* 0x3c29) as only 2.5 GT/s, despite the upstream bus supporting speeds
* from 2.5 GT/s up to 16 GT/s.
*/
static void loongson_pci_bridge_speed_quirk(struct pci_dev *pdev)
{
u8 old_supported_speeds = pdev->supported_speeds;
switch (pdev->bus->max_bus_speed) {
case PCIE_SPEED_16_0GT:
pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_16_0GB;
fallthrough;
case PCIE_SPEED_8_0GT:
pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_8_0GB;
fallthrough;
case PCIE_SPEED_5_0GT:
pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_5_0GB;
fallthrough;
case PCIE_SPEED_2_5GT:
pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_2_5GB;
break;
default:
pci_warn(pdev, "unexpected max bus speed");
return;
}
if (pdev->supported_speeds != old_supported_speeds)
pci_info(pdev, "fixed up supported link speeds: 0x%x => 0x%x",
old_supported_speeds, pdev->supported_speeds);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, loongson_pci_bridge_speed_quirk);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, loongson_pci_bridge_speed_quirk);
static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus)
{
struct pci_config_window *cfg;