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phy: phy-snps-eusb2: refactor reference clock init

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Instead of matching frequencies with a switch and case, introduce
a table-based lookup. This improves readability, reduces redundancy,
and makes it easier to extend support for additional frequencies in
the future.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250504144527.1723980-9-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Ivaylo Ivanov 2025-05-04 17:45:25 +03:00 committed by Vinod Koul
parent aba7a966b5
commit e36a5d1ecc
1 changed files with 32 additions and 29 deletions
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61
drivers/phy/phy-snps-eusb2.c
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@ -192,44 +192,47 @@ static void qcom_eusb2_default_parameters(struct snps_eusb2_hsphy *phy)
FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0));
}
struct snps_eusb2_ref_clk {
unsigned long freq;
u32 fsel_val;
u32 div_7_0_val;
u32 div_11_8_val;
};
static const struct snps_eusb2_ref_clk qcom_eusb2_ref_clk[] = {
{ 19200000, FSEL_19_2_MHZ_VAL, DIV_7_0_19_2_MHZ_VAL, DIV_11_8_19_2_MHZ_VAL },
{ 38400000, FSEL_38_4_MHZ_VAL, DIV_7_0_38_4_MHZ_VAL, DIV_11_8_38_4_MHZ_VAL },
};
static int qcom_eusb2_ref_clk_init(struct snps_eusb2_hsphy *phy)
{
const struct snps_eusb2_ref_clk *config = NULL;
unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk);
switch (ref_clk_freq) {
case 19200000:
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0,
FSEL_MASK,
FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL));
for (int i = 0; i < ARRAY_SIZE(qcom_eusb2_ref_clk); i++) {
if (qcom_eusb2_ref_clk[i].freq == ref_clk_freq) {
config = &qcom_eusb2_ref_clk[i];
break;
}
}
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_2,
PHY_CFG_PLL_FB_DIV_7_0_MASK,
DIV_7_0_19_2_MHZ_VAL);
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3,
PHY_CFG_PLL_FB_DIV_11_8_MASK,
DIV_11_8_19_2_MHZ_VAL);
break;
case 38400000:
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0,
FSEL_MASK,
FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL));
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_2,
PHY_CFG_PLL_FB_DIV_7_0_MASK,
DIV_7_0_38_4_MHZ_VAL);
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3,
PHY_CFG_PLL_FB_DIV_11_8_MASK,
DIV_11_8_38_4_MHZ_VAL);
break;
default:
if (!config) {
dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
return -EINVAL;
}
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_HS_PHY_CTRL_COMMON0,
FSEL_MASK,
FIELD_PREP(FSEL_MASK, config->fsel_val));
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_2,
PHY_CFG_PLL_FB_DIV_7_0_MASK,
config->div_7_0_val);
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3,
PHY_CFG_PLL_FB_DIV_11_8_MASK,
config->div_11_8_val);
snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_3,
PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL);