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ARM: dts: aspeed-g6: Enable more UART controllers

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Setup the configuration of UART6, UART7, UART8, and UART9 in
aspeed-g6.dtsi.

Signed-off-by: Ken Chen <j220584470k@gmail.com>
Link: https://lore.kernel.org/r/20220805090957.470434-1-j220584470k@gmail.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Ken Chen 2022-08-05 17:09:57 +08:00 committed by Joel Stanley
parent 3d50a89cb2
commit e360b84c33
1 changed files with 56 additions and 0 deletions
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56
arch/arm/boot/dts/aspeed-g6.dtsi
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@ -756,6 +756,62 @@ uart4: serial@1e78f000 {
status = "disabled";
};
uart6: serial@1e790000 {
compatible = "ns16550a";
reg = <0x1e790000 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6_default>;
status = "disabled";
};
uart7: serial@1e790100 {
compatible = "ns16550a";
reg = <0x1e790100 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7_default>;
status = "disabled";
};
uart8: serial@1e790200 {
compatible = "ns16550a";
reg = <0x1e790200 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8_default>;
status = "disabled";
};
uart9: serial@1e790300 {
compatible = "ns16550a";
reg = <0x1e790300 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart9_default>;
status = "disabled";
};
i2c: bus@1e78a000 {
compatible = "simple-bus";
#address-cells = <1>;