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drm/amdkfd: enable rs64mem for kfd queue
Enabled RS64mem for KFD queues by integrating process and gang context index allocation in the per KFD device process and queue creation. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Michael Chen <michael.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
08bb824ae3
commit
e32b68c6b1
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@ -226,8 +226,10 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
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/* MES unit for quantum is 100ns */
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queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */
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queue_input.process_context_addr = pdd->proc_ctx_gpu_addr;
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queue_input.process_context_array_index = pdd->proc_ctx_array_index;
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queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */
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queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
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queue_input.gang_context_array_index = q->gang_ctx_array_index;
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queue_input.inprocess_gang_priority = q->properties.priority;
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queue_input.gang_global_priority_level =
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AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
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@ -303,6 +305,7 @@ static int remove_queue_mes_on_reset_option(struct device_queue_manager *dqm, st
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queue_input.queue_type = convert_to_amdgpu_ring_type(q->properties.type);
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queue_input.remove_queue_after_reset = flush_mes_queue;
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queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1;
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queue_input.gang_context_array_index = q->gang_ctx_array_index;
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amdgpu_mes_lock(&adev->mes);
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r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
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@ -635,6 +635,7 @@ struct queue {
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void *gang_ctx_bo;
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uint64_t gang_ctx_gpu_addr;
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void *gang_ctx_cpu_ptr;
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uint32_t gang_ctx_array_index;
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struct amdgpu_bo *wptr_bo_gart;
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};
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@ -871,6 +872,8 @@ struct kfd_process_device {
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uint64_t proc_ctx_gpu_addr;
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void *proc_ctx_cpu_ptr;
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uint32_t proc_ctx_array_index;
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/* Tracks queue reset status */
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bool has_reset_queue;
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@ -1215,9 +1215,12 @@ static void kfd_process_destroy_pdds(struct kfd_process *p)
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kfd_free_process_doorbells(pdd->dev->kfd, pdd);
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if (pdd->dev->kfd->shared_resources.enable_mes &&
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pdd->proc_ctx_cpu_ptr)
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pdd->proc_ctx_cpu_ptr) {
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amdgpu_mes_free_proc_ctx_index(&pdd->dev->adev->mes,
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pdd->proc_ctx_array_index);
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amdgpu_amdkfd_free_kernel_mem(pdd->dev->adev,
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&pdd->proc_ctx_bo);
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}
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/*
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* before destroying pdd, make sure to report availability
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* for auto suspend
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@ -210,6 +210,7 @@ static void pqm_clean_queue_resource(struct process_queue_manager *pqm,
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}
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if (dev->kfd->shared_resources.enable_mes) {
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amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, pqn->q->gang_ctx_array_index);
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amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo);
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amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart);
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}
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@ -282,7 +283,15 @@ static int init_user_queue(struct process_queue_manager *pqm,
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goto cleanup;
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}
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memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE);
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/* Bind one MES gang context slot per queue (gang). */
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if (dev->adev->mes.use_rs64mem) {
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retval = amdgpu_mes_alloc_gang_ctx_index(&dev->adev->mes,
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&(*q)->gang_ctx_array_index);
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if (retval) {
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pr_err("failed to allocate gang context index slot\n");
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goto cleanup;
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}
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}
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/* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
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* on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
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*/
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@ -304,6 +313,7 @@ static int init_user_queue(struct process_queue_manager *pqm,
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return 0;
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free_gang_ctx_bo:
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amdgpu_mes_free_gang_ctx_index(&dev->adev->mes, (*q)->gang_ctx_array_index);
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amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo);
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cleanup:
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uninit_queue(*q);
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@ -386,6 +396,17 @@ int pqm_create_queue(struct process_queue_manager *pqm,
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goto err_allocate_pqn;
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}
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memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE);
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/* Bind one MES process context slot to the whole process
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* (per device); every queue of this process reuses it.
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*/
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if (dev->adev->mes.use_rs64mem) {
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retval = amdgpu_mes_alloc_proc_ctx_index(&dev->adev->mes,
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&pdd->proc_ctx_array_index);
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if (retval) {
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dev_err(dev->adev->dev, "failed to allocate process context index\n");
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goto err_allocate_pqn;
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}
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}
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}
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pqn = kzalloc_obj(*pqn);
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