From e3203a81238d59833adfe551ccad929245a1ea92 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 3 Jun 2026 15:33:36 +0100 Subject: [PATCH] arm64: dts: renesas: r9a09g047: Add max-frequency to SDHI nodes Add max-frequency properties of 200MHz to the sdhi0, sdhi1, and sdhi2 MMC controllers in the R9A09G047 SoC DTSI to define the maximum supported bus frequency. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260603143340.162457-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index be11cdde3cfe..cf3f77e5551a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -1281,6 +1281,7 @@ sdhi0: mmc@15c00000 { clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa7>; power-domains = <&cpg>; status = "disabled"; @@ -1301,6 +1302,7 @@ sdhi1: mmc@15c10000 { clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa8>; power-domains = <&cpg>; status = "disabled"; @@ -1321,6 +1323,7 @@ sdhi2: mmc@15c20000 { clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa9>; power-domains = <&cpg>; status = "disabled";