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arm64: dts: sprd: reorder clock-names after clocks

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DT convention is to have property-names after property.
While at it, cleanup indentation for some clocks.
No functional change.

Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com>
Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com>
Link: https://lore.kernel.org/r/13ea4a27f0d1428a925a6f817f9370673eaec938.1722842067.git.stano.jakubek@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Stanislav Jakubek 2024-08-05 09:24:35 +02:00 committed by Krzysztof Kozlowski
parent 0dcc203956
commit e2e0d4554d
3 changed files with 25 additions and 21 deletions
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4
arch/arm64/boot/dts/sprd/sc9863a.dtsi
View File

@ -556,9 +556,9 @@ sdio0: mmc@20300000 {
reg = <0 0x20300000 0 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable";
clocks = <&aon_clk CLK_SDIO0_2X>,
<&apahb_gate CLK_SDIO0_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&aon_clk CLK_SDIO0_2X>;
assigned-clock-parents = <&rpll CLK_RPLL_390M>;
@ -572,9 +572,9 @@ sdio3: mmc@20600000 {
reg = <0 0x20600000 0 0x1000>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable";
clocks = <&aon_clk CLK_EMMC_2X>,
<&apahb_gate CLK_EMMC_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&aon_clk CLK_EMMC_2X>;
assigned-clock-parents = <&rpll CLK_RPLL_390M>;

4
arch/arm64/boot/dts/sprd/ums512.dtsi
View File

@ -849,9 +849,9 @@ sdio0: mmc@1100000 {
compatible = "sprd,sdhci-r11";
reg = <0x1100000 0x1000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable";
clocks = <&ap_clk CLK_SDIO0_2X>,
<&apapb_gate CLK_SDIO0_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&ap_clk CLK_SDIO0_2X>;
assigned-clock-parents = <&pll1 CLK_RPLL>;
status = "disabled";
@ -861,9 +861,9 @@ sdio3: mmc@1400000 {
compatible = "sprd,sdhci-r11";
reg = <0x1400000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable";
clocks = <&ap_clk CLK_EMMC_2X>,
<&apapb_gate CLK_EMMC_EB>;
clock-names = "sdio", "enable";
assigned-clocks = <&ap_clk CLK_EMMC_2X>;
assigned-clock-parents = <&pll1 CLK_RPLL>;
status = "disabled";

38
arch/arm64/boot/dts/sprd/whale2.dtsi
View File

@ -75,9 +75,10 @@ uart0: serial@0 {
"sprd,sc9836-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "enable", "uart", "source";
clocks = <&apapb_gate CLK_UART0_EB>,
<&ap_clk CLK_UART0>, <&ext_26m>;
<&ap_clk CLK_UART0>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
@ -86,9 +87,10 @@ uart1: serial@100000 {
"sprd,sc9836-uart";
reg = <0x100000 0x100>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "enable", "uart", "source";
clocks = <&apapb_gate CLK_UART1_EB>,
<&ap_clk CLK_UART1>, <&ext_26m>;
<&ap_clk CLK_UART1>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
@ -97,9 +99,10 @@ uart2: serial@200000 {
"sprd,sc9836-uart";
reg = <0x200000 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "enable", "uart", "source";
clocks = <&apapb_gate CLK_UART2_EB>,
<&ap_clk CLK_UART2>, <&ext_26m>;
<&ap_clk CLK_UART2>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
@ -108,9 +111,10 @@ uart3: serial@300000 {
"sprd,sc9836-uart";
reg = <0x300000 0x100>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "enable", "uart", "source";
clocks = <&apapb_gate CLK_UART3_EB>,
<&ap_clk CLK_UART3>, <&ext_26m>;
<&ap_clk CLK_UART3>,
<&ext_26m>;
clock-names = "enable", "uart", "source";
status = "disabled";
};
};
@ -129,8 +133,8 @@ ap_dma: dma-controller@20100000 {
/* For backwards compatibility: */
#dma-channels = <32>;
dma-channels = <32>;
clock-names = "enable";
clocks = <&apahb_gate CLK_DMA_EB>;
clock-names = "enable";
};
sdio3: mmc@50430000 {
@ -138,10 +142,10 @@ sdio3: mmc@50430000 {
reg = <0 0x50430000 0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "sdio", "enable", "2x_enable";
clocks = <&aon_prediv CLK_EMMC_2X>,
<&apahb_gate CLK_EMMC_EB>,
<&aon_gate CLK_EMMC_2X_EN>;
<&apahb_gate CLK_EMMC_EB>,
<&aon_gate CLK_EMMC_2X_EN>;
clock-names = "sdio", "enable", "2x_enable";
assigned-clocks = <&aon_prediv CLK_EMMC_2X>;
assigned-clock-parents = <&clk_l0_409m6>;
@ -194,8 +198,8 @@ hwlock: hwspinlock@40500000 {
compatible = "sprd,hwspinlock-r3p0";
reg = <0 0x40500000 0 0x1000>;
#hwlock-cells = <1>;
clock-names = "enable";
clocks = <&aon_gate CLK_SPLK_EB>;
clock-names = "enable";
};
eic_debounce: gpio@40210000 {
@ -258,9 +262,9 @@ watchdog@40310000 {
reg = <0 0x40310000 0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <12>;
clock-names = "enable", "rtc_enable";
clocks = <&aon_gate CLK_APCPU_WDG_EB>,
<&aon_gate CLK_AP_WDG_RTC_EB>;
<&aon_gate CLK_AP_WDG_RTC_EB>;
clock-names = "enable", "rtc_enable";
};
};
@ -277,9 +281,9 @@ agcp_dma: dma-controller@41580000 {
/* For backwards compatibility: */
#dma-channels = <32>;
dma-channels = <32>;
clock-names = "enable", "ashb_eb";
clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>,
<&agcp_gate CLK_AGCP_AP_ASHB_EB>;
<&agcp_gate CLK_AGCP_AP_ASHB_EB>;
clock-names = "enable", "ashb_eb";
};
};
};