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drm/i915/edram: extract i915_edram.[ch] for edram detection

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While edram detection ostensibly belongs with the rest of the dram stuff
in soc/intel_dram.c, it's only required by i915 core, not
display. Extract it to a separate i915_edram.[ch] file.

This allows us to drop the edram_size_mb member from struct xe_device.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/612edb7b70755655fbf193ba8af1c539fb93b698.1763578288.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2025-11-19 20:52:40 +02:00
parent e4c8fde0bf
commit e2b1c3a127
7 changed files with 58 additions and 44 deletions
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1
drivers/gpu/drm/i915/Makefile
View File

@ -27,6 +27,7 @@ i915-y += \
i915_config.o \
i915_driver.o \
i915_drm_client.o \
i915_edram.o \
i915_getparam.o \
i915_ioctl.o \
i915_irq.o \

3
drivers/gpu/drm/i915/i915_driver.c
View File

@ -94,6 +94,7 @@
#include "i915_driver.h"
#include "i915_drm_client.h"
#include "i915_drv.h"
#include "i915_edram.h"
#include "i915_file_private.h"
#include "i915_getparam.h"
#include "i915_hwmon.h"
@ -493,7 +494,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
}
/* needs to be done before ggtt probe */
intel_dram_edram_detect(dev_priv);
i915_edram_detect(dev_priv);
ret = i915_set_dma_info(dev_priv);
if (ret)

44
drivers/gpu/drm/i915/i915_edram.c Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: MIT
/* Copyright © 2025 Intel Corporation */
#include <drm/drm_print.h>
#include "i915_drv.h"
#include "i915_edram.h"
#include "i915_reg.h"
static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
{
static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
static const u8 sets[4] = { 1, 1, 2, 2 };
return EDRAM_NUM_BANKS(cap) *
ways[EDRAM_WAYS_IDX(cap)] *
sets[EDRAM_SETS_IDX(cap)];
}
void i915_edram_detect(struct drm_i915_private *i915)
{
u32 edram_cap = 0;
if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
return;
edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);
/* NB: We can't write IDICR yet because we don't have gt funcs set up */
if (!(edram_cap & EDRAM_ENABLED))
return;
/*
* The needed capability bits for size calculation are not there with
* pre gen9 so return 128MB always.
*/
if (GRAPHICS_VER(i915) < 9)
i915->edram_size_mb = 128;
else
i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);
}

11
drivers/gpu/drm/i915/i915_edram.h Normal file
View File

@ -0,0 +1,11 @@
/* SPDX-License-Identifier: MIT */
/* Copyright © 2025 Intel Corporation */
#ifndef __I915_DRAM_H__
#define __I915_DRAM_H__
struct drm_i915_private;
void i915_edram_detect(struct drm_i915_private *i915);
#endif /* __I915_DRAM_H__ */

36
drivers/gpu/drm/i915/soc/intel_dram.c
View File

@ -861,39 +861,3 @@ const struct dram_info *intel_dram_info(struct drm_device *drm)
return i915->dram_info;
}
static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
{
static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
static const u8 sets[4] = { 1, 1, 2, 2 };
return EDRAM_NUM_BANKS(cap) *
ways[EDRAM_WAYS_IDX(cap)] *
sets[EDRAM_SETS_IDX(cap)];
}
void intel_dram_edram_detect(struct drm_i915_private *i915)
{
u32 edram_cap = 0;
if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
return;
edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);
/* NB: We can't write IDICR yet because we don't have gt funcs set up */
if (!(edram_cap & EDRAM_ENABLED))
return;
/*
* The needed capability bits for size calculation are not there with
* pre gen9 so return 128MB always.
*/
if (GRAPHICS_VER(i915) < 9)
i915->edram_size_mb = 128;
else
i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);
}

1
drivers/gpu/drm/i915/soc/intel_dram.h
View File

@ -35,7 +35,6 @@ struct dram_info {
bool has_16gb_dimms;
};
void intel_dram_edram_detect(struct drm_i915_private *i915);
int intel_dram_detect(struct drm_i915_private *i915);
unsigned int intel_fsb_freq(struct drm_i915_private *i915);
unsigned int intel_mem_freq(struct drm_i915_private *i915);

6
drivers/gpu/drm/xe/xe_device_types.h
View File

@ -639,12 +639,6 @@ struct xe_device {
*/
const struct dram_info *dram_info;
/*
* edram size in MB.
* Cannot be determined by PCIID. You must always read a register.
*/
u32 edram_size_mb;
struct intel_uncore {
spinlock_t lock;
} uncore;