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clk: qcom: ipq9650: Add clocks for the REFGEN block

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Add the clocks required to enable the REFGEN block which provides the
reference current to the PHYs in the SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260707-b4-ipq9650_refgen_clocks-v1-2-e070624d03d2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Kathiravan Thirumoorthy 2026-07-07 12:25:24 +05:30 committed by Bjorn Andersson
parent b14992f796
commit e27e02fff4
1 changed files with 89 additions and 0 deletions
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89
drivers/clk/qcom/gcc-ipq9650.c
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@ -3022,6 +3022,90 @@ static struct clk_branch gcc_usb1_sleep_clk = {
},
};
static struct clk_rcg2 gcc_refgen_core_clk_src = {
.cmd_rcgr = 0x23004,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_nss_ts_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_core_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
static struct clk_branch gcc_refgen_cmn_uphy_core_clk = {
.halt_reg = 0x2300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x2300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_cmn_uphy_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_refgen_core_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_refgen_pcie_core_clk = {
.halt_reg = 0x23020,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x23020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_pcie_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_refgen_core_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_refgen_pcie_hclk = {
.halt_reg = 0x23024,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x23024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_pcie_hclk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_refgen_cmn_uphy_hclk = {
.halt_reg = 0x23010,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x23010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_refgen_cmn_uphy_hclk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcnoc_bfdcd_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *gcc_ipq9650_clocks[] = {
[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
@ -3179,6 +3263,11 @@ static struct clk_regmap *gcc_ipq9650_clocks[] = {
[GPLL2] = &gpll2.clkr,
[GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
[GPLL4] = &gpll4.clkr,
[GCC_REFGEN_CORE_CLK_SRC] = &gcc_refgen_core_clk_src.clkr,
[GCC_REFGEN_PCIE_CORE_CLK] = &gcc_refgen_pcie_core_clk.clkr,
[GCC_REFGEN_PCIE_HCLK] = &gcc_refgen_pcie_hclk.clkr,
[GCC_REFGEN_CMN_UPHY_HCLK] = &gcc_refgen_cmn_uphy_hclk.clkr,
[GCC_REFGEN_CMN_UPHY_CORE_CLK] = &gcc_refgen_cmn_uphy_core_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq9650_resets[] = {