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KVM VMX changes for 7.2

Browse Source 
- Fix a largely benign bug where KVM TDX would incorrectly state it could
    emulate several x2APIC MSRs.
 
  - Use the "safe" WRMSR API when proxying LBR MSR writes as the to-be-written
    value is guest controlled and completely unvalidated.
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Merge tag 'kvm-x86-vmx-7.2' of https://github.com/kvm-x86/linux into HEAD

KVM VMX changes for 7.2

 - Fix a largely benign bug where KVM TDX would incorrectly state it could
   emulate several x2APIC MSRs.

 - Use the "safe" WRMSR API when proxying LBR MSR writes as the to-be-written
   value is guest controlled and completely unvalidated.
This commit is contained in:
Paolo Bonzini 2026-06-12 10:15:13 +02:00
commit e25db15a7f
2 changed files with 26 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/x86/kvm/vmx/pmu_intel.c
View File

@ -316,13 +316,15 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
*/
local_irq_disable();
if (lbr_desc->event->state == PERF_EVENT_STATE_ACTIVE) {
int err = 0;
if (read)
rdmsrq(index, msr_info->data);
else
wrmsrq(index, msr_info->data);
err = wrmsrq_safe(index, msr_info->data);
__set_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
local_irq_enable();
return true;
return !err;
}
clear_bit(INTEL_PMC_IDX_FIXED_VLBR, vcpu_to_pmu(vcpu)->pmc_in_use);
local_irq_enable();

38
arch/x86/kvm/vmx/tdx.c
View File

@ -2192,23 +2192,29 @@ bool tdx_has_emulated_msr(u32 index)
case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
/* MSR_IA32_MCx_{CTL, STATUS, ADDR, MISC, CTL2} */
case MSR_KVM_POLL_CONTROL:
/*
* Except for x2APIC registers that are virtualized by the CPU, which
* KVM can't emulate as KVM doesn't have access to the virtual APIC
* page, KVM emulates the same set of x2APIC registers for TDX versus
* non-TDX guests.
*/
case X2APIC_MSR(APIC_ID):
case X2APIC_MSR(APIC_LVR):
case X2APIC_MSR(APIC_LDR):
case X2APIC_MSR(APIC_SPIV):
case X2APIC_MSR(APIC_ESR):
case X2APIC_MSR(APIC_LVTCMCI):
case X2APIC_MSR(APIC_ICR):
case X2APIC_MSR(APIC_LVTT):
case X2APIC_MSR(APIC_LVTTHMR):
case X2APIC_MSR(APIC_LVTPC):
case X2APIC_MSR(APIC_LVT0):
case X2APIC_MSR(APIC_LVT1):
case X2APIC_MSR(APIC_LVTERR):
case X2APIC_MSR(APIC_TMICT):
case X2APIC_MSR(APIC_TMCCT):
case X2APIC_MSR(APIC_TDCR):
return true;
case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
/*
* x2APIC registers that are virtualized by the CPU can't be
* emulated, KVM doesn't have access to the virtual APIC page.
*/
switch (index) {
case X2APIC_MSR(APIC_TASKPRI):
case X2APIC_MSR(APIC_PROCPRI):
case X2APIC_MSR(APIC_EOI):
case X2APIC_MSR(APIC_ISR) ... X2APIC_MSR(APIC_ISR + APIC_ISR_NR):
case X2APIC_MSR(APIC_TMR) ... X2APIC_MSR(APIC_TMR + APIC_ISR_NR):
case X2APIC_MSR(APIC_IRR) ... X2APIC_MSR(APIC_IRR + APIC_ISR_NR):
return false;
default:
return true;
}
default:
return false;
}