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arm64: dts: ti: k3-j721s2-ti-ipc-firmware: Refactor IPC cfg into new dtsi
The TI K3 J721S2 SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J721S2 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Link: https://patch.msgid.link/20250908142826.1828676-27-b-padhi@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Beleswar Padhi
Nishanth Menon
parent
20ca55168b
commit
e2581d3e07
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@ -60,96 +60,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 {
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reg = <0x00 0xa0100000 0x00 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core0_dma_memory_region: memory@a4000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core0_memory_region: memory@a4100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core1_dma_memory_region: memory@a5000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core1_memory_region: memory@a5100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5100000 0x00 0xf00000>;
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no-map;
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};
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c71_0_dma_memory_region: memory@a6000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6000000 0x00 0x100000>;
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no-map;
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};
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c71_0_memory_region: memory@a6100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6100000 0x00 0xf00000>;
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no-map;
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};
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c71_1_dma_memory_region: memory@a7000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7000000 0x00 0x100000>;
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no-map;
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};
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c71_1_memory_region: memory@a7100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: memory@a8000000 {
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reg = <0x00 0xa8000000 0x00 0x01c00000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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vdd_sd_dv: regulator-sd {
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@ -243,80 +153,6 @@ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27) WKUP_I2C0_SDA */
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};
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};
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&c71_0 {
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mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
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memory-region = <&c71_0_dma_memory_region>,
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<&c71_0_memory_region>;
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status = "okay";
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};
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&c71_1 {
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mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
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memory-region = <&c71_1_dma_memory_region>,
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<&c71_1_memory_region>;
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status = "okay";
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};
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&mailbox0_cluster0 {
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interrupts = <436>;
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status = "okay";
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster1 {
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interrupts = <432>;
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status = "okay";
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster2 {
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interrupts = <428>;
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status = "okay";
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mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster4 {
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interrupts = <420>;
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status = "okay";
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mbox_c71_0: mbox-c71-0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_c71_1: mbox-c71-1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&main_cpsw {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins_default>;
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@ -367,34 +203,6 @@ &main_gpio0 {
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status = "okay";
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};
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&main_r5fss0_core0 {
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mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
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memory-region = <&main_r5fss0_core0_dma_memory_region>,
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<&main_r5fss0_core0_memory_region>;
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status = "okay";
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};
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&main_r5fss0_core1 {
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mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
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memory-region = <&main_r5fss0_core1_dma_memory_region>,
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<&main_r5fss0_core1_memory_region>;
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status = "okay";
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};
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&main_r5fss1_core0 {
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mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
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memory-region = <&main_r5fss1_core0_dma_memory_region>,
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<&main_r5fss1_core0_memory_region>;
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status = "okay";
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};
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&main_r5fss1_core1 {
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mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
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memory-region = <&main_r5fss1_core1_dma_memory_region>,
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<&main_r5fss1_core1_memory_region>;
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status = "okay";
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};
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/* eMMC */
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&main_sdhci0 {
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non-removable;
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@ -409,59 +217,6 @@ &main_sdhci1 {
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bootph-all;
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};
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&main_r5fss0 {
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ti,cluster-mode = <0>;
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status = "okay";
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};
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&main_r5fss1 {
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ti,cluster-mode = <0>;
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status = "okay";
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};
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/* Timers are used by Remoteproc firmware */
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&main_timer0 {
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status = "reserved";
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};
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&main_timer1 {
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status = "reserved";
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};
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&main_timer2 {
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status = "reserved";
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};
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&main_timer3 {
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status = "reserved";
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};
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&main_timer4 {
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status = "reserved";
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};
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&main_timer5 {
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status = "reserved";
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};
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&mcu_r5fss0 {
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status = "okay";
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};
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&mcu_r5fss0_core0 {
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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status = "okay";
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};
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&mcu_r5fss0_core1 {
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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status = "okay";
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};
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&ospi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
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@ -611,3 +366,5 @@ som_eeprom_opt: eeprom@51 {
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pagesize = <32>;
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};
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};
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#include "k3-j721s2-ti-ipc-firmware.dtsi"
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@ -38,96 +38,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 {
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reg = <0x00 0xa0100000 0x00 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1000000 0x00 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa1100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core0_dma_memory_region: memory@a2000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core0_memory_region: memory@a2100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa2100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss0_core1_dma_memory_region: memory@a3000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss0_core1_memory_region: memory@a3100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa3100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core0_dma_memory_region: memory@a4000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core0_memory_region: memory@a4100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa4100000 0x00 0xf00000>;
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no-map;
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};
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main_r5fss1_core1_dma_memory_region: memory@a5000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5000000 0x00 0x100000>;
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no-map;
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};
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main_r5fss1_core1_memory_region: memory@a5100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa5100000 0x00 0xf00000>;
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no-map;
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};
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c71_0_dma_memory_region: memory@a6000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6000000 0x00 0x100000>;
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no-map;
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};
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c71_0_memory_region: memory@a6100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa6100000 0x00 0xf00000>;
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no-map;
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};
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c71_1_dma_memory_region: memory@a7000000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7000000 0x00 0x100000>;
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no-map;
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};
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c71_1_memory_region: memory@a7100000 {
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compatible = "shared-dma-pool";
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reg = <0x00 0xa7100000 0x00 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: memory@a8000000 {
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reg = <0x00 0xa8000000 0x00 0x01c00000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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};
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@ -235,153 +145,4 @@ partition@3fc0000 {
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};
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};
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&mailbox0_cluster0 {
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status = "okay";
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster1 {
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status = "okay";
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interrupts = <432>;
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mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster2 {
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status = "okay";
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interrupts = <428>;
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mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mailbox0_cluster4 {
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status = "okay";
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interrupts = <420>;
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mbox_c71_0: mbox-c71-0 {
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ti,mbox-rx = <0 0 0>;
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ti,mbox-tx = <1 0 0>;
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};
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mbox_c71_1: mbox-c71-1 {
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ti,mbox-rx = <2 0 0>;
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ti,mbox-tx = <3 0 0>;
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};
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};
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&mcu_r5fss0 {
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status = "okay";
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};
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&mcu_r5fss0_core0 {
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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status = "okay";
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};
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&mcu_r5fss0_core1 {
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
#include "k3-j721s2-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
|
|
@ -42,96 +42,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 {
|
|||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: memory@a8000000 {
|
||||
reg = <0x00 0xa8000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
mux0: mux-controller-0 {
|
||||
|
|
@ -516,157 +426,6 @@ partition@3fc0000 {
|
|||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
|
||||
&main_i2c4 {
|
||||
bridge_dsi_edp: bridge-dsi-edp@2c {
|
||||
compatible = "ti,sn65dsi86";
|
||||
|
|
@ -693,3 +452,5 @@ port@1 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "k3-j721s2-ti-ipc-firmware.dtsi"
|
||||
|
|
|
|||
253
arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi
Normal file
253
arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi
Normal file
|
|
@ -0,0 +1,253 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only OR MIT
|
||||
/**
|
||||
* Device Tree Source for enabling IPC using TI SDK firmware on J721S2 SoCs
|
||||
*
|
||||
* Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&reserved_memory {
|
||||
mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_dma_memory_region: memory@a4000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core0_memory_region: memory@a4100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa4100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_dma_memory_region: memory@a5000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss1_core1_memory_region: memory@a5100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa5100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_dma_memory_region: memory@a6000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_0_memory_region: memory@a6100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa6100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_dma_memory_region: memory@a7000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
c71_1_memory_region: memory@a7100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa7100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: memory@a8000000 {
|
||||
reg = <0x00 0xa8000000 0x00 0x01c00000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster0 {
|
||||
status = "okay";
|
||||
interrupts = <436>;
|
||||
|
||||
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster1 {
|
||||
status = "okay";
|
||||
interrupts = <432>;
|
||||
|
||||
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster2 {
|
||||
status = "okay";
|
||||
interrupts = <428>;
|
||||
|
||||
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mailbox0_cluster4 {
|
||||
status = "okay";
|
||||
interrupts = <420>;
|
||||
|
||||
mbox_c71_0: mbox-c71-0 {
|
||||
ti,mbox-rx = <0 0 0>;
|
||||
ti,mbox-tx = <1 0 0>;
|
||||
};
|
||||
|
||||
mbox_c71_1: mbox-c71-1 {
|
||||
ti,mbox-rx = <2 0 0>;
|
||||
ti,mbox-tx = <3 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Timers are used by Remoteproc firmware */
|
||||
&main_timer0 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer1 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer2 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer3 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer4 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&main_timer5 {
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
&mcu_r5fss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1 {
|
||||
ti,cluster-mode = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core0 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
|
||||
memory-region = <&main_r5fss1_core0_dma_memory_region>,
|
||||
<&main_r5fss1_core0_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&main_r5fss1_core1 {
|
||||
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
|
||||
memory-region = <&main_r5fss1_core1_dma_memory_region>,
|
||||
<&main_r5fss1_core1_memory_region>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&c71_0 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
|
||||
memory-region = <&c71_0_dma_memory_region>,
|
||||
<&c71_0_memory_region>;
|
||||
};
|
||||
|
||||
&c71_1 {
|
||||
status = "okay";
|
||||
mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
|
||||
memory-region = <&c71_1_dma_memory_region>,
|
||||
<&c71_1_memory_region>;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user