From e1cd39eb793c33d4a06b3d0bdb25d307074ab4cc Mon Sep 17 00:00:00 2001 From: David Dai Date: Wed, 28 Aug 2019 21:30:45 -0700 Subject: [PATCH] clk: qcom: clk-alpha-pll: add callbacks to deal with voltage voting Specify prepare, unprepare, pre_change_rate, post_change_rate callbacks for alpha-pll clk_ops. This ensures that supply regulator requirements are managed properly at runtime. Change-Id: I578b81c2ab77a8d7e2332098bd737b0646cf577d Signed-off-by: David Dai Signed-off-by: Mike Tipton --- drivers/clk/qcom/clk-alpha-pll.c | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 6b5fa0d8433c..8c1b79830632 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -905,6 +905,10 @@ clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) } const struct clk_ops clk_alpha_pll_fixed_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, .is_enabled = clk_alpha_pll_is_enabled, @@ -913,6 +917,10 @@ const struct clk_ops clk_alpha_pll_fixed_ops = { EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); const struct clk_ops clk_alpha_pll_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, .is_enabled = clk_alpha_pll_is_enabled, @@ -923,6 +931,10 @@ const struct clk_ops clk_alpha_pll_ops = { EXPORT_SYMBOL_GPL(clk_alpha_pll_ops); const struct clk_ops clk_alpha_pll_huayra_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, .is_enabled = clk_alpha_pll_is_enabled, @@ -933,6 +945,10 @@ const struct clk_ops clk_alpha_pll_huayra_ops = { EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops); const struct clk_ops clk_alpha_pll_hwfsm_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_alpha_pll_hwfsm_enable, .disable = clk_alpha_pll_hwfsm_disable, .is_enabled = clk_alpha_pll_hwfsm_is_enabled, @@ -943,6 +959,10 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = { EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); const struct clk_ops clk_alpha_pll_fixed_trion_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_trion_pll_enable, .disable = clk_trion_pll_disable, .is_enabled = clk_trion_pll_is_enabled, @@ -1231,6 +1251,10 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw) u64 a; int ret; + ret = clk_prepare_regmap(hw); + if (ret) + return ret; + /* Check if calibration needs to be done i.e. PLL is in reset */ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (ret) @@ -1277,6 +1301,9 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw) const struct clk_ops clk_alpha_pll_fabia_ops = { .prepare = alpha_pll_fabia_prepare, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = alpha_pll_fabia_enable, .disable = alpha_pll_fabia_disable, .is_enabled = clk_alpha_pll_is_enabled, @@ -1287,6 +1314,10 @@ const struct clk_ops clk_alpha_pll_fabia_ops = { EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops); const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = alpha_pll_fabia_enable, .disable = alpha_pll_fabia_disable, .is_enabled = clk_alpha_pll_is_enabled, @@ -1495,6 +1526,10 @@ static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done) u32 val; int ret; + ret = clk_prepare_regmap(hw); + if (ret) + return ret; + /* Return early if calibration is not needed. */ regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val); if (val & pcal_done) @@ -1573,6 +1608,9 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops clk_alpha_pll_trion_ops = { .prepare = alpha_pll_trion_prepare, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_trion_pll_enable, .disable = clk_trion_pll_disable, .is_enabled = clk_trion_pll_is_enabled, @@ -1584,6 +1622,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops); const struct clk_ops clk_alpha_pll_lucid_ops = { .prepare = alpha_pll_lucid_prepare, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_trion_pll_enable, .disable = clk_trion_pll_disable, .is_enabled = clk_trion_pll_is_enabled, @@ -1643,6 +1684,10 @@ static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate, } const struct clk_ops clk_alpha_pll_agera_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, .is_enabled = clk_alpha_pll_is_enabled, @@ -1735,6 +1780,10 @@ static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw) u32 val = 0; int ret; + ret = clk_prepare_regmap(hw); + if (ret) + return ret; + /* Return early if calibration is not needed. */ regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); if (val & LUCID_5LPE_PCAL_DONE) @@ -1794,6 +1843,9 @@ static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { .prepare = alpha_pll_lucid_5lpe_prepare, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = alpha_pll_lucid_5lpe_enable, .disable = alpha_pll_lucid_5lpe_disable, .is_enabled = clk_trion_pll_is_enabled, @@ -1804,6 +1856,10 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = { EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops); const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = alpha_pll_lucid_5lpe_enable, .disable = alpha_pll_lucid_5lpe_disable, .is_enabled = clk_trion_pll_is_enabled, @@ -1963,6 +2019,10 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, } const struct clk_ops clk_alpha_pll_zonda_ops = { + .prepare = clk_prepare_regmap, + .unprepare = clk_unprepare_regmap, + .pre_rate_change = clk_pre_change_regmap, + .post_rate_change = clk_post_change_regmap, .enable = clk_zonda_pll_enable, .disable = clk_zonda_pll_disable, .is_enabled = clk_trion_pll_is_enabled,