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arm64: dts: qcom: glymur: add CPU capacity-dmips-mhz

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The Glymur SoC has two distinct core types within the same Oryon
microarchitecture generation:

  - qcom,oryon-2-2 (cpu0-cpu5, cluster 0)
  - qcom,oryon-2-1 (cpu6-cpu11, cluster 1; cpu12-cpu17, cluster 2)

Without capacity-dmips-mhz the Energy Aware Scheduler treats all 18
cores as equal, leading to suboptimal task placement and frequency
selection. In particular, heavy tasks may be pinned to cluster 0  driving
them to maximum frequency/voltage while cluster 1/2 sit idle.

Fix this by using distinct capacity-dmips-mhz numbers.
Values are derived from DPC (DMIPS-per-clock) measurements at the
825.6 MHz nominal operating point:

oryon-2-2: 1024  (normalised baseline)
oryon-2-1: 1372  (ratio ~1.34x vs oryon-2-2)

Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260706-add-cpu-capacity-dmips-mhz-v1-1-85deced44b20@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Pradyot Kumar Nayak 2026-07-06 12:25:59 +05:30 committed by Bjorn Andersson
parent 67be5d3da3
commit e1a6af9411
1 changed files with 18 additions and 0 deletions
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18
arch/arm64/boot/dts/qcom/glymur.dtsi
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@ -43,6 +43,7 @@ cpu0: cpu@0 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd0>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@ -60,6 +61,7 @@ cpu1: cpu@100 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd1>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@ -71,6 +73,7 @@ cpu2: cpu@200 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd2>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@ -82,6 +85,7 @@ cpu3: cpu@300 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd3>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@ -93,6 +97,7 @@ cpu4: cpu@400 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd4>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@ -104,6 +109,7 @@ cpu5: cpu@500 {
compatible = "qcom,oryon-2-2";
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
power-domains = <&cpu_pd5>, <&scmi_perf 0>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_0>;
@ -115,6 +121,7 @@ cpu6: cpu@10000 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10000>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd6>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@ -132,6 +139,7 @@ cpu7: cpu@10100 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10100>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd7>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@ -143,6 +151,7 @@ cpu8: cpu@10200 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10200>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd8>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@ -154,6 +163,7 @@ cpu9: cpu@10300 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10300>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd9>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@ -165,6 +175,7 @@ cpu10: cpu@10400 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10400>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd10>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@ -176,6 +187,7 @@ cpu11: cpu@10500 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x10500>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd11>, <&scmi_perf 1>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_1>;
@ -187,6 +199,7 @@ cpu12: cpu@20000 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20000>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd12>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@ -204,6 +217,7 @@ cpu13: cpu@20100 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20100>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd13>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@ -215,6 +229,7 @@ cpu14: cpu@20200 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20200>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd14>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@ -226,6 +241,7 @@ cpu15: cpu@20300 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20300>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd15>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@ -237,6 +253,7 @@ cpu16: cpu@20400 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20400>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd16>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;
@ -248,6 +265,7 @@ cpu17: cpu@20500 {
compatible = "qcom,oryon-2-1";
reg = <0x0 0x20500>;
enable-method = "psci";
capacity-dmips-mhz = <1372>;
power-domains = <&cpu_pd17>, <&scmi_perf 2>;
power-domain-names = "psci", "perf";
next-level-cache = <&l2_2>;