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arm/arm64: dts: marvell: Drop unused .dtsi
These .dtsi files are not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Elad Nachman <enachman@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
This commit is contained in:
Rob Herring (Arm)
Gregory CLEMENT
parent
e4cbff2deb
commit
e171a891c2
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@ -1,148 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada 380 SoC.
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*
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* Copyright (C) 2014 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*/
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#include "armada-38x.dtsi"
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/ {
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model = "Marvell Armada 380 family SoC";
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compatible = "marvell,armada380";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,armada-380-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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};
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soc {
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internal-regs {
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pinctrl@18000 {
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compatible = "marvell,mv88f6810-pinctrl";
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};
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};
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pcie {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
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0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
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0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
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/* x1 port */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie1_intc 0>,
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<0 0 0 2 &pcie1_intc 1>,
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<0 0 0 3 &pcie1_intc 2>,
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<0 0 0 4 &pcie1_intc 3>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 8>;
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status = "disabled";
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pcie1_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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/* x1 port */
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2_intc 0>,
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<0 0 0 2 &pcie2_intc 1>,
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<0 0 0 3 &pcie2_intc 2>,
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<0 0 0 4 &pcie2_intc 3>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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pcie2_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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/* x1 port */
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-names = "intx";
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interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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bus-range = <0x00 0xff>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3_intc 0>,
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<0 0 0 2 &pcie3_intc 1>,
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<0 0 0 3 &pcie3_intc 2>,
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<0 0 0 4 &pcie3_intc 3>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 6>;
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status = "disabled";
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pcie3_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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};
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};
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@ -1,20 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
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* two CP110.
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*/
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#include "armada-ap806-dual.dtsi"
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#include "armada-80x0.dtsi"
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/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
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* in CP master is not connected (by package) to the oscillator. So
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* disable it. However, the RTC clock in CP slave is connected to the
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* oscillator so this one is let enabled.
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*/
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&cp0_rtc {
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status = "disabled";
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};
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@ -1,96 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2023 Marvell International Ltd.
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*
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* Device tree for the CN9130-DB Com Express CPU module board.
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*/
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#include "cn9130-db.dtsi"
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/ {
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model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
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compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
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"marvell,armada-ap807-quad", "marvell,armada-ap807";
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};
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&ap0_reg_sd_vccq {
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regulator-max-microvolt = <1800000>;
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states = <1800000 0x1 1800000 0x0>;
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/delete-property/ gpios;
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};
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&cp0_reg_usb3_vbus0 {
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/delete-property/ gpio;
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};
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&cp0_reg_usb3_vbus1 {
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/delete-property/ gpio;
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};
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&cp0_reg_sd_vcc {
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status = "disabled";
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};
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&cp0_reg_sd_vccq {
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status = "disabled";
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};
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&cp0_sdhci0 {
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status = "disabled";
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};
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&cp0_eth0 {
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status = "disabled";
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};
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&cp0_eth1 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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&cp0_eth2 {
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status = "disabled";
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};
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&cp0_mdio {
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status = "okay";
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pinctrl-0 = <&cp0_ge_mdio_pins>;
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phy0: ethernet-phy@0 {
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status = "okay";
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};
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};
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&cp0_syscon0 {
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cp0_pinctrl: pinctrl {
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compatible = "marvell,cp115-standalone-pinctrl";
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cp0_ge_mdio_pins: ge-mdio-pins {
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marvell,pins = "mpp40", "mpp41";
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marvell,function = "ge";
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};
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};
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};
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&cp0_sdhci0 {
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status = "disabled";
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};
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&cp0_spi1 {
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status = "okay";
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};
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&cp0_usb3_0 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy0>;
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phy-names = "usb";
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/delete-property/ phys;
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};
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&cp0_usb3_1 {
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status = "okay";
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usb-phy = <&cp0_usb3_0_phy1>;
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phy-names = "usb";
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/delete-property/ phys;
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};
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