From e15bf208468b74a04fd4c9f75eb23a67b16f4d38 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 2 Jan 2018 15:46:50 +0800 Subject: [PATCH] arm64: dts: rockchip: add VOP and LVDS config for PX30/RK3326 Change-Id: I6532bf28b905351609a164f1c17898fb8ab1bdea Signed-off-by: Sandy Huang --- arch/arm64/boot/dts/rockchip/px30.dtsi | 104 +++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index d6b63f34a729..14c40d33e785 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -69,6 +70,12 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopb_out>, <&vopl_out>; + status = "disabled"; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -549,7 +556,38 @@ pmucru: pmu-clock-controller@ff2bc000 { <300000000>, <300000000>, <150000000>, <150000000>, <75000000>, <416000000>; + }; + + lvds: lvds@ff2e0000 { + compatible = "rockchip,px30-lvds"; + reg = <0x0 0xff2e0000 0x0 0x100>, <0x0 0xff2e0100 0x0 0x100>; + reg-names = "mipi_lvds_phy", "mipi_lvds_ctl"; + clocks = <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; + clock-names = "pclk_lvds", "pclk_lvds_ctl"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lvds_in: port@0 { + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + lvds_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; }; + }; sdmmc: dwmmc@ff370000 { compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; @@ -586,6 +624,72 @@ emmc: dwmmc@ff390000 { status = "disabled"; }; + vopb: vop@ff460000 { + compatible = "rockchip,px30-vop-big"; + reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOPM>, <&cru DCLK_VOPM>, + <&cru HCLK_VOPM>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vopb_mmu>; + status = "disabled"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopb_out_lvds: endpoint@0 { + reg = <0>; + remote-endpoint = <&lvds_in_vopb>; + }; + }; + }; + + vopb_mmu: iommu@ff460f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff460f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOPM>, <&cru HCLK_VOPM>; + clock-names = "aclk", "hclk"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vopl: vop@ff470000 { + compatible = "rockchip,px30-vop-lit"; + reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOPS>, <&cru DCLK_VOPS>, + <&cru HCLK_VOPS>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <&vopl_mmu>; + status = "disabled"; + + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopl_out_lvds: endpoint@0 { + reg = <0>; + remote-endpoint = <&lvds_in_vopl>; + }; + }; + }; + + vopl_mmu: iommu@ff470f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff470f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOPS>, <&cru HCLK_VOPS>; + clock-names = "aclk", "hclk"; + #iommu-cells = <0>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,px30-pinctrl"; rockchip,grf = <&grf>;