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drm/xe: Separate number of registers from MI_LRI opcode

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Keeping the number of registers to be loaded as a separate macro from
the instruction opcode will simplify some upcoming LRC parsing code.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231016163449.1300701-10-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Matt Roper 2023-10-16 09:34:52 -07:00 committed by Rodrigo Vivi
parent de54bb81d9
commit e12a64881e
4 changed files with 6 additions and 4 deletions
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4
drivers/gpu/drm/xe/regs/xe_gpu_commands.h
View File

@ -25,9 +25,11 @@
#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 0)
#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
#define MI_LRI_LENGTH GENMASK(5, 0)
#define MI_LRI_NUM_REGS(x) REG_FIELD_PREP(MI_LRI_LENGTH, 2 * (x) - 1)
#define MI_LRI_FORCE_POSTED (1<<12)
#define MI_FLUSH_DW MI_INSTR(0x26, 0)

2
drivers/gpu/drm/xe/xe_gt.c
View File

@ -145,7 +145,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
if (count) {
xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM(count);
bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
xa_for_each(&sr->xa, idx, entry) {
struct xe_reg reg = entry->reg;

2
drivers/gpu/drm/xe/xe_lrc.c
View File

@ -111,7 +111,7 @@ static void set_offsets(u32 *regs,
flags = *data >> 6;
data++;
*regs = MI_LOAD_REGISTER_IMM(count);
*regs = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
if (flags & POSTED)
*regs |= MI_LRI_FORCE_POSTED;
*regs |= MI_LRI_LRM_CS_MMIO;

2
drivers/gpu/drm/xe/xe_ring_ops.c
View File

@ -50,7 +50,7 @@ static u32 preparser_disable(bool state)
static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
u32 *dw, int i)
{
dw[i++] = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;
dw[i++] = reg.addr + gt->mmio.adj_offset;
dw[i++] = AUX_INV;
dw[i++] = MI_NOOP;