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drm/amdgpu: Convert update_supported_modes into a common helper

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So it can be used for future products

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2025-06-05 15:36:17 +08:00 committed by Alex Deucher
parent 4dbc17b455
commit e0f14a2abf
3 changed files with 39 additions and 40 deletions
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37
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c
View File

@ -597,6 +597,43 @@ int amdgpu_xcp_update_partition_sched_list(struct amdgpu_device *adev)
return amdgpu_xcp_sched_list_update(adev);
}
void amdgpu_xcp_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr)
{
struct amdgpu_device *adev = xcp_mgr->adev;
xcp_mgr->supp_xcp_modes = 0;
switch (NUM_XCC(adev->gfx.xcc_mask)) {
case 8:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_DPX_PARTITION_MODE) |
BIT(AMDGPU_QPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
case 6:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_TPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
case 4:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_DPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
case 2:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
case 1:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
default:
break;
}
}
/*====================== xcp sysfs - configuration ======================*/
#define XCP_CFG_SYSFS_RES_ATTR_SHOW(_name) \
static ssize_t amdgpu_xcp_res_sysfs_##_name##_show( \

1
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h
View File

@ -177,6 +177,7 @@ int amdgpu_xcp_select_scheds(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv,
unsigned int *num_scheds,
struct drm_gpu_scheduler ***scheds);
void amdgpu_xcp_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr);
int amdgpu_xcp_update_partition_sched_list(struct amdgpu_device *adev);
void amdgpu_xcp_sysfs_init(struct amdgpu_device *adev);
void amdgpu_xcp_sysfs_fini(struct amdgpu_device *adev);

41
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c
View File

@ -396,45 +396,6 @@ static int __aqua_vanjaram_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr,
return ret;
}
static void
__aqua_vanjaram_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr)
{
struct amdgpu_device *adev = xcp_mgr->adev;
xcp_mgr->supp_xcp_modes = 0;
switch (NUM_XCC(adev->gfx.xcc_mask)) {
case 8:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_DPX_PARTITION_MODE) |
BIT(AMDGPU_QPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
case 6:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_TPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
case 4:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_DPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
/* this seems only existing in emulation phase */
case 2:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
case 1:
xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) |
BIT(AMDGPU_CPX_PARTITION_MODE);
break;
default:
break;
}
}
static void __aqua_vanjaram_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr)
{
int mode;
@ -591,7 +552,7 @@ static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev)
if (ret)
return ret;
__aqua_vanjaram_update_supported_modes(adev->xcp_mgr);
amdgpu_xcp_update_supported_modes(adev->xcp_mgr);
/* TODO: Default memory node affinity init */
return ret;