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RISC-V: KVM: Use try_cmpxchg for IMSIC MRIF RMW

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Currently the RMW for IMSIC MRIF is implemented with word LRSC loop.
This will only cover the lower 32bit on a 64bit system. Instead of
guard the implementation with CONFIG_64BIT here, use try_cmpxchg()
wrapper which has already take care this to fix this issue.
It can also use AMO instructions on supported system.

Fixes: db8b7e97d6 ("RISC-V: KVM: Add in-kernel virtualization of AIA IMSIC")
Signed-off-by: Yicong Yang <yang.yicong@picoheart.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20260728141938.95845-1-yang.yicong@picoheart.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Yicong Yang 2026-07-28 22:19:38 +08:00 committed by Anup Patel
parent 739dfb8b4b
commit e0ba6bf657
1 changed files with 5 additions and 9 deletions
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14
arch/riscv/kvm/aia_imsic.c
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@ -220,15 +220,11 @@ static unsigned long imsic_mrif_atomic_rmw(struct imsic_mrif *mrif,
{
unsigned long old_val = 0, tmp = 0;
__asm__ __volatile__ (
"0: lr.w.aq %1, %0\n"
" and %2, %1, %3\n"
" or %2, %2, %4\n"
" sc.w.rl %2, %2, %0\n"
" bnez %2, 0b"
: "+A" (*ptr), "+r" (old_val), "+r" (tmp)
: "r" (~wr_mask), "r" (new_val & wr_mask)
: "memory");
new_val &= wr_mask;
old_val = READ_ONCE(*ptr);
do {
tmp = (old_val & ~wr_mask) | new_val;
} while (!try_cmpxchg(ptr, &old_val, tmp));
return old_val;
}