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ACPI: CPPC: Add cppc_set_reg_val()
Add cppc_set_reg_val() as a generic function for setting CPPC register
values, with this features:
1. Check register. If a register is writeable, it must be a buffer and
can not be null.
2. Extract the operations if register is in PCC out as
cppc_set_reg_val_in_pcc().
This function can be used to reduce some existing code duplication.
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Lifeng Zheng <zhenglifeng1@huawei.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://patch.msgid.link/20250411093855.982491-6-zhenglifeng1@huawei.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -1232,6 +1232,55 @@ static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
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return cpc_read(cpu, reg, val);
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}
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static int cppc_set_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 val)
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{
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int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
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struct cppc_pcc_data *pcc_ss_data = NULL;
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int ret;
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if (pcc_ss_id < 0) {
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pr_debug("Invalid pcc_ss_id\n");
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return -ENODEV;
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}
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ret = cpc_write(cpu, reg, val);
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if (ret)
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return ret;
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pcc_ss_data = pcc_data[pcc_ss_id];
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down_write(&pcc_ss_data->pcc_lock);
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/* after writing CPC, transfer the ownership of PCC to platform */
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ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
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up_write(&pcc_ss_data->pcc_lock);
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return ret;
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}
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static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
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{
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struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
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struct cpc_register_resource *reg;
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if (!cpc_desc) {
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pr_debug("No CPC descriptor for CPU:%d\n", cpu);
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return -ENODEV;
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}
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reg = &cpc_desc->cpc_regs[reg_idx];
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/* if a register is writeable, it must be a buffer and not null */
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if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(®->cpc_entry.reg)) {
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pr_debug("CPC register is not supported\n");
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return -EOPNOTSUPP;
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}
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if (CPC_IN_PCC(reg))
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return cppc_set_reg_val_in_pcc(cpu, reg, val);
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return cpc_write(cpu, reg, val);
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}
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/**
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* cppc_get_desired_perf - Get the desired performance register value.
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* @cpunum: CPU from which to get desired performance.
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