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ARM: tegra: lg-x3: Add panel and bridge nodes

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Add RGB-DSI bridge and panel nodes to LG Optimus 4X and Vu device trees.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Svyatoslav Ryhel 2026-01-26 12:10:15 +02:00 committed by Thierry Reding
parent 6369fd1d0e
commit e045ba8a56
3 changed files with 130 additions and 1 deletions
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23
arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts
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@ -116,6 +116,29 @@ rmi4-f11@11 {
};
};
spi@7000dc00 {
dsi@2 {
/*
* JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel
*/
panel@1 {
compatible = "jdi,dx12d100vm0eaa", "renesas,r69328";
reg = <1>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
vdd-supply = <&vcc_3v0_lcd>;
vddio-supply = <&iovcc_1v8_lcd>;
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
};
};
memory-controller@7000f000 {
emc-timings-0 {
/* SAMSUNG 1GB K4P8G304EB FGC1 533MHz */

27
arch/arm/boot/dts/nvidia/tegra30-lg-p895.dts
View File

@ -112,6 +112,33 @@ rmi4-f11@11 {
};
};
spi@7000dc00 {
dsi@2 {
/*
* HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel
*/
panel@1 {
compatible = "koe,tx13d100vm0eaa", "renesas,r61307";
reg = <1>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
renesas,gamma = <3>;
renesas,column-inversion;
renesas,contrast;
vcc-supply = <&vcc_3v0_lcd>;
iovcc-supply = <&iovcc_1v8_lcd>;
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
};
};
memory-controller@7000f000 {
emc-timings-2 {
/* Hynix 1GB H9TCNNN8JDMMPR LPDDR2 533MHz */

81
arch/arm/boot/dts/nvidia/tegra30-lg-x3.dtsi
View File

@ -20,6 +20,8 @@ aliases {
rtc0 = &pmic;
rtc1 = "/rtc@7000e000";
display0 = &lcd;
serial0 = &uartd; /* Console */
serial1 = &uartc; /* Bluetooth */
serial2 = &uartb; /* GPS */
@ -71,6 +73,21 @@ trustzone@bfe00000 {
};
};
host1x@50000000 {
lcd: dc@54200000 {
rgb {
status = "okay";
port {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;
};
};
};
};
};
vde@6001a000 {
assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
@ -1357,7 +1374,58 @@ spi@7000dc00 {
status = "okay";
spi-max-frequency = <25000000>;
/* DSI bridge */
dsi@2 {
compatible = "solomon,ssd2825";
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <1000000>;
spi-cpha;
spi-cpol;
reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>;
dvdd-supply = <&vdd_1v2_rgb>;
avdd-supply = <&vdd_1v2_rgb>;
vddio-supply = <&vdd_1v8_vio>;
solomon,hs-zero-delay-ns = <300>;
solomon,hs-prep-delay-ns = <65>;
clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_3>;
assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN3>,
<&tegra_pmc TEGRA_PMC_CLK_OUT_3>;
assigned-clock-rates = <24000000>;
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>,
<&tegra_car TEGRA30_CLK_EXTERN3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input: endpoint {
remote-endpoint = <&dpi_output>;
bus-width = <24>;
};
};
port@1 {
reg = <1>;
bridge_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
};
pmc@7000e400 {
@ -1617,6 +1685,17 @@ vdd_1v8_sen: regulator-sen1v8 {
vin-supply = <&vdd_3v3_vbat>;
};
vdd_1v2_rgb: regulator-rgb1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_vbat>;
};
vcc_3v0_lcd: regulator-lcd3v {
compatible = "regulator-fixed";
regulator-name = "vcc_3v0_lcd";