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iio: accel: bma400: Use index-based register addressing and lookup

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Introduce formula-based macros to compute GEN INTR configuration register
addresses from the interrupt number and register index. This reduces the
need for 22 explicit register macros to three base definitions.

Add a centralized lookup table keyed by IIO event direction and replace
get_gen_config_reg() with a helper integrated with this table.

Apply these changes across the affected callbacks to ensure consistent
access to generic interrupt registers.

No functional changes are intended.

Signed-off-by: Akshay Jindal <akshayaj.lkd@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Akshay Jindal 2025-10-12 23:36:10 +05:30 committed by Jonathan Cameron
parent a2ef0af192
commit e03d213848
2 changed files with 88 additions and 60 deletions
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17
drivers/iio/accel/bma400.h
View File

@ -98,6 +98,11 @@
#define BMA400_INT_CONFIG0_GEN2_MASK BIT(3)
#define BMA400_INT_CONFIG0_DRDY_MASK BIT(7)
enum bma400_generic_intr {
BMA400_GEN1_INTR = 0x1,
BMA400_GEN2_INTR = 0x2,
};
#define BMA400_INT_CONFIG1_REG 0x20
#define BMA400_INT_CONFIG1_STEP_INT_MASK BIT(0)
#define BMA400_INT_CONFIG1_S_TAP_MASK BIT(2)
@ -110,8 +115,12 @@
#define BMA400_TWO_BITS_MASK GENMASK(1, 0)
/* Generic interrupts register */
#define BMA400_GEN1INT_CONFIG0_REG 0x3f
#define BMA400_GEN2INT_CONFIG0_REG 0x4A
#define BMA400_GENINT_CONFIG_REG_BASE 0x3f
#define BMA400_NUM_GENINT_CONFIG_REGS 11
#define BMA400_GENINT_CONFIG_REG(gen_intr, config_idx) \
(BMA400_GENINT_CONFIG_REG_BASE + \
(gen_intr - 1) * BMA400_NUM_GENINT_CONFIG_REGS + \
(config_idx))
#define BMA400_GENINT_CONFIG0_HYST_MASK GENMASK(1, 0)
#define BMA400_GENINT_CONFIG0_REF_UPD_MODE_MASK GENMASK(3, 2)
#define BMA400_GENINT_CONFIG0_DATA_SRC_MASK BIT(4)
@ -145,10 +154,6 @@ enum bma400_detect_criterion {
BMA400_DETECT_ACTIVITY = 0x1,
};
#define BMA400_GEN_CONFIG2_OFF 0x02
#define BMA400_GEN_CONFIG3_OFF 0x03
#define BMA400_GEN_CONFIG31_OFF 0x04
/* TAP config registers */
#define BMA400_TAP_CONFIG_REG 0x57
#define BMA400_TAP_CONFIG_SEN_MASK GENMASK(2, 0)

131
drivers/iio/accel/bma400_core.c
View File

@ -121,6 +121,41 @@ struct bma400_data {
__be16 duration;
};
struct bma400_genintr_info {
enum bma400_generic_intr genintr;
unsigned int intrmask;
enum iio_event_direction dir;
enum bma400_detect_criterion detect_mode;
};
/* Lookup struct for determining GEN1/GEN2 based on dir */
static const struct bma400_genintr_info bma400_genintrs[] = {
[IIO_EV_DIR_RISING] = {
.genintr = BMA400_GEN1_INTR,
.intrmask = BMA400_INT_CONFIG0_GEN1_MASK,
.dir = IIO_EV_DIR_RISING,
.detect_mode = BMA400_DETECT_ACTIVITY,
},
[IIO_EV_DIR_FALLING] = {
.genintr = BMA400_GEN2_INTR,
.intrmask = BMA400_INT_CONFIG0_GEN2_MASK,
.dir = IIO_EV_DIR_FALLING,
.detect_mode = BMA400_DETECT_INACTIVITY,
}
};
static inline const struct bma400_genintr_info *
get_bma400_genintr_info(enum iio_event_direction dir)
{
switch (dir) {
case IIO_EV_DIR_RISING:
case IIO_EV_DIR_FALLING:
return &bma400_genintrs[dir];
default:
return NULL;
};
}
static bool bma400_is_writable_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
@ -1159,32 +1194,22 @@ static int bma400_activity_event_en(struct bma400_data *data,
enum iio_event_direction dir,
int state)
{
int ret, reg, msk, value;
int field_value = 0;
int ret;
unsigned int intrmask, regval;
enum bma400_generic_intr genintr;
enum bma400_detect_criterion detect_criterion;
const struct bma400_genintr_info *bma400_genintr;
switch (dir) {
case IIO_EV_DIR_RISING:
reg = BMA400_GEN1INT_CONFIG0_REG;
msk = BMA400_INT_CONFIG0_GEN1_MASK;
value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) |
FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_ACTIVITY);
set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN1_MASK,
FIELD_PREP(BMA400_INT_CONFIG0_GEN1_MASK, state));
break;
case IIO_EV_DIR_FALLING:
reg = BMA400_GEN2INT_CONFIG0_REG;
msk = BMA400_INT_CONFIG0_GEN2_MASK;
value = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) |
FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, BMA400_DETECT_INACTIVITY);
set_mask_bits(&field_value, BMA400_INT_CONFIG0_GEN2_MASK,
FIELD_PREP(BMA400_INT_CONFIG0_GEN2_MASK, state));
break;
default:
bma400_genintr = get_bma400_genintr_info(dir);
if (!bma400_genintr)
return -EINVAL;
}
genintr = bma400_genintr->genintr;
detect_criterion = bma400_genintr->detect_mode;
intrmask = bma400_genintr->intrmask;
/* Enabling all axis for interrupt evaluation */
ret = regmap_write(data->regmap, reg,
ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 0),
BMA400_GENINT_CONFIG0_X_EN_MASK |
BMA400_GENINT_CONFIG0_Y_EN_MASK |
BMA400_GENINT_CONFIG0_Z_EN_MASK|
@ -1195,31 +1220,32 @@ static int bma400_activity_event_en(struct bma400_data *data,
return ret;
/* OR combination of all axis for interrupt evaluation */
ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value);
regval = FIELD_PREP(BMA400_GENINT_CONFIG1_AXES_COMB_MASK, BMA400_EVAL_X_OR_Y_OR_Z) |
FIELD_PREP(BMA400_GENINT_CONFIG1_DETCT_CRIT_MASK, detect_criterion);
ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 1), regval);
if (ret)
return ret;
/* Initial value to avoid interrupts while enabling*/
ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A);
ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 2), 0x0A);
if (ret)
return ret;
/* Initial duration value to avoid interrupts while enabling*/
ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F);
ret = regmap_write(data->regmap, BMA400_GENINT_CONFIG_REG(genintr, 4), 0x0F);
if (ret)
return ret;
ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk,
field_value);
regval = state ? intrmask : 0;
ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, intrmask, regval);
if (ret)
return ret;
ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk,
field_value);
ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, intrmask, regval);
if (ret)
return ret;
set_mask_bits(&data->generic_event_en, msk, field_value);
set_mask_bits(&data->generic_event_en, intrmask, regval);
return 0;
}
@ -1344,18 +1370,6 @@ static int bma400_write_event_config(struct iio_dev *indio_dev,
}
}
static int get_gen_config_reg(enum iio_event_direction dir)
{
switch (dir) {
case IIO_EV_DIR_FALLING:
return BMA400_GEN2INT_CONFIG0_REG;
case IIO_EV_DIR_RISING:
return BMA400_GEN1INT_CONFIG0_REG;
default:
return -EINVAL;
}
}
static int bma400_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
@ -1364,22 +1378,25 @@ static int bma400_read_event_value(struct iio_dev *indio_dev,
int *val, int *val2)
{
struct bma400_data *data = iio_priv(indio_dev);
int ret, reg, reg_val, raw;
int ret, reg_val, raw;
enum bma400_generic_intr genintr;
const struct bma400_genintr_info *bma400_genintr;
if (chan->type != IIO_ACCEL)
return -EINVAL;
switch (type) {
case IIO_EV_TYPE_MAG:
reg = get_gen_config_reg(dir);
if (reg < 0)
bma400_genintr = get_bma400_genintr_info(dir);
if (!bma400_genintr)
return -EINVAL;
genintr = bma400_genintr->genintr;
*val2 = 0;
switch (info) {
case IIO_EV_INFO_VALUE:
ret = regmap_read(data->regmap,
reg + BMA400_GEN_CONFIG2_OFF,
BMA400_GENINT_CONFIG_REG(genintr, 2),
val);
if (ret)
return ret;
@ -1387,7 +1404,7 @@ static int bma400_read_event_value(struct iio_dev *indio_dev,
case IIO_EV_INFO_PERIOD:
mutex_lock(&data->mutex);
ret = regmap_bulk_read(data->regmap,
reg + BMA400_GEN_CONFIG3_OFF,
BMA400_GENINT_CONFIG_REG(genintr, 3),
&data->duration,
sizeof(data->duration));
if (ret) {
@ -1398,7 +1415,9 @@ static int bma400_read_event_value(struct iio_dev *indio_dev,
mutex_unlock(&data->mutex);
return IIO_VAL_INT;
case IIO_EV_INFO_HYSTERESIS:
ret = regmap_read(data->regmap, reg, val);
ret = regmap_read(data->regmap,
BMA400_GENINT_CONFIG_REG(genintr, 0),
val);
if (ret)
return ret;
*val = FIELD_GET(BMA400_GENINT_CONFIG0_HYST_MASK, *val);
@ -1452,16 +1471,19 @@ static int bma400_write_event_value(struct iio_dev *indio_dev,
int val, int val2)
{
struct bma400_data *data = iio_priv(indio_dev);
int reg, ret, raw;
int ret, raw;
enum bma400_generic_intr genintr;
const struct bma400_genintr_info *bma400_genintr;
if (chan->type != IIO_ACCEL)
return -EINVAL;
switch (type) {
case IIO_EV_TYPE_MAG:
reg = get_gen_config_reg(dir);
if (reg < 0)
bma400_genintr = get_bma400_genintr_info(dir);
if (!bma400_genintr)
return -EINVAL;
genintr = bma400_genintr->genintr;
switch (info) {
case IIO_EV_INFO_VALUE:
@ -1469,7 +1491,7 @@ static int bma400_write_event_value(struct iio_dev *indio_dev,
return -EINVAL;
return regmap_write(data->regmap,
reg + BMA400_GEN_CONFIG2_OFF,
BMA400_GENINT_CONFIG_REG(genintr, 2),
val);
case IIO_EV_INFO_PERIOD:
if (val < 1 || val > 65535)
@ -1478,7 +1500,7 @@ static int bma400_write_event_value(struct iio_dev *indio_dev,
mutex_lock(&data->mutex);
put_unaligned_be16(val, &data->duration);
ret = regmap_bulk_write(data->regmap,
reg + BMA400_GEN_CONFIG3_OFF,
BMA400_GENINT_CONFIG_REG(genintr, 3),
&data->duration,
sizeof(data->duration));
mutex_unlock(&data->mutex);
@ -1487,7 +1509,8 @@ static int bma400_write_event_value(struct iio_dev *indio_dev,
if (val < 0 || val > 3)
return -EINVAL;
return regmap_update_bits(data->regmap, reg,
return regmap_update_bits(data->regmap,
BMA400_GENINT_CONFIG_REG(genintr, 0),
BMA400_GENINT_CONFIG0_HYST_MASK,
FIELD_PREP(BMA400_GENINT_CONFIG0_HYST_MASK,
val));