mirror of
https://github.com/torvalds/linux.git
synced 2026-05-28 09:04:39 +02:00
arm64: dts: socionext: add missing cache properties
As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: uniphier-ld11-ref.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20231023021221.2884828-3-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
parent
0804f3bec9
commit
e035ddb68b
|
|
@ -53,6 +53,7 @@ cpu1: cpu@1 {
|
|||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -87,11 +87,13 @@ cpu3: cpu@101 {
|
|||
a72_l2: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
a53_l2: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -84,6 +84,7 @@ cpu3: cpu@3 {
|
|||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user