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interconnect: qcom: glymur: Add Mahua SoC support

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Mahua is a derivative of the Glymur SoC. Extend the
Glymur driver to support Mahua by:

  1. Adding new node definitions for interconnects that differ from Glymur
     (Config NoC, High-Speed Coherent NoC, PCIe West ANOC/Slave NoC).
  2. Reusing existing Glymur definitions for identical NoCs.
  3. Overriding the channel and buswidth, with Mahua specific values for
     the differing NoCs

Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Link: https://msgid.link/20260209-mahua_icc-v3-2-c65f3dfd72c8@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Raviteja Laggyshetty 2026-02-09 09:44:29 +00:00 committed by Georgi Djakov
parent 43cb0a21a4
commit dfff14a4a4
1 changed files with 33 additions and 5 deletions
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38
drivers/interconnect/qcom/glymur.c
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@ -9,6 +9,7 @@
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/property.h>
#include <dt-bindings/interconnect/qcom,glymur-rpmh.h>
#include "bcm-voter.h"
@ -1985,7 +1986,7 @@ static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = {
&bcm_cn1,
};
static struct qcom_icc_node * const cnoc_cfg_nodes[] = {
static struct qcom_icc_node *cnoc_cfg_nodes[] = {
[MASTER_CNOC_CFG] = &qsm_cfg,
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
@ -2093,7 +2094,7 @@ static struct qcom_icc_bcm * const hscnoc_bcms[] = {
&bcm_sh1,
};
static struct qcom_icc_node * const hscnoc_nodes[] = {
static struct qcom_icc_node *hscnoc_nodes[] = {
[MASTER_GPU_TCU] = &alm_gpu_tcu,
[MASTER_PCIE_TCU] = &alm_pcie_qtc,
[MASTER_SYS_TCU] = &alm_sys_tcu,
@ -2377,7 +2378,7 @@ static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = {
&bcm_sn6,
};
static struct qcom_icc_node * const pcie_west_anoc_nodes[] = {
static struct qcom_icc_node *pcie_west_anoc_nodes[] = {
[MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg,
[MASTER_PCIE_2] = &xm_pcie_2,
[MASTER_PCIE_3A] = &xm_pcie_3a,
@ -2409,7 +2410,7 @@ static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] = {
&bcm_sn6,
};
static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] = {
static struct qcom_icc_node *pcie_west_slv_noc_nodes[] = {
[MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west,
[MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg,
[SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg,
@ -2470,6 +2471,28 @@ static const struct qcom_icc_desc glymur_system_noc = {
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
static int glymur_qnoc_probe(struct platform_device *pdev)
{
if (device_is_compatible(&pdev->dev, "qcom,mahua-mc-virt")) {
llcc_mc.channels = 8;
ebi.channels = 8;
} else if (device_is_compatible(&pdev->dev, "qcom,mahua-hscnoc")) {
qns_llcc.channels = 8;
chm_apps.channels = 4;
qnm_pcie_west.buswidth = 32;
hscnoc_nodes[MASTER_WLAN_Q6] = NULL;
} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-anoc")) {
qns_pcie_west_mem_noc.buswidth = 32;
pcie_west_anoc_nodes[MASTER_PCIE_3A] = NULL;
} else if (device_is_compatible(&pdev->dev, "qcom,mahua-cnoc-cfg")) {
cnoc_cfg_nodes[SLAVE_PCIE_3A_CFG] = NULL;
} else if (device_is_compatible(&pdev->dev, "qcom,mahua-pcie-west-slv-noc")) {
pcie_west_slv_noc_nodes[SLAVE_PCIE_3A] = NULL;
}
return qcom_icc_rpmh_probe(pdev);
}
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc},
{ .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc},
@ -2477,12 +2500,15 @@ static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc},
{ .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt},
{ .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg},
{ .compatible = "qcom,mahua-cnoc-cfg", .data = &glymur_cnoc_cfg},
{ .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main},
{ .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc},
{ .compatible = "qcom,mahua-hscnoc", .data = &glymur_hscnoc},
{ .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc},
{ .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc},
{ .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc},
{ .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt},
{ .compatible = "qcom,mahua-mc-virt", .data = &glymur_mc_virt},
{ .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc},
{ .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc},
{ .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc},
@ -2490,14 +2516,16 @@ static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc},
{ .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc},
{ .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
{ .compatible = "qcom,mahua-pcie-west-anoc", .data = &glymur_pcie_west_anoc},
{ .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
{ .compatible = "qcom,mahua-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc},
{ .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc},
{ }
};
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
.probe = qcom_icc_rpmh_probe,
.probe = glymur_qnoc_probe,
.remove = qcom_icc_rpmh_remove,
.driver = {
.name = "qnoc-glymur",