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drm/amd/display: Improve registers write

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Add REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE to optimize the burst write for
the regama lut.

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rodrigo Siqueira 2024-04-17 10:59:56 -06:00 committed by Alex Deucher
parent e582c097d3
commit dff0360a49
1 changed files with 2 additions and 1 deletions
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3
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c
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@ -410,9 +410,10 @@ void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
}
REG_SEQ_SUBMIT();
REG_SEQ_WAIT_DONE();
}
void dpp1_cm_configure_regamma_lut(