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drm/i915/ltphy: Nuke extraneous timeout debugs

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The actual timeout used isn't particularly interesting, so
don't print it. Makes the code simpler.

The debugs are also using some random capitalizaton rule.
Clean that up a bit while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251106152049.21115-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2025-11-06 17:20:42 +02:00
parent df17e6bc55
commit dfd58249ff
1 changed files with 16 additions and 18 deletions
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34
drivers/gpu/drm/i915/display/intel_lt_phy.c
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@ -1180,8 +1180,8 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PCLK_PLL_ACK(0),
XE3PLPD_MACCLK_TURNON_LATENCY_US,
XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK assertion Ack not done after %dus.\n",
phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_MS * 1000);
drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n",
phy_name(phy));
intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
XELPDP_FORWARD_CLOCK_UNGATE,
@ -1193,15 +1193,14 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_current_status, 0,
XE3PLPD_RESET_END_LATENCY_US, 2, NULL))
drm_warn(display->drm,
"PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XE3PLPD_RESET_END_LATENCY_US);
drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n",
phy_name(phy));
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status, lane_phy_pulse_status,
XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 0, NULL))
drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
phy_name(phy));
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0);
}
@ -1654,8 +1653,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK Ack deassertion Timeout after %dus.\n",
phy_name(phy), XE3PLPD_MACCLK_TURNOFF_LATENCY_US);
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
phy_name(phy));
/*
* 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency
@ -1675,8 +1674,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
XELPDP_LANE_PCLK_PLL_ACK(0),
XELPDP_LANE_PCLK_PLL_ACK(0),
XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",
phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);
drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n",
phy_name(phy));
/*
* 13. Ungate the forward clock by setting
@ -1703,8 +1702,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status, lane_phy_pulse_status,
XE3PLPD_RATE_CALIB_DONE_LATENCY_US, 2, NULL))
drm_warn(display->drm, "PHY %c PLL rate not changed after %dus.\n",
phy_name(phy), XE3PLPD_RATE_CALIB_DONE_LATENCY_US);
drm_warn(display->drm, "PHY %c PLL rate not changed\n",
phy_name(phy));
/* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
@ -1762,9 +1761,8 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
lane_phy_current_status,
lane_phy_current_status,
XE3PLPD_RESET_START_LATENCY_US, 0, NULL))
drm_warn(display->drm,
"PHY %c failed to reset Lane after %dms.\n",
phy_name(phy), XE3PLPD_RESET_START_LATENCY_US);
drm_warn(display->drm, "PHY %c failed to reset lane\n",
phy_name(phy));
/* 4. Clear for PHY pulse status on owned PHY lanes. */
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
@ -1786,8 +1784,8 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
drm_warn(display->drm, "PHY %c PLL MacCLK Ack deassertion Timeout after %dus.\n",
phy_name(phy), XE3PLPD_MACCLK_TURNOFF_LATENCY_US);
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
phy_name(phy));
/*
* 9. Follow the Display Voltage Frequency Switching -