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accel/ivpu: Extend tile fuse config to 7 bits

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The buttress code that reads the tile fuse register is shared by all
generations, so the register field definition should not differ between
them. Extend the TILE_CONFIG mask from [6:1] to [7:1] and use it
everywhere, instead of having a different field width per generation.

The tile count range check in tile_disable_check() depended on the
previous field width. It only logs a warning, and it would now warn on a
valid value, so drop it together with the tile count defines it used.

Reviewed-by: Dawid Osuchowski <dawid.osuchowski@linux.intel.com>
Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com>
Link: https://patch.msgid.link/20261012083802.2778448-6-karol.wachowski@linux.intel.com
This commit is contained in:
Karol Wachowski 2026-10-12 10:38:02 +02:00
parent 1744fb87c4
commit dfc3c7b84d
2 changed files with 1 additions and 8 deletions
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7
drivers/accel/ivpu/ivpu_hw_btrs.c
View File

@ -45,9 +45,6 @@
#define BTRS_MTL_TILE_FUSE_ENABLE_BOTH 0x0
#define BTRS_MTL_TILE_SKU_BOTH 0x3630
#define BTRS_LNL_TILE_MAX_NUM 6
#define BTRS_LNL_TILE_MAX_MASK 0x3f
#define WEIGHTS_DEFAULT 0xf711f711u
#define WEIGHTS_ATS_DEFAULT 0x0000f711u
@ -99,13 +96,9 @@ void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev)
static bool tile_disable_check(u32 config)
{
/* Allowed values: 0 or one bit from range 0-5 (6 tiles) */
if (config == 0)
return true;
if (config > BIT(BTRS_LNL_TILE_MAX_NUM - 1))
return false;
if ((config & (config - 1)) == 0)
return true;

2
drivers/accel/ivpu/ivpu_hw_btrs_reg.h
View File

@ -151,7 +151,7 @@
#define VPU_HW_BTRS_LNL_TILE_FUSE 0x00000150u
#define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK BIT_MASK(0)
#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(6, 1)
#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(7, 1)
#define VPU_HW_BTRS_LNL_VPU_STATUS 0x00000154u
#define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK BIT_MASK(0)