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drm/i915/xe3p_lpd: Handle underrun debug bits
Xe3p_LPD added several bits containing information that can be relevant to debugging FIFO underruns. Add the logic necessary to handle them when reporting underruns. This was adapted from the initial patch[1] from Sai Teja Pottumuttu. [1] https://lore.kernel.org/all/20251015-xe3p_lpd-basic-enabling-v1-12-d2d1e26520aa@intel.com/ v2: - Handle FBC-related bits in intel_fbc.c. (Ville) - Do not use intel_fbc_id_for_pipe (promoted from skl_fbc_id_for_pipe), but use pipe's primary plane to get the FBC instance. (Ville, Matt) - Improve code readability by moving logic specific to logging fields of UNDERRUN_DBG1 to a separate function. (Jani) v3: - Use crtc->base.primary instead of cycling through all crtcs Bspec: 69111, 69561, 74411, 74412 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patch.msgid.link/20251202012306.9315-5-matthew.s.atwood@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Gustavo Sousa
Matt Roper
parent
df5dd52a6d
commit
df96701916
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@ -197,6 +197,7 @@ struct intel_display_platforms {
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#define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \
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BIT(trans)) != 0)
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#define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13)
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#define HAS_UNDERRUN_DBG_INFO(__display) (DISPLAY_VER(__display) >= 35)
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#define HAS_ULTRAJOINER(__display) (((__display)->platform.dgfx && \
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DISPLAY_VER(__display) == 14) && HAS_DSC(__display))
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#define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)
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@ -882,6 +882,21 @@
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#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
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#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
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#define _UNDERRUN_DBG1_A 0x70064
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#define _UNDERRUN_DBG1_B 0x71064
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#define UNDERRUN_DBG1(pipe) _MMIO_PIPE(pipe, _UNDERRUN_DBG1_A, _UNDERRUN_DBG1_B)
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#define UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK REG_GENMASK(29, 24)
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#define UNDERRUN_DDB_EMPTY_MASK REG_GENMASK(21, 16)
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#define UNDERRUN_DBUF_NOT_FILLED_MASK REG_GENMASK(13, 8)
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#define UNDERRUN_BELOW_WM0_MASK REG_GENMASK(5, 0)
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#define _UNDERRUN_DBG2_A 0x70068
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#define _UNDERRUN_DBG2_B 0x71068
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#define UNDERRUN_DBG2(pipe) _MMIO_PIPE(pipe, _UNDERRUN_DBG2_A, _UNDERRUN_DBG2_B)
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#define UNDERRUN_FRAME_LINE_COUNTERS_FROZEN REG_BIT(31)
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#define UNDERRUN_PIPE_FRAME_COUNT_MASK REG_GENMASK(30, 20)
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#define UNDERRUN_LINE_COUNT_MASK REG_GENMASK(19, 0)
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#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
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#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
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#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
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@ -1416,6 +1431,7 @@
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#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
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#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
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#define XE3P_UNDERRUN_PKGC REG_BIT(21)
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#define FUSE_STRAP _MMIO(0x42014)
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#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
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@ -127,6 +127,19 @@ struct intel_fbc {
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const char *no_fbc_reason;
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};
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static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe)
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{
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struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
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struct intel_plane *primary = NULL;
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primary = to_intel_plane(crtc->base.primary);
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if (drm_WARN_ON(display->drm, !primary))
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return NULL;
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return primary->fbc;
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}
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/* plane stride in pixels */
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static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
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{
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@ -2124,6 +2137,37 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
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__intel_fbc_handle_fifo_underrun_irq(fbc);
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}
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/**
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* intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info
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* @display: display device instance
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* @pipe: the pipe possibly containing the FBC
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* @log: log the info?
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*
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* If @pipe does not contain an FBC instance, this function bails early.
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* Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log
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* is true, printed with error level.
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*/
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void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
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enum pipe pipe, bool log)
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{
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struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe);
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u32 val;
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if (!fbc)
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return;
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val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id));
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if (!(val & FBC_UNDERRUN_DECMPR))
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return;
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intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR);
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if (log)
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drm_err(display->drm,
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"Pipe %c FIFO underrun info: FBC decompressing\n",
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pipe_name(pipe));
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}
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/*
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* The DDX driver changes its behavior depending on the value it reads from
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* i915.enable_fbc, so sanitize it by translating the default value into either
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@ -9,6 +9,7 @@
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#include <linux/types.h>
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enum fb_op_origin;
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enum pipe;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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@ -46,6 +47,8 @@ void intel_fbc_flush(struct intel_display *display,
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unsigned int frontbuffer_bits, enum fb_op_origin origin);
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void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
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void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
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void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
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enum pipe, bool log);
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void intel_fbc_reset_underrun(struct intel_display *display);
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void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
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void intel_fbc_debugfs_register(struct intel_display *display);
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@ -88,6 +88,8 @@
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#define DPFC_FENCE_YOFF _MMIO(0x3218)
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#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
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#define DPFC_CHICKEN _MMIO(0x3224)
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#define FBC_DEBUG_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43220, 0x43260)
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#define FBC_UNDERRUN_DECMPR REG_BIT(27)
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#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
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#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
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#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
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@ -25,6 +25,8 @@
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*
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*/
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#include <linux/seq_buf.h>
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#include <drm/drm_print.h>
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#include "i915_reg.h"
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@ -57,6 +59,100 @@
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* The code also supports underrun detection on the PCH transcoder.
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*/
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#define UNDERRUN_DBG1_NUM_PLANES 6
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static void log_underrun_dbg1(struct intel_display *display, enum pipe pipe,
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unsigned long plane_mask, const char *info)
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{
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DECLARE_SEQ_BUF(planes_desc, 32);
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unsigned int i;
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if (!plane_mask)
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return;
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for_each_set_bit(i, &plane_mask, UNDERRUN_DBG1_NUM_PLANES) {
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if (i == 0)
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seq_buf_puts(&planes_desc, "[C]");
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else
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seq_buf_printf(&planes_desc, "[%d]", i);
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}
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drm_err(display->drm, "Pipe %c FIFO underrun info: %s on planes: %s\n",
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pipe_name(pipe), info, seq_buf_str(&planes_desc));
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drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc));
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}
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static void read_underrun_dbg1(struct intel_display *display, enum pipe pipe, bool log)
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{
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u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe));
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if (!val)
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return;
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intel_de_write(display, UNDERRUN_DBG1(pipe), val);
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if (!log)
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return;
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log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val),
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"DBUF block not valid");
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log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val),
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"DDB empty");
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log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val),
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"DBUF not completely filled");
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log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val),
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"DBUF below WM0");
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}
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static void read_underrun_dbg2(struct intel_display *display, enum pipe pipe, bool log)
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{
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u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe));
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if (!(val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN))
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return;
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intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
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if (log)
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drm_err(display->drm,
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"Pipe %c FIFO underrun info: frame count: %u, line count: %u\n",
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pipe_name(pipe),
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REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val),
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REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val));
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}
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static void read_underrun_dbg_pkgc(struct intel_display *display, bool log)
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{
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u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1);
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if (!(val & XE3P_UNDERRUN_PKGC))
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return;
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/*
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* Note: If there are multiple pipes enabled, only one of them will see
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* XE3P_UNDERRUN_PKGC set.
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*/
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intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
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if (log)
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drm_err(display->drm,
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"General FIFO underrun info: Package C-state blocking memory\n");
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}
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static void read_underrun_dbg_info(struct intel_display *display,
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enum pipe pipe,
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bool log)
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{
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if (!HAS_UNDERRUN_DBG_INFO(display))
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return;
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read_underrun_dbg1(display, pipe, log);
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read_underrun_dbg2(display, pipe, log);
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intel_fbc_read_underrun_dbg_info(display, pipe, log);
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read_underrun_dbg_pkgc(display, log);
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}
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static bool ivb_can_enable_err_int(struct intel_display *display)
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{
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struct intel_crtc *crtc;
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@ -262,6 +358,17 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *displa
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old = !crtc->cpu_fifo_underrun_disabled;
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crtc->cpu_fifo_underrun_disabled = !enable;
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/*
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* The debug bits get latched at the time of the FIFO underrun ISR bit
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* getting set. That means that any non-zero debug bit that is read when
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* handling a FIFO underrun interrupt has the potential to belong to
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* another underrun event (past or future). To alleviate this problem,
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* let's clear existing bits before enabling the interrupt, so that at
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* least we don't get information that is too out-of-date.
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*/
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if (enable && !old)
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read_underrun_dbg_info(display, pipe, false);
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if (HAS_GMCH(display))
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i9xx_set_fifo_underrun_reporting(display, pipe, enable, old);
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else if (display->platform.ironlake || display->platform.sandybridge)
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@ -379,6 +486,8 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
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trace_intel_cpu_fifo_underrun(display, pipe);
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drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
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read_underrun_dbg_info(display, pipe, true);
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}
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intel_fbc_handle_fifo_underrun_irq(display);
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