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net: pcs: xpcs: fix SGMII state reading
Commit2a22b7ae2f("net: pcs: xpcs: adapt Wangxun NICs for SGMII mode") added a path in xpcs_get_state_c37_sgmii() that reads speed/duplex from BMCR after AN completes. However, BMCR does not reflect the negotiated result on the hardware where this has been tested: - On RK3568 (MAC side SGMII), BMCR returns a fixed hardware reset value - Wangxun engineer Jiawen Wu confirmed that on their side, "BMCR looks like it only wants to be return as 0" [0] The correct information is available in CL37_ANSGM_STS, which contains the actual link status and negotiated speed/duplex. This bug was previously masked by phylink core, which overrides the PCS link state with the PHY state when a PHY is present: /* If we have a phy, the "up" state is the union of both the * PHY and the MAC */ if (phy) link_state.link &= pl->phy_state.link; Thus, when the link is down, the PHY's link_down state is applied on top of whatever the PCS reports, hiding the broken PCS state reading path. Modify xpcs_get_state_c37_sgmii() to: 1. Read link state from CL37_ANSGM_STS 2. If link is up, report speed/duplex from CL37_ANSGM_STS 3. Remove the broken BMCR reading path entirely Also properly set state->an_complete to reflect the AN completion status, and clear CL37_ANCMPLT_INTR when link is down to avoid stale state. [0] https://lore.kernel.org/all/000c01dd1593$2ac0b0f0$804212d0$@trustnetic.com/ Fixes:2a22b7ae2f("net: pcs: xpcs: adapt Wangxun NICs for SGMII mode") Cc: stable@vger.kernel.org Tested-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: Coia Prant <coiaprant@gmail.com> Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Link: https://patch.msgid.link/20260717074324.3250043-2-coiaprant@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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@ -1058,6 +1058,7 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
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/* Reset link_state */
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state->link = false;
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state->an_complete = false;
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state->speed = SPEED_UNKNOWN;
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state->duplex = DUPLEX_UNKNOWN;
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state->pause = 0;
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@ -1069,6 +1070,8 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
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if (ret < 0)
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return ret;
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state->an_complete = ret & DW_VR_MII_AN_STS_C37_ANCMPLT_INTR;
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if (ret & DW_VR_MII_C37_ANSGM_SP_LNKSTS) {
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int speed_value;
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@ -1086,35 +1089,14 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
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state->duplex = DUPLEX_FULL;
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else
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state->duplex = DUPLEX_HALF;
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} else if (ret == DW_VR_MII_AN_STS_C37_ANCMPLT_INTR) {
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int speed, duplex;
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state->link = true;
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speed = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMCR);
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if (speed < 0)
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return speed;
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speed &= BMCR_SPEED100 | BMCR_SPEED1000;
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if (speed == BMCR_SPEED1000)
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state->speed = SPEED_1000;
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else if (speed == BMCR_SPEED100)
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state->speed = SPEED_100;
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else if (speed == 0)
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state->speed = SPEED_10;
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duplex = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
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if (duplex < 0)
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return duplex;
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if (duplex & ADVERTISE_1000XFULL)
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state->duplex = DUPLEX_FULL;
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else if (duplex & ADVERTISE_1000XHALF)
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state->duplex = DUPLEX_HALF;
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xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
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return 0;
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}
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/* Clear AN complete status or interrupt */
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if (state->an_complete)
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xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
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return 0;
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}
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