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ASoC: SOF: Intel: Add APL/CNL HW DSP support

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Add SOF hardware DSP support for Intel Apollolake and Cannonlake based
devices.

Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
This commit is contained in:
Liam Girdwood 2018-01-08 20:38:27 +00:00 committed by Pierre-Louis Bossart
parent 5358fd29b3
commit def495ebde
2 changed files with 1234 additions and 0 deletions
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712
sound/soc/sof/intel/hda.c Normal file
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
// Jeeja KP <jeeja.kp@intel.com>
// Rander Wang <rander.wang@intel.com>
// Keyon Jie <yang.jie@linux.intel.com>
//
/*
* Hardware interface for generic Intel audio DSP HDA IP
*/
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/firmware.h>
#include <linux/pci.h>
#include <sound/hdaudio_ext.h>
#include <sound/sof.h>
#include <sound/pcm_params.h>
#include <linux/pm_runtime.h>
#include <sound/hdaudio.h>
#include <sound/hda_i915.h>
#include "../sof-priv.h"
#include "../ops.h"
#include "hda.h"
#include "../../codecs/hdac_hda.h"
/* platform specific devices */
#include "shim.h"
/*
* Register IO
*/
void hda_dsp_write(struct snd_sof_dev *sdev, void __iomem *addr, u32 value)
{
writel(value, addr);
}
u32 hda_dsp_read(struct snd_sof_dev *sdev, void __iomem *addr)
{
return readl(addr);
}
void hda_dsp_write64(struct snd_sof_dev *sdev, void __iomem *addr, u64 value)
{
memcpy_toio(addr, &value, sizeof(value));
}
u64 hda_dsp_read64(struct snd_sof_dev *sdev, void __iomem *addr)
{
u64 val;
memcpy_fromio(&val, addr, sizeof(val));
return val;
}
/*
* Memory copy.
*/
void hda_dsp_block_write(struct snd_sof_dev *sdev, u32 offset, void *src,
size_t size)
{
void __iomem *dest = sdev->bar[sdev->mmio_bar] + offset;
u32 tmp = 0;
int i, m, n;
const u8 *src_byte = src;
u8 *dst_byte;
m = size / 4;
n = size % 4;
/* __iowrite32_copy use 32bit size values so divide by 4 */
__iowrite32_copy(dest, src, m);
if (n) {
/* first read the 32bit data of dest, then change affected
* bytes, and write back to dest. For unaffected bytes, it
* should not be changed
*/
__ioread32_copy(&tmp, dest + m * 4, 1);
dst_byte = (u8 *)&tmp;
for (i = 0; i < n; i++)
dst_byte[i] = src_byte[m * 4 + i];
__iowrite32_copy(dest + m * 4, &tmp, 1);
}
}
void hda_dsp_block_read(struct snd_sof_dev *sdev, u32 offset, void *dest,
size_t size)
{
void __iomem *src = sdev->bar[sdev->mmio_bar] + offset;
memcpy_fromio(dest, src, size);
}
/*
* Debug
*/
struct hda_dsp_msg_code {
u32 code;
const char *msg;
};
static const struct hda_dsp_msg_code hda_dsp_rom_msg[] = {
{HDA_DSP_ROM_FW_MANIFEST_LOADED, "status: manifest loaded"},
{HDA_DSP_ROM_FW_FW_LOADED, "status: fw loaded"},
{HDA_DSP_ROM_FW_ENTERED, "status: fw entered"},
{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatble"},
{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
{HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
};
static void hda_dsp_get_status(struct snd_sof_dev *sdev)
{
u32 status;
int i;
status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
HDA_DSP_SRAM_REG_ROM_STATUS);
for (i = 0; i < ARRAY_SIZE(hda_dsp_rom_msg); i++) {
if (status == hda_dsp_rom_msg[i].code) {
dev_err(sdev->dev, "%s - code %8.8x\n",
hda_dsp_rom_msg[i].msg, status);
return;
}
}
/* not for us, must be generic sof message */
dev_dbg(sdev->dev, "unknown ROM status value %8.8x\n", status);
}
static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_dsp_oops_xtensa *xoops,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
/* first read registers */
hda_dsp_block_read(sdev, sdev->dsp_oops_offset, xoops, sizeof(*xoops));
/* then get panic info */
hda_dsp_block_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops),
panic_info, sizeof(*panic_info));
/* then get the stack */
hda_dsp_block_read(sdev, sdev->dsp_oops_offset + sizeof(*xoops) +
sizeof(*panic_info), stack,
stack_words * sizeof(u32));
}
void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
struct sof_ipc_dsp_oops_xtensa xoops;
struct sof_ipc_panic_info panic_info;
u32 stack[HDA_DSP_STACK_DUMP_SIZE];
u32 status, panic;
/* try APL specific status message types first */
hda_dsp_get_status(sdev);
/* now try generic SOF status messages */
status = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
HDA_DSP_SRAM_REG_FW_STATUS);
panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
if (sdev->boot_complete) {
hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
HDA_DSP_STACK_DUMP_SIZE);
snd_sof_get_status(sdev, status, panic, &xoops, &panic_info,
stack, HDA_DSP_STACK_DUMP_SIZE);
} else {
dev_err(sdev->dev, "error: status = 0x%8.8x panic = 0x%8.8x\n",
status, panic);
hda_dsp_get_status(sdev);
}
}
/*
* IPC Mailbox IO
*/
void hda_dsp_mailbox_write(struct snd_sof_dev *sdev, u32 offset,
void *message, size_t bytes)
{
void __iomem *dest = sdev->bar[sdev->mailbox_bar] + offset;
memcpy_toio(dest, message, bytes);
}
void hda_dsp_mailbox_read(struct snd_sof_dev *sdev, u32 offset,
void *message, size_t bytes)
{
void __iomem *src = sdev->bar[sdev->mailbox_bar] + offset;
memcpy_fromio(message, src, bytes);
}
/*
* Supported devices.
*/
static const struct sof_intel_dsp_desc chip_info[] = {
{
/* Skylake */
.id = 0x9d70,
.cores_num = 2,
.cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
.ipc_req = HDA_DSP_REG_HIPCI,
.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
.ipc_ack = HDA_DSP_REG_HIPCIE,
.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
.ipc_ctl = HDA_DSP_REG_HIPCCTL,
.ops = &sof_skl_ops,
},
{
/* Kabylake */
.id = 0x9d71,
.cores_num = 2,
.cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
.ipc_req = HDA_DSP_REG_HIPCI,
.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
.ipc_ack = HDA_DSP_REG_HIPCIE,
.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
.ipc_ctl = HDA_DSP_REG_HIPCCTL,
.ops = &sof_skl_ops,
},
{
/* Apollolake - BXT-P */
.id = 0x5a98,
.cores_num = 2,
.cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
.ipc_req = HDA_DSP_REG_HIPCI,
.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
.ipc_ack = HDA_DSP_REG_HIPCIE,
.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
.ipc_ctl = HDA_DSP_REG_HIPCCTL,
.ops = &sof_apl_ops,
},
{
/* BXT-M */
.id = 0x1a98,
.cores_num = 2,
.cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
.ipc_req = HDA_DSP_REG_HIPCI,
.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
.ipc_ack = HDA_DSP_REG_HIPCIE,
.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
.ipc_ctl = HDA_DSP_REG_HIPCCTL,
.ops = &sof_apl_ops,
},
{
/* GeminiLake */
.id = 0x3198,
.cores_num = 2,
.cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
.ipc_req = HDA_DSP_REG_HIPCI,
.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
.ipc_ack = HDA_DSP_REG_HIPCIE,
.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
.ipc_ctl = HDA_DSP_REG_HIPCCTL,
.ops = &sof_apl_ops,
},
{
/* Cannonlake */
.id = 0x9dc8,
.cores_num = 4,
.cores_mask = HDA_DSP_CORE_MASK(0) |
HDA_DSP_CORE_MASK(1) |
HDA_DSP_CORE_MASK(2) |
HDA_DSP_CORE_MASK(3),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
.ops = &sof_cnl_ops,
},
{
/* Icelake */
.id = 0x34c8,
.cores_num = 4,
.cores_mask = HDA_DSP_CORE_MASK(0) |
HDA_DSP_CORE_MASK(1) |
HDA_DSP_CORE_MASK(2) |
HDA_DSP_CORE_MASK(3),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
.ops = &sof_cnl_ops,
},
};
static const struct sof_intel_dsp_desc *get_chip_info(int pci_id)
{
int i;
for (i = 0; i < ARRAY_SIZE(chip_info); i++) {
if (chip_info[i].id == pci_id)
return &chip_info[i];
}
return NULL;
}
static int hda_init(struct snd_sof_dev *sdev)
{
struct hda_bus *hbus;
struct hdac_bus *bus;
struct hdac_ext_bus_ops *ext_ops = NULL;
struct pci_dev *pci = sdev->pci;
int ret;
hbus = sof_to_hbus(sdev);
bus = sof_to_bus(sdev);
/* HDA bus init */
#if IS_ENABLED(CONFIG_SND_SOC_HDAC_HDA)
ext_ops = snd_soc_hdac_hda_get_ops();
#endif
sof_hda_bus_init(bus, &pci->dev, ext_ops);
bus->use_posbuf = 1;
bus->bdl_pos_adj = 0;
mutex_init(&hbus->prepare_mutex);
hbus->pci = pci;
hbus->mixer_assigned = -1;
hbus->modelname = "sofbus";
/* initialise hdac bus */
bus->addr = pci_resource_start(pci, 0);
bus->remap_addr = pci_ioremap_bar(pci, 0);
if (!bus->remap_addr) {
dev_err(bus->dev, "ioremap error\n");
return -ENXIO;
}
/* HDA base */
sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
/* get controller capabilities */
ret = hda_dsp_ctrl_get_caps(sdev);
if (ret < 0)
dev_err(&pci->dev, "error: get caps error\n");
return ret;
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
static int hda_init_caps(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
struct pci_dev *pci = sdev->pci;
struct hdac_ext_link *hlink = NULL;
int ret = 0;
/* The initialization process of HDA in SOF is:
* (1) init HDA to set up a context for i915 initialization
* then stop HDA bus.
*/
hda_dsp_ctrl_init_chip(sdev, true);
device_disable_async_suspend(bus->dev);
/* check if dsp is there */
if (bus->ppcap)
dev_dbg(&pci->dev, "PP capbility, will probe DSP later.\n");
if (bus->mlcap)
snd_hdac_ext_bus_get_ml_capabilities(bus);
snd_hdac_bus_stop_chip(bus);
/* (2) probe i915 and HDA codecs, HDMI codecs */
if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
ret = hda_codec_i915_init(sdev);
if (ret < 0)
return ret;
}
/* only HDA analog codec is detected in step (1) and
* codec_mask would be set. At step(3) HDMI codec can't
* be detected because HDA framework only check codecs
* when codec_mask is zero. So now set codec_mask to zero
* to force HDA framework to check codecs again.
*/
bus->codec_mask = 0;
/* (3) init HDA again to make everything ready so that all
* the codecs can be detected.
*/
ret = hda_dsp_ctrl_init_chip(sdev, true);
if (ret < 0) {
dev_err(bus->dev, "Init chip failed with ret: %d\n", ret);
if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
snd_hdac_display_power(bus, false);
return ret;
}
/* codec detection */
if (!bus->codec_mask)
dev_info(bus->dev, "no hda codecs found!\n");
/* used by hda machine driver to create dai links */
sdev->pdata->codec_mask = bus->codec_mask;
/* create codec instances */
hda_codec_probe_bus(sdev);
if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
ret = snd_hdac_display_power(bus, false);
if (ret < 0) {
dev_err(bus->dev, "Cannot turn off display power on i915\n");
return ret;
}
}
/*
* we are done probing so decrement link counts
*/
list_for_each_entry(hlink, &bus->hlink_list, list)
snd_hdac_ext_bus_link_put(bus, hlink);
return 0;
}
#else
static int hda_init_caps(struct snd_sof_dev *sdev)
{
/*
* set CGCTL.MISCBDCGE to 0 during reset and set back to 1
* when reset finished.
* TODO: maybe no need for init_caps?
*/
hda_dsp_ctrl_misc_clock_gating(sdev, 0);
/* clear WAKESTS */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
SOF_HDA_WAKESTS_INT_MASK,
SOF_HDA_WAKESTS_INT_MASK);
return 0;
}
#endif
/*
* We don't need to do a full HDA codec probe as external HDA codec mode is
* considered legacy and will not be supported under SOF. HDMI/DP HDA will
* be supported in the DSP.
*/
int hda_dsp_probe(struct snd_sof_dev *sdev)
{
struct pci_dev *pci = sdev->pci;
struct sof_intel_hda_dev *hdev;
struct hdac_bus *bus;
struct hdac_stream *stream;
const struct sof_intel_dsp_desc *chip;
int sd_offset, ret = 0;
/* set DSP arch ops */
sdev->arch_ops = &sof_xtensa_arch_ops;
chip = get_chip_info(pci->device);
if (!chip) {
dev_err(sdev->dev, "no such device supported, chip id:%x\n",
pci->device);
ret = -EIO;
goto err;
}
hdev = devm_kzalloc(&pci->dev, sizeof(*hdev), GFP_KERNEL);
if (!hdev)
return -ENOMEM;
sdev->hda = hdev;
hdev->desc = chip;
/*
* use position update IPC if either it is forced
* or we don't have other choice
*/
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION)
hdev->no_ipc_position = 0;
#else
hdev->no_ipc_position = sdev->ops->pcm_pointer ? 1 : 0;
#endif
/* set up HDA base */
ret = hda_init(sdev);
if (ret < 0)
return ret;
/* DSP base */
sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR);
if (!sdev->bar[HDA_DSP_BAR]) {
dev_err(&pci->dev, "error: ioremap error\n");
return -ENXIO;
}
sdev->mmio_bar = HDA_DSP_BAR;
sdev->mailbox_bar = HDA_DSP_BAR;
/* allow 64bit DMA address if supported by H/W */
if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(64))) {
dev_dbg(&pci->dev, "DMA mask is 64 bit\n");
dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(64));
} else {
dev_dbg(&pci->dev, "DMA mask is 32 bit\n");
dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
}
/* init streams */
ret = hda_dsp_stream_init(sdev);
if (ret < 0) {
dev_err(&pci->dev, "error: failed to init streams\n");
/*
* not all errors are due to memory issues, but trying
* to free everything does not harm
*/
goto err;
}
/*
* register our IRQ
* let's try to enable msi firstly
* if it fails, use legacy interrupt mode
* TODO: support interrupt mode selection with kernel parameter
* support msi multiple vectors
*/
// ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI);
/* todo: MSI mode doesn't work for HDMI yet, debug it later */
ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_LEGACY);
if (ret < 0) {
dev_info(sdev->dev, "use legacy interrupt mode\n");
sdev->hda->irq = pci->irq;
sdev->ipc_irq = pci->irq;
} else {
dev_info(sdev->dev, "use msi interrupt mode\n");
sdev->hda->irq = pci_irq_vector(pci, 0);
/* ipc irq number is the same of hda irq */
sdev->ipc_irq = sdev->hda->irq;
}
bus = sof_to_bus(sdev);
dev_dbg(sdev->dev, "using HDA IRQ %d\n", sdev->hda->irq);
ret = request_threaded_irq(sdev->hda->irq, hda_dsp_stream_interrupt,
hda_dsp_stream_threaded_handler,
IRQF_SHARED, "AudioHDA", bus);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to register HDA IRQ %d\n",
sdev->hda->irq);
goto free_streams;
}
dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq);
ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_ipc_irq_handler,
chip->ops->irq_thread, IRQF_SHARED,
"AudioDSP", sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n",
sdev->ipc_irq);
goto free_hda_irq;
}
pci_set_master(pci);
synchronize_irq(pci->irq);
/*
* clear TCSEL to clear playback on some HD Audio
* codecs. PCI TCSEL is defined in the Intel manuals.
*/
snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
/* init HDA capabilities */
ret = hda_init_caps(sdev);
if (ret < 0)
goto free_ipc_irq;
/* reset HDA controller */
ret = hda_dsp_ctrl_link_reset(sdev);
if (ret < 0) {
dev_err(&pci->dev, "error: failed to reset HDA controller\n");
goto free_ipc_irq;
}
/* clear stream status */
list_for_each_entry(stream, &bus->stream_list, list) {
sd_offset = SOF_STREAM_SD_OFFSET(stream);
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
sd_offset +
SOF_HDA_ADSP_REG_CL_SD_STS,
SOF_HDA_CL_DMA_SD_INT_MASK,
SOF_HDA_CL_DMA_SD_INT_MASK);
}
/* clear WAKESTS */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
SOF_HDA_WAKESTS_INT_MASK,
SOF_HDA_WAKESTS_INT_MASK);
/* clear interrupt status register */
snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
/* enable CIE and GIE interrupts */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
/* re-enable CGCTL.MISCBDCGE after reset */
hda_dsp_ctrl_misc_clock_gating(sdev, true);
device_disable_async_suspend(&pci->dev);
/* enable DSP features */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
SOF_HDA_PPCTL_GPROCEN, SOF_HDA_PPCTL_GPROCEN);
/* enable DSP IRQ */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
SOF_HDA_PPCTL_PIE, SOF_HDA_PPCTL_PIE);
/* initialize waitq for code loading */
init_waitqueue_head(&sdev->waitq);
/* set default mailbox offset for FW ready message */
sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET;
return 0;
free_ipc_irq:
free_irq(sdev->ipc_irq, sdev);
free_hda_irq:
free_irq(sdev->hda->irq, bus);
pci_free_irq_vectors(pci);
free_streams:
hda_dsp_stream_free(sdev);
err:
/* disable DSP */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
SOF_HDA_PPCTL_GPROCEN, 0);
return ret;
}
int hda_dsp_remove(struct snd_sof_dev *sdev)
{
struct hdac_bus *bus = sof_to_bus(sdev);
struct pci_dev *pci = sdev->pci;
const struct sof_intel_dsp_desc *chip = sdev->hda->desc;
/* disable DSP IRQ */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
SOF_HDA_PPCTL_PIE, 0);
/* disable CIE and GIE interrupts */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0);
/* disable cores */
if (chip)
hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
/* disable DSP */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
SOF_HDA_PPCTL_GPROCEN, 0);
free_irq(sdev->ipc_irq, sdev);
free_irq(sdev->pci->irq, bus);
pci_free_irq_vectors(pci);
hda_dsp_stream_free(sdev);
return 0;
}
MODULE_LICENSE("Dual BSD/GPL");

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sound/soc/sof/intel/hda.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
/*
* This file is provided under a dual BSD/GPLv2 license. When using or
* redistributing this file, you may do so under either license.
*
* Copyright(c) 2017 Intel Corporation. All rights reserved.
*
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
*/
#ifndef __SOF_INTEL_HDA_H
#define __SOF_INTEL_HDA_H
#include <sound/hda_codec.h>
/* PCI registers */
#define PCI_TCSEL 0x44
#define PCI_CGCTL 0x48
/* PCI_CGCTL bits */
#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
#define PCI_CGCTL_LSRMD_MASK BIT(4)
/* Legacy HDA registers and bits used - widths are variable */
#define SOF_HDA_GCAP 0x0
#define SOF_HDA_GCTL 0x8
/* accept unsol. response enable */
#define SOF_HDA_GCTL_UNSOL BIT(8)
#define SOF_HDA_LLCH 0x14
#define SOF_HDA_INTCTL 0x20
#define SOF_HDA_INTSTS 0x24
#define SOF_HDA_WAKESTS 0x0E
#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
#define SOF_HDA_RIRBSTS 0x5d
/* SOF_HDA_GCTL register bist */
#define SOF_HDA_GCTL_RESET BIT(0)
/* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */
#define SOF_HDA_INT_GLOBAL_EN BIT(31)
#define SOF_HDA_INT_CTRL_EN BIT(30)
#define SOF_HDA_INT_ALL_STREAM 0xff
#define SOF_HDA_MAX_CAPS 10
#define SOF_HDA_CAP_ID_OFF 16
#define SOF_HDA_CAP_ID_MASK (0xFFF << SOF_HDA_CAP_ID_OFF)
#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
#define SOF_HDA_GTS_CAP_ID 0x1
#define SOF_HDA_ML_CAP_ID 0x2
#define SOF_HDA_PP_CAP_ID 0x3
#define SOF_HDA_REG_PP_PPCH 0x10
#define SOF_HDA_REG_PP_PPCTL 0x04
#define SOF_HDA_PPCTL_PIE BIT(31)
#define SOF_HDA_PPCTL_GPROCEN BIT(30)
/* DPIB entry size: 8 Bytes = 2 DWords */
#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
#define SOF_HDA_SPIB_CAP_ID 0x4
#define SOF_HDA_DRSM_CAP_ID 0x5
#define SOF_HDA_SPIB_BASE 0x08
#define SOF_HDA_SPIB_INTERVAL 0x08
#define SOF_HDA_SPIB_SPIB 0x00
#define SOF_HDA_SPIB_MAXFIFO 0x04
#define SOF_HDA_PPHC_BASE 0x10
#define SOF_HDA_PPHC_INTERVAL 0x10
#define SOF_HDA_PPLC_BASE 0x10
#define SOF_HDA_PPLC_MULTI 0x10
#define SOF_HDA_PPLC_INTERVAL 0x10
#define SOF_HDA_DRSM_BASE 0x08
#define SOF_HDA_DRSM_INTERVAL 0x08
/* Descriptor error interrupt */
#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
/* FIFO error interrupt */
#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
/* Buffer completion interrupt */
#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
#define SOF_HDA_CL_DMA_SD_INT_MASK \
(SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
SOF_HDA_CL_DMA_SD_INT_COMPLETE)
#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
/* Intel HD Audio Code Loader DMA Registers */
#define SOF_HDA_ADSP_LOADER_BASE 0x80
#define SOF_HDA_ADSP_DPLBASE 0x70
#define SOF_HDA_ADSP_DPUBASE 0x74
#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
/* Stream Registers */
#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
/* CL: Software Position Based FIFO Capability Registers */
#define SOF_DSP_REG_CL_SPBFIFO \
(SOF_HDA_ADSP_LOADER_BASE + 0x20)
#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
/* Stream Number */
#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
(0xf << SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
#define HDA_DSP_HDA_BAR 0
#define HDA_DSP_PP_BAR 1
#define HDA_DSP_SPIB_BAR 2
#define HDA_DSP_DRSM_BAR 3
#define HDA_DSP_BAR 4
#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
#define HDA_DSP_PANIC_OFFSET(x) \
(((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
/* SRAM window 0 FW "registers" */
#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
/* FW and ROM share offset 4 */
#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
#define HDA_DSP_STREAM_RESET_TIMEOUT 300
#define HDA_DSP_CL_TRIGGER_TIMEOUT 300
#define HDA_DSP_SPIB_ENABLE 1
#define HDA_DSP_SPIB_DISABLE 0
#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
#define HDA_DSP_STACK_DUMP_SIZE 32
/* ROM status/error values */
#define HDA_DSP_ROM_STS_MASK 0xf
#define HDA_DSP_ROM_INIT 0x1
#define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
#define HDA_DSP_ROM_FW_FW_LOADED 0x4
#define HDA_DSP_ROM_FW_ENTERED 0x5
#define HDA_DSP_ROM_RFW_START 0xf
#define HDA_DSP_ROM_CSE_ERROR 40
#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
#define HDA_DSP_ROM_IMR_TO_SMALL 42
#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
#define HDA_DSP_ROM_L2_CACHE_ERROR 46
#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
#define HDA_DSP_ROM_API_PTR_INVALID 50
#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
#define HDA_DSP_IPC_PURGE_FW 0x01004000
/* various timeout values */
#define HDA_DSP_PU_TIMEOUT 50
#define HDA_DSP_PD_TIMEOUT 50
#define HDA_DSP_RESET_TIMEOUT 50
#define HDA_DSP_BASEFW_TIMEOUT 3000
#define HDA_DSP_INIT_TIMEOUT 500
#define HDA_DSP_CTRL_RESET_TIMEOUT 100
#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
#define HDA_DSP_ADSPIC_IPC 1
#define HDA_DSP_ADSPIS_IPC 1
/* Intel HD Audio General DSP Registers */
#define HDA_DSP_GEN_BASE 0x0
#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
/* Intel HD Audio Inter-Processor Communication Registers */
#define HDA_DSP_IPC_BASE 0x40
#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
/* HIPCI */
#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
/* HIPCIE */
#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
/* HIPCCTL */
#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
/* HIPCT */
#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
/* HIPCTE */
#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
#define HDA_DSP_ADSPIC_CL_DMA 0x2
#define HDA_DSP_ADSPIS_CL_DMA 0x2
/* Delay before scheduling D0i3 entry */
#define BXT_D0I3_DELAY 5000
#define FW_CL_STREAM_NUMBER 0x1
/* ADSPCS - Audio DSP Control & Status */
/*
* Core Reset - asserted high
* CRST Mask for a given core mask pattern, cm
*/
#define HDA_DSP_ADSPCS_CRST_SHIFT 0
#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
/*
* Core run/stall - when set to '1' core is stalled
* CSTALL Mask for a given core mask pattern, cm
*/
#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
/*
* Set Power Active - when set to '1' turn cores on
* SPA Mask for a given core mask pattern, cm
*/
#define HDA_DSP_ADSPCS_SPA_SHIFT 16
#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
/*
* Current Power Active - power status of cores, set by hardware
* CPA Mask for a given core mask pattern, cm
*/
#define HDA_DSP_ADSPCS_CPA_SHIFT 24
#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
/* Mask for a given core index, c = 0.. number of supported cores - 1 */
#define HDA_DSP_CORE_MASK(c) BIT(c)
/*
* Mask for a given number of cores
* nc = number of supported cores
*/
#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
#define CNL_DSP_IPC_BASE 0xc0
#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
/* HIPCI */
#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
/* HIPCIE */
#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
/* HIPCCTL */
#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
/* HIPCT */
#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
/* HIPCTDA */
#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
/* HIPCTDD */
#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
/* BDL */
#define HDA_DSP_BDL_SIZE 4096
#define HDA_DSP_MAX_BDL_ENTRIES \
(HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
/* Number of DAIs */
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
#define SOF_SKL_NUM_DAIS 14
#else
#define SOF_SKL_NUM_DAIS 8
#endif
#define HDA_DSP_SRAM_REG_ROM_STATUS_SKL 0x8000
struct sof_intel_dsp_bdl {
u32 addr_l;
u32 addr_h;
u32 size;
u32 ioc;
} __attribute((packed));
/* DSP hardware descriptor */
struct sof_intel_dsp_desc {
int id;
int cores_num;
int cores_mask;
int ipc_req;
int ipc_req_mask;
int ipc_ack;
int ipc_ack_mask;
int ipc_ctl;
struct snd_sof_dsp_ops *ops;
};
#define SOF_HDA_PLAYBACK_STREAMS 16
#define SOF_HDA_CAPTURE_STREAMS 16
#define SOF_HDA_PLAYBACK 0
#define SOF_HDA_CAPTURE 1
/* represents DSP HDA controller frontend - i.e. host facing control */
struct sof_intel_hda_dev {
struct hda_bus hbus;
/* hw config */
const struct sof_intel_dsp_desc *desc;
/*trace */
struct hdac_ext_stream *dtrace_stream;
/* if position update IPC needed */
bool no_ipc_position;
int irq;
};
#define bus_to_sof_hda(bus) \
container_of(bus, struct sof_intel_hda_dev, hbus.core)
#define SOF_STREAM_SD_OFFSET(s) \
(SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
+ SOF_HDA_ADSP_LOADER_BASE)
/*
* DSP Core services.
*/
int hda_dsp_probe(struct snd_sof_dev *sdev);
int hda_dsp_remove(struct snd_sof_dev *sdev);
int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
unsigned int core_mask);
int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
unsigned int core_mask);
int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
int hda_dsp_core_stall_reset_skl(struct snd_sof_dev *sdev,
unsigned int core_mask);
int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
unsigned int core_mask);
int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
unsigned int core_mask);
int hda_dsp_suspend(struct snd_sof_dev *sdev, int state);
int hda_dsp_resume(struct snd_sof_dev *sdev);
int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev, int state);
int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
/*
* DSP IO
*/
void hda_dsp_write(struct snd_sof_dev *sdev, void __iomem *addr, u32 value);
u32 hda_dsp_read(struct snd_sof_dev *sdev, void __iomem *addr);
void hda_dsp_write64(struct snd_sof_dev *sdev, void __iomem *addr, u64 value);
u64 hda_dsp_read64(struct snd_sof_dev *sdev, void __iomem *addr);
void hda_dsp_block_write(struct snd_sof_dev *sdev, u32 offset, void *src,
size_t size);
void hda_dsp_block_read(struct snd_sof_dev *sdev, u32 offset, void *dest,
size_t size);
void hda_dsp_mailbox_write(struct snd_sof_dev *sdev, u32 offset,
void *message, size_t bytes);
void hda_dsp_mailbox_read(struct snd_sof_dev *sdev, u32 offset,
void *message, size_t bytes);
/*
* DSP PCM Operations.
*/
int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream);
int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream);
int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct sof_ipc_stream_params *ipc_params);
int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream, int cmd);
snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
struct snd_pcm_substream *substream);
/*
* DSP Stream Operations.
*/
int hda_dsp_stream_init(struct snd_sof_dev *sdev);
void hda_dsp_stream_free(struct snd_sof_dev *sdev);
int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
struct hdac_ext_stream *stream,
struct snd_dma_buffer *dmab,
struct snd_pcm_hw_params *params);
int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
struct hdac_ext_stream *stream, int cmd);
irqreturn_t hda_dsp_stream_interrupt(int irq, void *context);
irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
struct snd_dma_buffer *dmab,
struct hdac_stream *stream);
struct hdac_ext_stream *
hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
struct hdac_ext_stream *
hda_dsp_stream_get_cstream(struct snd_sof_dev *sdev);
struct hdac_ext_stream *
hda_dsp_stream_get_pstream(struct snd_sof_dev *sdev);
int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
int hda_dsp_stream_put_pstream(struct snd_sof_dev *sdev, int stream_tag);
int hda_dsp_stream_put_cstream(struct snd_sof_dev *sdev, int stream_tag);
int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
struct hdac_ext_stream *stream,
int enable, u32 size);
/*
* DSP IPC Operations.
*/
int hda_dsp_ipc_is_ready(struct snd_sof_dev *sdev);
int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
struct snd_sof_ipc_msg *msg);
int hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev,
struct snd_sof_ipc_msg *msg);
int hda_dsp_ipc_fw_ready(struct snd_sof_dev *sdev, u32 msg_id);
irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context);
irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
/*
* DSP Code loader.
*/
int hda_dsp_cl_load_fw(struct snd_sof_dev *sdev, bool first_boot);
int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
/*
* HDA Controller Operations.
*/
int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev);
void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
/*
* HDA bus operations.
*/
int sof_hda_bus_init(struct hdac_bus *bus, struct device *dev,
const struct hdac_ext_bus_ops *ext_ops);
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
/*
* HDA Codec operations.
*/
int hda_codec_probe_bus(struct snd_sof_dev *sdev);
int hda_codec_i915_init(struct snd_sof_dev *sdev);
#endif
/*
* Trace Control.
*/
int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
int hda_dsp_trace_release(struct snd_sof_dev *sdev);
int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
/* common dai driver */
extern struct snd_soc_dai_driver skl_dai[];
/*
* Platform Specific HW abstraction Ops.
*/
extern struct snd_sof_dsp_ops sof_apl_ops;
extern struct snd_sof_dsp_ops sof_cnl_ops;
extern struct snd_sof_dsp_ops sof_skl_ops;
#endif