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rk3288 dts: modify lcdc0 as prmry(LCD) and lcdc1 as extend(HDMI) that just used for MID

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This commit is contained in:
zwl 2014-06-24 14:15:09 +08:00
parent e8242f4e1b
commit debf1d2237
6 changed files with 37 additions and 35 deletions
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7
arch/arm/boot/dts/rk3288-chrome.dts
View File

@ -476,8 +476,8 @@ &rk_screen {
display-timings = <&disp_timings>;
};
/*lcdc1 as PRMRY(LCD),lcdc0 as EXTEND(HDMI)*/
&lcdc1 {
/*lcdc0 as PRMRY(LCD),lcdc1 as EXTEND(HDMI)*/
&lcdc0 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
rockchip,cabc_mode = <0>;
@ -504,8 +504,9 @@ lcd_cs:lcd_cs {
};
};
&lcdc0 {
&lcdc1 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
};
&hdmi {

7
arch/arm/boot/dts/rk3288-p977.dts
View File

@ -446,8 +446,8 @@ &rk_screen {
display-timings = <&disp_timings>;
};
/*lcdc1 as PRMRY(LCD),lcdc0 as EXTEND(HDMI)*/
&lcdc1 {
/*lcdc0 as PRMRY(LCD),lcdc1 as EXTEND(HDMI)*/
&lcdc0 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
rockchip,cabc_mode = <0>;
@ -474,8 +474,9 @@ lcd_rst:lcd_rst {
};
};
&lcdc0 {
&lcdc1 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
};
&hdmi {

7
arch/arm/boot/dts/rk3288-p977_8846.dts
View File

@ -505,8 +505,8 @@ &rk_screen {
display-timings = <&disp_timings>;
};
/*lcdc1 as PRMRY(LCD),lcdc0 as EXTEND(HDMI)*/
&lcdc1 {
/*lcdc0 as PRMRY(LCD),lcdc1 as EXTEND(HDMI)*/
&lcdc0 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
rockchip,cabc_mode = <0>;
@ -533,8 +533,9 @@ lcd_rst:lcd_rst {
};
};
&lcdc0 {
&lcdc1 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
};
&hdmi {

7
arch/arm/boot/dts/rk3288-tb.dts
View File

@ -587,8 +587,8 @@ &rk_screen {
display-timings = <&disp_timings>;
};
/*lcdc1 as PRMRY(LCD),lcdc0 as EXTEND(HDMI)*/
&lcdc1 {
/*lcdc0 as PRMRY(LCD),lcdc1 as EXTEND(HDMI)*/
&lcdc0 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
rockchip,cabc_mode = <0>;
@ -615,8 +615,9 @@ lcd_cs:lcd_cs {
};
};
&lcdc0 {
&lcdc1 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
};
&hdmi {

9
arch/arm/boot/dts/rk3288-tesco.dts
View File

@ -442,8 +442,8 @@ &rk_screen {
display-timings = <&disp_timings>;
};
/*lcdc1 as PRMRY(LCD),lcdc0 as EXTEND(HDMI)*/
&lcdc1 {
/*lcdc0 as PRMRY(LCD),lcdc1 as EXTEND(HDMI)*/
&lcdc0 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
rockchip,cabc_mode = <0>;
@ -457,7 +457,7 @@ lcd_en:lcd_en {
};
lcd_cs:lcd_cs {
rockchip,power_type = <GPIO>;
rockchip,power_type = <GPIO>;
gpios = <&gpio7 GPIO_A4 GPIO_ACTIVE_HIGH>;
rockchip,delay = <10>;
};
@ -471,8 +471,9 @@ lcd_cs:lcd_cs {
};
};
&lcdc0 {
&lcdc1 {
status = "okay";
rockchip,mirror = <NO_MIRROR>;
};
&hdmi {

35
arch/arm/boot/dts/rk3288.dtsi
View File

@ -745,36 +745,33 @@ hdmi: hdmi@ff980000 {
status = "disabled";
};
lcdc1: lcdc@ff940000 {
compatible = "rockchip,rk3288-lcdc";
rockchip,prop = <PRMRY>;
rochchip,pwr18 = <0>;
rockchip,iommu-enabled = <1>;
reg = <0xff940000 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&lcdc0_lcdc>;
pinctrl-1 = <&lcdc0_gpio>;
status = "disabled";
clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
};
lcdc0: lcdc@ff930000 {
compatible = "rockchip,rk3288-lcdc";
rockchip,prop = <EXTEND>;
rockchip,prop = <PRMRY>;
rockchip,pwr18 = <0>;
rockchip,iommu-enabled = <1>;
reg = <0xff930000 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
//pinctrl-names = "default", "gpio";
//pinctrl-0 = <&lcdc0_lcdc>;
//pinctrl-1 = <&lcdc0_gpio>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&lcdc0_lcdc>;
pinctrl-1 = <&lcdc0_gpio>;
status = "disabled";
clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
};
lcdc1: lcdc@ff940000 {
compatible = "rockchip,rk3288-lcdc";
rockchip,prop = <EXTEND>;
rochchip,pwr18 = <0>;
rockchip,iommu-enabled = <1>;
reg = <0xff940000 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
};
adc: adc@ff100000 {
compatible = "rockchip,saradc";
reg = <0xff100000 0x100>;