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arm64: dts: qcom: sdm845: Fix the PCIe iommu-map entries

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The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe
iommu-map entries specify only one cell for the SID, omitting the SID
mask. This went unnoticed until the OF core started warning with commit
ccb2fd725d ("of: Respect #{iommu,msi}-cells in maps"):

  iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output

So fix the entries to match the provider's '#iommu-cells' property.

Fixes: 5c538e09cb ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-5-83405d37ba41@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam 2026-07-30 13:55:46 +02:00 committed by Bjorn Andersson
parent a454820482
commit deaea7e982
1 changed files with 32 additions and 32 deletions
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64
arch/arm64/boot/dts/qcom/sdm845.dtsi
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@ -2372,22 +2372,22 @@ pcie0: pcie@1c00000 {
"slave_q2a",
"tbu";
iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
<0x100 &apps_smmu 0x1c11 0x1>,
<0x200 &apps_smmu 0x1c12 0x1>,
<0x300 &apps_smmu 0x1c13 0x1>,
<0x400 &apps_smmu 0x1c14 0x1>,
<0x500 &apps_smmu 0x1c15 0x1>,
<0x600 &apps_smmu 0x1c16 0x1>,
<0x700 &apps_smmu 0x1c17 0x1>,
<0x800 &apps_smmu 0x1c18 0x1>,
<0x900 &apps_smmu 0x1c19 0x1>,
<0xa00 &apps_smmu 0x1c1a 0x1>,
<0xb00 &apps_smmu 0x1c1b 0x1>,
<0xc00 &apps_smmu 0x1c1c 0x1>,
<0xd00 &apps_smmu 0x1c1d 0x1>,
<0xe00 &apps_smmu 0x1c1e 0x1>,
<0xf00 &apps_smmu 0x1c1f 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c10 0x0 0x1>,
<0x100 &apps_smmu 0x1c11 0x0 0x1>,
<0x200 &apps_smmu 0x1c12 0x0 0x1>,
<0x300 &apps_smmu 0x1c13 0x0 0x1>,
<0x400 &apps_smmu 0x1c14 0x0 0x1>,
<0x500 &apps_smmu 0x1c15 0x0 0x1>,
<0x600 &apps_smmu 0x1c16 0x0 0x1>,
<0x700 &apps_smmu 0x1c17 0x0 0x1>,
<0x800 &apps_smmu 0x1c18 0x0 0x1>,
<0x900 &apps_smmu 0x1c19 0x0 0x1>,
<0xa00 &apps_smmu 0x1c1a 0x0 0x1>,
<0xb00 &apps_smmu 0x1c1b 0x0 0x1>,
<0xc00 &apps_smmu 0x1c1c 0x0 0x1>,
<0xd00 &apps_smmu 0x1c1d 0x0 0x1>,
<0xe00 &apps_smmu 0x1c1e 0x0 0x1>,
<0xf00 &apps_smmu 0x1c1f 0x0 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
@ -2502,22 +2502,22 @@ pcie1: pcie@1c08000 {
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>,
<0x200 &apps_smmu 0x1c02 0x1>,
<0x300 &apps_smmu 0x1c03 0x1>,
<0x400 &apps_smmu 0x1c04 0x1>,
<0x500 &apps_smmu 0x1c05 0x1>,
<0x600 &apps_smmu 0x1c06 0x1>,
<0x700 &apps_smmu 0x1c07 0x1>,
<0x800 &apps_smmu 0x1c08 0x1>,
<0x900 &apps_smmu 0x1c09 0x1>,
<0xa00 &apps_smmu 0x1c0a 0x1>,
<0xb00 &apps_smmu 0x1c0b 0x1>,
<0xc00 &apps_smmu 0x1c0c 0x1>,
<0xd00 &apps_smmu 0x1c0d 0x1>,
<0xe00 &apps_smmu 0x1c0e 0x1>,
<0xf00 &apps_smmu 0x1c0f 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>,
<0x100 &apps_smmu 0x1c01 0x0 0x1>,
<0x200 &apps_smmu 0x1c02 0x0 0x1>,
<0x300 &apps_smmu 0x1c03 0x0 0x1>,
<0x400 &apps_smmu 0x1c04 0x0 0x1>,
<0x500 &apps_smmu 0x1c05 0x0 0x1>,
<0x600 &apps_smmu 0x1c06 0x0 0x1>,
<0x700 &apps_smmu 0x1c07 0x0 0x1>,
<0x800 &apps_smmu 0x1c08 0x0 0x1>,
<0x900 &apps_smmu 0x1c09 0x0 0x1>,
<0xa00 &apps_smmu 0x1c0a 0x0 0x1>,
<0xb00 &apps_smmu 0x1c0b 0x0 0x1>,
<0xc00 &apps_smmu 0x1c0c 0x0 0x1>,
<0xd00 &apps_smmu 0x1c0d 0x0 0x1>,
<0xe00 &apps_smmu 0x1c0e 0x0 0x1>,
<0xf00 &apps_smmu 0x1c0f 0x0 0x1>;
resets = <&gcc GCC_PCIE_1_BCR>;
reset-names = "pci";